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authorMagnus Damm <damm@opensource.se>2012-02-29 08:17:32 -0500
committerRafael J. Wysocki <rjw@sisk.pl>2012-03-12 17:19:11 -0400
commit4ad2c061550faa8def698fa7c2e4f1c81e90ac18 (patch)
treee535578a1981dec43c66285994d5e424f217c0b2 /arch/sh
parent71984236d6112d6eb735f449cf3253c2d35d2767 (diff)
sh: sh2a sh_clk_ops rename
Convert sh2a SoCs to use sh_clk_ops. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7201.c12
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7203.c12
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7206.c12
3 files changed, 18 insertions, 18 deletions
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index 1174e2d96c03..532a36c72322 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -30,7 +30,7 @@ static void master_clk_init(struct clk *clk)
30 pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; 30 pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
31} 31}
32 32
33static struct clk_ops sh7201_master_clk_ops = { 33static struct sh_clk_ops sh7201_master_clk_ops = {
34 .init = master_clk_init, 34 .init = master_clk_init,
35}; 35};
36 36
@@ -40,7 +40,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
40 return clk->parent->rate / pfc_divisors[idx]; 40 return clk->parent->rate / pfc_divisors[idx];
41} 41}
42 42
43static struct clk_ops sh7201_module_clk_ops = { 43static struct sh_clk_ops sh7201_module_clk_ops = {
44 .recalc = module_clk_recalc, 44 .recalc = module_clk_recalc,
45}; 45};
46 46
@@ -50,7 +50,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
50 return clk->parent->rate / pfc_divisors[idx]; 50 return clk->parent->rate / pfc_divisors[idx];
51} 51}
52 52
53static struct clk_ops sh7201_bus_clk_ops = { 53static struct sh_clk_ops sh7201_bus_clk_ops = {
54 .recalc = bus_clk_recalc, 54 .recalc = bus_clk_recalc,
55}; 55};
56 56
@@ -60,18 +60,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
60 return clk->parent->rate / ifc_divisors[idx]; 60 return clk->parent->rate / ifc_divisors[idx];
61} 61}
62 62
63static struct clk_ops sh7201_cpu_clk_ops = { 63static struct sh_clk_ops sh7201_cpu_clk_ops = {
64 .recalc = cpu_clk_recalc, 64 .recalc = cpu_clk_recalc,
65}; 65};
66 66
67static struct clk_ops *sh7201_clk_ops[] = { 67static struct sh_clk_ops *sh7201_clk_ops[] = {
68 &sh7201_master_clk_ops, 68 &sh7201_master_clk_ops,
69 &sh7201_module_clk_ops, 69 &sh7201_module_clk_ops,
70 &sh7201_bus_clk_ops, 70 &sh7201_bus_clk_ops,
71 &sh7201_cpu_clk_ops, 71 &sh7201_cpu_clk_ops,
72}; 72};
73 73
74void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 74void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
75{ 75{
76 if (test_mode_pin(MODE_PIN1 | MODE_PIN0)) 76 if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
77 pll2_mult = 1; 77 pll2_mult = 1;
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index 95a008e8b735..529f719b6e33 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -32,7 +32,7 @@ static void master_clk_init(struct clk *clk)
32 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult; 32 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
33} 33}
34 34
35static struct clk_ops sh7203_master_clk_ops = { 35static struct sh_clk_ops sh7203_master_clk_ops = {
36 .init = master_clk_init, 36 .init = master_clk_init,
37}; 37};
38 38
@@ -42,7 +42,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
42 return clk->parent->rate / pfc_divisors[idx]; 42 return clk->parent->rate / pfc_divisors[idx];
43} 43}
44 44
45static struct clk_ops sh7203_module_clk_ops = { 45static struct sh_clk_ops sh7203_module_clk_ops = {
46 .recalc = module_clk_recalc, 46 .recalc = module_clk_recalc,
47}; 47};
48 48
@@ -52,22 +52,22 @@ static unsigned long bus_clk_recalc(struct clk *clk)
52 return clk->parent->rate / pfc_divisors[idx-2]; 52 return clk->parent->rate / pfc_divisors[idx-2];
53} 53}
54 54
55static struct clk_ops sh7203_bus_clk_ops = { 55static struct sh_clk_ops sh7203_bus_clk_ops = {
56 .recalc = bus_clk_recalc, 56 .recalc = bus_clk_recalc,
57}; 57};
58 58
59static struct clk_ops sh7203_cpu_clk_ops = { 59static struct sh_clk_ops sh7203_cpu_clk_ops = {
60 .recalc = followparent_recalc, 60 .recalc = followparent_recalc,
61}; 61};
62 62
63static struct clk_ops *sh7203_clk_ops[] = { 63static struct sh_clk_ops *sh7203_clk_ops[] = {
64 &sh7203_master_clk_ops, 64 &sh7203_master_clk_ops,
65 &sh7203_module_clk_ops, 65 &sh7203_module_clk_ops,
66 &sh7203_bus_clk_ops, 66 &sh7203_bus_clk_ops,
67 &sh7203_cpu_clk_ops, 67 &sh7203_cpu_clk_ops,
68}; 68};
69 69
70void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 70void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
71{ 71{
72 if (test_mode_pin(MODE_PIN1)) 72 if (test_mode_pin(MODE_PIN1))
73 pll2_mult = 4; 73 pll2_mult = 4;
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index 3c314d7cd6e6..177789834678 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -29,7 +29,7 @@ static void master_clk_init(struct clk *clk)
29 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; 29 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
30} 30}
31 31
32static struct clk_ops sh7206_master_clk_ops = { 32static struct sh_clk_ops sh7206_master_clk_ops = {
33 .init = master_clk_init, 33 .init = master_clk_init,
34}; 34};
35 35
@@ -39,7 +39,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
39 return clk->parent->rate / pfc_divisors[idx]; 39 return clk->parent->rate / pfc_divisors[idx];
40} 40}
41 41
42static struct clk_ops sh7206_module_clk_ops = { 42static struct sh_clk_ops sh7206_module_clk_ops = {
43 .recalc = module_clk_recalc, 43 .recalc = module_clk_recalc,
44}; 44};
45 45
@@ -48,7 +48,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
48 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; 48 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
49} 49}
50 50
51static struct clk_ops sh7206_bus_clk_ops = { 51static struct sh_clk_ops sh7206_bus_clk_ops = {
52 .recalc = bus_clk_recalc, 52 .recalc = bus_clk_recalc,
53}; 53};
54 54
@@ -58,18 +58,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
58 return clk->parent->rate / ifc_divisors[idx]; 58 return clk->parent->rate / ifc_divisors[idx];
59} 59}
60 60
61static struct clk_ops sh7206_cpu_clk_ops = { 61static struct sh_clk_ops sh7206_cpu_clk_ops = {
62 .recalc = cpu_clk_recalc, 62 .recalc = cpu_clk_recalc,
63}; 63};
64 64
65static struct clk_ops *sh7206_clk_ops[] = { 65static struct sh_clk_ops *sh7206_clk_ops[] = {
66 &sh7206_master_clk_ops, 66 &sh7206_master_clk_ops,
67 &sh7206_module_clk_ops, 67 &sh7206_module_clk_ops,
68 &sh7206_bus_clk_ops, 68 &sh7206_bus_clk_ops,
69 &sh7206_cpu_clk_ops, 69 &sh7206_cpu_clk_ops,
70}; 70};
71 71
72void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 72void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
73{ 73{
74 if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0)) 74 if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
75 pll2_mult = 1; 75 pll2_mult = 1;