sh: implement DMA_SLAVE capability in SH dmaengine driver

Tested to work with a SIU ASoC driver on sh7722 (migor).

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

2 files changed, 48 insertions, 8 deletions

diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h
index 01d2fc72551b..c8d8ce78f346 100644
--- a/arch/sh/include/asm/dma-sh.h
+++ b/arch/sh/include/asm/dma-sh.h
@@ -64,8 +64,10 @@ static int dmte_irq_map[] __maybe_unused = {
 #define ACK_L   0x00010000
 #define DM_INC  0x00004000
 #define DM_DEC  0x00008000
+#define DM_FIX  0x0000c000
 #define SM_INC  0x00001000
 #define SM_DEC  0x00002000
+#define SM_FIX  0x00003000
 #define RS_IN   0x00000200
 #define RS_OUT  0x00000300
 #define TS_BLK  0x00000040
@@ -123,10 +125,47 @@ static u32 dma_base_addr[] __maybe_unused = {
  */
 #define SHDMA_MIX_IRQ   (1 << 1)
 #define SHDMA_DMAOR1    (1 << 2)
-#define SHDMA_DMAE1             (1 << 3)
+#define SHDMA_DMAE1     (1 << 3)
+
+enum sh_dmae_slave_chan_id {
+        SHDMA_SLAVE_SCIF0_TX,
+        SHDMA_SLAVE_SCIF0_RX,
+        SHDMA_SLAVE_SCIF1_TX,
+        SHDMA_SLAVE_SCIF1_RX,
+        SHDMA_SLAVE_SCIF2_TX,
+        SHDMA_SLAVE_SCIF2_RX,
+        SHDMA_SLAVE_SCIF3_TX,
+        SHDMA_SLAVE_SCIF3_RX,
+        SHDMA_SLAVE_SCIF4_TX,
+        SHDMA_SLAVE_SCIF4_RX,
+        SHDMA_SLAVE_SCIF5_TX,
+        SHDMA_SLAVE_SCIF5_RX,
+        SHDMA_SLAVE_SIUA_TX,
+        SHDMA_SLAVE_SIUA_RX,
+        SHDMA_SLAVE_SIUB_TX,
+        SHDMA_SLAVE_SIUB_RX,
+        SHDMA_SLAVE_NUMBER,     /* Must stay last */
+};
+
+struct sh_dmae_slave_config {
+        enum sh_dmae_slave_chan_id      slave_id;
+        dma_addr_t                      addr;
+        u32                             chcr;
+        char                            mid_rid;
+};
 
 struct sh_dmae_pdata {
         unsigned int mode;
+        struct sh_dmae_slave_config *config;
+        int config_num;
+};
+
+struct device;
+
+struct sh_dmae_slave {
+        enum sh_dmae_slave_chan_id      slave_id; /* Set by the platform */
+        struct device                   *dma_dev; /* Set by the platform */
+        struct sh_dmae_slave_config     *config;  /* Set by the driver */
 };
 
 #endif /* __DMA_SH_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
index cc1cf3e8f163..e734ea47d8a0 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
@@ -7,7 +7,7 @@
 #define DMTE4_IRQ       76
 #define DMAE0_IRQ       78      /* DMA Error IRQ*/
 #define SH_DMAC_BASE0   0xFE008020
-#define SH_DMARS_BASE   0xFE009000
+#define SH_DMARS_BASE0  0xFE009000
 #define CHCR_TS_LOW_MASK        0x00000018
 #define CHCR_TS_LOW_SHIFT       3
 #define CHCR_TS_HIGH_MASK       0
@@ -17,7 +17,7 @@
 #define DMTE4_IRQ       76
 #define DMAE0_IRQ       78      /* DMA Error IRQ*/
 #define SH_DMAC_BASE0   0xFE008020
-#define SH_DMARS_BASE   0xFE009000
+#define SH_DMARS_BASE0  0xFE009000
 #define CHCR_TS_LOW_MASK        0x00000018
 #define CHCR_TS_LOW_SHIFT       3
 #define CHCR_TS_HIGH_MASK       0x00300000
@@ -28,7 +28,7 @@
 #define DMTE4_IRQ       44
 #define DMAE0_IRQ       38
 #define SH_DMAC_BASE0   0xFF608020
-#define SH_DMARS_BASE   0xFF609000
+#define SH_DMARS_BASE0  0xFF609000
 #define CHCR_TS_LOW_MASK        0x00000018
 #define CHCR_TS_LOW_SHIFT       3
 #define CHCR_TS_HIGH_MASK       0
@@ -45,7 +45,7 @@
 #define DMAE1_IRQ       74      /* DMA Error IRQ*/
 #define SH_DMAC_BASE0   0xFE008020
 #define SH_DMAC_BASE1   0xFDC08020
-#define SH_DMARS_BASE   0xFDC09000
+#define SH_DMARS_BASE0  0xFDC09000
 #define CHCR_TS_LOW_MASK        0x00000018
 #define CHCR_TS_LOW_SHIFT       3
 #define CHCR_TS_HIGH_MASK       0
@@ -62,7 +62,8 @@
 #define DMAE1_IRQ       74      /* DMA Error IRQ*/
 #define SH_DMAC_BASE0   0xFE008020
 #define SH_DMAC_BASE1   0xFDC08020
-#define SH_DMARS_BASE   0xFDC09000
+#define SH_DMARS_BASE0  0xFE009000
+#define SH_DMARS_BASE1  0xFDC09000
 #define CHCR_TS_LOW_MASK        0x00000018
 #define CHCR_TS_LOW_SHIFT       3
 #define CHCR_TS_HIGH_MASK       0x00600000
@@ -78,7 +79,7 @@
 #define DMAE0_IRQ       38      /* DMA Error IRQ */
 #define SH_DMAC_BASE0   0xFC808020
 #define SH_DMAC_BASE1   0xFC818020
-#define SH_DMARS_BASE   0xFC809000
+#define SH_DMARS_BASE0  0xFC809000
 #define CHCR_TS_LOW_MASK        0x00000018
 #define CHCR_TS_LOW_SHIFT       3
 #define CHCR_TS_HIGH_MASK       0
@@ -95,7 +96,7 @@
 #define DMAE1_IRQ       58      /* DMA Error IRQ1 */
 #define SH_DMAC_BASE0   0xFC808020
 #define SH_DMAC_BASE1   0xFCC08020
-#define SH_DMARS_BASE   0xFC809000
+#define SH_DMARS_BASE0  0xFC809000
 #define CHCR_TS_LOW_MASK        0x00000018
 #define CHCR_TS_LOW_SHIFT       3
 #define CHCR_TS_HIGH_MASK       0