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authorPaul Mundt <lethal@linux-sh.org>2006-09-27 05:28:34 -0400
committerPaul Mundt <lethal@linux-sh.org>2006-09-27 05:28:34 -0400
commitd15f456043175bdf3464514b92a825b88d0546ae (patch)
treeb98ee188453dd5d79ca433c63993bad21c9ca38b /arch/sh
parent72c35543f8cf1316773ffbd9619575bb84ac44fb (diff)
sh: More intelligent entry_mask/way_size calculation.
Figure out the cache desc entry_mask at runtime, and remove hard-coded assumption about the cacheline size. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c20
1 files changed, 13 insertions, 7 deletions
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index bee00cac0b16..c294de1e14a3 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -38,7 +38,6 @@ int __init detect_cpu_and_cache_system(void)
38 */ 38 */
39 cpu_data->icache.way_incr = (1 << 13); 39 cpu_data->icache.way_incr = (1 << 13);
40 cpu_data->icache.entry_shift = 5; 40 cpu_data->icache.entry_shift = 5;
41 cpu_data->icache.entry_mask = 0x1fe0;
42 cpu_data->icache.sets = 256; 41 cpu_data->icache.sets = 256;
43 cpu_data->icache.ways = 1; 42 cpu_data->icache.ways = 1;
44 cpu_data->icache.linesz = L1_CACHE_BYTES; 43 cpu_data->icache.linesz = L1_CACHE_BYTES;
@@ -48,7 +47,6 @@ int __init detect_cpu_and_cache_system(void)
48 */ 47 */
49 cpu_data->dcache.way_incr = (1 << 14); 48 cpu_data->dcache.way_incr = (1 << 14);
50 cpu_data->dcache.entry_shift = 5; 49 cpu_data->dcache.entry_shift = 5;
51 cpu_data->dcache.entry_mask = 0x3fe0;
52 cpu_data->dcache.sets = 512; 50 cpu_data->dcache.sets = 512;
53 cpu_data->dcache.ways = 1; 51 cpu_data->dcache.ways = 1;
54 cpu_data->dcache.linesz = L1_CACHE_BYTES; 52 cpu_data->dcache.linesz = L1_CACHE_BYTES;
@@ -183,21 +181,26 @@ int __init detect_cpu_and_cache_system(void)
183 size = sizes[(cvr >> 20) & 0xf]; 181 size = sizes[(cvr >> 20) & 0xf];
184 cpu_data->icache.way_incr = (size >> 1); 182 cpu_data->icache.way_incr = (size >> 1);
185 cpu_data->icache.sets = (size >> 6); 183 cpu_data->icache.sets = (size >> 6);
186 cpu_data->icache.entry_mask = 184
187 (cpu_data->icache.way_incr - (1 << 5));
188 } 185 }
189 186
187 /* Setup the rest of the I-cache info */
188 cpu_data->icache.entry_mask = cpu_data->icache.way_incr -
189 cpu_data->icache.linesz;
190
190 cpu_data->icache.way_size = cpu_data->icache.sets * 191 cpu_data->icache.way_size = cpu_data->icache.sets *
191 cpu_data->icache.linesz; 192 cpu_data->icache.linesz;
192 193
194 /* And the rest of the D-cache */
193 if (cpu_data->dcache.ways > 1) { 195 if (cpu_data->dcache.ways > 1) {
194 size = sizes[(cvr >> 16) & 0xf]; 196 size = sizes[(cvr >> 16) & 0xf];
195 cpu_data->dcache.way_incr = (size >> 1); 197 cpu_data->dcache.way_incr = (size >> 1);
196 cpu_data->dcache.sets = (size >> 6); 198 cpu_data->dcache.sets = (size >> 6);
197 cpu_data->dcache.entry_mask =
198 (cpu_data->dcache.way_incr - (1 << 5));
199 } 199 }
200 200
201 cpu_data->dcache.entry_mask = cpu_data->dcache.way_incr -
202 cpu_data->dcache.linesz;
203
201 cpu_data->dcache.way_size = cpu_data->dcache.sets * 204 cpu_data->dcache.way_size = cpu_data->dcache.sets *
202 cpu_data->dcache.linesz; 205 cpu_data->dcache.linesz;
203 206
@@ -219,11 +222,14 @@ int __init detect_cpu_and_cache_system(void)
219 222
220 cpu_data->scache.way_incr = (1 << 16); 223 cpu_data->scache.way_incr = (1 << 16);
221 cpu_data->scache.entry_shift = 5; 224 cpu_data->scache.entry_shift = 5;
222 cpu_data->scache.entry_mask = 0xffe0;
223 cpu_data->scache.ways = 4; 225 cpu_data->scache.ways = 4;
224 cpu_data->scache.linesz = L1_CACHE_BYTES; 226 cpu_data->scache.linesz = L1_CACHE_BYTES;
227 cpu_data->scache.entry_mask =
228 (cpu_data->scache.way_incr - cpu_data->scache.linesz);
225 cpu_data->scache.sets = size / 229 cpu_data->scache.sets = size /
226 (cpu_data->scache.linesz * cpu_data->scache.ways); 230 (cpu_data->scache.linesz * cpu_data->scache.ways);
231 cpu_data->scache.way_size =
232 (cpu_data->scache.sets * cpu_data->scache.linesz);
227 } 233 }
228 234
229 return 0; 235 return 0;