aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh
diff options
context:
space:
mode:
authorPaul Mundt <lethal@linux-sh.org>2007-03-08 04:12:17 -0500
committerPaul Mundt <lethal@hera.kernel.org>2007-05-06 22:10:51 -0400
commit45ed285b54930767937deb0eaf718b1d08c3c475 (patch)
tree6132a0116f3c6370884d64928dbc2825b964f510 /arch/sh
parentfc31b80957a14a60513d953cc67a55519a2b09c7 (diff)
sh: speculative execution support for SH7780.
SH7780 has a speculative execution mode where it can speculatively perform an instruction fetch for subroutine returns, this allows it to be enabled. There are some various pitfalls associated with this mode, so it's left as depending on CONFIG_EXPERIMENTAL and not enabled by default. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/Kconfig10
-rw-r--r--arch/sh/kernel/cpu/init.c19
2 files changed, 29 insertions, 0 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 4d16d8917074..2715834f72be 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -366,6 +366,16 @@ config SH_STORE_QUEUES
366 Selecting this option will enable an in-kernel API for manipulating 366 Selecting this option will enable an in-kernel API for manipulating
367 the store queues integrated in the SH-4 processors. 367 the store queues integrated in the SH-4 processors.
368 368
369config SPECULATIVE_EXECUTION
370 bool "Speculative subroutine return"
371 depends on CPU_SUBTYPE_SH7780 && EXPERIMENTAL
372 help
373 This enables support for a speculative instruction fetch for
374 subroutine return. There are various pitfalls associated with
375 this, as outlined in the SH7780 hardware manual.
376
377 If unsure, say N.
378
369config CPU_HAS_INTEVT 379config CPU_HAS_INTEVT
370 bool 380 bool
371 381
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index 726acfcb9b77..6451ad630174 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -41,6 +41,23 @@ __setup("no" __stringify(x), x##_setup);
41onchip_setup(fpu); 41onchip_setup(fpu);
42onchip_setup(dsp); 42onchip_setup(dsp);
43 43
44#ifdef CONFIG_SPECULATIVE_EXECUTION
45#define CPUOPM 0xff2f0000
46#define CPUOPM_RABD (1 << 5)
47
48static void __init speculative_execution_init(void)
49{
50 /* Clear RABD */
51 ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
52
53 /* Flush the update */
54 (void)ctrl_inl(CPUOPM);
55 ctrl_barrier();
56}
57#else
58#define speculative_execution_init() do { } while (0)
59#endif
60
44/* 61/*
45 * Generic first-level cache init 62 * Generic first-level cache init
46 */ 63 */
@@ -261,4 +278,6 @@ asmlinkage void __init sh_cpu_init(void)
261 */ 278 */
262 ubc_wakeup(); 279 ubc_wakeup();
263#endif 280#endif
281
282 speculative_execution_init();
264} 283}