diff options
author | Jamie Lenehan <lenehan@twibble.org> | 2006-10-30 22:35:02 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2006-10-30 22:53:28 -0500 |
commit | bd71ab88deab3358241f22ed6c035c427aacc4e7 (patch) | |
tree | 632aa998acac7feb7df79684f4c382a6d6bf2294 /arch/sh | |
parent | 1f6c526c409ed7ecdd02469c46ab4b4a50ebec45 (diff) |
sh: Fix IPR-IRQ's for IRQ-chip change breakage.
The conversion from IPR-IRQ to IRQ-chip resulted in the
ipr data being allocated in a local variable in
make_ipr_irq - breaking anything using IPR interrupts.
This changes all of the callers of make_ipr_irq to
allocate a static structure containing the IPR data which
is then passed to make_ipr_irq. This removes the need for
make_ipr_irq to allocate any additional space for the IPR
information.
Signed-off-by: Jamie Lenehan <lenehan@twibble.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r-- | arch/sh/boards/renesas/hs7751rvoip/setup.c | 12 | ||||
-rw-r--r-- | arch/sh/boards/renesas/sh7710voipgw/setup.c | 105 | ||||
-rw-r--r-- | arch/sh/boards/se/7300/irq.c | 20 | ||||
-rw-r--r-- | arch/sh/boards/se/73180/irq.c | 47 | ||||
-rw-r--r-- | arch/sh/boards/se/7343/irq.c | 90 | ||||
-rw-r--r-- | arch/sh/boards/se/770x/irq.c | 80 | ||||
-rw-r--r-- | arch/sh/boards/se/7751/irq.c | 85 | ||||
-rw-r--r-- | arch/sh/boards/sh03/setup.c | 13 | ||||
-rw-r--r-- | arch/sh/boards/snapgear/setup.c | 12 | ||||
-rw-r--r-- | arch/sh/boards/titan/setup.c | 12 | ||||
-rw-r--r-- | arch/sh/drivers/dma/dma-sh.c | 42 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/irq/ipr.c | 106 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/irq/pint.c | 8 |
13 files changed, 331 insertions, 301 deletions
diff --git a/arch/sh/boards/renesas/hs7751rvoip/setup.c b/arch/sh/boards/renesas/hs7751rvoip/setup.c index 1d997ffd7931..f7d0e304d899 100644 --- a/arch/sh/boards/renesas/hs7751rvoip/setup.c +++ b/arch/sh/boards/renesas/hs7751rvoip/setup.c | |||
@@ -15,12 +15,16 @@ | |||
15 | #include <asm/io.h> | 15 | #include <asm/io.h> |
16 | #include <asm/machvec.h> | 16 | #include <asm/machvec.h> |
17 | 17 | ||
18 | static void __init hs7751rvoip_init_irq(void) | 18 | static struct ipr_data hs77501rvoip_ipr_map[] = { |
19 | { | ||
20 | #if defined(CONFIG_HS7751RVOIP_CODEC) | 19 | #if defined(CONFIG_HS7751RVOIP_CODEC) |
21 | make_ipr_irq(DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); | 20 | { DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, |
22 | make_ipr_irq(DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); | 21 | { DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, |
23 | #endif | 22 | #endif |
23 | }; | ||
24 | |||
25 | static void __init hs7751rvoip_init_irq(void) | ||
26 | { | ||
27 | make_ipr_irq(hs77501rvoip_ipr_map, ARRAY_SIZE(hs77501rvoip_ipr_map)); | ||
24 | 28 | ||
25 | init_hs7751rvoip_IRQ(); | 29 | init_hs7751rvoip_IRQ(); |
26 | } | 30 | } |
diff --git a/arch/sh/boards/renesas/sh7710voipgw/setup.c b/arch/sh/boards/renesas/sh7710voipgw/setup.c index e57e7afab8c6..180810b12107 100644 --- a/arch/sh/boards/renesas/sh7710voipgw/setup.c +++ b/arch/sh/boards/renesas/sh7710voipgw/setup.c | |||
@@ -13,6 +13,51 @@ | |||
13 | #include <asm/io.h> | 13 | #include <asm/io.h> |
14 | #include <asm/irq.h> | 14 | #include <asm/irq.h> |
15 | 15 | ||
16 | static struct ipr_data sh7710voipgw_ipr_map[] = { | ||
17 | { TIMER2_IRQ, TIMER2_IPR_ADDR, TIMER2_IPR_POS, TIMER2_PRIORITY }, | ||
18 | { WDT_IRQ, WDT_IPR_ADDR, WDT_IPR_POS, WDT_PRIORITY }, | ||
19 | |||
20 | /* SCIF0 */ | ||
21 | { SCIF0_ERI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, | ||
22 | { SCIF0_RXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, | ||
23 | { SCIF0_BRI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, | ||
24 | { SCIF0_TXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, | ||
25 | |||
26 | /* DMAC-1 */ | ||
27 | { DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, | ||
28 | { DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, | ||
29 | { DMTE2_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, | ||
30 | { DMTE3_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, | ||
31 | |||
32 | /* DMAC-2 */ | ||
33 | { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, | ||
34 | { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, | ||
35 | |||
36 | /* IPSEC */ | ||
37 | { IPSEC_IRQ, IPSEC_IPR_ADDR, IPSEC_IPR_POS, IPSEC_PRIORITY }, | ||
38 | |||
39 | /* EDMAC */ | ||
40 | { EDMAC0_IRQ, EDMAC0_IPR_ADDR, EDMAC0_IPR_POS, EDMAC0_PRIORITY }, | ||
41 | { EDMAC1_IRQ, EDMAC1_IPR_ADDR, EDMAC1_IPR_POS, EDMAC1_PRIORITY }, | ||
42 | { EDMAC2_IRQ, EDMAC2_IPR_ADDR, EDMAC2_IPR_POS, EDMAC2_PRIORITY }, | ||
43 | |||
44 | /* SIOF0 */ | ||
45 | { SIOF0_ERI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, | ||
46 | { SIOF0_TXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, | ||
47 | { SIOF0_RXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, | ||
48 | { SIOF0_CCI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, | ||
49 | |||
50 | /* SIOF1 */ | ||
51 | { SIOF1_ERI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY }, | ||
52 | { SIOF1_TXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY }, | ||
53 | { SIOF1_RXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY }, | ||
54 | { SIOF1_CCI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY }, | ||
55 | |||
56 | /* SLIC IRQ's */ | ||
57 | { IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY }, | ||
58 | { IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY }, | ||
59 | }; | ||
60 | |||
16 | /* | 61 | /* |
17 | * Initialize IRQ setting | 62 | * Initialize IRQ setting |
18 | */ | 63 | */ |
@@ -37,65 +82,7 @@ static void __init sh7710voipgw_init_irq(void) | |||
37 | */ | 82 | */ |
38 | ctrl_outw(0x2aa, INTC_ICR1); | 83 | ctrl_outw(0x2aa, INTC_ICR1); |
39 | 84 | ||
40 | /* Now make IPR interrupts */ | 85 | make_ipr_irq(sh7710voipgw_ipr_map, ARRAY_SIZE(sh7710voipgw_ipr_map)); |
41 | make_ipr_irq(TIMER2_IRQ, TIMER2_IPR_ADDR, | ||
42 | TIMER2_IPR_POS, TIMER2_PRIORITY); | ||
43 | make_ipr_irq(WDT_IRQ, WDT_IPR_ADDR, WDT_IPR_POS, WDT_PRIORITY); | ||
44 | |||
45 | /* SCIF0 */ | ||
46 | make_ipr_irq(SCIF0_ERI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, | ||
47 | SCIF0_PRIORITY); | ||
48 | make_ipr_irq(SCIF0_RXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, | ||
49 | SCIF0_PRIORITY); | ||
50 | make_ipr_irq(SCIF0_BRI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, | ||
51 | SCIF0_PRIORITY); | ||
52 | make_ipr_irq(SCIF0_TXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, | ||
53 | SCIF0_PRIORITY); | ||
54 | |||
55 | /* DMAC-1 */ | ||
56 | make_ipr_irq(DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); | ||
57 | make_ipr_irq(DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); | ||
58 | make_ipr_irq(DMTE2_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); | ||
59 | make_ipr_irq(DMTE3_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); | ||
60 | |||
61 | /* DMAC-2 */ | ||
62 | make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY); | ||
63 | make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY); | ||
64 | |||
65 | /* IPSEC */ | ||
66 | make_ipr_irq(IPSEC_IRQ, IPSEC_IPR_ADDR, IPSEC_IPR_POS, IPSEC_PRIORITY); | ||
67 | |||
68 | /* EDMAC */ | ||
69 | make_ipr_irq(EDMAC0_IRQ, EDMAC0_IPR_ADDR, EDMAC0_IPR_POS, | ||
70 | EDMAC0_PRIORITY); | ||
71 | make_ipr_irq(EDMAC1_IRQ, EDMAC1_IPR_ADDR, EDMAC1_IPR_POS, | ||
72 | EDMAC1_PRIORITY); | ||
73 | make_ipr_irq(EDMAC2_IRQ, EDMAC2_IPR_ADDR, EDMAC2_IPR_POS, | ||
74 | EDMAC2_PRIORITY); | ||
75 | |||
76 | /* SIOF0 */ | ||
77 | make_ipr_irq(SIOF0_ERI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, | ||
78 | SIOF0_PRIORITY); | ||
79 | make_ipr_irq(SIOF0_TXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, | ||
80 | SIOF0_PRIORITY); | ||
81 | make_ipr_irq(SIOF0_RXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, | ||
82 | SIOF0_PRIORITY); | ||
83 | make_ipr_irq(SIOF0_CCI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, | ||
84 | SIOF0_PRIORITY); | ||
85 | |||
86 | /* SIOF1 */ | ||
87 | make_ipr_irq(SIOF1_ERI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, | ||
88 | SIOF1_PRIORITY); | ||
89 | make_ipr_irq(SIOF1_TXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, | ||
90 | SIOF1_PRIORITY); | ||
91 | make_ipr_irq(SIOF1_RXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, | ||
92 | SIOF1_PRIORITY); | ||
93 | make_ipr_irq(SIOF1_CCI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, | ||
94 | SIOF1_PRIORITY); | ||
95 | |||
96 | /* SLIC IRQ's */ | ||
97 | make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY); | ||
98 | make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY); | ||
99 | } | 86 | } |
100 | 87 | ||
101 | /* | 88 | /* |
diff --git a/arch/sh/boards/se/7300/irq.c b/arch/sh/boards/se/7300/irq.c index ad1034f98a29..1279d776d60f 100644 --- a/arch/sh/boards/se/7300/irq.c +++ b/arch/sh/boards/se/7300/irq.c | |||
@@ -13,6 +13,17 @@ | |||
13 | #include <asm/io.h> | 13 | #include <asm/io.h> |
14 | #include <asm/se7300.h> | 14 | #include <asm/se7300.h> |
15 | 15 | ||
16 | static struct ipr_data se7300_ipr_map[] = { | ||
17 | /* PC_IRQ[0-3] -> IRQ0 (32) */ | ||
18 | { IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, 0x0f - IRQ0_IRQ }, | ||
19 | /* A_IRQ[0-3] -> IRQ1 (33) */ | ||
20 | { IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, 0x0f - IRQ1_IRQ }, | ||
21 | { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, | ||
22 | { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, | ||
23 | { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, | ||
24 | { VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, | ||
25 | }; | ||
26 | |||
16 | /* | 27 | /* |
17 | * Initialize IRQ setting | 28 | * Initialize IRQ setting |
18 | */ | 29 | */ |
@@ -23,14 +34,7 @@ init_7300se_IRQ(void) | |||
23 | ctrl_outw(0xa000, INTC_ICR1); /* IRQ mode; IRQ0,1 enable. */ | 34 | ctrl_outw(0xa000, INTC_ICR1); /* IRQ mode; IRQ0,1 enable. */ |
24 | ctrl_outw(0x0000, PORT_PFCR); /* use F for IRQ[3:0] and SIU. */ | 35 | ctrl_outw(0x0000, PORT_PFCR); /* use F for IRQ[3:0] and SIU. */ |
25 | 36 | ||
26 | /* PC_IRQ[0-3] -> IRQ0 (32) */ | 37 | make_ipr_irq(se7300_ipr_map, ARRAY_SIZE(se7300_ipr_map)); |
27 | make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, 0x0f - IRQ0_IRQ); | ||
28 | /* A_IRQ[0-3] -> IRQ1 (33) */ | ||
29 | make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, 0x0f - IRQ1_IRQ); | ||
30 | make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY); | ||
31 | make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); | ||
32 | make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); | ||
33 | make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); | ||
34 | 38 | ||
35 | ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ | 39 | ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ |
36 | } | 40 | } |
diff --git a/arch/sh/boards/se/73180/irq.c b/arch/sh/boards/se/73180/irq.c index 2c62b8ea350e..e7200c56bb45 100644 --- a/arch/sh/boards/se/73180/irq.c +++ b/arch/sh/boards/se/73180/irq.c | |||
@@ -87,13 +87,38 @@ shmse_irq_demux(int irq) | |||
87 | return irq; | 87 | return irq; |
88 | } | 88 | } |
89 | 89 | ||
90 | static struct ipr_data se73180_siof0_ipr_map[] = { | ||
91 | { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, | ||
92 | }; | ||
93 | static struct ipr_data se73180_vpu_ipr_map[] = { | ||
94 | { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 }, | ||
95 | }; | ||
96 | static struct ipr_data se73180_other_ipr_map[] = { | ||
97 | { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, | ||
98 | { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, | ||
99 | { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, | ||
100 | { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, | ||
101 | { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, | ||
102 | { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, | ||
103 | { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, | ||
104 | { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, | ||
105 | { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY }, | ||
106 | |||
107 | /* VIO interrupt */ | ||
108 | { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, | ||
109 | { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, | ||
110 | { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, | ||
111 | |||
112 | { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY }, | ||
113 | }; | ||
114 | |||
90 | /* | 115 | /* |
91 | * Initialize IRQ setting | 116 | * Initialize IRQ setting |
92 | */ | 117 | */ |
93 | void __init | 118 | void __init |
94 | init_73180se_IRQ(void) | 119 | init_73180se_IRQ(void) |
95 | { | 120 | { |
96 | make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY); | 121 | make_ipr_irq(se73180_siof0_ipr_map, ARRAY_SIZE(se73180_siof0_ipr_map)); |
97 | 122 | ||
98 | ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */ | 123 | ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */ |
99 | ctrl_outw(0x2000, 0xb07fffec); /* mrshpc irq enable */ | 124 | ctrl_outw(0x2000, 0xb07fffec); /* mrshpc irq enable */ |
@@ -101,27 +126,11 @@ init_73180se_IRQ(void) | |||
101 | ctrl_outw(2 << ((7 - 5) * 2), INTC_ICR1); /* low-level irq */ | 126 | ctrl_outw(2 << ((7 - 5) * 2), INTC_ICR1); /* low-level irq */ |
102 | make_intreq_irq(10); | 127 | make_intreq_irq(10); |
103 | 128 | ||
104 | make_ipr_irq(VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8); | 129 | make_ipr_irq(se73180_vpu_ipr_map, ARRAY_SIZE(se73180_vpu_ipr_map)); |
105 | 130 | ||
106 | ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */ | 131 | ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */ |
107 | 132 | ||
108 | make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); | 133 | make_ipr_irq(se73180_other_ipr_map, ARRAY_SIZE(se73180_other_ipr_map)); |
109 | make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); | ||
110 | make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY); | ||
111 | make_ipr_irq(IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY); | ||
112 | make_ipr_irq(IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, | ||
113 | IIC0_PRIORITY); | ||
114 | make_ipr_irq(IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, | ||
115 | IIC0_PRIORITY); | ||
116 | make_ipr_irq(IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY); | ||
117 | make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY); | ||
118 | make_ipr_irq(SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY); | ||
119 | |||
120 | /* VIO interrupt */ | ||
121 | make_ipr_irq(CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); | ||
122 | make_ipr_irq(BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); | ||
123 | make_ipr_irq(VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); | ||
124 | 134 | ||
125 | make_ipr_irq(LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY); | ||
126 | ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ | 135 | ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ |
127 | } | 136 | } |
diff --git a/arch/sh/boards/se/7343/irq.c b/arch/sh/boards/se/7343/irq.c index 288b62f59419..360153ecc55b 100644 --- a/arch/sh/boards/se/7343/irq.c +++ b/arch/sh/boards/se/7343/irq.c | |||
@@ -102,6 +102,51 @@ shmse_irq_demux(int irq) | |||
102 | static struct irqaction irq5 = { no_action, 0, CPU_MASK_NONE, "IRQ5-cascade", | 102 | static struct irqaction irq5 = { no_action, 0, CPU_MASK_NONE, "IRQ5-cascade", |
103 | NULL, NULL}; | 103 | NULL, NULL}; |
104 | 104 | ||
105 | static struct ipr_data se7343_irq5_ipr_map[] = { | ||
106 | { IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY }, | ||
107 | }; | ||
108 | static struct ipr_data se7343_siof0_vpu_ipr_map[] = { | ||
109 | { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, | ||
110 | { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 }, | ||
111 | }; | ||
112 | static struct ipr_data se7343_other_ipr_map[] = { | ||
113 | { DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, | ||
114 | { DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, | ||
115 | { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, | ||
116 | { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, | ||
117 | { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, | ||
118 | { DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, | ||
119 | |||
120 | /* I2C block */ | ||
121 | { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, | ||
122 | { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, | ||
123 | { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, | ||
124 | { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, | ||
125 | |||
126 | { IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY }, | ||
127 | { IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY }, | ||
128 | { IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY }, | ||
129 | { IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY }, | ||
130 | |||
131 | /* SIOF */ | ||
132 | { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, | ||
133 | |||
134 | /* SIU */ | ||
135 | { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY }, | ||
136 | |||
137 | /* VIO interrupt */ | ||
138 | { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, | ||
139 | { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, | ||
140 | { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, | ||
141 | |||
142 | /*MFI interrupt*/ | ||
143 | |||
144 | { MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY }, | ||
145 | |||
146 | /* LCD controller */ | ||
147 | { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY }, | ||
148 | }; | ||
149 | |||
105 | /* | 150 | /* |
106 | * Initialize IRQ setting | 151 | * Initialize IRQ setting |
107 | */ | 152 | */ |
@@ -138,54 +183,17 @@ init_7343se_IRQ(void) | |||
138 | /* Setup all external interrupts to be active low */ | 183 | /* Setup all external interrupts to be active low */ |
139 | ctrl_outw(0xaaaa, INTC_ICR1); | 184 | ctrl_outw(0xaaaa, INTC_ICR1); |
140 | 185 | ||
141 | make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY); | 186 | make_ipr_irq(se7343_irq5_ipr_map, ARRAY_SIZE(se7343_irq5_ipr_map)); |
187 | |||
142 | setup_irq(IRQ5_IRQ, &irq5); | 188 | setup_irq(IRQ5_IRQ, &irq5); |
143 | /* Set port control to use IRQ5 */ | 189 | /* Set port control to use IRQ5 */ |
144 | *(u16 *)0xA4050108 &= ~0xc; | 190 | *(u16 *)0xA4050108 &= ~0xc; |
145 | 191 | ||
146 | make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY); | 192 | make_ipr_irq(se7343_siof0_vpu_ipr_map, ARRAY_SIZE(se7343_siof0_vpu_ipr_map)); |
147 | make_ipr_irq(VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8); | ||
148 | 193 | ||
149 | ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */ | 194 | ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */ |
150 | 195 | ||
151 | make_ipr_irq(DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); | 196 | make_ipr_irq(se7343_other_ipr_map, ARRAY_SIZE(se7343_other_ipr_map)); |
152 | make_ipr_irq(DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); | ||
153 | make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); | ||
154 | make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); | ||
155 | make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY); | ||
156 | make_ipr_irq(DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY); | ||
157 | |||
158 | /* I2C block */ | ||
159 | make_ipr_irq(IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY); | ||
160 | make_ipr_irq(IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, | ||
161 | IIC0_PRIORITY); | ||
162 | make_ipr_irq(IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, | ||
163 | IIC0_PRIORITY); | ||
164 | make_ipr_irq(IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY); | ||
165 | |||
166 | make_ipr_irq(IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY); | ||
167 | make_ipr_irq(IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, | ||
168 | IIC1_PRIORITY); | ||
169 | make_ipr_irq(IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, | ||
170 | IIC1_PRIORITY); | ||
171 | make_ipr_irq(IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY); | ||
172 | |||
173 | /* SIOF */ | ||
174 | make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY); | ||
175 | 197 | ||
176 | /* SIU */ | ||
177 | make_ipr_irq(SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY); | ||
178 | |||
179 | /* VIO interrupt */ | ||
180 | make_ipr_irq(CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); | ||
181 | make_ipr_irq(BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); | ||
182 | make_ipr_irq(VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); | ||
183 | |||
184 | /*MFI interrupt*/ | ||
185 | |||
186 | make_ipr_irq(MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY); | ||
187 | |||
188 | /* LCD controller */ | ||
189 | make_ipr_irq(LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY); | ||
190 | ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ | 198 | ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ |
191 | } | 199 | } |
diff --git a/arch/sh/boards/se/770x/irq.c b/arch/sh/boards/se/770x/irq.c index cff6700bbafd..fcd7cd7fa05f 100644 --- a/arch/sh/boards/se/770x/irq.c +++ b/arch/sh/boards/se/770x/irq.c | |||
@@ -13,6 +13,48 @@ | |||
13 | #include <asm/io.h> | 13 | #include <asm/io.h> |
14 | #include <asm/se.h> | 14 | #include <asm/se.h> |
15 | 15 | ||
16 | static struct ipr_data se770x_ipr_map[] = { | ||
17 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) | ||
18 | /* This is default value */ | ||
19 | { 0xf-0x2, BCR_ILCRA, 2, 0x2 }, | ||
20 | { 0xf-0xa, BCR_ILCRA, 1, 0xa }, | ||
21 | { 0xf-0x5, BCR_ILCRB, 0, 0x5 }, | ||
22 | { 0xf-0x8, BCR_ILCRC, 1, 0x8 }, | ||
23 | { 0xf-0xc, BCR_ILCRC, 0, 0xc }, | ||
24 | { 0xf-0xe, BCR_ILCRD, 3, 0xe }, | ||
25 | { 0xf-0x3, BCR_ILCRD, 1, 0x3 }, /* LAN */ | ||
26 | { 0xf-0xd, BCR_ILCRE, 2, 0xd }, | ||
27 | { 0xf-0x9, BCR_ILCRE, 1, 0x9 }, | ||
28 | { 0xf-0x1, BCR_ILCRE, 0, 0x1 }, | ||
29 | { 0xf-0xf, BCR_ILCRF, 3, 0xf }, | ||
30 | { 0xf-0xb, BCR_ILCRF, 1, 0xb }, | ||
31 | { 0xf-0x7, BCR_ILCRG, 3, 0x7 }, | ||
32 | { 0xf-0x6, BCR_ILCRG, 2, 0x6 }, | ||
33 | { 0xf-0x4, BCR_ILCRG, 1, 0x4 }, | ||
34 | #else | ||
35 | { 14, BCR_ILCRA, 2, 0x0f-14 }, | ||
36 | { 12, BCR_ILCRA, 1, 0x0f-12 }, | ||
37 | { 8, BCR_ILCRB, 1, 0x0f- 8 }, | ||
38 | { 6, BCR_ILCRC, 3, 0x0f- 6 }, | ||
39 | { 5, BCR_ILCRC, 2, 0x0f- 5 }, | ||
40 | { 4, BCR_ILCRC, 1, 0x0f- 4 }, | ||
41 | { 3, BCR_ILCRC, 0, 0x0f- 3 }, | ||
42 | { 1, BCR_ILCRD, 3, 0x0f- 1 }, | ||
43 | |||
44 | { 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */ | ||
45 | |||
46 | { 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */ | ||
47 | { 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */ | ||
48 | { 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */ | ||
49 | { 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */ | ||
50 | |||
51 | /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */ | ||
52 | /* NOTE: #2 and #13 are not used on PC */ | ||
53 | { 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */ | ||
54 | { 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */ | ||
55 | #endif | ||
56 | }; | ||
57 | |||
16 | /* | 58 | /* |
17 | * Initialize IRQ setting | 59 | * Initialize IRQ setting |
18 | */ | 60 | */ |
@@ -38,42 +80,6 @@ void __init init_se_IRQ(void) | |||
38 | ctrl_outw(0, BCR_ILCRE); | 80 | ctrl_outw(0, BCR_ILCRE); |
39 | ctrl_outw(0, BCR_ILCRF); | 81 | ctrl_outw(0, BCR_ILCRF); |
40 | ctrl_outw(0, BCR_ILCRG); | 82 | ctrl_outw(0, BCR_ILCRG); |
41 | /* This is default value */ | ||
42 | make_ipr_irq(0xf-0x2, BCR_ILCRA, 2, 0x2); | ||
43 | make_ipr_irq(0xf-0xa, BCR_ILCRA, 1, 0xa); | ||
44 | make_ipr_irq(0xf-0x5, BCR_ILCRB, 0, 0x5); | ||
45 | make_ipr_irq(0xf-0x8, BCR_ILCRC, 1, 0x8); | ||
46 | make_ipr_irq(0xf-0xc, BCR_ILCRC, 0, 0xc); | ||
47 | make_ipr_irq(0xf-0xe, BCR_ILCRD, 3, 0xe); | ||
48 | make_ipr_irq(0xf-0x3, BCR_ILCRD, 1, 0x3); /* LAN */ | ||
49 | make_ipr_irq(0xf-0xd, BCR_ILCRE, 2, 0xd); | ||
50 | make_ipr_irq(0xf-0x9, BCR_ILCRE, 1, 0x9); | ||
51 | make_ipr_irq(0xf-0x1, BCR_ILCRE, 0, 0x1); | ||
52 | make_ipr_irq(0xf-0xf, BCR_ILCRF, 3, 0xf); | ||
53 | make_ipr_irq(0xf-0xb, BCR_ILCRF, 1, 0xb); | ||
54 | make_ipr_irq(0xf-0x7, BCR_ILCRG, 3, 0x7); | ||
55 | make_ipr_irq(0xf-0x6, BCR_ILCRG, 2, 0x6); | ||
56 | make_ipr_irq(0xf-0x4, BCR_ILCRG, 1, 0x4); | ||
57 | #else | ||
58 | make_ipr_irq(14, BCR_ILCRA, 2, 0x0f-14); | ||
59 | make_ipr_irq(12, BCR_ILCRA, 1, 0x0f-12); | ||
60 | make_ipr_irq( 8, BCR_ILCRB, 1, 0x0f- 8); | ||
61 | make_ipr_irq( 6, BCR_ILCRC, 3, 0x0f- 6); | ||
62 | make_ipr_irq( 5, BCR_ILCRC, 2, 0x0f- 5); | ||
63 | make_ipr_irq( 4, BCR_ILCRC, 1, 0x0f- 4); | ||
64 | make_ipr_irq( 3, BCR_ILCRC, 0, 0x0f- 3); | ||
65 | make_ipr_irq( 1, BCR_ILCRD, 3, 0x0f- 1); | ||
66 | |||
67 | make_ipr_irq(10, BCR_ILCRD, 1, 0x0f-10); /* LAN */ | ||
68 | |||
69 | make_ipr_irq( 0, BCR_ILCRE, 3, 0x0f- 0); /* PCIRQ3 */ | ||
70 | make_ipr_irq(11, BCR_ILCRE, 2, 0x0f-11); /* PCIRQ2 */ | ||
71 | make_ipr_irq( 9, BCR_ILCRE, 1, 0x0f- 9); /* PCIRQ1 */ | ||
72 | make_ipr_irq( 7, BCR_ILCRE, 0, 0x0f- 7); /* PCIRQ0 */ | ||
73 | |||
74 | /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */ | ||
75 | /* NOTE: #2 and #13 are not used on PC */ | ||
76 | make_ipr_irq(13, BCR_ILCRG, 1, 0x0f-13); /* SLOTIRQ2 */ | ||
77 | make_ipr_irq( 2, BCR_ILCRG, 0, 0x0f- 2); /* SLOTIRQ1 */ | ||
78 | #endif | 83 | #endif |
84 | make_ipr_irq(se770x_ipr_map, ARRAY_SIZE(se770x_ipr_map)); | ||
79 | } | 85 | } |
diff --git a/arch/sh/boards/se/7751/irq.c b/arch/sh/boards/se/7751/irq.c index c607b0a48479..e4c63a48296c 100644 --- a/arch/sh/boards/se/7751/irq.c +++ b/arch/sh/boards/se/7751/irq.c | |||
@@ -14,53 +14,50 @@ | |||
14 | #include <asm/irq.h> | 14 | #include <asm/irq.h> |
15 | #include <asm/se7751.h> | 15 | #include <asm/se7751.h> |
16 | 16 | ||
17 | /* | 17 | static struct ipr_data se7751_ipr_map[] = { |
18 | * Initialize IRQ setting | ||
19 | */ | ||
20 | void __init init_7751se_IRQ(void) | ||
21 | { | ||
22 | |||
23 | /* Leave old Solution Engine code in for reference. */ | 18 | /* Leave old Solution Engine code in for reference. */ |
24 | #if defined(CONFIG_SH_SOLUTION_ENGINE) | 19 | #if defined(CONFIG_SH_SOLUTION_ENGINE) |
25 | /* | 20 | /* |
26 | * Super I/O (Just mimic PC): | 21 | * Super I/O (Just mimic PC): |
27 | * 1: keyboard | 22 | * 1: keyboard |
28 | * 3: serial 0 | 23 | * 3: serial 0 |
29 | * 4: serial 1 | 24 | * 4: serial 1 |
30 | * 5: printer | 25 | * 5: printer |
31 | * 6: floppy | 26 | * 6: floppy |
32 | * 8: rtc | 27 | * 8: rtc |
33 | * 12: mouse | 28 | * 12: mouse |
34 | * 14: ide0 | 29 | * 14: ide0 |
35 | */ | 30 | */ |
36 | make_ipr_irq(14, BCR_ILCRA, 2, 0x0f-14); | 31 | { 14, BCR_ILCRA, 2, 0x0f-14 }, |
37 | make_ipr_irq(12, BCR_ILCRA, 1, 0x0f-12); | 32 | { 12, BCR_ILCRA, 1, 0x0f-12 }, |
38 | make_ipr_irq( 8, BCR_ILCRB, 1, 0x0f- 8); | 33 | { 8, BCR_ILCRB, 1, 0x0f- 8 }, |
39 | make_ipr_irq( 6, BCR_ILCRC, 3, 0x0f- 6); | 34 | { 6, BCR_ILCRC, 3, 0x0f- 6 }, |
40 | make_ipr_irq( 5, BCR_ILCRC, 2, 0x0f- 5); | 35 | { 5, BCR_ILCRC, 2, 0x0f- 5 }, |
41 | make_ipr_irq( 4, BCR_ILCRC, 1, 0x0f- 4); | 36 | { 4, BCR_ILCRC, 1, 0x0f- 4 }, |
42 | make_ipr_irq( 3, BCR_ILCRC, 0, 0x0f- 3); | 37 | { 3, BCR_ILCRC, 0, 0x0f- 3 }, |
43 | make_ipr_irq( 1, BCR_ILCRD, 3, 0x0f- 1); | 38 | { 1, BCR_ILCRD, 3, 0x0f- 1 }, |
44 | 39 | ||
45 | make_ipr_irq(10, BCR_ILCRD, 1, 0x0f-10); /* LAN */ | 40 | { 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */ |
46 | 41 | ||
47 | make_ipr_irq( 0, BCR_ILCRE, 3, 0x0f- 0); /* PCIRQ3 */ | 42 | { 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */ |
48 | make_ipr_irq(11, BCR_ILCRE, 2, 0x0f-11); /* PCIRQ2 */ | 43 | { 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */ |
49 | make_ipr_irq( 9, BCR_ILCRE, 1, 0x0f- 9); /* PCIRQ1 */ | 44 | { 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */ |
50 | make_ipr_irq( 7, BCR_ILCRE, 0, 0x0f- 7); /* PCIRQ0 */ | 45 | { 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */ |
51 | 46 | ||
52 | /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */ | 47 | /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */ |
53 | /* NOTE: #2 and #13 are not used on PC */ | 48 | /* NOTE: #2 and #13 are not used on PC */ |
54 | make_ipr_irq(13, BCR_ILCRG, 1, 0x0f-13); /* SLOTIRQ2 */ | 49 | { 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */ |
55 | make_ipr_irq( 2, BCR_ILCRG, 0, 0x0f- 2); /* SLOTIRQ1 */ | 50 | { 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */ |
56 | |||
57 | #elif defined(CONFIG_SH_7751_SOLUTION_ENGINE) | 51 | #elif defined(CONFIG_SH_7751_SOLUTION_ENGINE) |
58 | 52 | { 13, BCR_ILCRD, 3, 2 }, | |
59 | make_ipr_irq(13, BCR_ILCRD, 3, 2); | 53 | /* Add additional entries here as drivers are added and tested. */ |
60 | |||
61 | /* Add additional calls to make_ipr_irq() as drivers are added | ||
62 | * and tested. | ||
63 | */ | ||
64 | #endif | 54 | #endif |
55 | }; | ||
65 | 56 | ||
57 | /* | ||
58 | * Initialize IRQ setting | ||
59 | */ | ||
60 | void __init init_7751se_IRQ(void) | ||
61 | { | ||
62 | make_ipr_irq(se7751_ipr_map, ARRAY_SIZE(se7751_ipr_map)); | ||
66 | } | 63 | } |
diff --git a/arch/sh/boards/sh03/setup.c b/arch/sh/boards/sh03/setup.c index 137e2ba9243e..5ad1e19771be 100644 --- a/arch/sh/boards/sh03/setup.c +++ b/arch/sh/boards/sh03/setup.c | |||
@@ -14,14 +14,17 @@ | |||
14 | #include <asm/sh03/sh03.h> | 14 | #include <asm/sh03/sh03.h> |
15 | #include <asm/addrspace.h> | 15 | #include <asm/addrspace.h> |
16 | 16 | ||
17 | static struct ipr_data sh03_ipr_map[] = { | ||
18 | { IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY }, | ||
19 | { IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY }, | ||
20 | { IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY }, | ||
21 | { IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY }, | ||
22 | }; | ||
23 | |||
17 | static void __init init_sh03_IRQ(void) | 24 | static void __init init_sh03_IRQ(void) |
18 | { | 25 | { |
19 | ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); | 26 | ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); |
20 | 27 | make_ipr_irq(sh03_ipr_map, ARRAY_SIZE(sh03_ipr_map)); | |
21 | make_ipr_irq(IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY); | ||
22 | make_ipr_irq(IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY); | ||
23 | make_ipr_irq(IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY); | ||
24 | make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY); | ||
25 | } | 28 | } |
26 | 29 | ||
27 | extern void *cf_io_base; | 30 | extern void *cf_io_base; |
diff --git a/arch/sh/boards/snapgear/setup.c b/arch/sh/boards/snapgear/setup.c index 540d0bf16446..650fb3645947 100644 --- a/arch/sh/boards/snapgear/setup.c +++ b/arch/sh/boards/snapgear/setup.c | |||
@@ -68,6 +68,13 @@ module_init(eraseconfig_init); | |||
68 | * IRL3 = crypto | 68 | * IRL3 = crypto |
69 | */ | 69 | */ |
70 | 70 | ||
71 | static struct ipr_data snapgear_ipr_map[] = { | ||
72 | make_ipr_irq(IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY); | ||
73 | make_ipr_irq(IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY); | ||
74 | make_ipr_irq(IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY); | ||
75 | make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY); | ||
76 | }; | ||
77 | |||
71 | static void __init init_snapgear_IRQ(void) | 78 | static void __init init_snapgear_IRQ(void) |
72 | { | 79 | { |
73 | /* enable individual interrupt mode for externals */ | 80 | /* enable individual interrupt mode for externals */ |
@@ -75,10 +82,7 @@ static void __init init_snapgear_IRQ(void) | |||
75 | 82 | ||
76 | printk("Setup SnapGear IRQ/IPR ...\n"); | 83 | printk("Setup SnapGear IRQ/IPR ...\n"); |
77 | 84 | ||
78 | make_ipr_irq(IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY); | 85 | make_ipr_irq(snapgear_ipr_map, ARRAY_SIZE(snapgear_ipr_map)); |
79 | make_ipr_irq(IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY); | ||
80 | make_ipr_irq(IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY); | ||
81 | make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY); | ||
82 | } | 86 | } |
83 | 87 | ||
84 | /* | 88 | /* |
diff --git a/arch/sh/boards/titan/setup.c b/arch/sh/boards/titan/setup.c index 52b66d8b8d2a..a6046d93758b 100644 --- a/arch/sh/boards/titan/setup.c +++ b/arch/sh/boards/titan/setup.c | |||
@@ -9,15 +9,19 @@ | |||
9 | 9 | ||
10 | extern void __init pcibios_init_platform(void); | 10 | extern void __init pcibios_init_platform(void); |
11 | 11 | ||
12 | static struct ipr_data titan_ipr_map[] = { | ||
13 | { TITAN_IRQ_WAN, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY }, | ||
14 | { TITAN_IRQ_LAN, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY }, | ||
15 | { TITAN_IRQ_MPCIA, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY }, | ||
16 | { TITAN_IRQ_USB, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY }, | ||
17 | }; | ||
18 | |||
12 | static void __init init_titan_irq(void) | 19 | static void __init init_titan_irq(void) |
13 | { | 20 | { |
14 | /* enable individual interrupt mode for externals */ | 21 | /* enable individual interrupt mode for externals */ |
15 | ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); | 22 | ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); |
16 | 23 | ||
17 | make_ipr_irq( TITAN_IRQ_WAN, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY); /* PCIRQ0 */ | 24 | make_ipr_irq(titan_ipr_map, ARRAY_SIZE(titan_ipr_map)); |
18 | make_ipr_irq( TITAN_IRQ_LAN, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY); /* PCIRQ1 */ | ||
19 | make_ipr_irq( TITAN_IRQ_MPCIA, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY); /* PCIRQ2 */ | ||
20 | make_ipr_irq( TITAN_IRQ_USB, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY); /* PCIRQ3 */ | ||
21 | } | 25 | } |
22 | 26 | ||
23 | struct sh_machine_vector mv_titan __initmv = { | 27 | struct sh_machine_vector mv_titan __initmv = { |
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c index d8ece20bb2cf..660786013350 100644 --- a/arch/sh/drivers/dma/dma-sh.c +++ b/arch/sh/drivers/dma/dma-sh.c | |||
@@ -19,23 +19,34 @@ | |||
19 | #include <asm/io.h> | 19 | #include <asm/io.h> |
20 | #include "dma-sh.h" | 20 | #include "dma-sh.h" |
21 | 21 | ||
22 | static inline unsigned int get_dmte_irq(unsigned int chan) | ||
23 | { | ||
24 | unsigned int irq = 0; | ||
25 | 22 | ||
23 | |||
24 | #ifdef CONFIG_CPU_SH4 | ||
25 | static struct ipr_data dmae_ipr_map[] = { | ||
26 | { DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, | ||
27 | }; | ||
28 | #endif | ||
29 | static struct ipr_data dmte_ipr_map[] = { | ||
26 | /* | 30 | /* |
27 | * Normally we could just do DMTE0_IRQ + chan outright, though in the | 31 | * Normally we could just do DMTE0_IRQ + chan outright, though in the |
28 | * case of the 7751R, the DMTE IRQs for channels > 4 start right above | 32 | * case of the 7751R, the DMTE IRQs for channels > 4 start right above |
29 | * the SCIF | 33 | * the SCIF |
30 | */ | 34 | */ |
31 | if (chan < 4) { | 35 | { DMTE0_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, |
32 | irq = DMTE0_IRQ + chan; | 36 | { DMTE0_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, |
33 | } else { | 37 | { DMTE0_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, |
34 | #ifdef DMTE4_IRQ | 38 | { DMTE0_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, |
35 | irq = DMTE4_IRQ + chan - 4; | 39 | { DMTE4_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, |
36 | #endif | 40 | { DMTE4_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, |
37 | } | 41 | { DMTE4_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, |
42 | { DMTE4_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, | ||
43 | }; | ||
38 | 44 | ||
45 | static inline unsigned int get_dmte_irq(unsigned int chan) | ||
46 | { | ||
47 | unsigned int irq = 0; | ||
48 | if (chan < ARRAY_SIZE(dmte_ipr_map)) | ||
49 | irq = dmte_ipr_map[chan].irq; | ||
39 | return irq; | 50 | return irq; |
40 | } | 51 | } |
41 | 52 | ||
@@ -258,17 +269,16 @@ static int __init sh_dmac_init(void) | |||
258 | int i; | 269 | int i; |
259 | 270 | ||
260 | #ifdef CONFIG_CPU_SH4 | 271 | #ifdef CONFIG_CPU_SH4 |
261 | make_ipr_irq(DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); | 272 | make_ipr_irq(dmae_ipr_map, ARRAY_SIZE(dmae_ipr_map)); |
262 | i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0); | 273 | i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0); |
263 | if (unlikely(i < 0)) | 274 | if (unlikely(i < 0)) |
264 | return i; | 275 | return i; |
265 | #endif | 276 | #endif |
266 | 277 | ||
267 | for (i = 0; i < info->nr_channels; i++) { | 278 | i = info->nr_channels; |
268 | int irq = get_dmte_irq(i); | 279 | if (i > ARRAY_SIZE(dmte_ipr_map)) |
269 | 280 | i = ARRAY_SIZE(dmte_ipr_map); | |
270 | make_ipr_irq(irq, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); | 281 | make_ipr_irq(dmte_ipr_map, i); |
271 | } | ||
272 | 282 | ||
273 | /* | 283 | /* |
274 | * Initialize DMAOR, and clean up any error flags that may have | 284 | * Initialize DMAOR, and clean up any error flags that may have |
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c index f7997312ef98..a0089563cbfc 100644 --- a/arch/sh/kernel/cpu/irq/ipr.c +++ b/arch/sh/kernel/cpu/irq/ipr.c | |||
@@ -23,24 +23,21 @@ | |||
23 | #include <asm/io.h> | 23 | #include <asm/io.h> |
24 | #include <asm/machvec.h> | 24 | #include <asm/machvec.h> |
25 | 25 | ||
26 | struct ipr_data { | ||
27 | unsigned int addr; /* Address of Interrupt Priority Register */ | ||
28 | int shift; /* Shifts of the 16-bit data */ | ||
29 | int priority; /* The priority */ | ||
30 | }; | ||
31 | 26 | ||
32 | static void disable_ipr_irq(unsigned int irq) | 27 | static void disable_ipr_irq(unsigned int irq) |
33 | { | 28 | { |
34 | struct ipr_data *p = get_irq_chip_data(irq); | 29 | struct ipr_data *p = get_irq_chip_data(irq); |
30 | int shift = p->shift*4; | ||
35 | /* Set the priority in IPR to 0 */ | 31 | /* Set the priority in IPR to 0 */ |
36 | ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr); | 32 | ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << shift)), p->addr); |
37 | } | 33 | } |
38 | 34 | ||
39 | static void enable_ipr_irq(unsigned int irq) | 35 | static void enable_ipr_irq(unsigned int irq) |
40 | { | 36 | { |
41 | struct ipr_data *p = get_irq_chip_data(irq); | 37 | struct ipr_data *p = get_irq_chip_data(irq); |
38 | int shift = p->shift*4; | ||
42 | /* Set priority in IPR back to original value */ | 39 | /* Set priority in IPR back to original value */ |
43 | ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr); | 40 | ctrl_outw(ctrl_inw(p->addr) | (p->priority << shift), p->addr); |
44 | } | 41 | } |
45 | 42 | ||
46 | static struct irq_chip ipr_irq_chip = { | 43 | static struct irq_chip ipr_irq_chip = { |
@@ -50,67 +47,57 @@ static struct irq_chip ipr_irq_chip = { | |||
50 | .mask_ack = disable_ipr_irq, | 47 | .mask_ack = disable_ipr_irq, |
51 | }; | 48 | }; |
52 | 49 | ||
53 | void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority) | 50 | void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs) |
54 | { | 51 | { |
55 | struct ipr_data ipr_data; | 52 | int i; |
56 | |||
57 | disable_irq_nosync(irq); | ||
58 | |||
59 | ipr_data.addr = addr; | ||
60 | ipr_data.shift = pos*4; /* POSition (0-3) x 4 means shift */ | ||
61 | ipr_data.priority = priority; | ||
62 | 53 | ||
63 | set_irq_chip_and_handler_name(irq, &ipr_irq_chip, | 54 | for (i = 0; i < nr_irqs; i++) { |
55 | unsigned int irq = table[i].irq; | ||
56 | disable_irq_nosync(irq); | ||
57 | set_irq_chip_and_handler_name(irq, &ipr_irq_chip, | ||
64 | handle_level_irq, "level"); | 58 | handle_level_irq, "level"); |
65 | set_irq_chip_data(irq, &ipr_data); | 59 | set_irq_chip_data(irq, &table[i]); |
66 | 60 | enable_ipr_irq(irq); | |
67 | enable_ipr_irq(irq); | 61 | } |
68 | } | 62 | } |
63 | EXPORT_SYMBOL(make_ipr_irq); | ||
69 | 64 | ||
70 | /* XXX: This needs to die a horrible death.. */ | 65 | static struct ipr_data sys_ipr_map[] = { |
71 | void __init init_IRQ(void) | ||
72 | { | ||
73 | #ifndef CONFIG_CPU_SUBTYPE_SH7780 | 66 | #ifndef CONFIG_CPU_SUBTYPE_SH7780 |
74 | make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY); | 67 | { TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY }, |
75 | make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY); | 68 | { TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY }, |
76 | #ifdef RTC_IRQ | 69 | #ifdef RTC_IRQ |
77 | make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY); | 70 | { RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY }, |
78 | #endif | 71 | #endif |
79 | |||
80 | #ifdef SCI_ERI_IRQ | 72 | #ifdef SCI_ERI_IRQ |
81 | make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); | 73 | { SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY }, |
82 | make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); | 74 | { SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY }, |
83 | make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); | 75 | { SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY }, |
84 | #endif | 76 | #endif |
85 | |||
86 | #ifdef SCIF1_ERI_IRQ | 77 | #ifdef SCIF1_ERI_IRQ |
87 | make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); | 78 | { SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, |
88 | make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); | 79 | { SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, |
89 | make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); | 80 | { SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, |
90 | make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); | 81 | { SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, |
91 | #endif | 82 | #endif |
92 | |||
93 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) | 83 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) |
94 | make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY); | 84 | { SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, |
95 | make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); | 85 | { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, |
96 | make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); | 86 | { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, |
97 | make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); | 87 | { VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, |
98 | #endif | 88 | #endif |
99 | |||
100 | #ifdef SCIF_ERI_IRQ | 89 | #ifdef SCIF_ERI_IRQ |
101 | make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); | 90 | { SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY }, |
102 | make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); | 91 | { SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY }, |
103 | make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); | 92 | { SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY }, |
104 | make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); | 93 | { SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY }, |
105 | #endif | 94 | #endif |
106 | |||
107 | #ifdef IRDA_ERI_IRQ | 95 | #ifdef IRDA_ERI_IRQ |
108 | make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); | 96 | { IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY }, |
109 | make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); | 97 | { IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY }, |
110 | make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); | 98 | { IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY }, |
111 | make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); | 99 | { IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY }, |
112 | #endif | 100 | #endif |
113 | |||
114 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | 101 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ |
115 | defined(CONFIG_CPU_SUBTYPE_SH7706) || \ | 102 | defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
116 | defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) | 103 | defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) |
@@ -124,14 +111,19 @@ void __init init_IRQ(void) | |||
124 | * You should set corresponding bits of PFC to "00" | 111 | * You should set corresponding bits of PFC to "00" |
125 | * to enable these interrupts. | 112 | * to enable these interrupts. |
126 | */ | 113 | */ |
127 | make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY); | 114 | { IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY }, |
128 | make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY); | 115 | { IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY }, |
129 | make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY); | 116 | { IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY }, |
130 | make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY); | 117 | { IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY }, |
131 | make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY); | 118 | { IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY }, |
132 | make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY); | 119 | { IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY }, |
133 | #endif | 120 | #endif |
134 | #endif | 121 | #endif |
122 | }; | ||
123 | |||
124 | void __init init_IRQ(void) | ||
125 | { | ||
126 | make_ipr_irq(sys_ipr_map, ARRAY_SIZE(sys_ipr_map)); | ||
135 | 127 | ||
136 | #ifdef CONFIG_CPU_HAS_PINT_IRQ | 128 | #ifdef CONFIG_CPU_HAS_PINT_IRQ |
137 | init_IRQ_pint(); | 129 | init_IRQ_pint(); |
@@ -153,5 +145,3 @@ int ipr_irq_demux(int irq) | |||
153 | return irq; | 145 | return irq; |
154 | } | 146 | } |
155 | #endif | 147 | #endif |
156 | |||
157 | EXPORT_SYMBOL(make_ipr_irq); | ||
diff --git a/arch/sh/kernel/cpu/irq/pint.c b/arch/sh/kernel/cpu/irq/pint.c index 17f47b373d6e..f60007783a21 100644 --- a/arch/sh/kernel/cpu/irq/pint.c +++ b/arch/sh/kernel/cpu/irq/pint.c | |||
@@ -84,12 +84,16 @@ void make_pint_irq(unsigned int irq) | |||
84 | disable_pint_irq(irq); | 84 | disable_pint_irq(irq); |
85 | } | 85 | } |
86 | 86 | ||
87 | static struct ipr_data pint_ipr_map[] = { | ||
88 | { PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY }, | ||
89 | { PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY }, | ||
90 | }; | ||
91 | |||
87 | void __init init_IRQ_pint(void) | 92 | void __init init_IRQ_pint(void) |
88 | { | 93 | { |
89 | int i; | 94 | int i; |
90 | 95 | ||
91 | make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY); | 96 | make_ipr_irq(pint_ipr_map, ARRAY_SIZE(pint_ipr_map)); |
92 | make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY); | ||
93 | 97 | ||
94 | enable_irq(PINT0_IRQ); | 98 | enable_irq(PINT0_IRQ); |
95 | enable_irq(PINT8_IRQ); | 99 | enable_irq(PINT8_IRQ); |