diff options
author | Paul Mundt <lethal@linux-sh.org> | 2010-10-14 13:13:04 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2010-10-14 13:13:04 -0400 |
commit | d8d6b902b8a3b2c66151529694bb4a9a3555cf43 (patch) | |
tree | e2ab4dff9888dc2cd0998299959bfa5b9409cdd5 /arch/sh | |
parent | c993487ec87ba6d9ea47b03dad562123d503f4a2 (diff) |
sh: mach-sdk7786: Add support for the FPGA SRAM.
This ties in the 2KiB of FPGA SRAM in to the generic SRAM pool.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r-- | arch/sh/boards/Kconfig | 1 | ||||
-rw-r--r-- | arch/sh/boards/mach-sdk7786/Makefile | 3 | ||||
-rw-r--r-- | arch/sh/boards/mach-sdk7786/sram.c | 72 | ||||
-rw-r--r-- | arch/sh/include/asm/sizes.h | 1 | ||||
-rw-r--r-- | arch/sh/include/mach-sdk7786/mach/fpga.h | 17 |
5 files changed, 92 insertions, 2 deletions
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index bb2cb27074e9..9c94711aa6ca 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig | |||
@@ -156,6 +156,7 @@ config SH_SDK7786 | |||
156 | select SYS_SUPPORTS_PCI | 156 | select SYS_SUPPORTS_PCI |
157 | select NO_IOPORT if !PCI | 157 | select NO_IOPORT if !PCI |
158 | select ARCH_WANT_OPTIONAL_GPIOLIB | 158 | select ARCH_WANT_OPTIONAL_GPIOLIB |
159 | select HAVE_SRAM_POOL | ||
159 | help | 160 | help |
160 | Select SDK7786 if configuring for a Renesas Technology Europe | 161 | Select SDK7786 if configuring for a Renesas Technology Europe |
161 | SH7786-65nm board. | 162 | SH7786-65nm board. |
diff --git a/arch/sh/boards/mach-sdk7786/Makefile b/arch/sh/boards/mach-sdk7786/Makefile index d0f801bd8416..23ff7d4ac491 100644 --- a/arch/sh/boards/mach-sdk7786/Makefile +++ b/arch/sh/boards/mach-sdk7786/Makefile | |||
@@ -1,3 +1,4 @@ | |||
1 | obj-y := setup.o fpga.o irq.o | 1 | obj-y := fpga.o irq.o setup.o |
2 | 2 | ||
3 | obj-$(CONFIG_GENERIC_GPIO) += gpio.o | 3 | obj-$(CONFIG_GENERIC_GPIO) += gpio.o |
4 | obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o | ||
diff --git a/arch/sh/boards/mach-sdk7786/sram.c b/arch/sh/boards/mach-sdk7786/sram.c new file mode 100644 index 000000000000..c81c3abbe01c --- /dev/null +++ b/arch/sh/boards/mach-sdk7786/sram.c | |||
@@ -0,0 +1,72 @@ | |||
1 | /* | ||
2 | * SDK7786 FPGA SRAM Support. | ||
3 | * | ||
4 | * Copyright (C) 2010 Paul Mundt | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | */ | ||
10 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
11 | |||
12 | #include <linux/init.h> | ||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/types.h> | ||
15 | #include <linux/io.h> | ||
16 | #include <linux/string.h> | ||
17 | #include <mach/fpga.h> | ||
18 | #include <asm/sram.h> | ||
19 | #include <asm/sizes.h> | ||
20 | |||
21 | static int __init fpga_sram_init(void) | ||
22 | { | ||
23 | unsigned long phys; | ||
24 | unsigned int area; | ||
25 | void __iomem *vaddr; | ||
26 | int ret; | ||
27 | u16 data; | ||
28 | |||
29 | /* Enable FPGA SRAM */ | ||
30 | data = fpga_read_reg(LCLASR); | ||
31 | data |= LCLASR_FRAMEN; | ||
32 | fpga_write_reg(data, LCLASR); | ||
33 | |||
34 | /* | ||
35 | * FPGA_SEL determines the area mapping | ||
36 | */ | ||
37 | area = (data & LCLASR_FPGA_SEL_MASK) >> LCLASR_FPGA_SEL_SHIFT; | ||
38 | if (unlikely(area == LCLASR_AREA_MASK)) { | ||
39 | pr_err("FPGA memory unmapped.\n"); | ||
40 | return -ENXIO; | ||
41 | } | ||
42 | |||
43 | /* | ||
44 | * The memory itself occupies a 2KiB range at the top of the area | ||
45 | * immediately below the system registers. | ||
46 | */ | ||
47 | phys = (area << 26) + SZ_64M - SZ_4K; | ||
48 | |||
49 | /* | ||
50 | * The FPGA SRAM resides in translatable physical space, so set | ||
51 | * up a mapping prior to inserting it in to the pool. | ||
52 | */ | ||
53 | vaddr = ioremap(phys, SZ_2K); | ||
54 | if (unlikely(!vaddr)) { | ||
55 | pr_err("Failed remapping FPGA memory.\n"); | ||
56 | return -ENXIO; | ||
57 | } | ||
58 | |||
59 | pr_info("Adding %dKiB of FPGA memory at 0x%08lx-0x%08lx " | ||
60 | "(area %d) to pool.\n", | ||
61 | SZ_2K >> 10, phys, phys + SZ_2K - 1, area); | ||
62 | |||
63 | ret = gen_pool_add(sram_pool, (unsigned long)vaddr, SZ_2K, -1); | ||
64 | if (unlikely(ret < 0)) { | ||
65 | pr_err("Failed adding memory\n"); | ||
66 | iounmap(vaddr); | ||
67 | return ret; | ||
68 | } | ||
69 | |||
70 | return 0; | ||
71 | } | ||
72 | postcore_initcall(fpga_sram_init); | ||
diff --git a/arch/sh/include/asm/sizes.h b/arch/sh/include/asm/sizes.h index 3a1fb97770f1..0b9fe2d5c36d 100644 --- a/arch/sh/include/asm/sizes.h +++ b/arch/sh/include/asm/sizes.h | |||
@@ -32,6 +32,7 @@ | |||
32 | #define SZ_512 0x00000200 | 32 | #define SZ_512 0x00000200 |
33 | 33 | ||
34 | #define SZ_1K 0x00000400 | 34 | #define SZ_1K 0x00000400 |
35 | #define SZ_2K 0x00000800 | ||
35 | #define SZ_4K 0x00001000 | 36 | #define SZ_4K 0x00001000 |
36 | #define SZ_8K 0x00002000 | 37 | #define SZ_8K 0x00002000 |
37 | #define SZ_16K 0x00004000 | 38 | #define SZ_16K 0x00004000 |
diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h index b7d93699b679..40f0c2d3690c 100644 --- a/arch/sh/include/mach-sdk7786/mach/fpga.h +++ b/arch/sh/include/mach-sdk7786/mach/fpga.h | |||
@@ -43,8 +43,23 @@ | |||
43 | 43 | ||
44 | #define FAER 0x150 | 44 | #define FAER 0x150 |
45 | #define USRGPIR 0x160 | 45 | #define USRGPIR 0x160 |
46 | |||
46 | /* 0x170 reserved */ | 47 | /* 0x170 reserved */ |
47 | #define LCLASR 0x180 | 48 | |
49 | #define LCLASR 0x180 | ||
50 | #define LCLASR_FRAMEN BIT(15) | ||
51 | |||
52 | #define LCLASR_FPGA_SEL_SHIFT 12 | ||
53 | #define LCLASR_NAND_SEL_SHIFT 8 | ||
54 | #define LCLASR_NORB_SEL_SHIFT 4 | ||
55 | #define LCLASR_NORA_SEL_SHIFT 0 | ||
56 | |||
57 | #define LCLASR_AREA_MASK 0x7 | ||
58 | |||
59 | #define LCLASR_FPGA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT) | ||
60 | #define LCLASR_NAND_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT) | ||
61 | #define LCLASR_NORB_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT) | ||
62 | #define LCLASR_NORA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT) | ||
48 | 63 | ||
49 | #define SBCR 0x190 | 64 | #define SBCR 0x190 |
50 | #define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */ | 65 | #define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */ |