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authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2010-12-03 00:37:53 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-12-03 00:41:57 -0500
commite17ca5cf3c5b2a769bcde2c37cf0d96f08c8cb17 (patch)
tree027d2fbf03bcd6f2d3bdd079dfa1e10ce7a9ffb6 /arch/sh
parent193006f7e3b1abd42d7a3677b54fa2996461a842 (diff)
sh: se/7724: Update clock framework of FSI clock to non-legacy
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/boards/mach-se/7724/setup.c33
1 files changed, 4 insertions, 29 deletions
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index 673530500e27..1486ab726ab7 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -283,31 +283,6 @@ static struct platform_device ceu1_device = {
283}; 283};
284 284
285/* FSI */ 285/* FSI */
286/*
287 * FSI-A use external clock which came from ak464x.
288 * So, we should change parent of fsi
289 */
290#define FCLKACR 0xa4150008
291static void fsimck_init(struct clk *clk)
292{
293 u32 status = __raw_readl(clk->enable_reg);
294
295 /* use external clock */
296 status &= ~0x000000ff;
297 status |= 0x00000080;
298 __raw_writel(status, clk->enable_reg);
299}
300
301static struct clk_ops fsimck_clk_ops = {
302 .init = fsimck_init,
303};
304
305static struct clk fsimcka_clk = {
306 .ops = &fsimck_clk_ops,
307 .enable_reg = (void __iomem *)FCLKACR,
308 .rate = 0, /* unknown */
309};
310
311/* change J20, J21, J22 pin to 1-2 connection to use slave mode */ 286/* change J20, J21, J22 pin to 1-2 connection to use slave mode */
312static struct sh_fsi_platform_info fsi_info = { 287static struct sh_fsi_platform_info fsi_info = {
313 .porta_flags = SH_FSI_BRS_INV | 288 .porta_flags = SH_FSI_BRS_INV |
@@ -879,10 +854,10 @@ static int __init devices_setup(void)
879 /* change parent of FSI A */ 854 /* change parent of FSI A */
880 clk = clk_get(NULL, "fsia_clk"); 855 clk = clk_get(NULL, "fsia_clk");
881 if (!IS_ERR(clk)) { 856 if (!IS_ERR(clk)) {
882 clk_register(&fsimcka_clk); 857 /* 48kHz dummy clock was used to make sure 1/1 divide */
883 clk_set_parent(clk, &fsimcka_clk); 858 clk_set_rate(&sh7724_fsimcka_clk, 48000);
884 clk_set_rate(clk, 11000); 859 clk_set_parent(clk, &sh7724_fsimcka_clk);
885 clk_set_rate(&fsimcka_clk, 11000); 860 clk_set_rate(clk, 48000);
886 clk_put(clk); 861 clk_put(clk);
887 } 862 }
888 863