diff options
author | Paul Mundt <lethal@linux-sh.org> | 2010-05-13 04:45:44 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2010-05-13 04:45:44 -0400 |
commit | c5eb5b372e7ea18a5eeb6b5192a6369967cb1afe (patch) | |
tree | 4e18e43ca25db9b8df6d332f9c2d3989288988a2 /arch/sh | |
parent | 15f2a7967a46c7fab579ab88b9f1e0c7f78ac495 (diff) | |
parent | f5ca6d4cbd49dbb6e179a71fa610eb321a3e9951 (diff) |
Merge branch 'sh/clkfwk'
Diffstat (limited to 'arch/sh')
-rw-r--r-- | arch/sh/boards/mach-ecovec24/setup.c | 26 | ||||
-rw-r--r-- | arch/sh/boards/mach-highlander/setup.c | 12 | ||||
-rw-r--r-- | arch/sh/boards/mach-se/7724/setup.c | 20 | ||||
-rw-r--r-- | arch/sh/include/asm/clock.h | 153 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/Makefile | 2 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/clock-cpg.c | 307 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/clock.c | 576 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4/clock-sh4-202.c | 17 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7343.c | 213 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7366.c | 192 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7722.c | 47 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7723.c | 47 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7724.c | 38 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7757.c | 11 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7763.c | 12 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7780.c | 12 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7785.c | 149 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7786.c | 181 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-shx3.c | 13 |
19 files changed, 702 insertions, 1326 deletions
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c index 6c13b92742e8..62123885a6fa 100644 --- a/arch/sh/boards/mach-ecovec24/setup.c +++ b/arch/sh/boards/mach-ecovec24/setup.c | |||
@@ -710,8 +710,6 @@ static struct clk_ops fsimck_clk_ops = { | |||
710 | }; | 710 | }; |
711 | 711 | ||
712 | static struct clk fsimckb_clk = { | 712 | static struct clk fsimckb_clk = { |
713 | .name = "fsimckb_clk", | ||
714 | .id = -1, | ||
715 | .ops = &fsimck_clk_ops, | 713 | .ops = &fsimck_clk_ops, |
716 | .enable_reg = (void __iomem *)FCLKBCR, | 714 | .enable_reg = (void __iomem *)FCLKBCR, |
717 | .rate = 0, /* unknown */ | 715 | .rate = 0, /* unknown */ |
@@ -1138,16 +1136,20 @@ static int __init arch_setup(void) | |||
1138 | 1136 | ||
1139 | /* set SPU2 clock to 83.4 MHz */ | 1137 | /* set SPU2 clock to 83.4 MHz */ |
1140 | clk = clk_get(NULL, "spu_clk"); | 1138 | clk = clk_get(NULL, "spu_clk"); |
1141 | clk_set_rate(clk, clk_round_rate(clk, 83333333)); | 1139 | if (clk) { |
1142 | clk_put(clk); | 1140 | clk_set_rate(clk, clk_round_rate(clk, 83333333)); |
1141 | clk_put(clk); | ||
1142 | } | ||
1143 | 1143 | ||
1144 | /* change parent of FSI B */ | 1144 | /* change parent of FSI B */ |
1145 | clk = clk_get(NULL, "fsib_clk"); | 1145 | clk = clk_get(NULL, "fsib_clk"); |
1146 | clk_register(&fsimckb_clk); | 1146 | if (clk) { |
1147 | clk_set_parent(clk, &fsimckb_clk); | 1147 | clk_register(&fsimckb_clk); |
1148 | clk_set_rate(clk, 11000); | 1148 | clk_set_parent(clk, &fsimckb_clk); |
1149 | clk_set_rate(&fsimckb_clk, 11000); | 1149 | clk_set_rate(clk, 11000); |
1150 | clk_put(clk); | 1150 | clk_set_rate(&fsimckb_clk, 11000); |
1151 | clk_put(clk); | ||
1152 | } | ||
1151 | 1153 | ||
1152 | gpio_request(GPIO_PTU0, NULL); | 1154 | gpio_request(GPIO_PTU0, NULL); |
1153 | gpio_direction_output(GPIO_PTU0, 0); | 1155 | gpio_direction_output(GPIO_PTU0, 0); |
@@ -1159,8 +1161,10 @@ static int __init arch_setup(void) | |||
1159 | 1161 | ||
1160 | /* set VPU clock to 166 MHz */ | 1162 | /* set VPU clock to 166 MHz */ |
1161 | clk = clk_get(NULL, "vpu_clk"); | 1163 | clk = clk_get(NULL, "vpu_clk"); |
1162 | clk_set_rate(clk, clk_round_rate(clk, 166000000)); | 1164 | if (clk) { |
1163 | clk_put(clk); | 1165 | clk_set_rate(clk, clk_round_rate(clk, 166000000)); |
1166 | clk_put(clk); | ||
1167 | } | ||
1164 | 1168 | ||
1165 | /* enable IrDA */ | 1169 | /* enable IrDA */ |
1166 | gpio_request(GPIO_FN_IRDA_OUT, NULL); | 1170 | gpio_request(GPIO_FN_IRDA_OUT, NULL); |
diff --git a/arch/sh/boards/mach-highlander/setup.c b/arch/sh/boards/mach-highlander/setup.c index affd66747ba3..a5ecfbacaf36 100644 --- a/arch/sh/boards/mach-highlander/setup.c +++ b/arch/sh/boards/mach-highlander/setup.c | |||
@@ -14,6 +14,7 @@ | |||
14 | * for more details. | 14 | * for more details. |
15 | */ | 15 | */ |
16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
17 | #include <linux/io.h> | ||
17 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
18 | #include <linux/ata_platform.h> | 19 | #include <linux/ata_platform.h> |
19 | #include <linux/types.h> | 20 | #include <linux/types.h> |
@@ -26,6 +27,7 @@ | |||
26 | #include <net/ax88796.h> | 27 | #include <net/ax88796.h> |
27 | #include <asm/machvec.h> | 28 | #include <asm/machvec.h> |
28 | #include <mach/highlander.h> | 29 | #include <mach/highlander.h> |
30 | #include <asm/clkdev.h> | ||
29 | #include <asm/clock.h> | 31 | #include <asm/clock.h> |
30 | #include <asm/heartbeat.h> | 32 | #include <asm/heartbeat.h> |
31 | #include <asm/io.h> | 33 | #include <asm/io.h> |
@@ -326,7 +328,6 @@ static struct clk_ops ivdr_clk_ops = { | |||
326 | }; | 328 | }; |
327 | 329 | ||
328 | static struct clk ivdr_clk = { | 330 | static struct clk ivdr_clk = { |
329 | .name = "ivdr_clk", | ||
330 | .ops = &ivdr_clk_ops, | 331 | .ops = &ivdr_clk_ops, |
331 | }; | 332 | }; |
332 | 333 | ||
@@ -334,6 +335,13 @@ static struct clk *r7780rp_clocks[] = { | |||
334 | &ivdr_clk, | 335 | &ivdr_clk, |
335 | }; | 336 | }; |
336 | 337 | ||
338 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | ||
339 | |||
340 | static struct clk_lookup lookups[] = { | ||
341 | /* main clocks */ | ||
342 | CLKDEV_CON_ID("ivdr_clk", &ivdr_clk), | ||
343 | }; | ||
344 | |||
337 | static void r7780rp_power_off(void) | 345 | static void r7780rp_power_off(void) |
338 | { | 346 | { |
339 | if (mach_is_r7780mp() || mach_is_r7785rp()) | 347 | if (mach_is_r7780mp() || mach_is_r7785rp()) |
@@ -370,6 +378,8 @@ static void __init highlander_setup(char **cmdline_p) | |||
370 | clk_enable(clk); | 378 | clk_enable(clk); |
371 | } | 379 | } |
372 | 380 | ||
381 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
382 | |||
373 | __raw_writew(0x0000, PA_OBLED); /* Clear LED. */ | 383 | __raw_writew(0x0000, PA_OBLED); /* Clear LED. */ |
374 | 384 | ||
375 | if (mach_is_r7780rp()) | 385 | if (mach_is_r7780rp()) |
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c index ccaa290e9aba..e74ae7b0d8bf 100644 --- a/arch/sh/boards/mach-se/7724/setup.c +++ b/arch/sh/boards/mach-se/7724/setup.c | |||
@@ -276,8 +276,6 @@ static struct clk_ops fsimck_clk_ops = { | |||
276 | }; | 276 | }; |
277 | 277 | ||
278 | static struct clk fsimcka_clk = { | 278 | static struct clk fsimcka_clk = { |
279 | .name = "fsimcka_clk", | ||
280 | .id = -1, | ||
281 | .ops = &fsimck_clk_ops, | 279 | .ops = &fsimck_clk_ops, |
282 | .enable_reg = (void __iomem *)FCLKACR, | 280 | .enable_reg = (void __iomem *)FCLKACR, |
283 | .rate = 0, /* unknown */ | 281 | .rate = 0, /* unknown */ |
@@ -771,16 +769,20 @@ static int __init devices_setup(void) | |||
771 | 769 | ||
772 | /* set SPU2 clock to 83.4 MHz */ | 770 | /* set SPU2 clock to 83.4 MHz */ |
773 | clk = clk_get(NULL, "spu_clk"); | 771 | clk = clk_get(NULL, "spu_clk"); |
774 | clk_set_rate(clk, clk_round_rate(clk, 83333333)); | 772 | if (clk) { |
775 | clk_put(clk); | 773 | clk_set_rate(clk, clk_round_rate(clk, 83333333)); |
774 | clk_put(clk); | ||
775 | } | ||
776 | 776 | ||
777 | /* change parent of FSI A */ | 777 | /* change parent of FSI A */ |
778 | clk = clk_get(NULL, "fsia_clk"); | 778 | clk = clk_get(NULL, "fsia_clk"); |
779 | clk_register(&fsimcka_clk); | 779 | if (clk) { |
780 | clk_set_parent(clk, &fsimcka_clk); | 780 | clk_register(&fsimcka_clk); |
781 | clk_set_rate(clk, 11000); | 781 | clk_set_parent(clk, &fsimcka_clk); |
782 | clk_set_rate(&fsimcka_clk, 11000); | 782 | clk_set_rate(clk, 11000); |
783 | clk_put(clk); | 783 | clk_set_rate(&fsimcka_clk, 11000); |
784 | clk_put(clk); | ||
785 | } | ||
784 | 786 | ||
785 | /* SDHI0 connected to cn7 */ | 787 | /* SDHI0 connected to cn7 */ |
786 | gpio_request(GPIO_FN_SDHI0CD, NULL); | 788 | gpio_request(GPIO_FN_SDHI0CD, NULL); |
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h index 405a12c09960..803d4c7f09dc 100644 --- a/arch/sh/include/asm/clock.h +++ b/arch/sh/include/asm/clock.h | |||
@@ -1,163 +1,16 @@ | |||
1 | #ifndef __ASM_SH_CLOCK_H | 1 | #ifndef __ASM_SH_CLOCK_H |
2 | #define __ASM_SH_CLOCK_H | 2 | #define __ASM_SH_CLOCK_H |
3 | 3 | ||
4 | #include <linux/list.h> | 4 | #include <linux/sh_clk.h> |
5 | #include <linux/seq_file.h> | ||
6 | #include <linux/cpufreq.h> | ||
7 | #include <linux/clk.h> | ||
8 | #include <linux/err.h> | ||
9 | |||
10 | struct clk; | ||
11 | |||
12 | struct clk_ops { | ||
13 | void (*init)(struct clk *clk); | ||
14 | int (*enable)(struct clk *clk); | ||
15 | void (*disable)(struct clk *clk); | ||
16 | unsigned long (*recalc)(struct clk *clk); | ||
17 | int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); | ||
18 | int (*set_parent)(struct clk *clk, struct clk *parent); | ||
19 | long (*round_rate)(struct clk *clk, unsigned long rate); | ||
20 | }; | ||
21 | |||
22 | struct clk { | ||
23 | struct list_head node; | ||
24 | const char *name; | ||
25 | int id; | ||
26 | struct module *owner; | ||
27 | |||
28 | struct clk *parent; | ||
29 | struct clk_ops *ops; | ||
30 | |||
31 | struct list_head children; | ||
32 | struct list_head sibling; /* node for children */ | ||
33 | |||
34 | int usecount; | ||
35 | |||
36 | unsigned long rate; | ||
37 | unsigned long flags; | ||
38 | |||
39 | void __iomem *enable_reg; | ||
40 | unsigned int enable_bit; | ||
41 | |||
42 | unsigned long arch_flags; | ||
43 | void *priv; | ||
44 | struct dentry *dentry; | ||
45 | struct cpufreq_frequency_table *freq_table; | ||
46 | }; | ||
47 | |||
48 | #define CLK_ENABLE_ON_INIT (1 << 0) | ||
49 | 5 | ||
50 | /* Should be defined by processor-specific code */ | 6 | /* Should be defined by processor-specific code */ |
51 | void __deprecated arch_init_clk_ops(struct clk_ops **, int type); | 7 | void __deprecated arch_init_clk_ops(struct clk_ops **, int type); |
52 | int __init arch_clk_init(void); | 8 | int __init arch_clk_init(void); |
53 | 9 | ||
54 | /* arch/sh/kernel/cpu/clock.c */ | ||
55 | int clk_init(void); | ||
56 | unsigned long followparent_recalc(struct clk *); | ||
57 | void recalculate_root_clocks(void); | ||
58 | void propagate_rate(struct clk *); | ||
59 | int clk_reparent(struct clk *child, struct clk *parent); | ||
60 | int clk_register(struct clk *); | ||
61 | void clk_unregister(struct clk *); | ||
62 | |||
63 | /* arch/sh/kernel/cpu/clock-cpg.c */ | 10 | /* arch/sh/kernel/cpu/clock-cpg.c */ |
64 | int __init __deprecated cpg_clk_init(void); | 11 | int __init __deprecated cpg_clk_init(void); |
65 | 12 | ||
66 | /* the exported API, in addition to clk_set_rate */ | 13 | /* arch/sh/kernel/cpu/clock.c */ |
67 | /** | 14 | int clk_init(void); |
68 | * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter | ||
69 | * @clk: clock source | ||
70 | * @rate: desired clock rate in Hz | ||
71 | * @algo_id: algorithm id to be passed down to ops->set_rate | ||
72 | * | ||
73 | * Returns success (0) or negative errno. | ||
74 | */ | ||
75 | int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id); | ||
76 | |||
77 | enum clk_sh_algo_id { | ||
78 | NO_CHANGE = 0, | ||
79 | |||
80 | IUS_N1_N1, | ||
81 | IUS_322, | ||
82 | IUS_522, | ||
83 | IUS_N11, | ||
84 | |||
85 | SB_N1, | ||
86 | |||
87 | SB3_N1, | ||
88 | SB3_32, | ||
89 | SB3_43, | ||
90 | SB3_54, | ||
91 | |||
92 | BP_N1, | ||
93 | |||
94 | IP_N1, | ||
95 | }; | ||
96 | |||
97 | struct clk_div_mult_table { | ||
98 | unsigned int *divisors; | ||
99 | unsigned int nr_divisors; | ||
100 | unsigned int *multipliers; | ||
101 | unsigned int nr_multipliers; | ||
102 | }; | ||
103 | |||
104 | struct cpufreq_frequency_table; | ||
105 | void clk_rate_table_build(struct clk *clk, | ||
106 | struct cpufreq_frequency_table *freq_table, | ||
107 | int nr_freqs, | ||
108 | struct clk_div_mult_table *src_table, | ||
109 | unsigned long *bitmap); | ||
110 | |||
111 | long clk_rate_table_round(struct clk *clk, | ||
112 | struct cpufreq_frequency_table *freq_table, | ||
113 | unsigned long rate); | ||
114 | |||
115 | int clk_rate_table_find(struct clk *clk, | ||
116 | struct cpufreq_frequency_table *freq_table, | ||
117 | unsigned long rate); | ||
118 | |||
119 | #define SH_CLK_MSTP32(_name, _id, _parent, _enable_reg, \ | ||
120 | _enable_bit, _flags) \ | ||
121 | { \ | ||
122 | .name = _name, \ | ||
123 | .id = _id, \ | ||
124 | .parent = _parent, \ | ||
125 | .enable_reg = (void __iomem *)_enable_reg, \ | ||
126 | .enable_bit = _enable_bit, \ | ||
127 | .flags = _flags, \ | ||
128 | } | ||
129 | |||
130 | int sh_clk_mstp32_register(struct clk *clks, int nr); | ||
131 | |||
132 | #define SH_CLK_DIV4(_name, _parent, _reg, _shift, _div_bitmap, _flags) \ | ||
133 | { \ | ||
134 | .name = _name, \ | ||
135 | .parent = _parent, \ | ||
136 | .enable_reg = (void __iomem *)_reg, \ | ||
137 | .enable_bit = _shift, \ | ||
138 | .arch_flags = _div_bitmap, \ | ||
139 | .flags = _flags, \ | ||
140 | } | ||
141 | |||
142 | struct clk_div4_table { | ||
143 | struct clk_div_mult_table *div_mult_table; | ||
144 | void (*kick)(struct clk *clk); | ||
145 | }; | ||
146 | |||
147 | int sh_clk_div4_register(struct clk *clks, int nr, | ||
148 | struct clk_div4_table *table); | ||
149 | int sh_clk_div4_enable_register(struct clk *clks, int nr, | ||
150 | struct clk_div4_table *table); | ||
151 | int sh_clk_div4_reparent_register(struct clk *clks, int nr, | ||
152 | struct clk_div4_table *table); | ||
153 | |||
154 | #define SH_CLK_DIV6(_parent, _reg, _flags) \ | ||
155 | { \ | ||
156 | .parent = _parent, \ | ||
157 | .enable_reg = (void __iomem *)_reg, \ | ||
158 | .flags = _flags, \ | ||
159 | } | ||
160 | |||
161 | int sh_clk_div6_register(struct clk *clks, int nr); | ||
162 | 15 | ||
163 | #endif /* __ASM_SH_CLOCK_H */ | 16 | #endif /* __ASM_SH_CLOCK_H */ |
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile index 0e48bc61c272..4edcb60a1355 100644 --- a/arch/sh/kernel/cpu/Makefile +++ b/arch/sh/kernel/cpu/Makefile | |||
@@ -16,7 +16,7 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/ | |||
16 | # Common interfaces. | 16 | # Common interfaces. |
17 | 17 | ||
18 | obj-$(CONFIG_SH_ADC) += adc.o | 18 | obj-$(CONFIG_SH_ADC) += adc.o |
19 | obj-$(CONFIG_SH_CLK_CPG) += clock-cpg.o | 19 | obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o |
20 | obj-$(CONFIG_SH_FPU) += fpu.o | 20 | obj-$(CONFIG_SH_FPU) += fpu.o |
21 | obj-$(CONFIG_SH_FPU_EMU) += fpu.o | 21 | obj-$(CONFIG_SH_FPU_EMU) += fpu.o |
22 | 22 | ||
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c index 17a73ad7a20d..e2f63d68da51 100644 --- a/arch/sh/kernel/cpu/clock-cpg.c +++ b/arch/sh/kernel/cpu/clock-cpg.c | |||
@@ -2,317 +2,25 @@ | |||
2 | #include <linux/compiler.h> | 2 | #include <linux/compiler.h> |
3 | #include <linux/slab.h> | 3 | #include <linux/slab.h> |
4 | #include <linux/io.h> | 4 | #include <linux/io.h> |
5 | #include <asm/clkdev.h> | ||
5 | #include <asm/clock.h> | 6 | #include <asm/clock.h> |
6 | 7 | ||
7 | static int sh_clk_mstp32_enable(struct clk *clk) | ||
8 | { | ||
9 | __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit), | ||
10 | clk->enable_reg); | ||
11 | return 0; | ||
12 | } | ||
13 | |||
14 | static void sh_clk_mstp32_disable(struct clk *clk) | ||
15 | { | ||
16 | __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit), | ||
17 | clk->enable_reg); | ||
18 | } | ||
19 | |||
20 | static struct clk_ops sh_clk_mstp32_clk_ops = { | ||
21 | .enable = sh_clk_mstp32_enable, | ||
22 | .disable = sh_clk_mstp32_disable, | ||
23 | .recalc = followparent_recalc, | ||
24 | }; | ||
25 | |||
26 | int __init sh_clk_mstp32_register(struct clk *clks, int nr) | ||
27 | { | ||
28 | struct clk *clkp; | ||
29 | int ret = 0; | ||
30 | int k; | ||
31 | |||
32 | for (k = 0; !ret && (k < nr); k++) { | ||
33 | clkp = clks + k; | ||
34 | clkp->ops = &sh_clk_mstp32_clk_ops; | ||
35 | ret |= clk_register(clkp); | ||
36 | } | ||
37 | |||
38 | return ret; | ||
39 | } | ||
40 | |||
41 | static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate) | ||
42 | { | ||
43 | return clk_rate_table_round(clk, clk->freq_table, rate); | ||
44 | } | ||
45 | |||
46 | static int sh_clk_div6_divisors[64] = { | ||
47 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, | ||
48 | 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, | ||
49 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, | ||
50 | 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 | ||
51 | }; | ||
52 | |||
53 | static struct clk_div_mult_table sh_clk_div6_table = { | ||
54 | .divisors = sh_clk_div6_divisors, | ||
55 | .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors), | ||
56 | }; | ||
57 | |||
58 | static unsigned long sh_clk_div6_recalc(struct clk *clk) | ||
59 | { | ||
60 | struct clk_div_mult_table *table = &sh_clk_div6_table; | ||
61 | unsigned int idx; | ||
62 | |||
63 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, | ||
64 | table, NULL); | ||
65 | |||
66 | idx = __raw_readl(clk->enable_reg) & 0x003f; | ||
67 | |||
68 | return clk->freq_table[idx].frequency; | ||
69 | } | ||
70 | |||
71 | static int sh_clk_div6_set_rate(struct clk *clk, | ||
72 | unsigned long rate, int algo_id) | ||
73 | { | ||
74 | unsigned long value; | ||
75 | int idx; | ||
76 | |||
77 | idx = clk_rate_table_find(clk, clk->freq_table, rate); | ||
78 | if (idx < 0) | ||
79 | return idx; | ||
80 | |||
81 | value = __raw_readl(clk->enable_reg); | ||
82 | value &= ~0x3f; | ||
83 | value |= idx; | ||
84 | __raw_writel(value, clk->enable_reg); | ||
85 | return 0; | ||
86 | } | ||
87 | |||
88 | static int sh_clk_div6_enable(struct clk *clk) | ||
89 | { | ||
90 | unsigned long value; | ||
91 | int ret; | ||
92 | |||
93 | ret = sh_clk_div6_set_rate(clk, clk->rate, 0); | ||
94 | if (ret == 0) { | ||
95 | value = __raw_readl(clk->enable_reg); | ||
96 | value &= ~0x100; /* clear stop bit to enable clock */ | ||
97 | __raw_writel(value, clk->enable_reg); | ||
98 | } | ||
99 | return ret; | ||
100 | } | ||
101 | |||
102 | static void sh_clk_div6_disable(struct clk *clk) | ||
103 | { | ||
104 | unsigned long value; | ||
105 | |||
106 | value = __raw_readl(clk->enable_reg); | ||
107 | value |= 0x100; /* stop clock */ | ||
108 | value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */ | ||
109 | __raw_writel(value, clk->enable_reg); | ||
110 | } | ||
111 | |||
112 | static struct clk_ops sh_clk_div6_clk_ops = { | ||
113 | .recalc = sh_clk_div6_recalc, | ||
114 | .round_rate = sh_clk_div_round_rate, | ||
115 | .set_rate = sh_clk_div6_set_rate, | ||
116 | .enable = sh_clk_div6_enable, | ||
117 | .disable = sh_clk_div6_disable, | ||
118 | }; | ||
119 | |||
120 | int __init sh_clk_div6_register(struct clk *clks, int nr) | ||
121 | { | ||
122 | struct clk *clkp; | ||
123 | void *freq_table; | ||
124 | int nr_divs = sh_clk_div6_table.nr_divisors; | ||
125 | int freq_table_size = sizeof(struct cpufreq_frequency_table); | ||
126 | int ret = 0; | ||
127 | int k; | ||
128 | |||
129 | freq_table_size *= (nr_divs + 1); | ||
130 | freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL); | ||
131 | if (!freq_table) { | ||
132 | pr_err("sh_clk_div6_register: unable to alloc memory\n"); | ||
133 | return -ENOMEM; | ||
134 | } | ||
135 | |||
136 | for (k = 0; !ret && (k < nr); k++) { | ||
137 | clkp = clks + k; | ||
138 | |||
139 | clkp->ops = &sh_clk_div6_clk_ops; | ||
140 | clkp->id = -1; | ||
141 | clkp->freq_table = freq_table + (k * freq_table_size); | ||
142 | clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END; | ||
143 | |||
144 | ret = clk_register(clkp); | ||
145 | } | ||
146 | |||
147 | return ret; | ||
148 | } | ||
149 | |||
150 | static unsigned long sh_clk_div4_recalc(struct clk *clk) | ||
151 | { | ||
152 | struct clk_div4_table *d4t = clk->priv; | ||
153 | struct clk_div_mult_table *table = d4t->div_mult_table; | ||
154 | unsigned int idx; | ||
155 | |||
156 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, | ||
157 | table, &clk->arch_flags); | ||
158 | |||
159 | idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f; | ||
160 | |||
161 | return clk->freq_table[idx].frequency; | ||
162 | } | ||
163 | |||
164 | static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) | ||
165 | { | ||
166 | struct clk_div4_table *d4t = clk->priv; | ||
167 | struct clk_div_mult_table *table = d4t->div_mult_table; | ||
168 | u32 value; | ||
169 | int ret; | ||
170 | |||
171 | if (!strcmp("pll_clk", parent->name)) | ||
172 | value = __raw_readl(clk->enable_reg) & ~(1 << 7); | ||
173 | else | ||
174 | value = __raw_readl(clk->enable_reg) | (1 << 7); | ||
175 | |||
176 | ret = clk_reparent(clk, parent); | ||
177 | if (ret < 0) | ||
178 | return ret; | ||
179 | |||
180 | __raw_writel(value, clk->enable_reg); | ||
181 | |||
182 | /* Rebiuld the frequency table */ | ||
183 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, | ||
184 | table, &clk->arch_flags); | ||
185 | |||
186 | return 0; | ||
187 | } | ||
188 | |||
189 | static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id) | ||
190 | { | ||
191 | struct clk_div4_table *d4t = clk->priv; | ||
192 | unsigned long value; | ||
193 | int idx = clk_rate_table_find(clk, clk->freq_table, rate); | ||
194 | if (idx < 0) | ||
195 | return idx; | ||
196 | |||
197 | value = __raw_readl(clk->enable_reg); | ||
198 | value &= ~(0xf << clk->enable_bit); | ||
199 | value |= (idx << clk->enable_bit); | ||
200 | __raw_writel(value, clk->enable_reg); | ||
201 | |||
202 | if (d4t->kick) | ||
203 | d4t->kick(clk); | ||
204 | |||
205 | return 0; | ||
206 | } | ||
207 | |||
208 | static int sh_clk_div4_enable(struct clk *clk) | ||
209 | { | ||
210 | __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg); | ||
211 | return 0; | ||
212 | } | ||
213 | |||
214 | static void sh_clk_div4_disable(struct clk *clk) | ||
215 | { | ||
216 | __raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg); | ||
217 | } | ||
218 | |||
219 | static struct clk_ops sh_clk_div4_clk_ops = { | ||
220 | .recalc = sh_clk_div4_recalc, | ||
221 | .set_rate = sh_clk_div4_set_rate, | ||
222 | .round_rate = sh_clk_div_round_rate, | ||
223 | }; | ||
224 | |||
225 | static struct clk_ops sh_clk_div4_enable_clk_ops = { | ||
226 | .recalc = sh_clk_div4_recalc, | ||
227 | .set_rate = sh_clk_div4_set_rate, | ||
228 | .round_rate = sh_clk_div_round_rate, | ||
229 | .enable = sh_clk_div4_enable, | ||
230 | .disable = sh_clk_div4_disable, | ||
231 | }; | ||
232 | |||
233 | static struct clk_ops sh_clk_div4_reparent_clk_ops = { | ||
234 | .recalc = sh_clk_div4_recalc, | ||
235 | .set_rate = sh_clk_div4_set_rate, | ||
236 | .round_rate = sh_clk_div_round_rate, | ||
237 | .enable = sh_clk_div4_enable, | ||
238 | .disable = sh_clk_div4_disable, | ||
239 | .set_parent = sh_clk_div4_set_parent, | ||
240 | }; | ||
241 | |||
242 | static int __init sh_clk_div4_register_ops(struct clk *clks, int nr, | ||
243 | struct clk_div4_table *table, struct clk_ops *ops) | ||
244 | { | ||
245 | struct clk *clkp; | ||
246 | void *freq_table; | ||
247 | int nr_divs = table->div_mult_table->nr_divisors; | ||
248 | int freq_table_size = sizeof(struct cpufreq_frequency_table); | ||
249 | int ret = 0; | ||
250 | int k; | ||
251 | |||
252 | freq_table_size *= (nr_divs + 1); | ||
253 | freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL); | ||
254 | if (!freq_table) { | ||
255 | pr_err("sh_clk_div4_register: unable to alloc memory\n"); | ||
256 | return -ENOMEM; | ||
257 | } | ||
258 | |||
259 | for (k = 0; !ret && (k < nr); k++) { | ||
260 | clkp = clks + k; | ||
261 | |||
262 | clkp->ops = ops; | ||
263 | clkp->id = -1; | ||
264 | clkp->priv = table; | ||
265 | |||
266 | clkp->freq_table = freq_table + (k * freq_table_size); | ||
267 | clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END; | ||
268 | |||
269 | ret = clk_register(clkp); | ||
270 | } | ||
271 | |||
272 | return ret; | ||
273 | } | ||
274 | |||
275 | int __init sh_clk_div4_register(struct clk *clks, int nr, | ||
276 | struct clk_div4_table *table) | ||
277 | { | ||
278 | return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops); | ||
279 | } | ||
280 | |||
281 | int __init sh_clk_div4_enable_register(struct clk *clks, int nr, | ||
282 | struct clk_div4_table *table) | ||
283 | { | ||
284 | return sh_clk_div4_register_ops(clks, nr, table, | ||
285 | &sh_clk_div4_enable_clk_ops); | ||
286 | } | ||
287 | |||
288 | int __init sh_clk_div4_reparent_register(struct clk *clks, int nr, | ||
289 | struct clk_div4_table *table) | ||
290 | { | ||
291 | return sh_clk_div4_register_ops(clks, nr, table, | ||
292 | &sh_clk_div4_reparent_clk_ops); | ||
293 | } | ||
294 | |||
295 | #ifdef CONFIG_SH_CLK_CPG_LEGACY | ||
296 | static struct clk master_clk = { | 8 | static struct clk master_clk = { |
297 | .name = "master_clk", | ||
298 | .flags = CLK_ENABLE_ON_INIT, | 9 | .flags = CLK_ENABLE_ON_INIT, |
299 | .rate = CONFIG_SH_PCLK_FREQ, | 10 | .rate = CONFIG_SH_PCLK_FREQ, |
300 | }; | 11 | }; |
301 | 12 | ||
302 | static struct clk peripheral_clk = { | 13 | static struct clk peripheral_clk = { |
303 | .name = "peripheral_clk", | ||
304 | .parent = &master_clk, | 14 | .parent = &master_clk, |
305 | .flags = CLK_ENABLE_ON_INIT, | 15 | .flags = CLK_ENABLE_ON_INIT, |
306 | }; | 16 | }; |
307 | 17 | ||
308 | static struct clk bus_clk = { | 18 | static struct clk bus_clk = { |
309 | .name = "bus_clk", | ||
310 | .parent = &master_clk, | 19 | .parent = &master_clk, |
311 | .flags = CLK_ENABLE_ON_INIT, | 20 | .flags = CLK_ENABLE_ON_INIT, |
312 | }; | 21 | }; |
313 | 22 | ||
314 | static struct clk cpu_clk = { | 23 | static struct clk cpu_clk = { |
315 | .name = "cpu_clk", | ||
316 | .parent = &master_clk, | 24 | .parent = &master_clk, |
317 | .flags = CLK_ENABLE_ON_INIT, | 25 | .flags = CLK_ENABLE_ON_INIT, |
318 | }; | 26 | }; |
@@ -327,6 +35,16 @@ static struct clk *onchip_clocks[] = { | |||
327 | &cpu_clk, | 35 | &cpu_clk, |
328 | }; | 36 | }; |
329 | 37 | ||
38 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | ||
39 | |||
40 | static struct clk_lookup lookups[] = { | ||
41 | /* main clocks */ | ||
42 | CLKDEV_CON_ID("master_clk", &master_clk), | ||
43 | CLKDEV_CON_ID("peripheral_clk", &peripheral_clk), | ||
44 | CLKDEV_CON_ID("bus_clk", &bus_clk), | ||
45 | CLKDEV_CON_ID("cpu_clk", &cpu_clk), | ||
46 | }; | ||
47 | |||
330 | int __init __deprecated cpg_clk_init(void) | 48 | int __init __deprecated cpg_clk_init(void) |
331 | { | 49 | { |
332 | int i, ret = 0; | 50 | int i, ret = 0; |
@@ -338,6 +56,8 @@ int __init __deprecated cpg_clk_init(void) | |||
338 | ret |= clk_register(clk); | 56 | ret |= clk_register(clk); |
339 | } | 57 | } |
340 | 58 | ||
59 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
60 | |||
341 | clk_add_alias("tmu_fck", NULL, "peripheral_clk", NULL); | 61 | clk_add_alias("tmu_fck", NULL, "peripheral_clk", NULL); |
342 | clk_add_alias("mtu2_fck", NULL, "peripheral_clk", NULL); | 62 | clk_add_alias("mtu2_fck", NULL, "peripheral_clk", NULL); |
343 | clk_add_alias("cmt_fck", NULL, "peripheral_clk", NULL); | 63 | clk_add_alias("cmt_fck", NULL, "peripheral_clk", NULL); |
@@ -354,4 +74,3 @@ int __init __weak arch_clk_init(void) | |||
354 | { | 74 | { |
355 | return cpg_clk_init(); | 75 | return cpg_clk_init(); |
356 | } | 76 | } |
357 | #endif /* CONFIG_SH_CPG_CLK_LEGACY */ | ||
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c index a725c7feb747..50f887dda565 100644 --- a/arch/sh/kernel/cpu/clock.c +++ b/arch/sh/kernel/cpu/clock.c | |||
@@ -16,500 +16,10 @@ | |||
16 | */ | 16 | */ |
17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/module.h> | ||
20 | #include <linux/mutex.h> | ||
21 | #include <linux/list.h> | ||
22 | #include <linux/kobject.h> | ||
23 | #include <linux/sysdev.h> | ||
24 | #include <linux/seq_file.h> | ||
25 | #include <linux/err.h> | ||
26 | #include <linux/platform_device.h> | ||
27 | #include <linux/debugfs.h> | ||
28 | #include <linux/cpufreq.h> | ||
29 | #include <linux/clk.h> | 19 | #include <linux/clk.h> |
30 | #include <asm/clock.h> | 20 | #include <asm/clock.h> |
31 | #include <asm/machvec.h> | 21 | #include <asm/machvec.h> |
32 | 22 | ||
33 | static LIST_HEAD(clock_list); | ||
34 | static DEFINE_SPINLOCK(clock_lock); | ||
35 | static DEFINE_MUTEX(clock_list_sem); | ||
36 | |||
37 | void clk_rate_table_build(struct clk *clk, | ||
38 | struct cpufreq_frequency_table *freq_table, | ||
39 | int nr_freqs, | ||
40 | struct clk_div_mult_table *src_table, | ||
41 | unsigned long *bitmap) | ||
42 | { | ||
43 | unsigned long mult, div; | ||
44 | unsigned long freq; | ||
45 | int i; | ||
46 | |||
47 | for (i = 0; i < nr_freqs; i++) { | ||
48 | div = 1; | ||
49 | mult = 1; | ||
50 | |||
51 | if (src_table->divisors && i < src_table->nr_divisors) | ||
52 | div = src_table->divisors[i]; | ||
53 | |||
54 | if (src_table->multipliers && i < src_table->nr_multipliers) | ||
55 | mult = src_table->multipliers[i]; | ||
56 | |||
57 | if (!div || !mult || (bitmap && !test_bit(i, bitmap))) | ||
58 | freq = CPUFREQ_ENTRY_INVALID; | ||
59 | else | ||
60 | freq = clk->parent->rate * mult / div; | ||
61 | |||
62 | freq_table[i].index = i; | ||
63 | freq_table[i].frequency = freq; | ||
64 | } | ||
65 | |||
66 | /* Termination entry */ | ||
67 | freq_table[i].index = i; | ||
68 | freq_table[i].frequency = CPUFREQ_TABLE_END; | ||
69 | } | ||
70 | |||
71 | long clk_rate_table_round(struct clk *clk, | ||
72 | struct cpufreq_frequency_table *freq_table, | ||
73 | unsigned long rate) | ||
74 | { | ||
75 | unsigned long rate_error, rate_error_prev = ~0UL; | ||
76 | unsigned long rate_best_fit = rate; | ||
77 | unsigned long highest, lowest; | ||
78 | int i; | ||
79 | |||
80 | highest = lowest = 0; | ||
81 | |||
82 | for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { | ||
83 | unsigned long freq = freq_table[i].frequency; | ||
84 | |||
85 | if (freq == CPUFREQ_ENTRY_INVALID) | ||
86 | continue; | ||
87 | |||
88 | if (freq > highest) | ||
89 | highest = freq; | ||
90 | if (freq < lowest) | ||
91 | lowest = freq; | ||
92 | |||
93 | rate_error = abs(freq - rate); | ||
94 | if (rate_error < rate_error_prev) { | ||
95 | rate_best_fit = freq; | ||
96 | rate_error_prev = rate_error; | ||
97 | } | ||
98 | |||
99 | if (rate_error == 0) | ||
100 | break; | ||
101 | } | ||
102 | |||
103 | if (rate >= highest) | ||
104 | rate_best_fit = highest; | ||
105 | if (rate <= lowest) | ||
106 | rate_best_fit = lowest; | ||
107 | |||
108 | return rate_best_fit; | ||
109 | } | ||
110 | |||
111 | int clk_rate_table_find(struct clk *clk, | ||
112 | struct cpufreq_frequency_table *freq_table, | ||
113 | unsigned long rate) | ||
114 | { | ||
115 | int i; | ||
116 | |||
117 | for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { | ||
118 | unsigned long freq = freq_table[i].frequency; | ||
119 | |||
120 | if (freq == CPUFREQ_ENTRY_INVALID) | ||
121 | continue; | ||
122 | |||
123 | if (freq == rate) | ||
124 | return i; | ||
125 | } | ||
126 | |||
127 | return -ENOENT; | ||
128 | } | ||
129 | |||
130 | /* Used for clocks that always have same value as the parent clock */ | ||
131 | unsigned long followparent_recalc(struct clk *clk) | ||
132 | { | ||
133 | return clk->parent ? clk->parent->rate : 0; | ||
134 | } | ||
135 | |||
136 | int clk_reparent(struct clk *child, struct clk *parent) | ||
137 | { | ||
138 | list_del_init(&child->sibling); | ||
139 | if (parent) | ||
140 | list_add(&child->sibling, &parent->children); | ||
141 | child->parent = parent; | ||
142 | |||
143 | /* now do the debugfs renaming to reattach the child | ||
144 | to the proper parent */ | ||
145 | |||
146 | return 0; | ||
147 | } | ||
148 | |||
149 | /* Propagate rate to children */ | ||
150 | void propagate_rate(struct clk *tclk) | ||
151 | { | ||
152 | struct clk *clkp; | ||
153 | |||
154 | list_for_each_entry(clkp, &tclk->children, sibling) { | ||
155 | if (clkp->ops && clkp->ops->recalc) | ||
156 | clkp->rate = clkp->ops->recalc(clkp); | ||
157 | |||
158 | propagate_rate(clkp); | ||
159 | } | ||
160 | } | ||
161 | |||
162 | static void __clk_disable(struct clk *clk) | ||
163 | { | ||
164 | if (clk->usecount == 0) { | ||
165 | printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", | ||
166 | clk->name); | ||
167 | WARN_ON(1); | ||
168 | return; | ||
169 | } | ||
170 | |||
171 | if (!(--clk->usecount)) { | ||
172 | if (likely(clk->ops && clk->ops->disable)) | ||
173 | clk->ops->disable(clk); | ||
174 | if (likely(clk->parent)) | ||
175 | __clk_disable(clk->parent); | ||
176 | } | ||
177 | } | ||
178 | |||
179 | void clk_disable(struct clk *clk) | ||
180 | { | ||
181 | unsigned long flags; | ||
182 | |||
183 | if (!clk) | ||
184 | return; | ||
185 | |||
186 | spin_lock_irqsave(&clock_lock, flags); | ||
187 | __clk_disable(clk); | ||
188 | spin_unlock_irqrestore(&clock_lock, flags); | ||
189 | } | ||
190 | EXPORT_SYMBOL_GPL(clk_disable); | ||
191 | |||
192 | static int __clk_enable(struct clk *clk) | ||
193 | { | ||
194 | int ret = 0; | ||
195 | |||
196 | if (clk->usecount++ == 0) { | ||
197 | if (clk->parent) { | ||
198 | ret = __clk_enable(clk->parent); | ||
199 | if (unlikely(ret)) | ||
200 | goto err; | ||
201 | } | ||
202 | |||
203 | if (clk->ops && clk->ops->enable) { | ||
204 | ret = clk->ops->enable(clk); | ||
205 | if (ret) { | ||
206 | if (clk->parent) | ||
207 | __clk_disable(clk->parent); | ||
208 | goto err; | ||
209 | } | ||
210 | } | ||
211 | } | ||
212 | |||
213 | return ret; | ||
214 | err: | ||
215 | clk->usecount--; | ||
216 | return ret; | ||
217 | } | ||
218 | |||
219 | int clk_enable(struct clk *clk) | ||
220 | { | ||
221 | unsigned long flags; | ||
222 | int ret; | ||
223 | |||
224 | if (!clk) | ||
225 | return -EINVAL; | ||
226 | |||
227 | spin_lock_irqsave(&clock_lock, flags); | ||
228 | ret = __clk_enable(clk); | ||
229 | spin_unlock_irqrestore(&clock_lock, flags); | ||
230 | |||
231 | return ret; | ||
232 | } | ||
233 | EXPORT_SYMBOL_GPL(clk_enable); | ||
234 | |||
235 | static LIST_HEAD(root_clks); | ||
236 | |||
237 | /** | ||
238 | * recalculate_root_clocks - recalculate and propagate all root clocks | ||
239 | * | ||
240 | * Recalculates all root clocks (clocks with no parent), which if the | ||
241 | * clock's .recalc is set correctly, should also propagate their rates. | ||
242 | * Called at init. | ||
243 | */ | ||
244 | void recalculate_root_clocks(void) | ||
245 | { | ||
246 | struct clk *clkp; | ||
247 | |||
248 | list_for_each_entry(clkp, &root_clks, sibling) { | ||
249 | if (clkp->ops && clkp->ops->recalc) | ||
250 | clkp->rate = clkp->ops->recalc(clkp); | ||
251 | propagate_rate(clkp); | ||
252 | } | ||
253 | } | ||
254 | |||
255 | int clk_register(struct clk *clk) | ||
256 | { | ||
257 | if (clk == NULL || IS_ERR(clk)) | ||
258 | return -EINVAL; | ||
259 | |||
260 | /* | ||
261 | * trap out already registered clocks | ||
262 | */ | ||
263 | if (clk->node.next || clk->node.prev) | ||
264 | return 0; | ||
265 | |||
266 | mutex_lock(&clock_list_sem); | ||
267 | |||
268 | INIT_LIST_HEAD(&clk->children); | ||
269 | clk->usecount = 0; | ||
270 | |||
271 | if (clk->parent) | ||
272 | list_add(&clk->sibling, &clk->parent->children); | ||
273 | else | ||
274 | list_add(&clk->sibling, &root_clks); | ||
275 | |||
276 | list_add(&clk->node, &clock_list); | ||
277 | if (clk->ops && clk->ops->init) | ||
278 | clk->ops->init(clk); | ||
279 | mutex_unlock(&clock_list_sem); | ||
280 | |||
281 | return 0; | ||
282 | } | ||
283 | EXPORT_SYMBOL_GPL(clk_register); | ||
284 | |||
285 | void clk_unregister(struct clk *clk) | ||
286 | { | ||
287 | mutex_lock(&clock_list_sem); | ||
288 | list_del(&clk->sibling); | ||
289 | list_del(&clk->node); | ||
290 | mutex_unlock(&clock_list_sem); | ||
291 | } | ||
292 | EXPORT_SYMBOL_GPL(clk_unregister); | ||
293 | |||
294 | static void clk_enable_init_clocks(void) | ||
295 | { | ||
296 | struct clk *clkp; | ||
297 | |||
298 | list_for_each_entry(clkp, &clock_list, node) | ||
299 | if (clkp->flags & CLK_ENABLE_ON_INIT) | ||
300 | clk_enable(clkp); | ||
301 | } | ||
302 | |||
303 | unsigned long clk_get_rate(struct clk *clk) | ||
304 | { | ||
305 | return clk->rate; | ||
306 | } | ||
307 | EXPORT_SYMBOL_GPL(clk_get_rate); | ||
308 | |||
309 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
310 | { | ||
311 | return clk_set_rate_ex(clk, rate, 0); | ||
312 | } | ||
313 | EXPORT_SYMBOL_GPL(clk_set_rate); | ||
314 | |||
315 | int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id) | ||
316 | { | ||
317 | int ret = -EOPNOTSUPP; | ||
318 | unsigned long flags; | ||
319 | |||
320 | spin_lock_irqsave(&clock_lock, flags); | ||
321 | |||
322 | if (likely(clk->ops && clk->ops->set_rate)) { | ||
323 | ret = clk->ops->set_rate(clk, rate, algo_id); | ||
324 | if (ret != 0) | ||
325 | goto out_unlock; | ||
326 | } else { | ||
327 | clk->rate = rate; | ||
328 | ret = 0; | ||
329 | } | ||
330 | |||
331 | if (clk->ops && clk->ops->recalc) | ||
332 | clk->rate = clk->ops->recalc(clk); | ||
333 | |||
334 | propagate_rate(clk); | ||
335 | |||
336 | out_unlock: | ||
337 | spin_unlock_irqrestore(&clock_lock, flags); | ||
338 | |||
339 | return ret; | ||
340 | } | ||
341 | EXPORT_SYMBOL_GPL(clk_set_rate_ex); | ||
342 | |||
343 | int clk_set_parent(struct clk *clk, struct clk *parent) | ||
344 | { | ||
345 | unsigned long flags; | ||
346 | int ret = -EINVAL; | ||
347 | |||
348 | if (!parent || !clk) | ||
349 | return ret; | ||
350 | if (clk->parent == parent) | ||
351 | return 0; | ||
352 | |||
353 | spin_lock_irqsave(&clock_lock, flags); | ||
354 | if (clk->usecount == 0) { | ||
355 | if (clk->ops->set_parent) | ||
356 | ret = clk->ops->set_parent(clk, parent); | ||
357 | else | ||
358 | ret = clk_reparent(clk, parent); | ||
359 | |||
360 | if (ret == 0) { | ||
361 | pr_debug("clock: set parent of %s to %s (new rate %ld)\n", | ||
362 | clk->name, clk->parent->name, clk->rate); | ||
363 | if (clk->ops->recalc) | ||
364 | clk->rate = clk->ops->recalc(clk); | ||
365 | propagate_rate(clk); | ||
366 | } | ||
367 | } else | ||
368 | ret = -EBUSY; | ||
369 | spin_unlock_irqrestore(&clock_lock, flags); | ||
370 | |||
371 | return ret; | ||
372 | } | ||
373 | EXPORT_SYMBOL_GPL(clk_set_parent); | ||
374 | |||
375 | struct clk *clk_get_parent(struct clk *clk) | ||
376 | { | ||
377 | return clk->parent; | ||
378 | } | ||
379 | EXPORT_SYMBOL_GPL(clk_get_parent); | ||
380 | |||
381 | long clk_round_rate(struct clk *clk, unsigned long rate) | ||
382 | { | ||
383 | if (likely(clk->ops && clk->ops->round_rate)) { | ||
384 | unsigned long flags, rounded; | ||
385 | |||
386 | spin_lock_irqsave(&clock_lock, flags); | ||
387 | rounded = clk->ops->round_rate(clk, rate); | ||
388 | spin_unlock_irqrestore(&clock_lock, flags); | ||
389 | |||
390 | return rounded; | ||
391 | } | ||
392 | |||
393 | return clk_get_rate(clk); | ||
394 | } | ||
395 | EXPORT_SYMBOL_GPL(clk_round_rate); | ||
396 | |||
397 | /* | ||
398 | * Returns a clock. Note that we first try to use device id on the bus | ||
399 | * and clock name. If this fails, we try to use clock name only. | ||
400 | */ | ||
401 | struct clk *clk_get(struct device *dev, const char *id) | ||
402 | { | ||
403 | const char *dev_id = dev ? dev_name(dev) : NULL; | ||
404 | struct clk *p, *clk = ERR_PTR(-ENOENT); | ||
405 | int idno; | ||
406 | |||
407 | clk = clk_get_sys(dev_id, id); | ||
408 | if (clk && !IS_ERR(clk)) | ||
409 | return clk; | ||
410 | |||
411 | if (dev == NULL || dev->bus != &platform_bus_type) | ||
412 | idno = -1; | ||
413 | else | ||
414 | idno = to_platform_device(dev)->id; | ||
415 | |||
416 | mutex_lock(&clock_list_sem); | ||
417 | list_for_each_entry(p, &clock_list, node) { | ||
418 | if (p->name && p->id == idno && | ||
419 | strcmp(id, p->name) == 0 && try_module_get(p->owner)) { | ||
420 | clk = p; | ||
421 | goto found; | ||
422 | } | ||
423 | } | ||
424 | |||
425 | list_for_each_entry(p, &clock_list, node) { | ||
426 | if (p->name && | ||
427 | strcmp(id, p->name) == 0 && try_module_get(p->owner)) { | ||
428 | clk = p; | ||
429 | break; | ||
430 | } | ||
431 | } | ||
432 | |||
433 | found: | ||
434 | mutex_unlock(&clock_list_sem); | ||
435 | |||
436 | return clk; | ||
437 | } | ||
438 | EXPORT_SYMBOL_GPL(clk_get); | ||
439 | |||
440 | void clk_put(struct clk *clk) | ||
441 | { | ||
442 | if (clk && !IS_ERR(clk)) | ||
443 | module_put(clk->owner); | ||
444 | } | ||
445 | EXPORT_SYMBOL_GPL(clk_put); | ||
446 | |||
447 | #ifdef CONFIG_PM | ||
448 | static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state) | ||
449 | { | ||
450 | static pm_message_t prev_state; | ||
451 | struct clk *clkp; | ||
452 | |||
453 | switch (state.event) { | ||
454 | case PM_EVENT_ON: | ||
455 | /* Resumeing from hibernation */ | ||
456 | if (prev_state.event != PM_EVENT_FREEZE) | ||
457 | break; | ||
458 | |||
459 | list_for_each_entry(clkp, &clock_list, node) { | ||
460 | if (likely(clkp->ops)) { | ||
461 | unsigned long rate = clkp->rate; | ||
462 | |||
463 | if (likely(clkp->ops->set_parent)) | ||
464 | clkp->ops->set_parent(clkp, | ||
465 | clkp->parent); | ||
466 | if (likely(clkp->ops->set_rate)) | ||
467 | clkp->ops->set_rate(clkp, | ||
468 | rate, NO_CHANGE); | ||
469 | else if (likely(clkp->ops->recalc)) | ||
470 | clkp->rate = clkp->ops->recalc(clkp); | ||
471 | } | ||
472 | } | ||
473 | break; | ||
474 | case PM_EVENT_FREEZE: | ||
475 | break; | ||
476 | case PM_EVENT_SUSPEND: | ||
477 | break; | ||
478 | } | ||
479 | |||
480 | prev_state = state; | ||
481 | return 0; | ||
482 | } | ||
483 | |||
484 | static int clks_sysdev_resume(struct sys_device *dev) | ||
485 | { | ||
486 | return clks_sysdev_suspend(dev, PMSG_ON); | ||
487 | } | ||
488 | |||
489 | static struct sysdev_class clks_sysdev_class = { | ||
490 | .name = "clks", | ||
491 | }; | ||
492 | |||
493 | static struct sysdev_driver clks_sysdev_driver = { | ||
494 | .suspend = clks_sysdev_suspend, | ||
495 | .resume = clks_sysdev_resume, | ||
496 | }; | ||
497 | |||
498 | static struct sys_device clks_sysdev_dev = { | ||
499 | .cls = &clks_sysdev_class, | ||
500 | }; | ||
501 | |||
502 | static int __init clk_sysdev_init(void) | ||
503 | { | ||
504 | sysdev_class_register(&clks_sysdev_class); | ||
505 | sysdev_driver_register(&clks_sysdev_class, &clks_sysdev_driver); | ||
506 | sysdev_register(&clks_sysdev_dev); | ||
507 | |||
508 | return 0; | ||
509 | } | ||
510 | subsys_initcall(clk_sysdev_init); | ||
511 | #endif | ||
512 | |||
513 | int __init clk_init(void) | 23 | int __init clk_init(void) |
514 | { | 24 | { |
515 | int ret; | 25 | int ret; |
@@ -539,89 +49,19 @@ int __init clk_init(void) | |||
539 | } | 49 | } |
540 | 50 | ||
541 | /* | 51 | /* |
542 | * debugfs support to trace clock tree hierarchy and attributes | 52 | * Returns a clock. Note that we first try to use device id on the bus |
53 | * and clock name. If this fails, we try to use clock name only. | ||
543 | */ | 54 | */ |
544 | static struct dentry *clk_debugfs_root; | 55 | struct clk *clk_get(struct device *dev, const char *con_id) |
545 | |||
546 | static int clk_debugfs_register_one(struct clk *c) | ||
547 | { | 56 | { |
548 | int err; | 57 | const char *dev_id = dev ? dev_name(dev) : NULL; |
549 | struct dentry *d, *child, *child_tmp; | ||
550 | struct clk *pa = c->parent; | ||
551 | char s[255]; | ||
552 | char *p = s; | ||
553 | |||
554 | p += sprintf(p, "%s", c->name); | ||
555 | if (c->id >= 0) | ||
556 | sprintf(p, ":%d", c->id); | ||
557 | d = debugfs_create_dir(s, pa ? pa->dentry : clk_debugfs_root); | ||
558 | if (!d) | ||
559 | return -ENOMEM; | ||
560 | c->dentry = d; | ||
561 | |||
562 | d = debugfs_create_u8("usecount", S_IRUGO, c->dentry, (u8 *)&c->usecount); | ||
563 | if (!d) { | ||
564 | err = -ENOMEM; | ||
565 | goto err_out; | ||
566 | } | ||
567 | d = debugfs_create_u32("rate", S_IRUGO, c->dentry, (u32 *)&c->rate); | ||
568 | if (!d) { | ||
569 | err = -ENOMEM; | ||
570 | goto err_out; | ||
571 | } | ||
572 | d = debugfs_create_x32("flags", S_IRUGO, c->dentry, (u32 *)&c->flags); | ||
573 | if (!d) { | ||
574 | err = -ENOMEM; | ||
575 | goto err_out; | ||
576 | } | ||
577 | return 0; | ||
578 | 58 | ||
579 | err_out: | 59 | return clk_get_sys(dev_id, con_id); |
580 | d = c->dentry; | ||
581 | list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child) | ||
582 | debugfs_remove(child); | ||
583 | debugfs_remove(c->dentry); | ||
584 | return err; | ||
585 | } | 60 | } |
61 | EXPORT_SYMBOL_GPL(clk_get); | ||
586 | 62 | ||
587 | static int clk_debugfs_register(struct clk *c) | 63 | void clk_put(struct clk *clk) |
588 | { | 64 | { |
589 | int err; | ||
590 | struct clk *pa = c->parent; | ||
591 | |||
592 | if (pa && !pa->dentry) { | ||
593 | err = clk_debugfs_register(pa); | ||
594 | if (err) | ||
595 | return err; | ||
596 | } | ||
597 | |||
598 | if (!c->dentry && c->name) { | ||
599 | err = clk_debugfs_register_one(c); | ||
600 | if (err) | ||
601 | return err; | ||
602 | } | ||
603 | return 0; | ||
604 | } | 65 | } |
66 | EXPORT_SYMBOL_GPL(clk_put); | ||
605 | 67 | ||
606 | static int __init clk_debugfs_init(void) | ||
607 | { | ||
608 | struct clk *c; | ||
609 | struct dentry *d; | ||
610 | int err; | ||
611 | |||
612 | d = debugfs_create_dir("clock", NULL); | ||
613 | if (!d) | ||
614 | return -ENOMEM; | ||
615 | clk_debugfs_root = d; | ||
616 | |||
617 | list_for_each_entry(c, &clock_list, node) { | ||
618 | err = clk_debugfs_register(c); | ||
619 | if (err) | ||
620 | goto err_out; | ||
621 | } | ||
622 | return 0; | ||
623 | err_out: | ||
624 | debugfs_remove_recursive(clk_debugfs_root); | ||
625 | return err; | ||
626 | } | ||
627 | late_initcall(clk_debugfs_init); | ||
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c index 6b80850294da..4eabc68cd753 100644 --- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c +++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c | |||
@@ -12,9 +12,10 @@ | |||
12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/err.h> | 14 | #include <linux/err.h> |
15 | #include <linux/io.h> | ||
16 | #include <asm/clkdev.h> | ||
15 | #include <asm/clock.h> | 17 | #include <asm/clock.h> |
16 | #include <asm/freq.h> | 18 | #include <asm/freq.h> |
17 | #include <asm/io.h> | ||
18 | 19 | ||
19 | #define CPG2_FRQCR3 0xfe0a0018 | 20 | #define CPG2_FRQCR3 0xfe0a0018 |
20 | 21 | ||
@@ -45,7 +46,6 @@ static struct clk_ops sh4202_emi_clk_ops = { | |||
45 | }; | 46 | }; |
46 | 47 | ||
47 | static struct clk sh4202_emi_clk = { | 48 | static struct clk sh4202_emi_clk = { |
48 | .name = "emi_clk", | ||
49 | .flags = CLK_ENABLE_ON_INIT, | 49 | .flags = CLK_ENABLE_ON_INIT, |
50 | .ops = &sh4202_emi_clk_ops, | 50 | .ops = &sh4202_emi_clk_ops, |
51 | }; | 51 | }; |
@@ -61,7 +61,6 @@ static struct clk_ops sh4202_femi_clk_ops = { | |||
61 | }; | 61 | }; |
62 | 62 | ||
63 | static struct clk sh4202_femi_clk = { | 63 | static struct clk sh4202_femi_clk = { |
64 | .name = "femi_clk", | ||
65 | .flags = CLK_ENABLE_ON_INIT, | 64 | .flags = CLK_ENABLE_ON_INIT, |
66 | .ops = &sh4202_femi_clk_ops, | 65 | .ops = &sh4202_femi_clk_ops, |
67 | }; | 66 | }; |
@@ -139,7 +138,6 @@ static struct clk_ops sh4202_shoc_clk_ops = { | |||
139 | }; | 138 | }; |
140 | 139 | ||
141 | static struct clk sh4202_shoc_clk = { | 140 | static struct clk sh4202_shoc_clk = { |
142 | .name = "shoc_clk", | ||
143 | .flags = CLK_ENABLE_ON_INIT, | 141 | .flags = CLK_ENABLE_ON_INIT, |
144 | .ops = &sh4202_shoc_clk_ops, | 142 | .ops = &sh4202_shoc_clk_ops, |
145 | }; | 143 | }; |
@@ -150,6 +148,15 @@ static struct clk *sh4202_onchip_clocks[] = { | |||
150 | &sh4202_shoc_clk, | 148 | &sh4202_shoc_clk, |
151 | }; | 149 | }; |
152 | 150 | ||
151 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | ||
152 | |||
153 | static struct clk_lookup lookups[] = { | ||
154 | /* main clocks */ | ||
155 | CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk), | ||
156 | CLKDEV_CON_ID("femi_clk", &sh4202_femi_clk), | ||
157 | CLKDEV_CON_ID("shoc_clk", &sh4202_shoc_clk), | ||
158 | }; | ||
159 | |||
153 | int __init arch_clk_init(void) | 160 | int __init arch_clk_init(void) |
154 | { | 161 | { |
155 | struct clk *clk; | 162 | struct clk *clk; |
@@ -167,5 +174,7 @@ int __init arch_clk_init(void) | |||
167 | 174 | ||
168 | clk_put(clk); | 175 | clk_put(clk); |
169 | 176 | ||
177 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
178 | |||
170 | return ret; | 179 | return ret; |
171 | } | 180 | } |
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c index a066c438b404..71291ae201b9 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c | |||
@@ -37,8 +37,6 @@ | |||
37 | 37 | ||
38 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ | 38 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ |
39 | static struct clk r_clk = { | 39 | static struct clk r_clk = { |
40 | .name = "rclk", | ||
41 | .id = -1, | ||
42 | .rate = 32768, | 40 | .rate = 32768, |
43 | }; | 41 | }; |
44 | 42 | ||
@@ -47,8 +45,6 @@ static struct clk r_clk = { | |||
47 | * from the platform code. | 45 | * from the platform code. |
48 | */ | 46 | */ |
49 | struct clk extal_clk = { | 47 | struct clk extal_clk = { |
50 | .name = "extal", | ||
51 | .id = -1, | ||
52 | .rate = 33333333, | 48 | .rate = 33333333, |
53 | }; | 49 | }; |
54 | 50 | ||
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = { | |||
70 | }; | 66 | }; |
71 | 67 | ||
72 | static struct clk dll_clk = { | 68 | static struct clk dll_clk = { |
73 | .name = "dll_clk", | ||
74 | .id = -1, | ||
75 | .ops = &dll_clk_ops, | 69 | .ops = &dll_clk_ops, |
76 | .parent = &r_clk, | 70 | .parent = &r_clk, |
77 | .flags = CLK_ENABLE_ON_INIT, | 71 | .flags = CLK_ENABLE_ON_INIT, |
@@ -92,8 +86,6 @@ static struct clk_ops pll_clk_ops = { | |||
92 | }; | 86 | }; |
93 | 87 | ||
94 | static struct clk pll_clk = { | 88 | static struct clk pll_clk = { |
95 | .name = "pll_clk", | ||
96 | .id = -1, | ||
97 | .ops = &pll_clk_ops, | 89 | .ops = &pll_clk_ops, |
98 | .flags = CLK_ENABLE_ON_INIT, | 90 | .flags = CLK_ENABLE_ON_INIT, |
99 | }; | 91 | }; |
@@ -122,18 +114,18 @@ static struct clk_div4_table div4_table = { | |||
122 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, | 114 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, |
123 | DIV4_SIUA, DIV4_SIUB, DIV4_NR }; | 115 | DIV4_SIUA, DIV4_SIUB, DIV4_NR }; |
124 | 116 | ||
125 | #define DIV4(_str, _reg, _bit, _mask, _flags) \ | 117 | #define DIV4(_reg, _bit, _mask, _flags) \ |
126 | SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) | 118 | SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) |
127 | 119 | ||
128 | struct clk div4_clks[DIV4_NR] = { | 120 | struct clk div4_clks[DIV4_NR] = { |
129 | [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), | 121 | [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), |
130 | [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), | 122 | [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), |
131 | [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), | 123 | [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), |
132 | [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), | 124 | [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), |
133 | [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), | 125 | [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), |
134 | [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), | 126 | [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), |
135 | [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), | 127 | [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0), |
136 | [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), | 128 | [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0), |
137 | }; | 129 | }; |
138 | 130 | ||
139 | enum { DIV6_V, DIV6_NR }; | 131 | enum { DIV6_V, DIV6_NR }; |
@@ -142,61 +134,148 @@ struct clk div6_clks[DIV6_NR] = { | |||
142 | [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), | 134 | [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), |
143 | }; | 135 | }; |
144 | 136 | ||
145 | #define MSTP(_str, _parent, _reg, _bit, _flags) \ | 137 | #define MSTP(_parent, _reg, _bit, _flags) \ |
146 | SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) | 138 | SH_CLK_MSTP32(_parent, _reg, _bit, _flags) |
147 | 139 | ||
148 | static struct clk mstp_clks[] = { | 140 | enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026, |
149 | MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), | 141 | MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016, |
150 | MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), | 142 | MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010, |
151 | MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), | 143 | MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001, |
152 | MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), | 144 | MSTP109, MSTP108, MSTP100, |
153 | MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), | 145 | MSTP225, MSTP224, MSTP218, MSTP217, MSTP216, |
154 | MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), | 146 | MSTP214, MSTP213, MSTP212, MSTP211, MSTP208, |
155 | MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), | 147 | MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, |
156 | MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), | 148 | MSTP_NR }; |
157 | MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), | 149 | |
158 | MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), | 150 | static struct clk mstp_clks[MSTP_NR] = { |
159 | MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), | 151 | [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), |
160 | MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0), | 152 | [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), |
161 | MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0), | 153 | [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), |
162 | MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), | 154 | [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), |
163 | MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), | 155 | [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), |
164 | MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), | 156 | [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), |
165 | SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0), | 157 | [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), |
166 | SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0), | 158 | [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), |
167 | SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0), | 159 | [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0), |
168 | SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 4, 0), | 160 | [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0), |
169 | MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0), | 161 | [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0), |
170 | MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), | 162 | [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0), |
171 | MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0), | 163 | [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0), |
172 | 164 | [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0), | |
173 | MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), | 165 | [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0), |
174 | MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0), | 166 | [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0), |
175 | 167 | [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0), | |
176 | MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0), | 168 | [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0), |
177 | MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0), | 169 | [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0), |
178 | MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), | 170 | [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0), |
179 | MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), | 171 | [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0), |
180 | MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0), | 172 | [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0), |
181 | MSTP("keysc0", &r_clk, MSTPCR2, 14, 0), | 173 | [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0), |
182 | MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0), | 174 | |
183 | MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0), | 175 | [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0), |
184 | MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), | 176 | [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0), |
185 | MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0), | 177 | |
186 | MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), | 178 | [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0), |
187 | MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), | 179 | [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0), |
188 | MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), | 180 | [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0), |
189 | MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), | 181 | [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0), |
190 | MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), | 182 | [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0), |
191 | MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), | 183 | [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0), |
192 | MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), | 184 | [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0), |
185 | [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0), | ||
186 | [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0), | ||
187 | [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0), | ||
188 | [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), | ||
189 | [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), | ||
190 | [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), | ||
191 | [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), | ||
192 | [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), | ||
193 | [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), | ||
194 | [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0), | ||
193 | }; | 195 | }; |
194 | 196 | ||
195 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | 197 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
196 | 198 | ||
197 | static struct clk_lookup lookups[] = { | 199 | static struct clk_lookup lookups[] = { |
200 | /* main clocks */ | ||
201 | CLKDEV_CON_ID("rclk", &r_clk), | ||
202 | CLKDEV_CON_ID("extal", &extal_clk), | ||
203 | CLKDEV_CON_ID("dll_clk", &dll_clk), | ||
204 | CLKDEV_CON_ID("pll_clk", &pll_clk), | ||
205 | |||
206 | /* DIV4 clocks */ | ||
207 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | ||
208 | CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), | ||
209 | CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), | ||
210 | CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), | ||
211 | CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), | ||
212 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), | ||
213 | CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]), | ||
214 | CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]), | ||
215 | |||
198 | /* DIV6 clocks */ | 216 | /* DIV6 clocks */ |
199 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), | 217 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), |
218 | |||
219 | /* MSTP32 clocks */ | ||
220 | CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]), | ||
221 | CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]), | ||
222 | CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]), | ||
223 | CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]), | ||
224 | CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]), | ||
225 | CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]), | ||
226 | CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]), | ||
227 | CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]), | ||
228 | CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]), | ||
229 | CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]), | ||
230 | CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]), | ||
231 | CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]), | ||
232 | CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]), | ||
233 | CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]), | ||
234 | CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]), | ||
235 | CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]), | ||
236 | { | ||
237 | /* SCIF0 */ | ||
238 | .dev_id = "sh-sci.0", | ||
239 | .con_id = "sci_fck", | ||
240 | .clk = &mstp_clks[MSTP007], | ||
241 | }, { | ||
242 | /* SCIF1 */ | ||
243 | .dev_id = "sh-sci.1", | ||
244 | .con_id = "sci_fck", | ||
245 | .clk = &mstp_clks[MSTP006], | ||
246 | }, { | ||
247 | /* SCIF2 */ | ||
248 | .dev_id = "sh-sci.2", | ||
249 | .con_id = "sci_fck", | ||
250 | .clk = &mstp_clks[MSTP005], | ||
251 | }, { | ||
252 | /* SCIF3 */ | ||
253 | .dev_id = "sh-sci.3", | ||
254 | .con_id = "sci_fck", | ||
255 | .clk = &mstp_clks[MSTP004], | ||
256 | }, | ||
257 | CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]), | ||
258 | CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]), | ||
259 | CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]), | ||
260 | CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]), | ||
261 | CLKDEV_CON_ID("i2c1", &mstp_clks[MSTP108]), | ||
262 | CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]), | ||
263 | CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]), | ||
264 | CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]), | ||
265 | CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]), | ||
266 | CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]), | ||
267 | CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]), | ||
268 | CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]), | ||
269 | CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]), | ||
270 | CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]), | ||
271 | CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]), | ||
272 | CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]), | ||
273 | CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]), | ||
274 | CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]), | ||
275 | CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]), | ||
276 | CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]), | ||
277 | CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]), | ||
278 | CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]), | ||
200 | }; | 279 | }; |
201 | 280 | ||
202 | int __init arch_clk_init(void) | 281 | int __init arch_clk_init(void) |
@@ -221,7 +300,7 @@ int __init arch_clk_init(void) | |||
221 | ret = sh_clk_div6_register(div6_clks, DIV6_NR); | 300 | ret = sh_clk_div6_register(div6_clks, DIV6_NR); |
222 | 301 | ||
223 | if (!ret) | 302 | if (!ret) |
224 | ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); | 303 | ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); |
225 | 304 | ||
226 | return ret; | 305 | return ret; |
227 | } | 306 | } |
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c index 44cc5a0965d9..7ce5bbcd4084 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c | |||
@@ -37,8 +37,6 @@ | |||
37 | 37 | ||
38 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ | 38 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ |
39 | static struct clk r_clk = { | 39 | static struct clk r_clk = { |
40 | .name = "rclk", | ||
41 | .id = -1, | ||
42 | .rate = 32768, | 40 | .rate = 32768, |
43 | }; | 41 | }; |
44 | 42 | ||
@@ -47,8 +45,6 @@ static struct clk r_clk = { | |||
47 | * from the platform code. | 45 | * from the platform code. |
48 | */ | 46 | */ |
49 | struct clk extal_clk = { | 47 | struct clk extal_clk = { |
50 | .name = "extal", | ||
51 | .id = -1, | ||
52 | .rate = 33333333, | 48 | .rate = 33333333, |
53 | }; | 49 | }; |
54 | 50 | ||
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = { | |||
70 | }; | 66 | }; |
71 | 67 | ||
72 | static struct clk dll_clk = { | 68 | static struct clk dll_clk = { |
73 | .name = "dll_clk", | ||
74 | .id = -1, | ||
75 | .ops = &dll_clk_ops, | 69 | .ops = &dll_clk_ops, |
76 | .parent = &r_clk, | 70 | .parent = &r_clk, |
77 | .flags = CLK_ENABLE_ON_INIT, | 71 | .flags = CLK_ENABLE_ON_INIT, |
@@ -95,8 +89,6 @@ static struct clk_ops pll_clk_ops = { | |||
95 | }; | 89 | }; |
96 | 90 | ||
97 | static struct clk pll_clk = { | 91 | static struct clk pll_clk = { |
98 | .name = "pll_clk", | ||
99 | .id = -1, | ||
100 | .ops = &pll_clk_ops, | 92 | .ops = &pll_clk_ops, |
101 | .flags = CLK_ENABLE_ON_INIT, | 93 | .flags = CLK_ENABLE_ON_INIT, |
102 | }; | 94 | }; |
@@ -125,18 +117,18 @@ static struct clk_div4_table div4_table = { | |||
125 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, | 117 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, |
126 | DIV4_SIUA, DIV4_SIUB, DIV4_NR }; | 118 | DIV4_SIUA, DIV4_SIUB, DIV4_NR }; |
127 | 119 | ||
128 | #define DIV4(_str, _reg, _bit, _mask, _flags) \ | 120 | #define DIV4(_reg, _bit, _mask, _flags) \ |
129 | SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) | 121 | SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) |
130 | 122 | ||
131 | struct clk div4_clks[DIV4_NR] = { | 123 | struct clk div4_clks[DIV4_NR] = { |
132 | [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), | 124 | [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), |
133 | [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), | 125 | [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), |
134 | [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), | 126 | [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), |
135 | [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), | 127 | [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), |
136 | [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), | 128 | [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), |
137 | [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), | 129 | [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), |
138 | [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), | 130 | [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0), |
139 | [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), | 131 | [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0), |
140 | }; | 132 | }; |
141 | 133 | ||
142 | enum { DIV6_V, DIV6_NR }; | 134 | enum { DIV6_V, DIV6_NR }; |
@@ -145,58 +137,134 @@ struct clk div6_clks[DIV6_NR] = { | |||
145 | [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), | 137 | [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), |
146 | }; | 138 | }; |
147 | 139 | ||
148 | #define MSTP(_str, _parent, _reg, _bit, _flags) \ | 140 | #define MSTP(_parent, _reg, _bit, _flags) \ |
149 | SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) | 141 | SH_CLK_MSTP32(_parent, _reg, _bit, _flags) |
150 | 142 | ||
151 | static struct clk mstp_clks[] = { | 143 | enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026, |
144 | MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016, | ||
145 | MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010, | ||
146 | MSTP007, MSTP006, MSTP005, MSTP002, MSTP001, | ||
147 | MSTP109, MSTP100, | ||
148 | MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217, | ||
149 | MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, | ||
150 | MSTP_NR }; | ||
151 | |||
152 | static struct clk mstp_clks[MSTP_NR] = { | ||
152 | /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ | 153 | /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ |
153 | MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), | 154 | [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), |
154 | MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), | 155 | [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), |
155 | MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), | 156 | [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), |
156 | MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), | 157 | [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), |
157 | MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), | 158 | [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), |
158 | MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), | 159 | [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0), |
159 | MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), | 160 | [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0), |
160 | MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), | 161 | [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0), |
161 | MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), | 162 | [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0), |
162 | MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), | 163 | [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0), |
163 | MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), | 164 | [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0), |
164 | MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0), | 165 | [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0), |
165 | MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0), | 166 | [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0), |
166 | MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), | 167 | [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0), |
167 | MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), | 168 | [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0), |
168 | MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), | 169 | [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0), |
169 | SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0), | 170 | [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0), |
170 | SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0), | 171 | [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0), |
171 | SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0), | 172 | [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0), |
172 | MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), | 173 | [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0), |
173 | MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0), | 174 | [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0), |
174 | 175 | ||
175 | MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), | 176 | [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0), |
176 | 177 | ||
177 | MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0), | 178 | [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0), |
178 | MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0), | 179 | [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0), |
179 | MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0), | 180 | [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0), |
180 | MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0), | 181 | [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0), |
181 | MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0), | 182 | [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0), |
182 | MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), | 183 | [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0), |
183 | MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), | 184 | [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0), |
184 | MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), | 185 | [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0), |
185 | MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0), | 186 | [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), |
186 | MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), | 187 | [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), |
187 | MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), | 188 | [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), |
188 | MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), | 189 | [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), |
189 | MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), | 190 | [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), |
190 | MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), | 191 | [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), |
191 | MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), | 192 | [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0), |
192 | MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), | ||
193 | }; | 193 | }; |
194 | 194 | ||
195 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | 195 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
196 | 196 | ||
197 | static struct clk_lookup lookups[] = { | 197 | static struct clk_lookup lookups[] = { |
198 | /* main clocks */ | ||
199 | CLKDEV_CON_ID("rclk", &r_clk), | ||
200 | CLKDEV_CON_ID("extal", &extal_clk), | ||
201 | CLKDEV_CON_ID("dll_clk", &dll_clk), | ||
202 | CLKDEV_CON_ID("pll_clk", &pll_clk), | ||
203 | |||
204 | /* DIV4 clocks */ | ||
205 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | ||
206 | CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), | ||
207 | CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), | ||
208 | CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), | ||
209 | CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), | ||
210 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), | ||
211 | CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]), | ||
212 | CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]), | ||
213 | |||
198 | /* DIV6 clocks */ | 214 | /* DIV6 clocks */ |
199 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), | 215 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), |
216 | |||
217 | /* MSTP32 clocks */ | ||
218 | CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]), | ||
219 | CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]), | ||
220 | CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]), | ||
221 | CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]), | ||
222 | CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]), | ||
223 | CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]), | ||
224 | CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]), | ||
225 | CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]), | ||
226 | CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]), | ||
227 | CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]), | ||
228 | CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]), | ||
229 | CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]), | ||
230 | CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]), | ||
231 | CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]), | ||
232 | CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]), | ||
233 | CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]), | ||
234 | { | ||
235 | /* SCIF0 */ | ||
236 | .dev_id = "sh-sci.0", | ||
237 | .con_id = "sci_fck", | ||
238 | .clk = &mstp_clks[MSTP007], | ||
239 | }, { | ||
240 | /* SCIF1 */ | ||
241 | .dev_id = "sh-sci.1", | ||
242 | .con_id = "sci_fck", | ||
243 | .clk = &mstp_clks[MSTP006], | ||
244 | }, { | ||
245 | /* SCIF2 */ | ||
246 | .dev_id = "sh-sci.2", | ||
247 | .con_id = "sci_fck", | ||
248 | .clk = &mstp_clks[MSTP005], | ||
249 | }, | ||
250 | CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]), | ||
251 | CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]), | ||
252 | CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]), | ||
253 | CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]), | ||
254 | CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]), | ||
255 | CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]), | ||
256 | CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]), | ||
257 | CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]), | ||
258 | CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]), | ||
259 | CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]), | ||
260 | CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]), | ||
261 | CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]), | ||
262 | CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]), | ||
263 | CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]), | ||
264 | CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]), | ||
265 | CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]), | ||
266 | CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]), | ||
267 | CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]), | ||
200 | }; | 268 | }; |
201 | 269 | ||
202 | int __init arch_clk_init(void) | 270 | int __init arch_clk_init(void) |
@@ -221,7 +289,7 @@ int __init arch_clk_init(void) | |||
221 | ret = sh_clk_div6_register(div6_clks, DIV6_NR); | 289 | ret = sh_clk_div6_register(div6_clks, DIV6_NR); |
222 | 290 | ||
223 | if (!ret) | 291 | if (!ret) |
224 | ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); | 292 | ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); |
225 | 293 | ||
226 | return ret; | 294 | return ret; |
227 | } | 295 | } |
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c index 2798ceaa648f..2030f3d9fac7 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c | |||
@@ -37,8 +37,6 @@ | |||
37 | 37 | ||
38 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ | 38 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ |
39 | static struct clk r_clk = { | 39 | static struct clk r_clk = { |
40 | .name = "rclk", | ||
41 | .id = -1, | ||
42 | .rate = 32768, | 40 | .rate = 32768, |
43 | }; | 41 | }; |
44 | 42 | ||
@@ -47,8 +45,6 @@ static struct clk r_clk = { | |||
47 | * from the platform code. | 45 | * from the platform code. |
48 | */ | 46 | */ |
49 | struct clk extal_clk = { | 47 | struct clk extal_clk = { |
50 | .name = "extal", | ||
51 | .id = -1, | ||
52 | .rate = 33333333, | 48 | .rate = 33333333, |
53 | }; | 49 | }; |
54 | 50 | ||
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = { | |||
70 | }; | 66 | }; |
71 | 67 | ||
72 | static struct clk dll_clk = { | 68 | static struct clk dll_clk = { |
73 | .name = "dll_clk", | ||
74 | .id = -1, | ||
75 | .ops = &dll_clk_ops, | 69 | .ops = &dll_clk_ops, |
76 | .parent = &r_clk, | 70 | .parent = &r_clk, |
77 | .flags = CLK_ENABLE_ON_INIT, | 71 | .flags = CLK_ENABLE_ON_INIT, |
@@ -95,8 +89,6 @@ static struct clk_ops pll_clk_ops = { | |||
95 | }; | 89 | }; |
96 | 90 | ||
97 | static struct clk pll_clk = { | 91 | static struct clk pll_clk = { |
98 | .name = "pll_clk", | ||
99 | .id = -1, | ||
100 | .ops = &pll_clk_ops, | 92 | .ops = &pll_clk_ops, |
101 | .flags = CLK_ENABLE_ON_INIT, | 93 | .flags = CLK_ENABLE_ON_INIT, |
102 | }; | 94 | }; |
@@ -122,31 +114,31 @@ static struct clk_div4_table div4_table = { | |||
122 | .div_mult_table = &div4_div_mult_table, | 114 | .div_mult_table = &div4_div_mult_table, |
123 | }; | 115 | }; |
124 | 116 | ||
125 | #define DIV4(_str, _reg, _bit, _mask, _flags) \ | 117 | #define DIV4(_reg, _bit, _mask, _flags) \ |
126 | SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) | 118 | SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) |
127 | 119 | ||
128 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; | 120 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; |
129 | 121 | ||
130 | struct clk div4_clks[DIV4_NR] = { | 122 | struct clk div4_clks[DIV4_NR] = { |
131 | [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), | 123 | [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), |
132 | [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), | 124 | [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), |
133 | [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), | 125 | [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), |
134 | [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), | 126 | [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), |
135 | [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), | 127 | [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), |
136 | [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), | 128 | [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), |
137 | }; | 129 | }; |
138 | 130 | ||
139 | enum { DIV4_IRDA, DIV4_ENABLE_NR }; | 131 | enum { DIV4_IRDA, DIV4_ENABLE_NR }; |
140 | 132 | ||
141 | struct clk div4_enable_clks[DIV4_ENABLE_NR] = { | 133 | struct clk div4_enable_clks[DIV4_ENABLE_NR] = { |
142 | [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0), | 134 | [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0), |
143 | }; | 135 | }; |
144 | 136 | ||
145 | enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; | 137 | enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; |
146 | 138 | ||
147 | struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { | 139 | struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { |
148 | [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), | 140 | [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0), |
149 | [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), | 141 | [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0), |
150 | }; | 142 | }; |
151 | 143 | ||
152 | enum { DIV6_V, DIV6_NR }; | 144 | enum { DIV6_V, DIV6_NR }; |
@@ -186,6 +178,23 @@ static struct clk mstp_clks[HWBLK_NR] = { | |||
186 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | 178 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
187 | 179 | ||
188 | static struct clk_lookup lookups[] = { | 180 | static struct clk_lookup lookups[] = { |
181 | /* main clocks */ | ||
182 | CLKDEV_CON_ID("rclk", &r_clk), | ||
183 | CLKDEV_CON_ID("extal", &extal_clk), | ||
184 | CLKDEV_CON_ID("dll_clk", &dll_clk), | ||
185 | CLKDEV_CON_ID("pll_clk", &pll_clk), | ||
186 | |||
187 | /* DIV4 clocks */ | ||
188 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | ||
189 | CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), | ||
190 | CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), | ||
191 | CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), | ||
192 | CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), | ||
193 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), | ||
194 | CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]), | ||
195 | CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]), | ||
196 | CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]), | ||
197 | |||
189 | /* DIV6 clocks */ | 198 | /* DIV6 clocks */ |
190 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), | 199 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), |
191 | 200 | ||
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c index 500715f78142..d3938f0d3702 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c | |||
@@ -38,8 +38,6 @@ | |||
38 | 38 | ||
39 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ | 39 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ |
40 | static struct clk r_clk = { | 40 | static struct clk r_clk = { |
41 | .name = "rclk", | ||
42 | .id = -1, | ||
43 | .rate = 32768, | 41 | .rate = 32768, |
44 | }; | 42 | }; |
45 | 43 | ||
@@ -48,8 +46,6 @@ static struct clk r_clk = { | |||
48 | * from the platform code. | 46 | * from the platform code. |
49 | */ | 47 | */ |
50 | struct clk extal_clk = { | 48 | struct clk extal_clk = { |
51 | .name = "extal", | ||
52 | .id = -1, | ||
53 | .rate = 33333333, | 49 | .rate = 33333333, |
54 | }; | 50 | }; |
55 | 51 | ||
@@ -71,8 +67,6 @@ static struct clk_ops dll_clk_ops = { | |||
71 | }; | 67 | }; |
72 | 68 | ||
73 | static struct clk dll_clk = { | 69 | static struct clk dll_clk = { |
74 | .name = "dll_clk", | ||
75 | .id = -1, | ||
76 | .ops = &dll_clk_ops, | 70 | .ops = &dll_clk_ops, |
77 | .parent = &r_clk, | 71 | .parent = &r_clk, |
78 | .flags = CLK_ENABLE_ON_INIT, | 72 | .flags = CLK_ENABLE_ON_INIT, |
@@ -96,8 +90,6 @@ static struct clk_ops pll_clk_ops = { | |||
96 | }; | 90 | }; |
97 | 91 | ||
98 | static struct clk pll_clk = { | 92 | static struct clk pll_clk = { |
99 | .name = "pll_clk", | ||
100 | .id = -1, | ||
101 | .ops = &pll_clk_ops, | 93 | .ops = &pll_clk_ops, |
102 | .flags = CLK_ENABLE_ON_INIT, | 94 | .flags = CLK_ENABLE_ON_INIT, |
103 | }; | 95 | }; |
@@ -125,29 +117,29 @@ static struct clk_div4_table div4_table = { | |||
125 | 117 | ||
126 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; | 118 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; |
127 | 119 | ||
128 | #define DIV4(_str, _reg, _bit, _mask, _flags) \ | 120 | #define DIV4(_reg, _bit, _mask, _flags) \ |
129 | SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) | 121 | SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) |
130 | 122 | ||
131 | struct clk div4_clks[DIV4_NR] = { | 123 | struct clk div4_clks[DIV4_NR] = { |
132 | [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), | 124 | [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), |
133 | [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), | 125 | [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), |
134 | [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), | 126 | [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), |
135 | [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), | 127 | [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), |
136 | [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), | 128 | [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), |
137 | [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0), | 129 | [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0), |
138 | }; | 130 | }; |
139 | 131 | ||
140 | enum { DIV4_IRDA, DIV4_ENABLE_NR }; | 132 | enum { DIV4_IRDA, DIV4_ENABLE_NR }; |
141 | 133 | ||
142 | struct clk div4_enable_clks[DIV4_ENABLE_NR] = { | 134 | struct clk div4_enable_clks[DIV4_ENABLE_NR] = { |
143 | [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0), | 135 | [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0), |
144 | }; | 136 | }; |
145 | 137 | ||
146 | enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; | 138 | enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; |
147 | 139 | ||
148 | struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { | 140 | struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { |
149 | [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0), | 141 | [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0), |
150 | [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0), | 142 | [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0), |
151 | }; | 143 | }; |
152 | enum { DIV6_V, DIV6_NR }; | 144 | enum { DIV6_V, DIV6_NR }; |
153 | 145 | ||
@@ -211,6 +203,23 @@ static struct clk mstp_clks[] = { | |||
211 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | 203 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
212 | 204 | ||
213 | static struct clk_lookup lookups[] = { | 205 | static struct clk_lookup lookups[] = { |
206 | /* main clocks */ | ||
207 | CLKDEV_CON_ID("rclk", &r_clk), | ||
208 | CLKDEV_CON_ID("extal", &extal_clk), | ||
209 | CLKDEV_CON_ID("dll_clk", &dll_clk), | ||
210 | CLKDEV_CON_ID("pll_clk", &pll_clk), | ||
211 | |||
212 | /* DIV4 clocks */ | ||
213 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | ||
214 | CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), | ||
215 | CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), | ||
216 | CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), | ||
217 | CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), | ||
218 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), | ||
219 | CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]), | ||
220 | CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]), | ||
221 | CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]), | ||
222 | |||
214 | /* DIV6 clocks */ | 223 | /* DIV6 clocks */ |
215 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), | 224 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), |
216 | 225 | ||
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c index 2bbff53fcd87..2d9700c6b53a 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c | |||
@@ -41,8 +41,6 @@ | |||
41 | 41 | ||
42 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ | 42 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ |
43 | static struct clk r_clk = { | 43 | static struct clk r_clk = { |
44 | .name = "rclk", | ||
45 | .id = -1, | ||
46 | .rate = 32768, | 44 | .rate = 32768, |
47 | }; | 45 | }; |
48 | 46 | ||
@@ -51,8 +49,6 @@ static struct clk r_clk = { | |||
51 | * from the platform code. | 49 | * from the platform code. |
52 | */ | 50 | */ |
53 | struct clk extal_clk = { | 51 | struct clk extal_clk = { |
54 | .name = "extal", | ||
55 | .id = -1, | ||
56 | .rate = 33333333, | 52 | .rate = 33333333, |
57 | }; | 53 | }; |
58 | 54 | ||
@@ -76,8 +72,6 @@ static struct clk_ops fll_clk_ops = { | |||
76 | }; | 72 | }; |
77 | 73 | ||
78 | static struct clk fll_clk = { | 74 | static struct clk fll_clk = { |
79 | .name = "fll_clk", | ||
80 | .id = -1, | ||
81 | .ops = &fll_clk_ops, | 75 | .ops = &fll_clk_ops, |
82 | .parent = &r_clk, | 76 | .parent = &r_clk, |
83 | .flags = CLK_ENABLE_ON_INIT, | 77 | .flags = CLK_ENABLE_ON_INIT, |
@@ -98,8 +92,6 @@ static struct clk_ops pll_clk_ops = { | |||
98 | }; | 92 | }; |
99 | 93 | ||
100 | static struct clk pll_clk = { | 94 | static struct clk pll_clk = { |
101 | .name = "pll_clk", | ||
102 | .id = -1, | ||
103 | .ops = &pll_clk_ops, | 95 | .ops = &pll_clk_ops, |
104 | .flags = CLK_ENABLE_ON_INIT, | 96 | .flags = CLK_ENABLE_ON_INIT, |
105 | }; | 97 | }; |
@@ -115,8 +107,6 @@ static struct clk_ops div3_clk_ops = { | |||
115 | }; | 107 | }; |
116 | 108 | ||
117 | static struct clk div3_clk = { | 109 | static struct clk div3_clk = { |
118 | .name = "div3_clk", | ||
119 | .id = -1, | ||
120 | .ops = &div3_clk_ops, | 110 | .ops = &div3_clk_ops, |
121 | .parent = &pll_clk, | 111 | .parent = &pll_clk, |
122 | }; | 112 | }; |
@@ -153,15 +143,15 @@ static struct clk_div4_table div4_table = { | |||
153 | 143 | ||
154 | enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; | 144 | enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; |
155 | 145 | ||
156 | #define DIV4(_str, _reg, _bit, _mask, _flags) \ | 146 | #define DIV4(_reg, _bit, _mask, _flags) \ |
157 | SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) | 147 | SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) |
158 | 148 | ||
159 | struct clk div4_clks[DIV4_NR] = { | 149 | struct clk div4_clks[DIV4_NR] = { |
160 | [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), | 150 | [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), |
161 | [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), | 151 | [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), |
162 | [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), | 152 | [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), |
163 | [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0), | 153 | [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0), |
164 | [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), | 154 | [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), |
165 | }; | 155 | }; |
166 | 156 | ||
167 | enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR }; | 157 | enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR }; |
@@ -234,6 +224,20 @@ static struct clk mstp_clks[HWBLK_NR] = { | |||
234 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | 224 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
235 | 225 | ||
236 | static struct clk_lookup lookups[] = { | 226 | static struct clk_lookup lookups[] = { |
227 | /* main clocks */ | ||
228 | CLKDEV_CON_ID("rclk", &r_clk), | ||
229 | CLKDEV_CON_ID("extal", &extal_clk), | ||
230 | CLKDEV_CON_ID("fll_clk", &fll_clk), | ||
231 | CLKDEV_CON_ID("pll_clk", &pll_clk), | ||
232 | CLKDEV_CON_ID("div3_clk", &div3_clk), | ||
233 | |||
234 | /* DIV4 clocks */ | ||
235 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | ||
236 | CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), | ||
237 | CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), | ||
238 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), | ||
239 | CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]), | ||
240 | |||
237 | /* DIV6 clocks */ | 241 | /* DIV6 clocks */ |
238 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), | 242 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), |
239 | CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]), | 243 | CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]), |
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c index 86aae60677dc..0a752bd324ac 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c | |||
@@ -12,6 +12,7 @@ | |||
12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
15 | #include <asm/clkdev.h> | ||
15 | #include <asm/clock.h> | 16 | #include <asm/clock.h> |
16 | #include <asm/freq.h> | 17 | #include <asm/freq.h> |
17 | 18 | ||
@@ -87,7 +88,6 @@ static struct clk_ops sh7757_shyway_clk_ops = { | |||
87 | }; | 88 | }; |
88 | 89 | ||
89 | static struct clk sh7757_shyway_clk = { | 90 | static struct clk sh7757_shyway_clk = { |
90 | .name = "shyway_clk", | ||
91 | .flags = CLK_ENABLE_ON_INIT, | 91 | .flags = CLK_ENABLE_ON_INIT, |
92 | .ops = &sh7757_shyway_clk_ops, | 92 | .ops = &sh7757_shyway_clk_ops, |
93 | }; | 93 | }; |
@@ -100,6 +100,13 @@ static struct clk *sh7757_onchip_clocks[] = { | |||
100 | &sh7757_shyway_clk, | 100 | &sh7757_shyway_clk, |
101 | }; | 101 | }; |
102 | 102 | ||
103 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | ||
104 | |||
105 | static struct clk_lookup lookups[] = { | ||
106 | /* main clocks */ | ||
107 | CLKDEV_CON_ID("shyway_clk", &sh7757_shyway_clk), | ||
108 | }; | ||
109 | |||
103 | static int __init sh7757_clk_init(void) | 110 | static int __init sh7757_clk_init(void) |
104 | { | 111 | { |
105 | struct clk *clk = clk_get(NULL, "master_clk"); | 112 | struct clk *clk = clk_get(NULL, "master_clk"); |
@@ -123,6 +130,8 @@ static int __init sh7757_clk_init(void) | |||
123 | 130 | ||
124 | clk_put(clk); | 131 | clk_put(clk); |
125 | 132 | ||
133 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
134 | |||
126 | return 0; | 135 | return 0; |
127 | } | 136 | } |
128 | 137 | ||
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c index 9f401163e71e..1f1df48008cd 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c | |||
@@ -12,6 +12,8 @@ | |||
12 | */ | 12 | */ |
13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
15 | #include <linux/io.h> | ||
16 | #include <asm/clkdev.h> | ||
15 | #include <asm/clock.h> | 17 | #include <asm/clock.h> |
16 | #include <asm/freq.h> | 18 | #include <asm/freq.h> |
17 | #include <asm/io.h> | 19 | #include <asm/io.h> |
@@ -77,7 +79,6 @@ static struct clk_ops sh7763_shyway_clk_ops = { | |||
77 | }; | 79 | }; |
78 | 80 | ||
79 | static struct clk sh7763_shyway_clk = { | 81 | static struct clk sh7763_shyway_clk = { |
80 | .name = "shyway_clk", | ||
81 | .flags = CLK_ENABLE_ON_INIT, | 82 | .flags = CLK_ENABLE_ON_INIT, |
82 | .ops = &sh7763_shyway_clk_ops, | 83 | .ops = &sh7763_shyway_clk_ops, |
83 | }; | 84 | }; |
@@ -90,6 +91,13 @@ static struct clk *sh7763_onchip_clocks[] = { | |||
90 | &sh7763_shyway_clk, | 91 | &sh7763_shyway_clk, |
91 | }; | 92 | }; |
92 | 93 | ||
94 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | ||
95 | |||
96 | static struct clk_lookup lookups[] = { | ||
97 | /* main clocks */ | ||
98 | CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk), | ||
99 | }; | ||
100 | |||
93 | int __init arch_clk_init(void) | 101 | int __init arch_clk_init(void) |
94 | { | 102 | { |
95 | struct clk *clk; | 103 | struct clk *clk; |
@@ -107,5 +115,7 @@ int __init arch_clk_init(void) | |||
107 | 115 | ||
108 | clk_put(clk); | 116 | clk_put(clk); |
109 | 117 | ||
118 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
119 | |||
110 | return ret; | 120 | return ret; |
111 | } | 121 | } |
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c index 150963a6001e..62d706350060 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c | |||
@@ -11,6 +11,8 @@ | |||
11 | */ | 11 | */ |
12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/io.h> | ||
15 | #include <asm/clkdev.h> | ||
14 | #include <asm/clock.h> | 16 | #include <asm/clock.h> |
15 | #include <asm/freq.h> | 17 | #include <asm/freq.h> |
16 | #include <asm/io.h> | 18 | #include <asm/io.h> |
@@ -83,7 +85,6 @@ static struct clk_ops sh7780_shyway_clk_ops = { | |||
83 | }; | 85 | }; |
84 | 86 | ||
85 | static struct clk sh7780_shyway_clk = { | 87 | static struct clk sh7780_shyway_clk = { |
86 | .name = "shyway_clk", | ||
87 | .flags = CLK_ENABLE_ON_INIT, | 88 | .flags = CLK_ENABLE_ON_INIT, |
88 | .ops = &sh7780_shyway_clk_ops, | 89 | .ops = &sh7780_shyway_clk_ops, |
89 | }; | 90 | }; |
@@ -96,6 +97,13 @@ static struct clk *sh7780_onchip_clocks[] = { | |||
96 | &sh7780_shyway_clk, | 97 | &sh7780_shyway_clk, |
97 | }; | 98 | }; |
98 | 99 | ||
100 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | ||
101 | |||
102 | static struct clk_lookup lookups[] = { | ||
103 | /* main clocks */ | ||
104 | CLKDEV_CON_ID("shyway_clk", &sh7780_shyway_clk), | ||
105 | }; | ||
106 | |||
99 | int __init arch_clk_init(void) | 107 | int __init arch_clk_init(void) |
100 | { | 108 | { |
101 | struct clk *clk; | 109 | struct clk *clk; |
@@ -113,5 +121,7 @@ int __init arch_clk_init(void) | |||
113 | 121 | ||
114 | clk_put(clk); | 122 | clk_put(clk); |
115 | 123 | ||
124 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
125 | |||
116 | return ret; | 126 | return ret; |
117 | } | 127 | } |
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c index 28de049a59b1..c3e458aaa2b7 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c | |||
@@ -24,8 +24,6 @@ | |||
24 | * from the platform code. | 24 | * from the platform code. |
25 | */ | 25 | */ |
26 | static struct clk extal_clk = { | 26 | static struct clk extal_clk = { |
27 | .name = "extal", | ||
28 | .id = -1, | ||
29 | .rate = 33333333, | 27 | .rate = 33333333, |
30 | }; | 28 | }; |
31 | 29 | ||
@@ -43,8 +41,6 @@ static struct clk_ops pll_clk_ops = { | |||
43 | }; | 41 | }; |
44 | 42 | ||
45 | static struct clk pll_clk = { | 43 | static struct clk pll_clk = { |
46 | .name = "pll_clk", | ||
47 | .id = -1, | ||
48 | .ops = &pll_clk_ops, | 44 | .ops = &pll_clk_ops, |
49 | .parent = &extal_clk, | 45 | .parent = &extal_clk, |
50 | .flags = CLK_ENABLE_ON_INIT, | 46 | .flags = CLK_ENABLE_ON_INIT, |
@@ -70,82 +66,149 @@ static struct clk_div4_table div4_table = { | |||
70 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, | 66 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, |
71 | DIV4_DU, DIV4_P, DIV4_NR }; | 67 | DIV4_DU, DIV4_P, DIV4_NR }; |
72 | 68 | ||
73 | #define DIV4(_str, _bit, _mask, _flags) \ | 69 | #define DIV4(_bit, _mask, _flags) \ |
74 | SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) | 70 | SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) |
75 | 71 | ||
76 | struct clk div4_clks[DIV4_NR] = { | 72 | struct clk div4_clks[DIV4_NR] = { |
77 | [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0), | 73 | [DIV4_P] = DIV4(0, 0x0f80, 0), |
78 | [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0), | 74 | [DIV4_DU] = DIV4(4, 0x0ff0, 0), |
79 | [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0), | 75 | [DIV4_GA] = DIV4(8, 0x0030, 0), |
80 | [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT), | 76 | [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT), |
81 | [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT), | 77 | [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), |
82 | [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT), | 78 | [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), |
83 | [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT), | 79 | [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT), |
84 | [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT), | 80 | [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT), |
85 | }; | 81 | }; |
86 | 82 | ||
87 | #define MSTPCR0 0xffc80030 | 83 | #define MSTPCR0 0xffc80030 |
88 | #define MSTPCR1 0xffc80034 | 84 | #define MSTPCR1 0xffc80034 |
89 | 85 | ||
90 | static struct clk mstp_clks[] = { | 86 | enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, |
87 | MSTP021, MSTP020, MSTP017, MSTP016, | ||
88 | MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002, | ||
89 | MSTP119, MSTP117, MSTP105, MSTP104, MSTP100, | ||
90 | MSTP_NR }; | ||
91 | |||
92 | static struct clk mstp_clks[MSTP_NR] = { | ||
91 | /* MSTPCR0 */ | 93 | /* MSTPCR0 */ |
92 | SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), | 94 | [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), |
93 | SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), | 95 | [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), |
94 | SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), | 96 | [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), |
95 | SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), | 97 | [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), |
96 | SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), | 98 | [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), |
97 | SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), | 99 | [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), |
98 | SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), | 100 | [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), |
99 | SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), | 101 | [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), |
100 | SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), | 102 | [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0), |
101 | SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), | 103 | [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), |
102 | SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0), | 104 | [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0), |
103 | SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0), | 105 | [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0), |
104 | SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), | 106 | [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), |
105 | SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), | 107 | [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), |
106 | SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0), | 108 | [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0), |
107 | SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), | 109 | [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), |
108 | 110 | ||
109 | /* MSTPCR1 */ | 111 | /* MSTPCR1 */ |
110 | SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0), | 112 | [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0), |
111 | SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0), | 113 | [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0), |
112 | SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), | 114 | [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0), |
113 | SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), | 115 | [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0), |
114 | SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0), | 116 | [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0), |
115 | }; | 117 | }; |
116 | 118 | ||
119 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | ||
120 | |||
117 | static struct clk_lookup lookups[] = { | 121 | static struct clk_lookup lookups[] = { |
122 | /* main clocks */ | ||
123 | CLKDEV_CON_ID("extal", &extal_clk), | ||
124 | CLKDEV_CON_ID("pll_clk", &pll_clk), | ||
125 | |||
126 | /* DIV4 clocks */ | ||
127 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), | ||
128 | CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), | ||
129 | CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]), | ||
130 | CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), | ||
131 | CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), | ||
132 | CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), | ||
133 | CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), | ||
134 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | ||
135 | |||
136 | /* MSTP32 clocks */ | ||
137 | { | ||
138 | /* SCIF5 */ | ||
139 | .dev_id = "sh-sci.5", | ||
140 | .con_id = "sci_fck", | ||
141 | .clk = &mstp_clks[MSTP029], | ||
142 | }, { | ||
143 | /* SCIF4 */ | ||
144 | .dev_id = "sh-sci.4", | ||
145 | .con_id = "sci_fck", | ||
146 | .clk = &mstp_clks[MSTP028], | ||
147 | }, { | ||
148 | /* SCIF3 */ | ||
149 | .dev_id = "sh-sci.3", | ||
150 | .con_id = "sci_fck", | ||
151 | .clk = &mstp_clks[MSTP027], | ||
152 | }, { | ||
153 | /* SCIF2 */ | ||
154 | .dev_id = "sh-sci.2", | ||
155 | .con_id = "sci_fck", | ||
156 | .clk = &mstp_clks[MSTP026], | ||
157 | }, { | ||
158 | /* SCIF1 */ | ||
159 | .dev_id = "sh-sci.1", | ||
160 | .con_id = "sci_fck", | ||
161 | .clk = &mstp_clks[MSTP025], | ||
162 | }, { | ||
163 | /* SCIF0 */ | ||
164 | .dev_id = "sh-sci.0", | ||
165 | .con_id = "sci_fck", | ||
166 | .clk = &mstp_clks[MSTP024], | ||
167 | }, | ||
168 | CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]), | ||
169 | CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]), | ||
170 | CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]), | ||
171 | CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]), | ||
172 | CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]), | ||
173 | CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]), | ||
118 | { | 174 | { |
119 | /* TMU0 */ | 175 | /* TMU0 */ |
120 | .dev_id = "sh_tmu.0", | 176 | .dev_id = "sh_tmu.0", |
121 | .con_id = "tmu_fck", | 177 | .con_id = "tmu_fck", |
122 | .clk = &mstp_clks[13], /* tmu012_fck */ | 178 | .clk = &mstp_clks[MSTP008], |
123 | }, { | 179 | }, { |
124 | /* TMU1 */ | 180 | /* TMU1 */ |
125 | .dev_id = "sh_tmu.1", | 181 | .dev_id = "sh_tmu.1", |
126 | .con_id = "tmu_fck", | 182 | .con_id = "tmu_fck", |
127 | .clk = &mstp_clks[13], | 183 | .clk = &mstp_clks[MSTP008], |
128 | }, { | 184 | }, { |
129 | /* TMU2 */ | 185 | /* TMU2 */ |
130 | .dev_id = "sh_tmu.2", | 186 | .dev_id = "sh_tmu.2", |
131 | .con_id = "tmu_fck", | 187 | .con_id = "tmu_fck", |
132 | .clk = &mstp_clks[13], | 188 | .clk = &mstp_clks[MSTP008], |
133 | }, { | 189 | }, { |
134 | /* TMU3 */ | 190 | /* TMU3 */ |
135 | .dev_id = "sh_tmu.3", | 191 | .dev_id = "sh_tmu.3", |
136 | .con_id = "tmu_fck", | 192 | .con_id = "tmu_fck", |
137 | .clk = &mstp_clks[12], /* tmu345_fck */ | 193 | .clk = &mstp_clks[MSTP009], |
138 | }, { | 194 | }, { |
139 | /* TMU4 */ | 195 | /* TMU4 */ |
140 | .dev_id = "sh_tmu.4", | 196 | .dev_id = "sh_tmu.4", |
141 | .con_id = "tmu_fck", | 197 | .con_id = "tmu_fck", |
142 | .clk = &mstp_clks[12], | 198 | .clk = &mstp_clks[MSTP009], |
143 | }, { | 199 | }, { |
144 | /* TMU5 */ | 200 | /* TMU5 */ |
145 | .dev_id = "sh_tmu.5", | 201 | .dev_id = "sh_tmu.5", |
146 | .con_id = "tmu_fck", | 202 | .con_id = "tmu_fck", |
147 | .clk = &mstp_clks[12], | 203 | .clk = &mstp_clks[MSTP009], |
148 | }, | 204 | }, |
205 | CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]), | ||
206 | CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]), | ||
207 | CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]), | ||
208 | CLKDEV_CON_ID("ubc_fck", &mstp_clks[MSTP117]), | ||
209 | CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]), | ||
210 | CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]), | ||
211 | CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]), | ||
149 | }; | 212 | }; |
150 | 213 | ||
151 | int __init arch_clk_init(void) | 214 | int __init arch_clk_init(void) |
@@ -161,7 +224,7 @@ int __init arch_clk_init(void) | |||
161 | ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), | 224 | ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), |
162 | &div4_table); | 225 | &div4_table); |
163 | if (!ret) | 226 | if (!ret) |
164 | ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); | 227 | ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); |
165 | 228 | ||
166 | return ret; | 229 | return ret; |
167 | } | 230 | } |
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c index c4a84bb2f3d9..105a6d41b569 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c | |||
@@ -23,8 +23,6 @@ | |||
23 | * from the platform code. | 23 | * from the platform code. |
24 | */ | 24 | */ |
25 | static struct clk extal_clk = { | 25 | static struct clk extal_clk = { |
26 | .name = "extal", | ||
27 | .id = -1, | ||
28 | .rate = 33333333, | 26 | .rate = 33333333, |
29 | }; | 27 | }; |
30 | 28 | ||
@@ -46,8 +44,6 @@ static struct clk_ops pll_clk_ops = { | |||
46 | }; | 44 | }; |
47 | 45 | ||
48 | static struct clk pll_clk = { | 46 | static struct clk pll_clk = { |
49 | .name = "pll_clk", | ||
50 | .id = -1, | ||
51 | .ops = &pll_clk_ops, | 47 | .ops = &pll_clk_ops, |
52 | .parent = &extal_clk, | 48 | .parent = &extal_clk, |
53 | .flags = CLK_ENABLE_ON_INIT, | 49 | .flags = CLK_ENABLE_ON_INIT, |
@@ -72,118 +68,191 @@ static struct clk_div4_table div4_table = { | |||
72 | 68 | ||
73 | enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; | 69 | enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; |
74 | 70 | ||
75 | #define DIV4(_str, _bit, _mask, _flags) \ | 71 | #define DIV4(_bit, _mask, _flags) \ |
76 | SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) | 72 | SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) |
77 | 73 | ||
78 | struct clk div4_clks[DIV4_NR] = { | 74 | struct clk div4_clks[DIV4_NR] = { |
79 | [DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0), | 75 | [DIV4_P] = DIV4(0, 0x0b40, 0), |
80 | [DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0), | 76 | [DIV4_DU] = DIV4(4, 0x0010, 0), |
81 | [DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT), | 77 | [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT), |
82 | [DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT), | 78 | [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT), |
83 | [DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT), | 79 | [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT), |
84 | [DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT), | 80 | [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT), |
85 | }; | 81 | }; |
86 | 82 | ||
87 | #define MSTPCR0 0xffc40030 | 83 | #define MSTPCR0 0xffc40030 |
88 | #define MSTPCR1 0xffc40034 | 84 | #define MSTPCR1 0xffc40034 |
89 | 85 | ||
90 | static struct clk mstp_clks[] = { | 86 | enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, |
87 | MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016, | ||
88 | MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008, | ||
89 | MSTP005, MSTP004, MSTP002, | ||
90 | MSTP112, MSTP110, MSTP109, MSTP108, | ||
91 | MSTP105, MSTP104, MSTP103, MSTP102, | ||
92 | MSTP_NR }; | ||
93 | |||
94 | static struct clk mstp_clks[MSTP_NR] = { | ||
91 | /* MSTPCR0 */ | 95 | /* MSTPCR0 */ |
92 | SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), | 96 | [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), |
93 | SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), | 97 | [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), |
94 | SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), | 98 | [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), |
95 | SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), | 99 | [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), |
96 | SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), | 100 | [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), |
97 | SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), | 101 | [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), |
98 | SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0), | 102 | [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), |
99 | SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0), | 103 | [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), |
100 | SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), | 104 | [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), |
101 | SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), | 105 | [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), |
102 | SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), | 106 | [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0), |
103 | SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), | 107 | [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), |
104 | SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0), | 108 | [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), |
105 | SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0), | 109 | [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), |
106 | SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0), | 110 | [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0), |
107 | SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0), | 111 | [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), |
108 | SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), | 112 | [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), |
109 | SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), | 113 | [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), |
110 | SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0), | 114 | [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0), |
111 | SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0), | 115 | [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0), |
112 | SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), | 116 | [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), |
113 | 117 | ||
114 | /* MSTPCR1 */ | 118 | /* MSTPCR1 */ |
115 | SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0), | 119 | [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0), |
116 | SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0), | 120 | [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0), |
117 | SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0), | 121 | [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0), |
118 | SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0), | 122 | [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0), |
119 | SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), | 123 | [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0), |
120 | SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), | 124 | [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0), |
121 | SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0), | 125 | [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0), |
122 | SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0), | 126 | [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0), |
123 | }; | 127 | }; |
124 | 128 | ||
129 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | ||
130 | |||
125 | static struct clk_lookup lookups[] = { | 131 | static struct clk_lookup lookups[] = { |
132 | /* main clocks */ | ||
133 | CLKDEV_CON_ID("extal", &extal_clk), | ||
134 | CLKDEV_CON_ID("pll_clk", &pll_clk), | ||
135 | |||
136 | /* DIV4 clocks */ | ||
137 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), | ||
138 | CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), | ||
139 | CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), | ||
140 | CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), | ||
141 | CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), | ||
142 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | ||
143 | |||
144 | /* MSTP32 clocks */ | ||
145 | { | ||
146 | /* SCIF5 */ | ||
147 | .dev_id = "sh-sci.5", | ||
148 | .con_id = "sci_fck", | ||
149 | .clk = &mstp_clks[MSTP029], | ||
150 | }, { | ||
151 | /* SCIF4 */ | ||
152 | .dev_id = "sh-sci.4", | ||
153 | .con_id = "sci_fck", | ||
154 | .clk = &mstp_clks[MSTP028], | ||
155 | }, { | ||
156 | /* SCIF3 */ | ||
157 | .dev_id = "sh-sci.3", | ||
158 | .con_id = "sci_fck", | ||
159 | .clk = &mstp_clks[MSTP027], | ||
160 | }, { | ||
161 | /* SCIF2 */ | ||
162 | .dev_id = "sh-sci.2", | ||
163 | .con_id = "sci_fck", | ||
164 | .clk = &mstp_clks[MSTP026], | ||
165 | }, { | ||
166 | /* SCIF1 */ | ||
167 | .dev_id = "sh-sci.1", | ||
168 | .con_id = "sci_fck", | ||
169 | .clk = &mstp_clks[MSTP025], | ||
170 | }, { | ||
171 | /* SCIF0 */ | ||
172 | .dev_id = "sh-sci.0", | ||
173 | .con_id = "sci_fck", | ||
174 | .clk = &mstp_clks[MSTP024], | ||
175 | }, | ||
176 | CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]), | ||
177 | CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]), | ||
178 | CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]), | ||
179 | CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]), | ||
180 | CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]), | ||
181 | CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]), | ||
182 | CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]), | ||
183 | CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]), | ||
126 | { | 184 | { |
127 | /* TMU0 */ | 185 | /* TMU0 */ |
128 | .dev_id = "sh_tmu.0", | 186 | .dev_id = "sh_tmu.0", |
129 | .con_id = "tmu_fck", | 187 | .con_id = "tmu_fck", |
130 | .clk = &mstp_clks[17], /* tmu012_fck */ | 188 | .clk = &mstp_clks[MSTP008], |
131 | }, { | 189 | }, { |
132 | /* TMU1 */ | 190 | /* TMU1 */ |
133 | .dev_id = "sh_tmu.1", | 191 | .dev_id = "sh_tmu.1", |
134 | .con_id = "tmu_fck", | 192 | .con_id = "tmu_fck", |
135 | .clk = &mstp_clks[17], | 193 | .clk = &mstp_clks[MSTP008], |
136 | }, { | 194 | }, { |
137 | /* TMU2 */ | 195 | /* TMU2 */ |
138 | .dev_id = "sh_tmu.2", | 196 | .dev_id = "sh_tmu.2", |
139 | .con_id = "tmu_fck", | 197 | .con_id = "tmu_fck", |
140 | .clk = &mstp_clks[17], | 198 | .clk = &mstp_clks[MSTP008], |
141 | }, { | 199 | }, { |
142 | /* TMU3 */ | 200 | /* TMU3 */ |
143 | .dev_id = "sh_tmu.3", | 201 | .dev_id = "sh_tmu.3", |
144 | .con_id = "tmu_fck", | 202 | .con_id = "tmu_fck", |
145 | .clk = &mstp_clks[16], /* tmu345_fck */ | 203 | .clk = &mstp_clks[MSTP009], |
146 | }, { | 204 | }, { |
147 | /* TMU4 */ | 205 | /* TMU4 */ |
148 | .dev_id = "sh_tmu.4", | 206 | .dev_id = "sh_tmu.4", |
149 | .con_id = "tmu_fck", | 207 | .con_id = "tmu_fck", |
150 | .clk = &mstp_clks[16], | 208 | .clk = &mstp_clks[MSTP009], |
151 | }, { | 209 | }, { |
152 | /* TMU5 */ | 210 | /* TMU5 */ |
153 | .dev_id = "sh_tmu.5", | 211 | .dev_id = "sh_tmu.5", |
154 | .con_id = "tmu_fck", | 212 | .con_id = "tmu_fck", |
155 | .clk = &mstp_clks[16], | 213 | .clk = &mstp_clks[MSTP009], |
156 | }, { | 214 | }, { |
157 | /* TMU6 */ | 215 | /* TMU6 */ |
158 | .dev_id = "sh_tmu.6", | 216 | .dev_id = "sh_tmu.6", |
159 | .con_id = "tmu_fck", | 217 | .con_id = "tmu_fck", |
160 | .clk = &mstp_clks[15], /* tmu678_fck */ | 218 | .clk = &mstp_clks[MSTP010], |
161 | }, { | 219 | }, { |
162 | /* TMU7 */ | 220 | /* TMU7 */ |
163 | .dev_id = "sh_tmu.7", | 221 | .dev_id = "sh_tmu.7", |
164 | .con_id = "tmu_fck", | 222 | .con_id = "tmu_fck", |
165 | .clk = &mstp_clks[15], | 223 | .clk = &mstp_clks[MSTP010], |
166 | }, { | 224 | }, { |
167 | /* TMU8 */ | 225 | /* TMU8 */ |
168 | .dev_id = "sh_tmu.8", | 226 | .dev_id = "sh_tmu.8", |
169 | .con_id = "tmu_fck", | 227 | .con_id = "tmu_fck", |
170 | .clk = &mstp_clks[15], | 228 | .clk = &mstp_clks[MSTP010], |
171 | }, { | 229 | }, { |
172 | /* TMU9 */ | 230 | /* TMU9 */ |
173 | .dev_id = "sh_tmu.9", | 231 | .dev_id = "sh_tmu.9", |
174 | .con_id = "tmu_fck", | 232 | .con_id = "tmu_fck", |
175 | .clk = &mstp_clks[14], /* tmu9_11_fck */ | 233 | .clk = &mstp_clks[MSTP011], |
176 | }, { | 234 | }, { |
177 | /* TMU10 */ | 235 | /* TMU10 */ |
178 | .dev_id = "sh_tmu.10", | 236 | .dev_id = "sh_tmu.10", |
179 | .con_id = "tmu_fck", | 237 | .con_id = "tmu_fck", |
180 | .clk = &mstp_clks[14], | 238 | .clk = &mstp_clks[MSTP011], |
181 | }, { | 239 | }, { |
182 | /* TMU11 */ | 240 | /* TMU11 */ |
183 | .dev_id = "sh_tmu.11", | 241 | .dev_id = "sh_tmu.11", |
184 | .con_id = "tmu_fck", | 242 | .con_id = "tmu_fck", |
185 | .clk = &mstp_clks[14], | 243 | .clk = &mstp_clks[MSTP011], |
186 | } | 244 | }, |
245 | CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]), | ||
246 | CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]), | ||
247 | CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]), | ||
248 | CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]), | ||
249 | CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]), | ||
250 | CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]), | ||
251 | CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]), | ||
252 | CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]), | ||
253 | CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]), | ||
254 | CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]), | ||
255 | CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]), | ||
187 | }; | 256 | }; |
188 | 257 | ||
189 | int __init arch_clk_init(void) | 258 | int __init arch_clk_init(void) |
@@ -199,7 +268,7 @@ int __init arch_clk_init(void) | |||
199 | ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), | 268 | ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), |
200 | &div4_table); | 269 | &div4_table); |
201 | if (!ret) | 270 | if (!ret) |
202 | ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); | 271 | ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); |
203 | 272 | ||
204 | return ret; | 273 | return ret; |
205 | } | 274 | } |
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c index e75c57bdfa5e..236a6282d778 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c | |||
@@ -13,9 +13,10 @@ | |||
13 | */ | 13 | */ |
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
16 | #include <linux/io.h> | ||
17 | #include <asm/clkdev.h> | ||
16 | #include <asm/clock.h> | 18 | #include <asm/clock.h> |
17 | #include <asm/freq.h> | 19 | #include <asm/freq.h> |
18 | #include <asm/io.h> | ||
19 | 20 | ||
20 | static int ifc_divisors[] = { 1, 2, 4 ,6 }; | 21 | static int ifc_divisors[] = { 1, 2, 4 ,6 }; |
21 | static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 }; | 22 | static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 }; |
@@ -94,7 +95,6 @@ static struct clk_ops shx3_shyway_clk_ops = { | |||
94 | }; | 95 | }; |
95 | 96 | ||
96 | static struct clk shx3_shyway_clk = { | 97 | static struct clk shx3_shyway_clk = { |
97 | .name = "shyway_clk", | ||
98 | .flags = CLK_ENABLE_ON_INIT, | 98 | .flags = CLK_ENABLE_ON_INIT, |
99 | .ops = &shx3_shyway_clk_ops, | 99 | .ops = &shx3_shyway_clk_ops, |
100 | }; | 100 | }; |
@@ -107,6 +107,13 @@ static struct clk *shx3_onchip_clocks[] = { | |||
107 | &shx3_shyway_clk, | 107 | &shx3_shyway_clk, |
108 | }; | 108 | }; |
109 | 109 | ||
110 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | ||
111 | |||
112 | static struct clk_lookup lookups[] = { | ||
113 | /* main clocks */ | ||
114 | CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk), | ||
115 | }; | ||
116 | |||
110 | int __init arch_clk_init(void) | 117 | int __init arch_clk_init(void) |
111 | { | 118 | { |
112 | struct clk *clk; | 119 | struct clk *clk; |
@@ -124,5 +131,7 @@ int __init arch_clk_init(void) | |||
124 | 131 | ||
125 | clk_put(clk); | 132 | clk_put(clk); |
126 | 133 | ||
134 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
135 | |||
127 | return ret; | 136 | return ret; |
128 | } | 137 | } |