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authorPaul Mundt <lethal@linux-sh.org>2009-05-26 10:50:40 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-05-26 10:50:40 -0400
commit464c9e10376b24f04402fa8ef72b66257561bffa (patch)
treeac95ad416a2d3f3afcc92ca1790267a03b2be10d /arch/sh
parentb7e2ac619465f1774b827d9997109ceef4a61851 (diff)
parent61ce5393e4c8914c46ec99cbda76823515109709 (diff)
Merge branch 'sh/clkfwk'
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/Kconfig7
-rw-r--r--arch/sh/boards/board-sh7785lcr.c22
-rw-r--r--arch/sh/include/asm/clock.h69
-rw-r--r--arch/sh/include/asm/machvec.h2
-rw-r--r--arch/sh/kernel/cpu/Makefile1
-rw-r--r--arch/sh/kernel/cpu/clock-cpg.c62
-rw-r--r--arch/sh/kernel/cpu/clock.c598
-rw-r--r--arch/sh/kernel/cpu/sh2/clock-sh7619.c16
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c4
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7201.c14
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7203.c15
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7206.c12
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c6
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c6
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c8
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c10
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh3.c12
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7705.c12
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7706.c12
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7709.c12
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7710.c12
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7712.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c6
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c6
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c6
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c16
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4-202.c43
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4.c12
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c6
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c10
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c424
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7763.c46
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7770.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7780.c43
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7785.c317
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c47
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-shx3.c41
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c5
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c4
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c18
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c18
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c24
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c12
-rw-r--r--arch/sh/kernel/cpu/sh5/clock-sh5.c12
-rw-r--r--arch/sh/kernel/cpu/sh5/setup-sh5.c6
51 files changed, 1211 insertions, 891 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index fb75c2d1928d..c815975b8d75 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -513,6 +513,13 @@ config SH_PCLK_FREQ
513 This is necessary for determining the reference clock value on 513 This is necessary for determining the reference clock value on
514 platforms lacking an RTC. 514 platforms lacking an RTC.
515 515
516config SH_CLK_CPG
517 def_bool y
518
519config SH_CLK_CPG_LEGACY
520 depends on SH_CLK_CPG
521 def_bool y if !CPU_SUBTYPE_SH7785
522
516config SH_CLK_MD 523config SH_CLK_MD
517 int "CPU Mode Pin Setting" 524 int "CPU Mode Pin Setting"
518 depends on CPU_SH2 525 depends on CPU_SH2
diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c
index 6f94f17adc46..33b194b0454d 100644
--- a/arch/sh/boards/board-sh7785lcr.c
+++ b/arch/sh/boards/board-sh7785lcr.c
@@ -2,12 +2,12 @@
2 * Renesas Technology Corp. R0P7785LC0011RL Support. 2 * Renesas Technology Corp. R0P7785LC0011RL Support.
3 * 3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda 4 * Copyright (C) 2008 Yoshihiro Shimoda
5 * Copyright (C) 2009 Paul Mundt
5 * 6 *
6 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
8 * for more details. 9 * for more details.
9 */ 10 */
10
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13#include <linux/sm501.h> 13#include <linux/sm501.h>
@@ -19,8 +19,11 @@
19#include <linux/i2c-pca-platform.h> 19#include <linux/i2c-pca-platform.h>
20#include <linux/i2c-algo-pca.h> 20#include <linux/i2c-algo-pca.h>
21#include <linux/irq.h> 21#include <linux/irq.h>
22#include <asm/heartbeat.h> 22#include <linux/clk.h>
23#include <linux/errno.h>
23#include <mach/sh7785lcr.h> 24#include <mach/sh7785lcr.h>
25#include <asm/heartbeat.h>
26#include <asm/clock.h>
24 27
25/* 28/*
26 * NOTE: This board has 2 physical memory maps. 29 * NOTE: This board has 2 physical memory maps.
@@ -273,6 +276,20 @@ void __init init_sh7785lcr_IRQ(void)
273 plat_irq_setup_pins(IRQ_MODE_IRQ3210); 276 plat_irq_setup_pins(IRQ_MODE_IRQ3210);
274} 277}
275 278
279static int sh7785lcr_clk_init(void)
280{
281 struct clk *clk;
282 int ret;
283
284 clk = clk_get(NULL, "extal");
285 if (!clk || IS_ERR(clk))
286 return PTR_ERR(clk);
287 ret = clk_set_rate(clk, 33333333);
288 clk_put(clk);
289
290 return ret;
291}
292
276static void sh7785lcr_power_off(void) 293static void sh7785lcr_power_off(void)
277{ 294{
278 unsigned char *p; 295 unsigned char *p;
@@ -309,6 +326,7 @@ static void __init sh7785lcr_setup(char **cmdline_p)
309static struct sh_machine_vector mv_sh7785lcr __initmv = { 326static struct sh_machine_vector mv_sh7785lcr __initmv = {
310 .mv_name = "SH7785LCR", 327 .mv_name = "SH7785LCR",
311 .mv_setup = sh7785lcr_setup, 328 .mv_setup = sh7785lcr_setup,
329 .mv_clk_init = sh7785lcr_clk_init,
312 .mv_init_irq = init_sh7785lcr_IRQ, 330 .mv_init_irq = init_sh7785lcr_IRQ,
313}; 331};
314 332
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index b1f29199e4bd..aa9480d4aa05 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -10,9 +10,9 @@ struct clk;
10 10
11struct clk_ops { 11struct clk_ops {
12 void (*init)(struct clk *clk); 12 void (*init)(struct clk *clk);
13 void (*enable)(struct clk *clk); 13 int (*enable)(struct clk *clk);
14 void (*disable)(struct clk *clk); 14 void (*disable)(struct clk *clk);
15 void (*recalc)(struct clk *clk); 15 unsigned long (*recalc)(struct clk *clk);
16 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); 16 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
17 int (*set_parent)(struct clk *clk, struct clk *parent); 17 int (*set_parent)(struct clk *clk, struct clk *parent);
18 long (*round_rate)(struct clk *clk, unsigned long rate); 18 long (*round_rate)(struct clk *clk, unsigned long rate);
@@ -27,44 +27,46 @@ struct clk {
27 struct clk *parent; 27 struct clk *parent;
28 struct clk_ops *ops; 28 struct clk_ops *ops;
29 29
30 struct list_head children;
31 struct list_head sibling; /* node for children */
32
30 int usecount; 33 int usecount;
31 34
32 unsigned long rate; 35 unsigned long rate;
33 unsigned long flags; 36 unsigned long flags;
37
38 void __iomem *enable_reg;
39 unsigned int enable_bit;
40
34 unsigned long arch_flags; 41 unsigned long arch_flags;
42 void *priv;
43 struct dentry *dentry;
44};
45
46struct clk_lookup {
47 struct list_head node;
48 const char *dev_id;
49 const char *con_id;
50 struct clk *clk;
35}; 51};
36 52
37#define CLK_ALWAYS_ENABLED (1 << 0) 53#define CLK_ENABLE_ON_INIT (1 << 0)
38#define CLK_RATE_PROPAGATES (1 << 1)
39#define CLK_NEEDS_INIT (1 << 2)
40 54
41/* Should be defined by processor-specific code */ 55/* Should be defined by processor-specific code */
42void arch_init_clk_ops(struct clk_ops **, int type); 56void __deprecated arch_init_clk_ops(struct clk_ops **, int type);
43int __init arch_clk_init(void); 57int __init arch_clk_init(void);
44 58
45/* arch/sh/kernel/cpu/clock.c */ 59/* arch/sh/kernel/cpu/clock.c */
46int clk_init(void); 60int clk_init(void);
47 61unsigned long followparent_recalc(struct clk *);
48void clk_recalc_rate(struct clk *); 62void recalculate_root_clocks(void);
49 63void propagate_rate(struct clk *);
64int clk_reparent(struct clk *child, struct clk *parent);
50int clk_register(struct clk *); 65int clk_register(struct clk *);
51void clk_unregister(struct clk *); 66void clk_unregister(struct clk *);
52 67
53static inline int clk_always_enable(const char *id) 68/* arch/sh/kernel/cpu/clock-cpg.c */
54{ 69int __init __deprecated cpg_clk_init(void);
55 struct clk *clk;
56 int ret;
57
58 clk = clk_get(NULL, id);
59 if (IS_ERR(clk))
60 return PTR_ERR(clk);
61
62 ret = clk_enable(clk);
63 if (ret)
64 clk_put(clk);
65
66 return ret;
67}
68 70
69/* the exported API, in addition to clk_set_rate */ 71/* the exported API, in addition to clk_set_rate */
70/** 72/**
@@ -96,4 +98,23 @@ enum clk_sh_algo_id {
96 98
97 IP_N1, 99 IP_N1,
98}; 100};
101
102struct clk_div_mult_table {
103 unsigned int *divisors;
104 unsigned int nr_divisors;
105 unsigned int *multipliers;
106 unsigned int nr_multipliers;
107};
108
109struct cpufreq_frequency_table;
110void clk_rate_table_build(struct clk *clk,
111 struct cpufreq_frequency_table *freq_table,
112 int nr_freqs,
113 struct clk_div_mult_table *src_table,
114 unsigned long *bitmap);
115
116long clk_rate_table_round(struct clk *clk,
117 struct cpufreq_frequency_table *freq_table,
118 unsigned long rate);
119
99#endif /* __ASM_SH_CLOCK_H */ 120#endif /* __ASM_SH_CLOCK_H */
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
index 64b1c16a0f03..73d6d16fa06b 100644
--- a/arch/sh/include/asm/machvec.h
+++ b/arch/sh/include/asm/machvec.h
@@ -46,6 +46,8 @@ struct sh_machine_vector {
46 46
47 void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size); 47 void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
48 void (*mv_ioport_unmap)(void __iomem *); 48 void (*mv_ioport_unmap)(void __iomem *);
49
50 int (*mv_clk_init)(void);
49}; 51};
50 52
51extern struct sh_machine_vector sh_mv; 53extern struct sh_machine_vector sh_mv;
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index 2600641a483f..eecad7cbd61e 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -17,5 +17,6 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
17 17
18obj-$(CONFIG_UBC_WAKEUP) += ubc.o 18obj-$(CONFIG_UBC_WAKEUP) += ubc.o
19obj-$(CONFIG_SH_ADC) += adc.o 19obj-$(CONFIG_SH_ADC) += adc.o
20obj-$(CONFIG_SH_CLK_CPG) += clock-cpg.o
20 21
21obj-y += irq/ init.o clock.o 22obj-y += irq/ init.o clock.o
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
new file mode 100644
index 000000000000..b78c237ab366
--- /dev/null
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -0,0 +1,62 @@
1#include <linux/clk.h>
2#include <linux/compiler.h>
3#include <asm/clock.h>
4
5#ifdef CONFIG_SH_CLK_CPG_LEGACY
6static struct clk master_clk = {
7 .name = "master_clk",
8 .flags = CLK_ENABLE_ON_INIT,
9 .rate = CONFIG_SH_PCLK_FREQ,
10};
11
12static struct clk peripheral_clk = {
13 .name = "peripheral_clk",
14 .parent = &master_clk,
15 .flags = CLK_ENABLE_ON_INIT,
16};
17
18static struct clk bus_clk = {
19 .name = "bus_clk",
20 .parent = &master_clk,
21 .flags = CLK_ENABLE_ON_INIT,
22};
23
24static struct clk cpu_clk = {
25 .name = "cpu_clk",
26 .parent = &master_clk,
27 .flags = CLK_ENABLE_ON_INIT,
28};
29
30/*
31 * The ordering of these clocks matters, do not change it.
32 */
33static struct clk *onchip_clocks[] = {
34 &master_clk,
35 &peripheral_clk,
36 &bus_clk,
37 &cpu_clk,
38};
39
40int __init __deprecated cpg_clk_init(void)
41{
42 int i, ret = 0;
43
44 for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
45 struct clk *clk = onchip_clocks[i];
46 arch_init_clk_ops(&clk->ops, i);
47 if (clk->ops)
48 ret |= clk_register(clk);
49 }
50
51 return ret;
52}
53
54/*
55 * Placeholder for compatability, until the lazy CPUs do this
56 * on their own.
57 */
58int __init __weak arch_clk_init(void)
59{
60 return cpg_clk_init();
61}
62#endif /* CONFIG_SH_CPG_CLK_LEGACY */
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index f54769f455b1..aa0fd0893585 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -1,15 +1,19 @@
1/* 1/*
2 * arch/sh/kernel/cpu/clock.c - SuperH clock framework 2 * arch/sh/kernel/cpu/clock.c - SuperH clock framework
3 * 3 *
4 * Copyright (C) 2005, 2006, 2007 Paul Mundt 4 * Copyright (C) 2005 - 2009 Paul Mundt
5 * 5 *
6 * This clock framework is derived from the OMAP version by: 6 * This clock framework is derived from the OMAP version by:
7 * 7 *
8 * Copyright (C) 2004 - 2005 Nokia Corporation 8 * Copyright (C) 2004 - 2008 Nokia Corporation
9 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 9 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * 10 *
11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> 11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
12 * 12 *
13 * With clkdev bits:
14 *
15 * Copyright (C) 2008 Russell King.
16 *
13 * This file is subject to the terms and conditions of the GNU General Public 17 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive 18 * License. See the file "COPYING" in the main directory of this archive
15 * for more details. 19 * for more details.
@@ -24,141 +28,135 @@
24#include <linux/seq_file.h> 28#include <linux/seq_file.h>
25#include <linux/err.h> 29#include <linux/err.h>
26#include <linux/platform_device.h> 30#include <linux/platform_device.h>
27#include <linux/proc_fs.h> 31#include <linux/debugfs.h>
32#include <linux/cpufreq.h>
28#include <asm/clock.h> 33#include <asm/clock.h>
34#include <asm/machvec.h>
29 35
30static LIST_HEAD(clock_list); 36static LIST_HEAD(clock_list);
31static DEFINE_SPINLOCK(clock_lock); 37static DEFINE_SPINLOCK(clock_lock);
32static DEFINE_MUTEX(clock_list_sem); 38static DEFINE_MUTEX(clock_list_sem);
33 39
34/* 40void clk_rate_table_build(struct clk *clk,
35 * Each subtype is expected to define the init routines for these clocks, 41 struct cpufreq_frequency_table *freq_table,
36 * as each subtype (or processor family) will have these clocks at the 42 int nr_freqs,
37 * very least. These are all provided through the CPG, which even some of 43 struct clk_div_mult_table *src_table,
38 * the more quirky parts (such as ST40, SH4-202, etc.) still have. 44 unsigned long *bitmap)
39 * 45{
40 * The processor-specific code is expected to register any additional 46 unsigned long mult, div;
41 * clock sources that are of interest. 47 unsigned long freq;
42 */ 48 int i;
43static struct clk master_clk = {
44 .name = "master_clk",
45 .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
46 .rate = CONFIG_SH_PCLK_FREQ,
47};
48 49
49static struct clk module_clk = { 50 for (i = 0; i < nr_freqs; i++) {
50 .name = "module_clk", 51 div = 1;
51 .parent = &master_clk, 52 mult = 1;
52 .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
53};
54 53
55static struct clk bus_clk = { 54 if (src_table->divisors && i < src_table->nr_divisors)
56 .name = "bus_clk", 55 div = src_table->divisors[i];
57 .parent = &master_clk,
58 .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
59};
60 56
61static struct clk cpu_clk = { 57 if (src_table->multipliers && i < src_table->nr_multipliers)
62 .name = "cpu_clk", 58 mult = src_table->multipliers[i];
63 .parent = &master_clk,
64 .flags = CLK_ALWAYS_ENABLED,
65};
66 59
67/* 60 if (!div || !mult || (bitmap && !test_bit(i, bitmap)))
68 * The ordering of these clocks matters, do not change it. 61 freq = CPUFREQ_ENTRY_INVALID;
69 */ 62 else
70static struct clk *onchip_clocks[] = { 63 freq = clk->parent->rate * mult / div;
71 &master_clk,
72 &module_clk,
73 &bus_clk,
74 &cpu_clk,
75};
76 64
77static void propagate_rate(struct clk *clk) 65 freq_table[i].index = i;
78{ 66 freq_table[i].frequency = freq;
79 struct clk *clkp;
80
81 list_for_each_entry(clkp, &clock_list, node) {
82 if (likely(clkp->parent != clk))
83 continue;
84 if (likely(clkp->ops && clkp->ops->recalc))
85 clkp->ops->recalc(clkp);
86 if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
87 propagate_rate(clkp);
88 } 67 }
68
69 /* Termination entry */
70 freq_table[i].index = i;
71 freq_table[i].frequency = CPUFREQ_TABLE_END;
89} 72}
90 73
91static void __clk_init(struct clk *clk) 74long clk_rate_table_round(struct clk *clk,
75 struct cpufreq_frequency_table *freq_table,
76 unsigned long rate)
92{ 77{
93 /* 78 unsigned long rate_error, rate_error_prev = ~0UL;
94 * See if this is the first time we're enabling the clock, some 79 unsigned long rate_best_fit = rate;
95 * clocks that are always enabled still require "special" 80 unsigned long highest, lowest;
96 * initialization. This is especially true if the clock mode 81 int i;
97 * changes and the clock needs to hunt for the proper set of
98 * divisors to use before it can effectively recalc.
99 */
100 82
101 if (clk->flags & CLK_NEEDS_INIT) { 83 highest = lowest = 0;
102 if (clk->ops && clk->ops->init)
103 clk->ops->init(clk);
104 84
105 clk->flags &= ~CLK_NEEDS_INIT; 85 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
106 } 86 unsigned long freq = freq_table[i].frequency;
107}
108 87
109static int __clk_enable(struct clk *clk) 88 if (freq == CPUFREQ_ENTRY_INVALID)
110{ 89 continue;
111 if (!clk)
112 return -EINVAL;
113 90
114 clk->usecount++; 91 if (freq > highest)
92 highest = freq;
93 if (freq < lowest)
94 lowest = freq;
115 95
116 /* nothing to do if always enabled */ 96 rate_error = abs(freq - rate);
117 if (clk->flags & CLK_ALWAYS_ENABLED) 97 if (rate_error < rate_error_prev) {
118 return 0; 98 rate_best_fit = freq;
99 rate_error_prev = rate_error;
100 }
119 101
120 if (clk->usecount == 1) { 102 if (rate_error == 0)
121 __clk_init(clk); 103 break;
104 }
122 105
123 __clk_enable(clk->parent); 106 if (rate >= highest)
107 rate_best_fit = highest;
108 if (rate <= lowest)
109 rate_best_fit = lowest;
124 110
125 if (clk->ops && clk->ops->enable) 111 return rate_best_fit;
126 clk->ops->enable(clk); 112}
127 }
128 113
129 return 0; 114/* Used for clocks that always have same value as the parent clock */
115unsigned long followparent_recalc(struct clk *clk)
116{
117 return clk->parent ? clk->parent->rate : 0;
130} 118}
131 119
132int clk_enable(struct clk *clk) 120int clk_reparent(struct clk *child, struct clk *parent)
133{ 121{
134 unsigned long flags; 122 list_del_init(&child->sibling);
135 int ret; 123 if (parent)
124 list_add(&child->sibling, &parent->children);
125 child->parent = parent;
136 126
137 spin_lock_irqsave(&clock_lock, flags); 127 /* now do the debugfs renaming to reattach the child
138 ret = __clk_enable(clk); 128 to the proper parent */
139 spin_unlock_irqrestore(&clock_lock, flags);
140 129
141 return ret; 130 return 0;
142} 131}
143EXPORT_SYMBOL_GPL(clk_enable);
144 132
145static void __clk_disable(struct clk *clk) 133/* Propagate rate to children */
134void propagate_rate(struct clk *tclk)
146{ 135{
147 if (!clk) 136 struct clk *clkp;
148 return;
149 137
150 clk->usecount--; 138 list_for_each_entry(clkp, &tclk->children, sibling) {
139 if (clkp->ops && clkp->ops->recalc)
140 clkp->rate = clkp->ops->recalc(clkp);
151 141
152 WARN_ON(clk->usecount < 0); 142 propagate_rate(clkp);
143 }
144}
153 145
154 if (clk->flags & CLK_ALWAYS_ENABLED) 146static void __clk_disable(struct clk *clk)
147{
148 if (clk->usecount == 0) {
149 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n",
150 clk->name);
151 WARN_ON(1);
155 return; 152 return;
153 }
156 154
157 if (clk->usecount == 0) { 155 if (!(--clk->usecount)) {
158 if (likely(clk->ops && clk->ops->disable)) 156 if (likely(clk->ops && clk->ops->disable))
159 clk->ops->disable(clk); 157 clk->ops->disable(clk);
160 158 if (likely(clk->parent))
161 __clk_disable(clk->parent); 159 __clk_disable(clk->parent);
162 } 160 }
163} 161}
164 162
@@ -166,29 +164,103 @@ void clk_disable(struct clk *clk)
166{ 164{
167 unsigned long flags; 165 unsigned long flags;
168 166
167 if (!clk)
168 return;
169
169 spin_lock_irqsave(&clock_lock, flags); 170 spin_lock_irqsave(&clock_lock, flags);
170 __clk_disable(clk); 171 __clk_disable(clk);
171 spin_unlock_irqrestore(&clock_lock, flags); 172 spin_unlock_irqrestore(&clock_lock, flags);
172} 173}
173EXPORT_SYMBOL_GPL(clk_disable); 174EXPORT_SYMBOL_GPL(clk_disable);
174 175
176static int __clk_enable(struct clk *clk)
177{
178 int ret = 0;
179
180 if (clk->usecount++ == 0) {
181 if (clk->parent) {
182 ret = __clk_enable(clk->parent);
183 if (unlikely(ret))
184 goto err;
185 }
186
187 if (clk->ops && clk->ops->enable) {
188 ret = clk->ops->enable(clk);
189 if (ret) {
190 if (clk->parent)
191 __clk_disable(clk->parent);
192 goto err;
193 }
194 }
195 }
196
197 return ret;
198err:
199 clk->usecount--;
200 return ret;
201}
202
203int clk_enable(struct clk *clk)
204{
205 unsigned long flags;
206 int ret;
207
208 if (!clk)
209 return -EINVAL;
210
211 spin_lock_irqsave(&clock_lock, flags);
212 ret = __clk_enable(clk);
213 spin_unlock_irqrestore(&clock_lock, flags);
214
215 return ret;
216}
217EXPORT_SYMBOL_GPL(clk_enable);
218
219static LIST_HEAD(root_clks);
220
221/**
222 * recalculate_root_clocks - recalculate and propagate all root clocks
223 *
224 * Recalculates all root clocks (clocks with no parent), which if the
225 * clock's .recalc is set correctly, should also propagate their rates.
226 * Called at init.
227 */
228void recalculate_root_clocks(void)
229{
230 struct clk *clkp;
231
232 list_for_each_entry(clkp, &root_clks, sibling) {
233 if (clkp->ops && clkp->ops->recalc)
234 clkp->rate = clkp->ops->recalc(clkp);
235 propagate_rate(clkp);
236 }
237}
238
175int clk_register(struct clk *clk) 239int clk_register(struct clk *clk)
176{ 240{
241 if (clk == NULL || IS_ERR(clk))
242 return -EINVAL;
243
244 /*
245 * trap out already registered clocks
246 */
247 if (clk->node.next || clk->node.prev)
248 return 0;
249
177 mutex_lock(&clock_list_sem); 250 mutex_lock(&clock_list_sem);
178 251
179 list_add(&clk->node, &clock_list); 252 INIT_LIST_HEAD(&clk->children);
180 clk->usecount = 0; 253 clk->usecount = 0;
181 clk->flags |= CLK_NEEDS_INIT;
182 254
183 mutex_unlock(&clock_list_sem); 255 if (clk->parent)
256 list_add(&clk->sibling, &clk->parent->children);
257 else
258 list_add(&clk->sibling, &root_clks);
184 259
185 if (clk->flags & CLK_ALWAYS_ENABLED) { 260 list_add(&clk->node, &clock_list);
186 __clk_init(clk); 261 if (clk->ops && clk->ops->init)
187 pr_debug( "Clock '%s' is ALWAYS_ENABLED\n", clk->name); 262 clk->ops->init(clk);
188 if (clk->ops && clk->ops->enable) 263 mutex_unlock(&clock_list_sem);
189 clk->ops->enable(clk);
190 pr_debug( "Enabled.");
191 }
192 264
193 return 0; 265 return 0;
194} 266}
@@ -197,11 +269,21 @@ EXPORT_SYMBOL_GPL(clk_register);
197void clk_unregister(struct clk *clk) 269void clk_unregister(struct clk *clk)
198{ 270{
199 mutex_lock(&clock_list_sem); 271 mutex_lock(&clock_list_sem);
272 list_del(&clk->sibling);
200 list_del(&clk->node); 273 list_del(&clk->node);
201 mutex_unlock(&clock_list_sem); 274 mutex_unlock(&clock_list_sem);
202} 275}
203EXPORT_SYMBOL_GPL(clk_unregister); 276EXPORT_SYMBOL_GPL(clk_unregister);
204 277
278static void clk_enable_init_clocks(void)
279{
280 struct clk *clkp;
281
282 list_for_each_entry(clkp, &clock_list, node)
283 if (clkp->flags & CLK_ENABLE_ON_INIT)
284 clk_enable(clkp);
285}
286
205unsigned long clk_get_rate(struct clk *clk) 287unsigned long clk_get_rate(struct clk *clk)
206{ 288{
207 return clk->rate; 289 return clk->rate;
@@ -217,56 +299,59 @@ EXPORT_SYMBOL_GPL(clk_set_rate);
217int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id) 299int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
218{ 300{
219 int ret = -EOPNOTSUPP; 301 int ret = -EOPNOTSUPP;
302 unsigned long flags;
220 303
221 if (likely(clk->ops && clk->ops->set_rate)) { 304 spin_lock_irqsave(&clock_lock, flags);
222 unsigned long flags;
223 305
224 spin_lock_irqsave(&clock_lock, flags); 306 if (likely(clk->ops && clk->ops->set_rate)) {
225 ret = clk->ops->set_rate(clk, rate, algo_id); 307 ret = clk->ops->set_rate(clk, rate, algo_id);
226 spin_unlock_irqrestore(&clock_lock, flags); 308 if (ret != 0)
309 goto out_unlock;
310 } else {
311 clk->rate = rate;
312 ret = 0;
227 } 313 }
228 314
229 if (unlikely(clk->flags & CLK_RATE_PROPAGATES)) 315 if (clk->ops && clk->ops->recalc)
230 propagate_rate(clk); 316 clk->rate = clk->ops->recalc(clk);
231 317
232 return ret; 318 propagate_rate(clk);
233}
234EXPORT_SYMBOL_GPL(clk_set_rate_ex);
235 319
236void clk_recalc_rate(struct clk *clk) 320out_unlock:
237{ 321 spin_unlock_irqrestore(&clock_lock, flags);
238 if (likely(clk->ops && clk->ops->recalc)) {
239 unsigned long flags;
240
241 spin_lock_irqsave(&clock_lock, flags);
242 clk->ops->recalc(clk);
243 spin_unlock_irqrestore(&clock_lock, flags);
244 }
245 322
246 if (unlikely(clk->flags & CLK_RATE_PROPAGATES)) 323 return ret;
247 propagate_rate(clk);
248} 324}
249EXPORT_SYMBOL_GPL(clk_recalc_rate); 325EXPORT_SYMBOL_GPL(clk_set_rate_ex);
250 326
251int clk_set_parent(struct clk *clk, struct clk *parent) 327int clk_set_parent(struct clk *clk, struct clk *parent)
252{ 328{
329 unsigned long flags;
253 int ret = -EINVAL; 330 int ret = -EINVAL;
254 struct clk *old;
255 331
256 if (!parent || !clk) 332 if (!parent || !clk)
257 return ret; 333 return ret;
334 if (clk->parent == parent)
335 return 0;
258 336
259 old = clk->parent; 337 spin_lock_irqsave(&clock_lock, flags);
260 if (likely(clk->ops && clk->ops->set_parent)) { 338 if (clk->usecount == 0) {
261 unsigned long flags; 339 if (clk->ops->set_parent)
262 spin_lock_irqsave(&clock_lock, flags); 340 ret = clk->ops->set_parent(clk, parent);
263 ret = clk->ops->set_parent(clk, parent); 341 else
264 spin_unlock_irqrestore(&clock_lock, flags); 342 ret = clk_reparent(clk, parent);
265 clk->parent = (ret ? old : parent); 343
266 } 344 if (ret == 0) {
345 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
346 clk->name, clk->parent->name, clk->rate);
347 if (clk->ops->recalc)
348 clk->rate = clk->ops->recalc(clk);
349 propagate_rate(clk);
350 }
351 } else
352 ret = -EBUSY;
353 spin_unlock_irqrestore(&clock_lock, flags);
267 354
268 if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
269 propagate_rate(clk);
270 return ret; 355 return ret;
271} 356}
272EXPORT_SYMBOL_GPL(clk_set_parent); 357EXPORT_SYMBOL_GPL(clk_set_parent);
@@ -294,14 +379,69 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
294EXPORT_SYMBOL_GPL(clk_round_rate); 379EXPORT_SYMBOL_GPL(clk_round_rate);
295 380
296/* 381/*
382 * Find the correct struct clk for the device and connection ID.
383 * We do slightly fuzzy matching here:
384 * An entry with a NULL ID is assumed to be a wildcard.
385 * If an entry has a device ID, it must match
386 * If an entry has a connection ID, it must match
387 * Then we take the most specific entry - with the following
388 * order of precidence: dev+con > dev only > con only.
389 */
390static struct clk *clk_find(const char *dev_id, const char *con_id)
391{
392 struct clk_lookup *p;
393 struct clk *clk = NULL;
394 int match, best = 0;
395
396 list_for_each_entry(p, &clock_list, node) {
397 match = 0;
398 if (p->dev_id) {
399 if (!dev_id || strcmp(p->dev_id, dev_id))
400 continue;
401 match += 2;
402 }
403 if (p->con_id) {
404 if (!con_id || strcmp(p->con_id, con_id))
405 continue;
406 match += 1;
407 }
408 if (match == 0)
409 continue;
410
411 if (match > best) {
412 clk = p->clk;
413 best = match;
414 }
415 }
416 return clk;
417}
418
419struct clk *clk_get_sys(const char *dev_id, const char *con_id)
420{
421 struct clk *clk;
422
423 mutex_lock(&clock_list_sem);
424 clk = clk_find(dev_id, con_id);
425 mutex_unlock(&clock_list_sem);
426
427 return clk ? clk : ERR_PTR(-ENOENT);
428}
429EXPORT_SYMBOL_GPL(clk_get_sys);
430
431/*
297 * Returns a clock. Note that we first try to use device id on the bus 432 * Returns a clock. Note that we first try to use device id on the bus
298 * and clock name. If this fails, we try to use clock name only. 433 * and clock name. If this fails, we try to use clock name only.
299 */ 434 */
300struct clk *clk_get(struct device *dev, const char *id) 435struct clk *clk_get(struct device *dev, const char *id)
301{ 436{
437 const char *dev_id = dev ? dev_name(dev) : NULL;
302 struct clk *p, *clk = ERR_PTR(-ENOENT); 438 struct clk *p, *clk = ERR_PTR(-ENOENT);
303 int idno; 439 int idno;
304 440
441 clk = clk_get_sys(dev_id, id);
442 if (clk && !IS_ERR(clk))
443 return clk;
444
305 if (dev == NULL || dev->bus != &platform_bus_type) 445 if (dev == NULL || dev->bus != &platform_bus_type)
306 idno = -1; 446 idno = -1;
307 else 447 else
@@ -337,36 +477,6 @@ void clk_put(struct clk *clk)
337} 477}
338EXPORT_SYMBOL_GPL(clk_put); 478EXPORT_SYMBOL_GPL(clk_put);
339 479
340void __init __attribute__ ((weak))
341arch_init_clk_ops(struct clk_ops **ops, int type)
342{
343}
344
345int __init __attribute__ ((weak))
346arch_clk_init(void)
347{
348 return 0;
349}
350
351static int show_clocks(char *buf, char **start, off_t off,
352 int len, int *eof, void *data)
353{
354 struct clk *clk;
355 char *p = buf;
356
357 list_for_each_entry_reverse(clk, &clock_list, node) {
358 unsigned long rate = clk_get_rate(clk);
359
360 p += sprintf(p, "%-12s\t: %ld.%02ldMHz\t%s\n", clk->name,
361 rate / 1000000, (rate % 1000000) / 10000,
362 ((clk->flags & CLK_ALWAYS_ENABLED) ||
363 clk->usecount > 0) ?
364 "enabled" : "disabled");
365 }
366
367 return p - buf;
368}
369
370#ifdef CONFIG_PM 480#ifdef CONFIG_PM
371static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state) 481static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
372{ 482{
@@ -376,20 +486,22 @@ static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
376 switch (state.event) { 486 switch (state.event) {
377 case PM_EVENT_ON: 487 case PM_EVENT_ON:
378 /* Resumeing from hibernation */ 488 /* Resumeing from hibernation */
379 if (prev_state.event == PM_EVENT_FREEZE) { 489 if (prev_state.event != PM_EVENT_FREEZE)
380 list_for_each_entry(clkp, &clock_list, node) 490 break;
381 if (likely(clkp->ops)) { 491
382 unsigned long rate = clkp->rate; 492 list_for_each_entry(clkp, &clock_list, node) {
383 493 if (likely(clkp->ops)) {
384 if (likely(clkp->ops->set_parent)) 494 unsigned long rate = clkp->rate;
385 clkp->ops->set_parent(clkp, 495
386 clkp->parent); 496 if (likely(clkp->ops->set_parent))
387 if (likely(clkp->ops->set_rate)) 497 clkp->ops->set_parent(clkp,
388 clkp->ops->set_rate(clkp, 498 clkp->parent);
389 rate, NO_CHANGE); 499 if (likely(clkp->ops->set_rate))
390 else if (likely(clkp->ops->recalc)) 500 clkp->ops->set_rate(clkp,
391 clkp->ops->recalc(clkp); 501 rate, NO_CHANGE);
392 } 502 else if (likely(clkp->ops->recalc))
503 clkp->rate = clkp->ops->recalc(clkp);
504 }
393 } 505 }
394 break; 506 break;
395 case PM_EVENT_FREEZE: 507 case PM_EVENT_FREEZE:
@@ -433,34 +545,116 @@ subsys_initcall(clk_sysdev_init);
433 545
434int __init clk_init(void) 546int __init clk_init(void)
435{ 547{
436 int i, ret = 0; 548 int ret;
437
438 BUG_ON(!master_clk.rate);
439
440 for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
441 struct clk *clk = onchip_clocks[i];
442 549
443 arch_init_clk_ops(&clk->ops, i); 550 ret = arch_clk_init();
444 ret |= clk_register(clk); 551 if (unlikely(ret)) {
552 pr_err("%s: CPU clock registration failed.\n", __func__);
553 return ret;
445 } 554 }
446 555
447 ret |= arch_clk_init(); 556 if (sh_mv.mv_clk_init) {
557 ret = sh_mv.mv_clk_init();
558 if (unlikely(ret)) {
559 pr_err("%s: machvec clock initialization failed.\n",
560 __func__);
561 return ret;
562 }
563 }
448 564
449 /* Kick the child clocks.. */ 565 /* Kick the child clocks.. */
450 propagate_rate(&master_clk); 566 recalculate_root_clocks();
451 propagate_rate(&bus_clk); 567
568 /* Enable the necessary init clocks */
569 clk_enable_init_clocks();
452 570
453 return ret; 571 return ret;
454} 572}
455 573
456static int __init clk_proc_init(void) 574/*
575 * debugfs support to trace clock tree hierarchy and attributes
576 */
577static struct dentry *clk_debugfs_root;
578
579static int clk_debugfs_register_one(struct clk *c)
457{ 580{
458 struct proc_dir_entry *p; 581 int err;
459 p = create_proc_read_entry("clocks", S_IRUSR, NULL, 582 struct dentry *d, *child;
460 show_clocks, NULL); 583 struct clk *pa = c->parent;
461 if (unlikely(!p)) 584 char s[255];
462 return -EINVAL; 585 char *p = s;
586
587 p += sprintf(p, "%s", c->name);
588 if (c->id >= 0)
589 sprintf(p, ":%d", c->id);
590 d = debugfs_create_dir(s, pa ? pa->dentry : clk_debugfs_root);
591 if (!d)
592 return -ENOMEM;
593 c->dentry = d;
594
595 d = debugfs_create_u8("usecount", S_IRUGO, c->dentry, (u8 *)&c->usecount);
596 if (!d) {
597 err = -ENOMEM;
598 goto err_out;
599 }
600 d = debugfs_create_u32("rate", S_IRUGO, c->dentry, (u32 *)&c->rate);
601 if (!d) {
602 err = -ENOMEM;
603 goto err_out;
604 }
605 d = debugfs_create_x32("flags", S_IRUGO, c->dentry, (u32 *)&c->flags);
606 if (!d) {
607 err = -ENOMEM;
608 goto err_out;
609 }
610 return 0;
611
612err_out:
613 d = c->dentry;
614 list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
615 debugfs_remove(child);
616 debugfs_remove(c->dentry);
617 return err;
618}
619
620static int clk_debugfs_register(struct clk *c)
621{
622 int err;
623 struct clk *pa = c->parent;
624
625 if (pa && !pa->dentry) {
626 err = clk_debugfs_register(pa);
627 if (err)
628 return err;
629 }
463 630
631 if (!c->dentry) {
632 err = clk_debugfs_register_one(c);
633 if (err)
634 return err;
635 }
636 return 0;
637}
638
639static int __init clk_debugfs_init(void)
640{
641 struct clk *c;
642 struct dentry *d;
643 int err;
644
645 d = debugfs_create_dir("clock", NULL);
646 if (!d)
647 return -ENOMEM;
648 clk_debugfs_root = d;
649
650 list_for_each_entry(c, &clock_list, node) {
651 err = clk_debugfs_register(c);
652 if (err)
653 goto err_out;
654 }
464 return 0; 655 return 0;
656err_out:
657 debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */
658 return err;
465} 659}
466subsys_initcall(clk_proc_init); 660late_initcall(clk_debugfs_init);
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index d2c157917999..4fe863170e31 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -38,32 +38,27 @@ static struct clk_ops sh7619_master_clk_ops = {
38 .init = master_clk_init, 38 .init = master_clk_init,
39}; 39};
40 40
41static void module_clk_recalc(struct clk *clk) 41static unsigned long module_clk_recalc(struct clk *clk)
42{ 42{
43 int idx = (ctrl_inw(FREQCR) & 0x0007); 43 int idx = (ctrl_inw(FREQCR) & 0x0007);
44 clk->rate = clk->parent->rate / pfc_divisors[idx]; 44 return clk->parent->rate / pfc_divisors[idx];
45} 45}
46 46
47static struct clk_ops sh7619_module_clk_ops = { 47static struct clk_ops sh7619_module_clk_ops = {
48 .recalc = module_clk_recalc, 48 .recalc = module_clk_recalc,
49}; 49};
50 50
51static void bus_clk_recalc(struct clk *clk) 51static unsigned long bus_clk_recalc(struct clk *clk)
52{ 52{
53 clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7]; 53 return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
54} 54}
55 55
56static struct clk_ops sh7619_bus_clk_ops = { 56static struct clk_ops sh7619_bus_clk_ops = {
57 .recalc = bus_clk_recalc, 57 .recalc = bus_clk_recalc,
58}; 58};
59 59
60static void cpu_clk_recalc(struct clk *clk)
61{
62 clk->rate = clk->parent->rate;
63}
64
65static struct clk_ops sh7619_cpu_clk_ops = { 60static struct clk_ops sh7619_cpu_clk_ops = {
66 .recalc = cpu_clk_recalc, 61 .recalc = followparent_recalc,
67}; 62};
68 63
69static struct clk_ops *sh7619_clk_ops[] = { 64static struct clk_ops *sh7619_clk_ops[] = {
@@ -78,4 +73,3 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
78 if (idx < ARRAY_SIZE(sh7619_clk_ops)) 73 if (idx < ARRAY_SIZE(sh7619_clk_ops))
79 *ops = sh7619_clk_ops[idx]; 74 *ops = sh7619_clk_ops[idx];
80} 75}
81
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 94ac27fc2237..13798733f2db 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -115,7 +115,7 @@ static struct sh_timer_config cmt0_platform_data = {
115 .name = "CMT0", 115 .name = "CMT0",
116 .channel_offset = 0x02, 116 .channel_offset = 0x02,
117 .timer_bit = 0, 117 .timer_bit = 0,
118 .clk = "module_clk", 118 .clk = "peripheral_clk",
119 .clockevent_rating = 125, 119 .clockevent_rating = 125,
120 .clocksource_rating = 0, /* disabled due to code generation issues */ 120 .clocksource_rating = 0, /* disabled due to code generation issues */
121}; 121};
@@ -147,7 +147,7 @@ static struct sh_timer_config cmt1_platform_data = {
147 .name = "CMT1", 147 .name = "CMT1",
148 .channel_offset = 0x08, 148 .channel_offset = 0x08,
149 .timer_bit = 1, 149 .timer_bit = 1,
150 .clk = "module_clk", 150 .clk = "peripheral_clk",
151 .clockevent_rating = 125, 151 .clockevent_rating = 125,
152 .clocksource_rating = 0, /* disabled due to code generation issues */ 152 .clocksource_rating = 0, /* disabled due to code generation issues */
153}; 153};
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index 4a5e59732334..7814c76159a7 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -34,37 +34,37 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12};
34 34
35static void master_clk_init(struct clk *clk) 35static void master_clk_init(struct clk *clk)
36{ 36{
37 clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; 37 return 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
38} 38}
39 39
40static struct clk_ops sh7201_master_clk_ops = { 40static struct clk_ops sh7201_master_clk_ops = {
41 .init = master_clk_init, 41 .init = master_clk_init,
42}; 42};
43 43
44static void module_clk_recalc(struct clk *clk) 44static unsigned long module_clk_recalc(struct clk *clk)
45{ 45{
46 int idx = (ctrl_inw(FREQCR) & 0x0007); 46 int idx = (ctrl_inw(FREQCR) & 0x0007);
47 clk->rate = clk->parent->rate / pfc_divisors[idx]; 47 return clk->parent->rate / pfc_divisors[idx];
48} 48}
49 49
50static struct clk_ops sh7201_module_clk_ops = { 50static struct clk_ops sh7201_module_clk_ops = {
51 .recalc = module_clk_recalc, 51 .recalc = module_clk_recalc,
52}; 52};
53 53
54static void bus_clk_recalc(struct clk *clk) 54static unsigned long bus_clk_recalc(struct clk *clk)
55{ 55{
56 int idx = (ctrl_inw(FREQCR) & 0x0007); 56 int idx = (ctrl_inw(FREQCR) & 0x0007);
57 clk->rate = clk->parent->rate / pfc_divisors[idx]; 57 return clk->parent->rate / pfc_divisors[idx];
58} 58}
59 59
60static struct clk_ops sh7201_bus_clk_ops = { 60static struct clk_ops sh7201_bus_clk_ops = {
61 .recalc = bus_clk_recalc, 61 .recalc = bus_clk_recalc,
62}; 62};
63 63
64static void cpu_clk_recalc(struct clk *clk) 64static unsigned long cpu_clk_recalc(struct clk *clk)
65{ 65{
66 int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007); 66 int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007);
67 clk->rate = clk->parent->rate / ifc_divisors[idx]; 67 return clk->parent->rate / ifc_divisors[idx];
68} 68}
69 69
70static struct clk_ops sh7201_cpu_clk_ops = { 70static struct clk_ops sh7201_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index fb781329848a..940986965102 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -46,33 +46,28 @@ static struct clk_ops sh7203_master_clk_ops = {
46 .init = master_clk_init, 46 .init = master_clk_init,
47}; 47};
48 48
49static void module_clk_recalc(struct clk *clk) 49static unsigned long module_clk_recalc(struct clk *clk)
50{ 50{
51 int idx = (ctrl_inw(FREQCR) & 0x0007); 51 int idx = (ctrl_inw(FREQCR) & 0x0007);
52 clk->rate = clk->parent->rate / pfc_divisors[idx]; 52 return clk->parent->rate / pfc_divisors[idx];
53} 53}
54 54
55static struct clk_ops sh7203_module_clk_ops = { 55static struct clk_ops sh7203_module_clk_ops = {
56 .recalc = module_clk_recalc, 56 .recalc = module_clk_recalc,
57}; 57};
58 58
59static void bus_clk_recalc(struct clk *clk) 59static unsigned long bus_clk_recalc(struct clk *clk)
60{ 60{
61 int idx = (ctrl_inw(FREQCR) & 0x0007); 61 int idx = (ctrl_inw(FREQCR) & 0x0007);
62 clk->rate = clk->parent->rate / pfc_divisors[idx-2]; 62 return clk->parent->rate / pfc_divisors[idx-2];
63} 63}
64 64
65static struct clk_ops sh7203_bus_clk_ops = { 65static struct clk_ops sh7203_bus_clk_ops = {
66 .recalc = bus_clk_recalc, 66 .recalc = bus_clk_recalc,
67}; 67};
68 68
69static void cpu_clk_recalc(struct clk *clk)
70{
71 clk->rate = clk->parent->rate;
72}
73
74static struct clk_ops sh7203_cpu_clk_ops = { 69static struct clk_ops sh7203_cpu_clk_ops = {
75 .recalc = cpu_clk_recalc, 70 .recalc = followparent_recalc,
76}; 71};
77 72
78static struct clk_ops *sh7203_clk_ops[] = { 73static struct clk_ops *sh7203_clk_ops[] = {
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index 82d7f991ef6b..c2268bdeceeb 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -41,29 +41,29 @@ static struct clk_ops sh7206_master_clk_ops = {
41 .init = master_clk_init, 41 .init = master_clk_init,
42}; 42};
43 43
44static void module_clk_recalc(struct clk *clk) 44static unsigned long module_clk_recalc(struct clk *clk)
45{ 45{
46 int idx = (ctrl_inw(FREQCR) & 0x0007); 46 int idx = (ctrl_inw(FREQCR) & 0x0007);
47 clk->rate = clk->parent->rate / pfc_divisors[idx]; 47 return clk->parent->rate / pfc_divisors[idx];
48} 48}
49 49
50static struct clk_ops sh7206_module_clk_ops = { 50static struct clk_ops sh7206_module_clk_ops = {
51 .recalc = module_clk_recalc, 51 .recalc = module_clk_recalc,
52}; 52};
53 53
54static void bus_clk_recalc(struct clk *clk) 54static unsigned long bus_clk_recalc(struct clk *clk)
55{ 55{
56 clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; 56 return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
57} 57}
58 58
59static struct clk_ops sh7206_bus_clk_ops = { 59static struct clk_ops sh7206_bus_clk_ops = {
60 .recalc = bus_clk_recalc, 60 .recalc = bus_clk_recalc,
61}; 61};
62 62
63static void cpu_clk_recalc(struct clk *clk) 63static unsigned long cpu_clk_recalc(struct clk *clk)
64{ 64{
65 int idx = (ctrl_inw(FREQCR) & 0x0007); 65 int idx = (ctrl_inw(FREQCR) & 0x0007);
66 clk->rate = clk->parent->rate / ifc_divisors[idx]; 66 return clk->parent->rate / ifc_divisors[idx];
67} 67}
68 68
69static struct clk_ops sh7206_cpu_clk_ops = { 69static struct clk_ops sh7206_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index a452d9649069..869c2da4820b 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -118,7 +118,7 @@ static struct sh_timer_config mtu2_0_platform_data = {
118 .name = "MTU2_0", 118 .name = "MTU2_0",
119 .channel_offset = -0x80, 119 .channel_offset = -0x80,
120 .timer_bit = 0, 120 .timer_bit = 0,
121 .clk = "module_clk", 121 .clk = "peripheral_clk",
122 .clockevent_rating = 200, 122 .clockevent_rating = 200,
123}; 123};
124 124
@@ -149,7 +149,7 @@ static struct sh_timer_config mtu2_1_platform_data = {
149 .name = "MTU2_1", 149 .name = "MTU2_1",
150 .channel_offset = -0x100, 150 .channel_offset = -0x100,
151 .timer_bit = 1, 151 .timer_bit = 1,
152 .clk = "module_clk", 152 .clk = "peripheral_clk",
153 .clockevent_rating = 200, 153 .clockevent_rating = 200,
154}; 154};
155 155
@@ -180,7 +180,7 @@ static struct sh_timer_config mtu2_2_platform_data = {
180 .name = "MTU2_2", 180 .name = "MTU2_2",
181 .channel_offset = 0x80, 181 .channel_offset = 0x80,
182 .timer_bit = 2, 182 .timer_bit = 2,
183 .clk = "module_clk", 183 .clk = "peripheral_clk",
184 .clockevent_rating = 200, 184 .clockevent_rating = 200,
185}; 185};
186 186
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 772358b7685e..d8febe128066 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -255,7 +255,7 @@ static struct sh_timer_config mtu2_0_platform_data = {
255 .name = "MTU2_0", 255 .name = "MTU2_0",
256 .channel_offset = -0x80, 256 .channel_offset = -0x80,
257 .timer_bit = 0, 257 .timer_bit = 0,
258 .clk = "module_clk", 258 .clk = "peripheral_clk",
259 .clockevent_rating = 200, 259 .clockevent_rating = 200,
260}; 260};
261 261
@@ -286,7 +286,7 @@ static struct sh_timer_config mtu2_1_platform_data = {
286 .name = "MTU2_1", 286 .name = "MTU2_1",
287 .channel_offset = -0x100, 287 .channel_offset = -0x100,
288 .timer_bit = 1, 288 .timer_bit = 1,
289 .clk = "module_clk", 289 .clk = "peripheral_clk",
290 .clockevent_rating = 200, 290 .clockevent_rating = 200,
291}; 291};
292 292
@@ -317,7 +317,7 @@ static struct sh_timer_config mtu2_2_platform_data = {
317 .name = "MTU2_2", 317 .name = "MTU2_2",
318 .channel_offset = 0x80, 318 .channel_offset = 0x80,
319 .timer_bit = 2, 319 .timer_bit = 2,
320 .clk = "module_clk", 320 .clk = "peripheral_clk",
321 .clockevent_rating = 200, 321 .clockevent_rating = 200,
322}; 322};
323 323
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index d7493418ba60..62e3039d2398 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -211,7 +211,7 @@ static struct sh_timer_config cmt0_platform_data = {
211 .name = "CMT0", 211 .name = "CMT0",
212 .channel_offset = 0x02, 212 .channel_offset = 0x02,
213 .timer_bit = 0, 213 .timer_bit = 0,
214 .clk = "module_clk", 214 .clk = "peripheral_clk",
215 .clockevent_rating = 125, 215 .clockevent_rating = 125,
216 .clocksource_rating = 0, /* disabled due to code generation issues */ 216 .clocksource_rating = 0, /* disabled due to code generation issues */
217}; 217};
@@ -243,7 +243,7 @@ static struct sh_timer_config cmt1_platform_data = {
243 .name = "CMT1", 243 .name = "CMT1",
244 .channel_offset = 0x08, 244 .channel_offset = 0x08,
245 .timer_bit = 1, 245 .timer_bit = 1,
246 .clk = "module_clk", 246 .clk = "peripheral_clk",
247 .clockevent_rating = 125, 247 .clockevent_rating = 125,
248 .clocksource_rating = 0, /* disabled due to code generation issues */ 248 .clocksource_rating = 0, /* disabled due to code generation issues */
249}; 249};
@@ -275,7 +275,7 @@ static struct sh_timer_config mtu2_0_platform_data = {
275 .name = "MTU2_0", 275 .name = "MTU2_0",
276 .channel_offset = -0x80, 276 .channel_offset = -0x80,
277 .timer_bit = 0, 277 .timer_bit = 0,
278 .clk = "module_clk", 278 .clk = "peripheral_clk",
279 .clockevent_rating = 200, 279 .clockevent_rating = 200,
280}; 280};
281 281
@@ -306,7 +306,7 @@ static struct sh_timer_config mtu2_1_platform_data = {
306 .name = "MTU2_1", 306 .name = "MTU2_1",
307 .channel_offset = -0x100, 307 .channel_offset = -0x100,
308 .timer_bit = 1, 308 .timer_bit = 1,
309 .clk = "module_clk", 309 .clk = "peripheral_clk",
310 .clockevent_rating = 200, 310 .clockevent_rating = 200,
311}; 311};
312 312
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index 2fc6bff5c5fb..3e6f3d7a58be 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -171,7 +171,7 @@ static struct sh_timer_config cmt0_platform_data = {
171 .name = "CMT0", 171 .name = "CMT0",
172 .channel_offset = 0x02, 172 .channel_offset = 0x02,
173 .timer_bit = 0, 173 .timer_bit = 0,
174 .clk = "module_clk", 174 .clk = "peripheral_clk",
175 .clockevent_rating = 125, 175 .clockevent_rating = 125,
176 .clocksource_rating = 0, /* disabled due to code generation issues */ 176 .clocksource_rating = 0, /* disabled due to code generation issues */
177}; 177};
@@ -203,7 +203,7 @@ static struct sh_timer_config cmt1_platform_data = {
203 .name = "CMT1", 203 .name = "CMT1",
204 .channel_offset = 0x08, 204 .channel_offset = 0x08,
205 .timer_bit = 1, 205 .timer_bit = 1,
206 .clk = "module_clk", 206 .clk = "peripheral_clk",
207 .clockevent_rating = 125, 207 .clockevent_rating = 125,
208 .clocksource_rating = 0, /* disabled due to code generation issues */ 208 .clocksource_rating = 0, /* disabled due to code generation issues */
209}; 209};
@@ -235,7 +235,7 @@ static struct sh_timer_config mtu2_0_platform_data = {
235 .name = "MTU2_0", 235 .name = "MTU2_0",
236 .channel_offset = -0x80, 236 .channel_offset = -0x80,
237 .timer_bit = 0, 237 .timer_bit = 0,
238 .clk = "module_clk", 238 .clk = "peripheral_clk",
239 .clockevent_rating = 200, 239 .clockevent_rating = 200,
240}; 240};
241 241
@@ -266,7 +266,7 @@ static struct sh_timer_config mtu2_1_platform_data = {
266 .name = "MTU2_1", 266 .name = "MTU2_1",
267 .channel_offset = -0x100, 267 .channel_offset = -0x100,
268 .timer_bit = 1, 268 .timer_bit = 1,
269 .clk = "module_clk", 269 .clk = "peripheral_clk",
270 .clockevent_rating = 200, 270 .clockevent_rating = 200,
271}; 271};
272 272
@@ -297,7 +297,7 @@ static struct sh_timer_config mtu2_2_platform_data = {
297 .name = "MTU2_2", 297 .name = "MTU2_2",
298 .channel_offset = 0x80, 298 .channel_offset = 0x80,
299 .timer_bit = 2, 299 .timer_bit = 2,
300 .clk = "module_clk", 300 .clk = "peripheral_clk",
301 .clockevent_rating = 200, 301 .clockevent_rating = 200,
302}; 302};
303 303
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh3.c b/arch/sh/kernel/cpu/sh3/clock-sh3.c
index c3c945958baf..27b8738f0b09 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh3.c
@@ -38,36 +38,36 @@ static struct clk_ops sh3_master_clk_ops = {
38 .init = master_clk_init, 38 .init = master_clk_init,
39}; 39};
40 40
41static void module_clk_recalc(struct clk *clk) 41static unsigned long module_clk_recalc(struct clk *clk)
42{ 42{
43 int frqcr = ctrl_inw(FRQCR); 43 int frqcr = ctrl_inw(FRQCR);
44 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 44 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
45 45
46 clk->rate = clk->parent->rate / pfc_divisors[idx]; 46 return clk->parent->rate / pfc_divisors[idx];
47} 47}
48 48
49static struct clk_ops sh3_module_clk_ops = { 49static struct clk_ops sh3_module_clk_ops = {
50 .recalc = module_clk_recalc, 50 .recalc = module_clk_recalc,
51}; 51};
52 52
53static void bus_clk_recalc(struct clk *clk) 53static unsigned long bus_clk_recalc(struct clk *clk)
54{ 54{
55 int frqcr = ctrl_inw(FRQCR); 55 int frqcr = ctrl_inw(FRQCR);
56 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); 56 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
57 57
58 clk->rate = clk->parent->rate / stc_multipliers[idx]; 58 return clk->parent->rate / stc_multipliers[idx];
59} 59}
60 60
61static struct clk_ops sh3_bus_clk_ops = { 61static struct clk_ops sh3_bus_clk_ops = {
62 .recalc = bus_clk_recalc, 62 .recalc = bus_clk_recalc,
63}; 63};
64 64
65static void cpu_clk_recalc(struct clk *clk) 65static unsigned long cpu_clk_recalc(struct clk *clk)
66{ 66{
67 int frqcr = ctrl_inw(FRQCR); 67 int frqcr = ctrl_inw(FRQCR);
68 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); 68 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
69 69
70 clk->rate = clk->parent->rate / ifc_divisors[idx]; 70 return clk->parent->rate / ifc_divisors[idx];
71} 71}
72 72
73static struct clk_ops sh3_cpu_clk_ops = { 73static struct clk_ops sh3_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7705.c b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
index dfdbf3277fd7..0ca8f2c3646c 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
@@ -39,30 +39,30 @@ static struct clk_ops sh7705_master_clk_ops = {
39 .init = master_clk_init, 39 .init = master_clk_init,
40}; 40};
41 41
42static void module_clk_recalc(struct clk *clk) 42static unsigned long module_clk_recalc(struct clk *clk)
43{ 43{
44 int idx = ctrl_inw(FRQCR) & 0x0003; 44 int idx = ctrl_inw(FRQCR) & 0x0003;
45 clk->rate = clk->parent->rate / pfc_divisors[idx]; 45 return clk->parent->rate / pfc_divisors[idx];
46} 46}
47 47
48static struct clk_ops sh7705_module_clk_ops = { 48static struct clk_ops sh7705_module_clk_ops = {
49 .recalc = module_clk_recalc, 49 .recalc = module_clk_recalc,
50}; 50};
51 51
52static void bus_clk_recalc(struct clk *clk) 52static unsigned long bus_clk_recalc(struct clk *clk)
53{ 53{
54 int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8; 54 int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8;
55 clk->rate = clk->parent->rate / stc_multipliers[idx]; 55 return clk->parent->rate / stc_multipliers[idx];
56} 56}
57 57
58static struct clk_ops sh7705_bus_clk_ops = { 58static struct clk_ops sh7705_bus_clk_ops = {
59 .recalc = bus_clk_recalc, 59 .recalc = bus_clk_recalc,
60}; 60};
61 61
62static void cpu_clk_recalc(struct clk *clk) 62static unsigned long cpu_clk_recalc(struct clk *clk)
63{ 63{
64 int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4; 64 int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4;
65 clk->rate = clk->parent->rate / ifc_divisors[idx]; 65 return clk->parent->rate / ifc_divisors[idx];
66} 66}
67 67
68static struct clk_ops sh7705_cpu_clk_ops = { 68static struct clk_ops sh7705_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7706.c b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
index 0cf96f9833bc..4bf7887d310a 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7706.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
@@ -34,36 +34,36 @@ static struct clk_ops sh7706_master_clk_ops = {
34 .init = master_clk_init, 34 .init = master_clk_init,
35}; 35};
36 36
37static void module_clk_recalc(struct clk *clk) 37static unsigned long module_clk_recalc(struct clk *clk)
38{ 38{
39 int frqcr = ctrl_inw(FRQCR); 39 int frqcr = ctrl_inw(FRQCR);
40 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 40 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
41 41
42 clk->rate = clk->parent->rate / pfc_divisors[idx]; 42 return clk->parent->rate / pfc_divisors[idx];
43} 43}
44 44
45static struct clk_ops sh7706_module_clk_ops = { 45static struct clk_ops sh7706_module_clk_ops = {
46 .recalc = module_clk_recalc, 46 .recalc = module_clk_recalc,
47}; 47};
48 48
49static void bus_clk_recalc(struct clk *clk) 49static unsigned long bus_clk_recalc(struct clk *clk)
50{ 50{
51 int frqcr = ctrl_inw(FRQCR); 51 int frqcr = ctrl_inw(FRQCR);
52 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); 52 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
53 53
54 clk->rate = clk->parent->rate / stc_multipliers[idx]; 54 return clk->parent->rate / stc_multipliers[idx];
55} 55}
56 56
57static struct clk_ops sh7706_bus_clk_ops = { 57static struct clk_ops sh7706_bus_clk_ops = {
58 .recalc = bus_clk_recalc, 58 .recalc = bus_clk_recalc,
59}; 59};
60 60
61static void cpu_clk_recalc(struct clk *clk) 61static unsigned long cpu_clk_recalc(struct clk *clk)
62{ 62{
63 int frqcr = ctrl_inw(FRQCR); 63 int frqcr = ctrl_inw(FRQCR);
64 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); 64 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
65 65
66 clk->rate = clk->parent->rate / ifc_divisors[idx]; 66 return clk->parent->rate / ifc_divisors[idx];
67} 67}
68 68
69static struct clk_ops sh7706_cpu_clk_ops = { 69static struct clk_ops sh7706_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7709.c b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
index b791a29fdb62..fa30b6017730 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
@@ -41,12 +41,12 @@ static struct clk_ops sh7709_master_clk_ops = {
41 .init = master_clk_init, 41 .init = master_clk_init,
42}; 42};
43 43
44static void module_clk_recalc(struct clk *clk) 44static unsigned long module_clk_recalc(struct clk *clk)
45{ 45{
46 int frqcr = ctrl_inw(FRQCR); 46 int frqcr = ctrl_inw(FRQCR);
47 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 47 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
48 48
49 clk->rate = clk->parent->rate / pfc_divisors[idx]; 49 return clk->parent->rate / pfc_divisors[idx];
50} 50}
51 51
52static struct clk_ops sh7709_module_clk_ops = { 52static struct clk_ops sh7709_module_clk_ops = {
@@ -56,25 +56,25 @@ static struct clk_ops sh7709_module_clk_ops = {
56 .recalc = module_clk_recalc, 56 .recalc = module_clk_recalc,
57}; 57};
58 58
59static void bus_clk_recalc(struct clk *clk) 59static unsigned long bus_clk_recalc(struct clk *clk)
60{ 60{
61 int frqcr = ctrl_inw(FRQCR); 61 int frqcr = ctrl_inw(FRQCR);
62 int idx = (frqcr & 0x0080) ? 62 int idx = (frqcr & 0x0080) ?
63 ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1; 63 ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1;
64 64
65 clk->rate = clk->parent->rate * stc_multipliers[idx]; 65 return clk->parent->rate * stc_multipliers[idx];
66} 66}
67 67
68static struct clk_ops sh7709_bus_clk_ops = { 68static struct clk_ops sh7709_bus_clk_ops = {
69 .recalc = bus_clk_recalc, 69 .recalc = bus_clk_recalc,
70}; 70};
71 71
72static void cpu_clk_recalc(struct clk *clk) 72static unsigned long cpu_clk_recalc(struct clk *clk)
73{ 73{
74 int frqcr = ctrl_inw(FRQCR); 74 int frqcr = ctrl_inw(FRQCR);
75 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); 75 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
76 76
77 clk->rate = clk->parent->rate / ifc_divisors[idx]; 77 return clk->parent->rate / ifc_divisors[idx];
78} 78}
79 79
80static struct clk_ops sh7709_cpu_clk_ops = { 80static struct clk_ops sh7709_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7710.c b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
index 4744c50ec449..030a58ba18a5 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
@@ -33,30 +33,30 @@ static struct clk_ops sh7710_master_clk_ops = {
33 .init = master_clk_init, 33 .init = master_clk_init,
34}; 34};
35 35
36static void module_clk_recalc(struct clk *clk) 36static unsigned long module_clk_recalc(struct clk *clk)
37{ 37{
38 int idx = (ctrl_inw(FRQCR) & 0x0007); 38 int idx = (ctrl_inw(FRQCR) & 0x0007);
39 clk->rate = clk->parent->rate / md_table[idx]; 39 return clk->parent->rate / md_table[idx];
40} 40}
41 41
42static struct clk_ops sh7710_module_clk_ops = { 42static struct clk_ops sh7710_module_clk_ops = {
43 .recalc = module_clk_recalc, 43 .recalc = module_clk_recalc,
44}; 44};
45 45
46static void bus_clk_recalc(struct clk *clk) 46static unsigned long bus_clk_recalc(struct clk *clk)
47{ 47{
48 int idx = (ctrl_inw(FRQCR) & 0x0700) >> 8; 48 int idx = (ctrl_inw(FRQCR) & 0x0700) >> 8;
49 clk->rate = clk->parent->rate / md_table[idx]; 49 return clk->parent->rate / md_table[idx];
50} 50}
51 51
52static struct clk_ops sh7710_bus_clk_ops = { 52static struct clk_ops sh7710_bus_clk_ops = {
53 .recalc = bus_clk_recalc, 53 .recalc = bus_clk_recalc,
54}; 54};
55 55
56static void cpu_clk_recalc(struct clk *clk) 56static unsigned long cpu_clk_recalc(struct clk *clk)
57{ 57{
58 int idx = (ctrl_inw(FRQCR) & 0x0070) >> 4; 58 int idx = (ctrl_inw(FRQCR) & 0x0070) >> 4;
59 clk->rate = clk->parent->rate / md_table[idx]; 59 return clk->parent->rate / md_table[idx];
60} 60}
61 61
62static struct clk_ops sh7710_cpu_clk_ops = { 62static struct clk_ops sh7710_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7712.c b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
index 54f54df51ef0..6428ee6c77ed 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7712.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
@@ -33,24 +33,24 @@ static struct clk_ops sh7712_master_clk_ops = {
33 .init = master_clk_init, 33 .init = master_clk_init,
34}; 34};
35 35
36static void module_clk_recalc(struct clk *clk) 36static unsigned long module_clk_recalc(struct clk *clk)
37{ 37{
38 int frqcr = ctrl_inw(FRQCR); 38 int frqcr = ctrl_inw(FRQCR);
39 int idx = frqcr & 0x0007; 39 int idx = frqcr & 0x0007;
40 40
41 clk->rate = clk->parent->rate / divisors[idx]; 41 return clk->parent->rate / divisors[idx];
42} 42}
43 43
44static struct clk_ops sh7712_module_clk_ops = { 44static struct clk_ops sh7712_module_clk_ops = {
45 .recalc = module_clk_recalc, 45 .recalc = module_clk_recalc,
46}; 46};
47 47
48static void cpu_clk_recalc(struct clk *clk) 48static unsigned long cpu_clk_recalc(struct clk *clk)
49{ 49{
50 int frqcr = ctrl_inw(FRQCR); 50 int frqcr = ctrl_inw(FRQCR);
51 int idx = (frqcr & 0x0030) >> 4; 51 int idx = (frqcr & 0x0030) >> 4;
52 52
53 clk->rate = clk->parent->rate / divisors[idx]; 53 return clk->parent->rate / divisors[idx];
54} 54}
55 55
56static struct clk_ops sh7712_cpu_clk_ops = { 56static struct clk_ops sh7712_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 39513664d5d7..88f742fed9ed 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -121,7 +121,7 @@ static struct sh_timer_config tmu0_platform_data = {
121 .name = "TMU0", 121 .name = "TMU0",
122 .channel_offset = 0x02, 122 .channel_offset = 0x02,
123 .timer_bit = 0, 123 .timer_bit = 0,
124 .clk = "module_clk", 124 .clk = "peripheral_clk",
125 .clockevent_rating = 200, 125 .clockevent_rating = 200,
126}; 126};
127 127
@@ -152,7 +152,7 @@ static struct sh_timer_config tmu1_platform_data = {
152 .name = "TMU1", 152 .name = "TMU1",
153 .channel_offset = 0xe, 153 .channel_offset = 0xe,
154 .timer_bit = 1, 154 .timer_bit = 1,
155 .clk = "module_clk", 155 .clk = "peripheral_clk",
156 .clocksource_rating = 200, 156 .clocksource_rating = 200,
157}; 157};
158 158
@@ -183,7 +183,7 @@ static struct sh_timer_config tmu2_platform_data = {
183 .name = "TMU2", 183 .name = "TMU2",
184 .channel_offset = 0x1a, 184 .channel_offset = 0x1a,
185 .timer_bit = 2, 185 .timer_bit = 2,
186 .clk = "module_clk", 186 .clk = "peripheral_clk",
187}; 187};
188 188
189static struct resource tmu2_resources[] = { 189static struct resource tmu2_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 9412d915b84e..c56306798584 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -149,7 +149,7 @@ static struct sh_timer_config tmu0_platform_data = {
149 .name = "TMU0", 149 .name = "TMU0",
150 .channel_offset = 0x02, 150 .channel_offset = 0x02,
151 .timer_bit = 0, 151 .timer_bit = 0,
152 .clk = "module_clk", 152 .clk = "peripheral_clk",
153 .clockevent_rating = 200, 153 .clockevent_rating = 200,
154}; 154};
155 155
@@ -180,7 +180,7 @@ static struct sh_timer_config tmu1_platform_data = {
180 .name = "TMU1", 180 .name = "TMU1",
181 .channel_offset = 0xe, 181 .channel_offset = 0xe,
182 .timer_bit = 1, 182 .timer_bit = 1,
183 .clk = "module_clk", 183 .clk = "peripheral_clk",
184 .clocksource_rating = 200, 184 .clocksource_rating = 200,
185}; 185};
186 186
@@ -211,7 +211,7 @@ static struct sh_timer_config tmu2_platform_data = {
211 .name = "TMU2", 211 .name = "TMU2",
212 .channel_offset = 0x1a, 212 .channel_offset = 0x1a,
213 .timer_bit = 2, 213 .timer_bit = 2,
214 .clk = "module_clk", 214 .clk = "peripheral_clk",
215}; 215};
216 216
217static struct resource tmu2_resources[] = { 217static struct resource tmu2_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 07ff38d055a7..efa76c8148f4 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -125,7 +125,7 @@ static struct sh_timer_config tmu0_platform_data = {
125 .name = "TMU0", 125 .name = "TMU0",
126 .channel_offset = 0x02, 126 .channel_offset = 0x02,
127 .timer_bit = 0, 127 .timer_bit = 0,
128 .clk = "module_clk", 128 .clk = "peripheral_clk",
129 .clockevent_rating = 200, 129 .clockevent_rating = 200,
130}; 130};
131 131
@@ -156,7 +156,7 @@ static struct sh_timer_config tmu1_platform_data = {
156 .name = "TMU1", 156 .name = "TMU1",
157 .channel_offset = 0xe, 157 .channel_offset = 0xe,
158 .timer_bit = 1, 158 .timer_bit = 1,
159 .clk = "module_clk", 159 .clk = "peripheral_clk",
160 .clocksource_rating = 200, 160 .clocksource_rating = 200,
161}; 161};
162 162
@@ -187,7 +187,7 @@ static struct sh_timer_config tmu2_platform_data = {
187 .name = "TMU2", 187 .name = "TMU2",
188 .channel_offset = 0x1a, 188 .channel_offset = 0x1a,
189 .timer_bit = 2, 189 .timer_bit = 2,
190 .clk = "module_clk", 190 .clk = "peripheral_clk",
191}; 191};
192 192
193static struct resource tmu2_resources[] = { 193static struct resource tmu2_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index d8b46f5dff60..5b2107798edb 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -128,7 +128,7 @@ static struct sh_timer_config cmt0_platform_data = {
128 .name = "CMT0", 128 .name = "CMT0",
129 .channel_offset = 0x10, 129 .channel_offset = 0x10,
130 .timer_bit = 0, 130 .timer_bit = 0,
131 .clk = "module_clk", 131 .clk = "peripheral_clk",
132 .clockevent_rating = 125, 132 .clockevent_rating = 125,
133 .clocksource_rating = 125, 133 .clocksource_rating = 125,
134}; 134};
@@ -160,7 +160,7 @@ static struct sh_timer_config cmt1_platform_data = {
160 .name = "CMT1", 160 .name = "CMT1",
161 .channel_offset = 0x20, 161 .channel_offset = 0x20,
162 .timer_bit = 1, 162 .timer_bit = 1,
163 .clk = "module_clk", 163 .clk = "peripheral_clk",
164}; 164};
165 165
166static struct resource cmt1_resources[] = { 166static struct resource cmt1_resources[] = {
@@ -190,7 +190,7 @@ static struct sh_timer_config cmt2_platform_data = {
190 .name = "CMT2", 190 .name = "CMT2",
191 .channel_offset = 0x30, 191 .channel_offset = 0x30,
192 .timer_bit = 2, 192 .timer_bit = 2,
193 .clk = "module_clk", 193 .clk = "peripheral_clk",
194}; 194};
195 195
196static struct resource cmt2_resources[] = { 196static struct resource cmt2_resources[] = {
@@ -220,7 +220,7 @@ static struct sh_timer_config cmt3_platform_data = {
220 .name = "CMT3", 220 .name = "CMT3",
221 .channel_offset = 0x40, 221 .channel_offset = 0x40,
222 .timer_bit = 3, 222 .timer_bit = 3,
223 .clk = "module_clk", 223 .clk = "peripheral_clk",
224}; 224};
225 225
226static struct resource cmt3_resources[] = { 226static struct resource cmt3_resources[] = {
@@ -250,7 +250,7 @@ static struct sh_timer_config cmt4_platform_data = {
250 .name = "CMT4", 250 .name = "CMT4",
251 .channel_offset = 0x50, 251 .channel_offset = 0x50,
252 .timer_bit = 4, 252 .timer_bit = 4,
253 .clk = "module_clk", 253 .clk = "peripheral_clk",
254}; 254};
255 255
256static struct resource cmt4_resources[] = { 256static struct resource cmt4_resources[] = {
@@ -280,7 +280,7 @@ static struct sh_timer_config tmu0_platform_data = {
280 .name = "TMU0", 280 .name = "TMU0",
281 .channel_offset = 0x02, 281 .channel_offset = 0x02,
282 .timer_bit = 0, 282 .timer_bit = 0,
283 .clk = "module_clk", 283 .clk = "peripheral_clk",
284 .clockevent_rating = 200, 284 .clockevent_rating = 200,
285}; 285};
286 286
@@ -311,7 +311,7 @@ static struct sh_timer_config tmu1_platform_data = {
311 .name = "TMU1", 311 .name = "TMU1",
312 .channel_offset = 0xe, 312 .channel_offset = 0xe,
313 .timer_bit = 1, 313 .timer_bit = 1,
314 .clk = "module_clk", 314 .clk = "peripheral_clk",
315 .clocksource_rating = 200, 315 .clocksource_rating = 200,
316}; 316};
317 317
@@ -342,7 +342,7 @@ static struct sh_timer_config tmu2_platform_data = {
342 .name = "TMU2", 342 .name = "TMU2",
343 .channel_offset = 0x1a, 343 .channel_offset = 0x1a,
344 .timer_bit = 2, 344 .timer_bit = 2,
345 .clk = "module_clk", 345 .clk = "peripheral_clk",
346}; 346};
347 347
348static struct resource tmu2_resources[] = { 348static struct resource tmu2_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index a33429463e96..21421e34e7d5 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -21,10 +21,10 @@
21static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 }; 21static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 };
22static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 }; 22static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 };
23 23
24static void emi_clk_recalc(struct clk *clk) 24static unsigned long emi_clk_recalc(struct clk *clk)
25{ 25{
26 int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007; 26 int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007;
27 clk->rate = clk->parent->rate / frqcr3_divisors[idx]; 27 return clk->parent->rate / frqcr3_divisors[idx];
28} 28}
29 29
30static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) 30static inline int frqcr3_lookup(struct clk *clk, unsigned long rate)
@@ -46,14 +46,14 @@ static struct clk_ops sh4202_emi_clk_ops = {
46 46
47static struct clk sh4202_emi_clk = { 47static struct clk sh4202_emi_clk = {
48 .name = "emi_clk", 48 .name = "emi_clk",
49 .flags = CLK_ALWAYS_ENABLED, 49 .flags = CLK_ENABLE_ON_INIT,
50 .ops = &sh4202_emi_clk_ops, 50 .ops = &sh4202_emi_clk_ops,
51}; 51};
52 52
53static void femi_clk_recalc(struct clk *clk) 53static unsigned long femi_clk_recalc(struct clk *clk)
54{ 54{
55 int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007; 55 int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007;
56 clk->rate = clk->parent->rate / frqcr3_divisors[idx]; 56 return clk->parent->rate / frqcr3_divisors[idx];
57} 57}
58 58
59static struct clk_ops sh4202_femi_clk_ops = { 59static struct clk_ops sh4202_femi_clk_ops = {
@@ -62,7 +62,7 @@ static struct clk_ops sh4202_femi_clk_ops = {
62 62
63static struct clk sh4202_femi_clk = { 63static struct clk sh4202_femi_clk = {
64 .name = "femi_clk", 64 .name = "femi_clk",
65 .flags = CLK_ALWAYS_ENABLED, 65 .flags = CLK_ENABLE_ON_INIT,
66 .ops = &sh4202_femi_clk_ops, 66 .ops = &sh4202_femi_clk_ops,
67}; 67};
68 68
@@ -90,10 +90,10 @@ static void shoc_clk_init(struct clk *clk)
90 WARN_ON(i == ARRAY_SIZE(frqcr3_divisors)); /* Undefined clock */ 90 WARN_ON(i == ARRAY_SIZE(frqcr3_divisors)); /* Undefined clock */
91} 91}
92 92
93static void shoc_clk_recalc(struct clk *clk) 93static unsigned long shoc_clk_recalc(struct clk *clk)
94{ 94{
95 int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007; 95 int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007;
96 clk->rate = clk->parent->rate / frqcr3_divisors[idx]; 96 return clk->parent->rate / frqcr3_divisors[idx];
97} 97}
98 98
99static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate) 99static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
@@ -140,7 +140,7 @@ static struct clk_ops sh4202_shoc_clk_ops = {
140 140
141static struct clk sh4202_shoc_clk = { 141static struct clk sh4202_shoc_clk = {
142 .name = "shoc_clk", 142 .name = "shoc_clk",
143 .flags = CLK_ALWAYS_ENABLED, 143 .flags = CLK_ENABLE_ON_INIT,
144 .ops = &sh4202_shoc_clk_ops, 144 .ops = &sh4202_shoc_clk_ops,
145}; 145};
146 146
@@ -150,31 +150,22 @@ static struct clk *sh4202_onchip_clocks[] = {
150 &sh4202_shoc_clk, 150 &sh4202_shoc_clk,
151}; 151};
152 152
153static int __init sh4202_clk_init(void) 153int __init arch_clk_init(void)
154{ 154{
155 struct clk *clk = clk_get(NULL, "master_clk"); 155 struct clk *clk;
156 int i; 156 int i, ret = 0;
157
158 cpg_clk_init();
157 159
160 clk = clk_get(NULL, "master_clk");
158 for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) { 161 for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) {
159 struct clk *clkp = sh4202_onchip_clocks[i]; 162 struct clk *clkp = sh4202_onchip_clocks[i];
160 163
161 clkp->parent = clk; 164 clkp->parent = clk;
162 clk_register(clkp); 165 ret |= clk_register(clkp);
163 clk_enable(clkp);
164 } 166 }
165 167
166 /*
167 * Now that we have the rest of the clocks registered, we need to
168 * force the parent clock to propagate so that these clocks will
169 * automatically figure out their rate. We cheat by handing the
170 * parent clock its current rate and forcing child propagation.
171 */
172 clk_set_rate(clk, clk_get_rate(clk));
173
174 clk_put(clk); 168 clk_put(clk);
175 169
176 return 0; 170 return ret;
177} 171}
178
179arch_initcall(sh4202_clk_init);
180
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4.c b/arch/sh/kernel/cpu/sh4/clock-sh4.c
index dca9f87a12d6..73294d9cd049 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4.c
@@ -35,30 +35,30 @@ static struct clk_ops sh4_master_clk_ops = {
35 .init = master_clk_init, 35 .init = master_clk_init,
36}; 36};
37 37
38static void module_clk_recalc(struct clk *clk) 38static unsigned long module_clk_recalc(struct clk *clk)
39{ 39{
40 int idx = (ctrl_inw(FRQCR) & 0x0007); 40 int idx = (ctrl_inw(FRQCR) & 0x0007);
41 clk->rate = clk->parent->rate / pfc_divisors[idx]; 41 return clk->parent->rate / pfc_divisors[idx];
42} 42}
43 43
44static struct clk_ops sh4_module_clk_ops = { 44static struct clk_ops sh4_module_clk_ops = {
45 .recalc = module_clk_recalc, 45 .recalc = module_clk_recalc,
46}; 46};
47 47
48static void bus_clk_recalc(struct clk *clk) 48static unsigned long bus_clk_recalc(struct clk *clk)
49{ 49{
50 int idx = (ctrl_inw(FRQCR) >> 3) & 0x0007; 50 int idx = (ctrl_inw(FRQCR) >> 3) & 0x0007;
51 clk->rate = clk->parent->rate / bfc_divisors[idx]; 51 return clk->parent->rate / bfc_divisors[idx];
52} 52}
53 53
54static struct clk_ops sh4_bus_clk_ops = { 54static struct clk_ops sh4_bus_clk_ops = {
55 .recalc = bus_clk_recalc, 55 .recalc = bus_clk_recalc,
56}; 56};
57 57
58static void cpu_clk_recalc(struct clk *clk) 58static unsigned long cpu_clk_recalc(struct clk *clk)
59{ 59{
60 int idx = (ctrl_inw(FRQCR) >> 6) & 0x0007; 60 int idx = (ctrl_inw(FRQCR) >> 6) & 0x0007;
61 clk->rate = clk->parent->rate / ifc_divisors[idx]; 61 return clk->parent->rate / ifc_divisors[idx];
62} 62}
63 63
64static struct clk_ops sh4_cpu_clk_ops = { 64static struct clk_ops sh4_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index be79fa136255..6d088d123591 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -38,7 +38,7 @@ static struct sh_timer_config tmu0_platform_data = {
38 .name = "TMU0", 38 .name = "TMU0",
39 .channel_offset = 0x04, 39 .channel_offset = 0x04,
40 .timer_bit = 0, 40 .timer_bit = 0,
41 .clk = "module_clk", 41 .clk = "peripheral_clk",
42 .clockevent_rating = 200, 42 .clockevent_rating = 200,
43}; 43};
44 44
@@ -69,7 +69,7 @@ static struct sh_timer_config tmu1_platform_data = {
69 .name = "TMU1", 69 .name = "TMU1",
70 .channel_offset = 0x10, 70 .channel_offset = 0x10,
71 .timer_bit = 1, 71 .timer_bit = 1,
72 .clk = "module_clk", 72 .clk = "peripheral_clk",
73 .clocksource_rating = 200, 73 .clocksource_rating = 200,
74}; 74};
75 75
@@ -100,7 +100,7 @@ static struct sh_timer_config tmu2_platform_data = {
100 .name = "TMU2", 100 .name = "TMU2",
101 .channel_offset = 0x1c, 101 .channel_offset = 0x1c,
102 .timer_bit = 2, 102 .timer_bit = 2,
103 .clk = "module_clk", 103 .clk = "peripheral_clk",
104}; 104};
105 105
106static struct resource tmu2_resources[] = { 106static struct resource tmu2_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 09da0c187d4c..851672d15cf4 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -65,7 +65,7 @@ static struct sh_timer_config tmu0_platform_data = {
65 .name = "TMU0", 65 .name = "TMU0",
66 .channel_offset = 0x04, 66 .channel_offset = 0x04,
67 .timer_bit = 0, 67 .timer_bit = 0,
68 .clk = "module_clk", 68 .clk = "peripheral_clk",
69 .clockevent_rating = 200, 69 .clockevent_rating = 200,
70}; 70};
71 71
@@ -96,7 +96,7 @@ static struct sh_timer_config tmu1_platform_data = {
96 .name = "TMU1", 96 .name = "TMU1",
97 .channel_offset = 0x10, 97 .channel_offset = 0x10,
98 .timer_bit = 1, 98 .timer_bit = 1,
99 .clk = "module_clk", 99 .clk = "peripheral_clk",
100 .clocksource_rating = 200, 100 .clocksource_rating = 200,
101}; 101};
102 102
@@ -127,7 +127,7 @@ static struct sh_timer_config tmu2_platform_data = {
127 .name = "TMU2", 127 .name = "TMU2",
128 .channel_offset = 0x1c, 128 .channel_offset = 0x1c,
129 .timer_bit = 2, 129 .timer_bit = 2,
130 .clk = "module_clk", 130 .clk = "peripheral_clk",
131}; 131};
132 132
133static struct resource tmu2_resources[] = { 133static struct resource tmu2_resources[] = {
@@ -162,7 +162,7 @@ static struct sh_timer_config tmu3_platform_data = {
162 .name = "TMU3", 162 .name = "TMU3",
163 .channel_offset = 0x04, 163 .channel_offset = 0x04,
164 .timer_bit = 0, 164 .timer_bit = 0,
165 .clk = "module_clk", 165 .clk = "peripheral_clk",
166}; 166};
167 167
168static struct resource tmu3_resources[] = { 168static struct resource tmu3_resources[] = {
@@ -192,7 +192,7 @@ static struct sh_timer_config tmu4_platform_data = {
192 .name = "TMU4", 192 .name = "TMU4",
193 .channel_offset = 0x10, 193 .channel_offset = 0x10,
194 .timer_bit = 1, 194 .timer_bit = 1,
195 .clk = "module_clk", 195 .clk = "peripheral_clk",
196}; 196};
197 197
198static struct resource tmu4_resources[] = { 198static struct resource tmu4_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index cd097335758f..5b822519bd90 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -164,7 +164,7 @@ static struct sh_timer_config tmu0_platform_data = {
164 .name = "TMU0", 164 .name = "TMU0",
165 .channel_offset = 0x04, 165 .channel_offset = 0x04,
166 .timer_bit = 0, 166 .timer_bit = 0,
167 .clk = "module_clk", 167 .clk = "peripheral_clk",
168 .clockevent_rating = 200, 168 .clockevent_rating = 200,
169}; 169};
170 170
@@ -195,7 +195,7 @@ static struct sh_timer_config tmu1_platform_data = {
195 .name = "TMU1", 195 .name = "TMU1",
196 .channel_offset = 0x10, 196 .channel_offset = 0x10,
197 .timer_bit = 1, 197 .timer_bit = 1,
198 .clk = "module_clk", 198 .clk = "peripheral_clk",
199 .clocksource_rating = 200, 199 .clocksource_rating = 200,
200}; 200};
201 201
@@ -226,7 +226,7 @@ static struct sh_timer_config tmu2_platform_data = {
226 .name = "TMU2", 226 .name = "TMU2",
227 .channel_offset = 0x1c, 227 .channel_offset = 0x1c,
228 .timer_bit = 2, 228 .timer_bit = 2,
229 .clk = "module_clk", 229 .clk = "peripheral_clk",
230}; 230};
231 231
232static struct resource tmu2_resources[] = { 232static struct resource tmu2_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 1ccdfc561fef..c090c9a373f6 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -151,27 +151,24 @@ static int divisors2[] = { 4, 1, 8, 12, 16, 24, 32, 1, 48, 64, 72, 96, 1, 144 };
151static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 }; 151static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
152#endif 152#endif
153 153
154static void master_clk_recalc(struct clk *clk) 154static unsigned long master_clk_recalc(struct clk *clk)
155{ 155{
156 unsigned frqcr = ctrl_inl(FRQCR); 156 unsigned frqcr = ctrl_inl(FRQCR);
157 157
158 clk->rate = CONFIG_SH_PCLK_FREQ * STCPLL(frqcr); 158 return CONFIG_SH_PCLK_FREQ * STCPLL(frqcr);
159} 159}
160 160
161static void master_clk_init(struct clk *clk) 161static void master_clk_init(struct clk *clk)
162{ 162{
163 clk->parent = NULL; 163 clk->parent = NULL;
164 clk->flags |= CLK_RATE_PROPAGATES; 164 clk->rate = master_clk_recalc(clk);
165 clk->rate = CONFIG_SH_PCLK_FREQ;
166 master_clk_recalc(clk);
167} 165}
168 166
169 167static unsigned long module_clk_recalc(struct clk *clk)
170static void module_clk_recalc(struct clk *clk)
171{ 168{
172 unsigned long frqcr = ctrl_inl(FRQCR); 169 unsigned long frqcr = ctrl_inl(FRQCR);
173 170
174 clk->rate = clk->parent->rate / STCPLL(frqcr); 171 return clk->parent->rate / STCPLL(frqcr);
175} 172}
176 173
177#if defined(CONFIG_CPU_SUBTYPE_SH7724) 174#if defined(CONFIG_CPU_SUBTYPE_SH7724)
@@ -283,14 +280,14 @@ static int sh7722_find_div_index(unsigned long parent_rate, unsigned rate)
283 return index; 280 return index;
284} 281}
285 282
286static void sh7722_frqcr_recalc(struct clk *clk) 283static unsigned long sh7722_frqcr_recalc(struct clk *clk)
287{ 284{
288 struct frqcr_context ctx = sh7722_get_clk_context(clk->name); 285 struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
289 unsigned long frqcr = ctrl_inl(FRQCR); 286 unsigned long frqcr = ctrl_inl(FRQCR);
290 int index; 287 int index;
291 288
292 index = (frqcr >> ctx.shift) & ctx.mask; 289 index = (frqcr >> ctx.shift) & ctx.mask;
293 clk->rate = clk->parent->rate * 2 / divisors2[index]; 290 return clk->parent->rate * 2 / divisors2[index];
294} 291}
295 292
296static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate, 293static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
@@ -439,11 +436,8 @@ static struct clk_ops sh7722_frqcr_clk_ops = {
439 436
440/* 437/*
441 * clock ops methods for SIU A/B and IrDA clock 438 * clock ops methods for SIU A/B and IrDA clock
442 *
443 */ 439 */
444
445#ifndef CONFIG_CPU_SUBTYPE_SH7343 440#ifndef CONFIG_CPU_SUBTYPE_SH7343
446
447static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id) 441static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
448{ 442{
449 unsigned long r; 443 unsigned long r;
@@ -458,12 +452,12 @@ static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
458 return 0; 452 return 0;
459} 453}
460 454
461static void sh7722_siu_recalc(struct clk *clk) 455static unsigned long sh7722_siu_recalc(struct clk *clk)
462{ 456{
463 unsigned long r; 457 unsigned long r;
464 458
465 r = ctrl_inl(clk->arch_flags); 459 r = ctrl_inl(clk->arch_flags);
466 clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF]; 460 return clk->parent->rate * 2 / divisors2[r & 0xF];
467} 461}
468 462
469static int sh7722_siu_start_stop(struct clk *clk, int enable) 463static int sh7722_siu_start_stop(struct clk *clk, int enable)
@@ -478,9 +472,9 @@ static int sh7722_siu_start_stop(struct clk *clk, int enable)
478 return 0; 472 return 0;
479} 473}
480 474
481static void sh7722_siu_enable(struct clk *clk) 475static int sh7722_siu_enable(struct clk *clk)
482{ 476{
483 sh7722_siu_start_stop(clk, 1); 477 return sh7722_siu_start_stop(clk, 1);
484} 478}
485 479
486static void sh7722_siu_disable(struct clk *clk) 480static void sh7722_siu_disable(struct clk *clk)
@@ -497,12 +491,13 @@ static struct clk_ops sh7722_siu_clk_ops = {
497 491
498#endif /* CONFIG_CPU_SUBTYPE_SH7343 */ 492#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
499 493
500static void sh7722_video_enable(struct clk *clk) 494static int sh7722_video_enable(struct clk *clk)
501{ 495{
502 unsigned long r; 496 unsigned long r;
503 497
504 r = ctrl_inl(VCLKCR); 498 r = ctrl_inl(VCLKCR);
505 ctrl_outl( r & ~(1<<8), VCLKCR); 499 ctrl_outl( r & ~(1<<8), VCLKCR);
500 return 0;
506} 501}
507 502
508static void sh7722_video_disable(struct clk *clk) 503static void sh7722_video_disable(struct clk *clk)
@@ -525,12 +520,12 @@ static int sh7722_video_set_rate(struct clk *clk, unsigned long rate,
525 return 0; 520 return 0;
526} 521}
527 522
528static void sh7722_video_recalc(struct clk *clk) 523static unsigned long sh7722_video_recalc(struct clk *clk)
529{ 524{
530 unsigned long r; 525 unsigned long r;
531 526
532 r = ctrl_inl(VCLKCR); 527 r = ctrl_inl(VCLKCR);
533 clk->rate = clk->parent->rate / ((r & 0x3F) + 1); 528 return clk->parent->rate / ((r & 0x3F) + 1);
534} 529}
535 530
536static struct clk_ops sh7722_video_clk_ops = { 531static struct clk_ops sh7722_video_clk_ops = {
@@ -545,19 +540,16 @@ static struct clk_ops sh7722_video_clk_ops = {
545static struct clk sh7722_umem_clock = { 540static struct clk sh7722_umem_clock = {
546 .name = "umem_clk", 541 .name = "umem_clk",
547 .ops = &sh7722_frqcr_clk_ops, 542 .ops = &sh7722_frqcr_clk_ops,
548 .flags = CLK_RATE_PROPAGATES,
549}; 543};
550 544
551static struct clk sh7722_sh_clock = { 545static struct clk sh7722_sh_clock = {
552 .name = "sh_clk", 546 .name = "sh_clk",
553 .ops = &sh7722_frqcr_clk_ops, 547 .ops = &sh7722_frqcr_clk_ops,
554 .flags = CLK_RATE_PROPAGATES,
555}; 548};
556 549
557static struct clk sh7722_peripheral_clock = { 550static struct clk sh7722_peripheral_clock = {
558 .name = "peripheral_clk", 551 .name = "peripheral_clk",
559 .ops = &sh7722_frqcr_clk_ops, 552 .ops = &sh7722_frqcr_clk_ops,
560 .flags = CLK_RATE_PROPAGATES,
561}; 553};
562 554
563static struct clk sh7722_sdram_clock = { 555static struct clk sh7722_sdram_clock = {
@@ -568,7 +560,6 @@ static struct clk sh7722_sdram_clock = {
568static struct clk sh7722_r_clock = { 560static struct clk sh7722_r_clock = {
569 .name = "r_clk", 561 .name = "r_clk",
570 .rate = 32768, 562 .rate = 32768,
571 .flags = CLK_RATE_PROPAGATES,
572}; 563};
573 564
574#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\ 565#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\
@@ -627,7 +618,7 @@ static int sh7722_mstpcr_start_stop(struct clk *clk, int enable)
627 break; 618 break;
628 default: 619 default:
629 return -EINVAL; 620 return -EINVAL;
630 } 621 }
631 622
632 r = ctrl_inl(reg); 623 r = ctrl_inl(reg);
633 624
@@ -640,9 +631,9 @@ static int sh7722_mstpcr_start_stop(struct clk *clk, int enable)
640 return 0; 631 return 0;
641} 632}
642 633
643static void sh7722_mstpcr_enable(struct clk *clk) 634static int sh7722_mstpcr_enable(struct clk *clk)
644{ 635{
645 sh7722_mstpcr_start_stop(clk, 1); 636 return sh7722_mstpcr_start_stop(clk, 1);
646} 637}
647 638
648static void sh7722_mstpcr_disable(struct clk *clk) 639static void sh7722_mstpcr_disable(struct clk *clk)
@@ -650,219 +641,214 @@ static void sh7722_mstpcr_disable(struct clk *clk)
650 sh7722_mstpcr_start_stop(clk, 0); 641 sh7722_mstpcr_start_stop(clk, 0);
651} 642}
652 643
653static void sh7722_mstpcr_recalc(struct clk *clk)
654{
655 if (clk->parent)
656 clk->rate = clk->parent->rate;
657}
658
659static struct clk_ops sh7722_mstpcr_clk_ops = { 644static struct clk_ops sh7722_mstpcr_clk_ops = {
660 .enable = sh7722_mstpcr_enable, 645 .enable = sh7722_mstpcr_enable,
661 .disable = sh7722_mstpcr_disable, 646 .disable = sh7722_mstpcr_disable,
662 .recalc = sh7722_mstpcr_recalc, 647 .recalc = followparent_recalc,
663}; 648};
664 649
665#define MSTPCR(_name, _parent, regnr, bitnr) \ 650#define MSTPCR(_name, _parent, regnr, bitnr, _flags) \
666{ \ 651{ \
667 .name = _name, \ 652 .name = _name, \
653 .flags = _flags, \
668 .arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \ 654 .arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \
669 .ops = (void *)_parent, \ 655 .ops = (void *)_parent, \
670} 656}
671 657
672static struct clk sh7722_mstpcr_clocks[] = { 658static struct clk sh7722_mstpcr_clocks[] = {
673#if defined(CONFIG_CPU_SUBTYPE_SH7722) 659#if defined(CONFIG_CPU_SUBTYPE_SH7722)
674 MSTPCR("uram0", "umem_clk", 0, 28), 660 MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT),
675 MSTPCR("xymem0", "bus_clk", 0, 26), 661 MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT),
676 MSTPCR("tmu0", "peripheral_clk", 0, 15), 662 MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
677 MSTPCR("cmt0", "r_clk", 0, 14), 663 MSTPCR("cmt0", "r_clk", 0, 14, 0),
678 MSTPCR("rwdt0", "r_clk", 0, 13), 664 MSTPCR("rwdt0", "r_clk", 0, 13, 0),
679 MSTPCR("flctl0", "peripheral_clk", 0, 10), 665 MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
680 MSTPCR("scif0", "peripheral_clk", 0, 7), 666 MSTPCR("scif0", "peripheral_clk", 0, 7, 0),
681 MSTPCR("scif1", "peripheral_clk", 0, 6), 667 MSTPCR("scif1", "peripheral_clk", 0, 6, 0),
682 MSTPCR("scif2", "peripheral_clk", 0, 5), 668 MSTPCR("scif2", "peripheral_clk", 0, 5, 0),
683 MSTPCR("i2c0", "peripheral_clk", 1, 9), 669 MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
684 MSTPCR("rtc0", "r_clk", 1, 8), 670 MSTPCR("rtc0", "r_clk", 1, 8, 0),
685 MSTPCR("sdhi0", "peripheral_clk", 2, 18), 671 MSTPCR("sdhi0", "peripheral_clk", 2, 18, 0),
686 MSTPCR("keysc0", "r_clk", 2, 14), 672 MSTPCR("keysc0", "r_clk", 2, 14, 0),
687 MSTPCR("usbf0", "peripheral_clk", 2, 11), 673 MSTPCR("usbf0", "peripheral_clk", 2, 11, 0),
688 MSTPCR("2dg0", "bus_clk", 2, 9), 674 MSTPCR("2dg0", "bus_clk", 2, 9, 0),
689 MSTPCR("siu0", "bus_clk", 2, 8), 675 MSTPCR("siu0", "bus_clk", 2, 8, 0),
690 MSTPCR("vou0", "bus_clk", 2, 5), 676 MSTPCR("vou0", "bus_clk", 2, 5, 0),
691 MSTPCR("jpu0", "bus_clk", 2, 6), 677 MSTPCR("jpu0", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT),
692 MSTPCR("beu0", "bus_clk", 2, 4), 678 MSTPCR("beu0", "bus_clk", 2, 4, 0),
693 MSTPCR("ceu0", "bus_clk", 2, 3), 679 MSTPCR("ceu0", "bus_clk", 2, 3, 0),
694 MSTPCR("veu0", "bus_clk", 2, 2), 680 MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
695 MSTPCR("vpu0", "bus_clk", 2, 1), 681 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
696 MSTPCR("lcdc0", "bus_clk", 2, 0), 682 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
697#endif 683#endif
698#if defined(CONFIG_CPU_SUBTYPE_SH7723) 684#if defined(CONFIG_CPU_SUBTYPE_SH7723)
699 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ 685 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
700 MSTPCR("tlb0", "cpu_clk", 0, 31), 686 MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
701 MSTPCR("ic0", "cpu_clk", 0, 30), 687 MSTPCR("ic0", "cpu_clk", 0, 30, 0),
702 MSTPCR("oc0", "cpu_clk", 0, 29), 688 MSTPCR("oc0", "cpu_clk", 0, 29, 0),
703 MSTPCR("l2c0", "sh_clk", 0, 28), 689 MSTPCR("l2c0", "sh_clk", 0, 28, 0),
704 MSTPCR("ilmem0", "cpu_clk", 0, 27), 690 MSTPCR("ilmem0", "cpu_clk", 0, 27, 0),
705 MSTPCR("fpu0", "cpu_clk", 0, 24), 691 MSTPCR("fpu0", "cpu_clk", 0, 24, 0),
706 MSTPCR("intc0", "cpu_clk", 0, 22), 692 MSTPCR("intc0", "cpu_clk", 0, 22, 0),
707 MSTPCR("dmac0", "bus_clk", 0, 21), 693 MSTPCR("dmac0", "bus_clk", 0, 21, 0),
708 MSTPCR("sh0", "sh_clk", 0, 20), 694 MSTPCR("sh0", "sh_clk", 0, 20, 0),
709 MSTPCR("hudi0", "peripheral_clk", 0, 19), 695 MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
710 MSTPCR("ubc0", "cpu_clk", 0, 17), 696 MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
711 MSTPCR("tmu0", "peripheral_clk", 0, 15), 697 MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
712 MSTPCR("cmt0", "r_clk", 0, 14), 698 MSTPCR("cmt0", "r_clk", 0, 14, 0),
713 MSTPCR("rwdt0", "r_clk", 0, 13), 699 MSTPCR("rwdt0", "r_clk", 0, 13, 0),
714 MSTPCR("dmac1", "bus_clk", 0, 12), 700 MSTPCR("dmac1", "bus_clk", 0, 12, 0),
715 MSTPCR("tmu1", "peripheral_clk", 0, 11), 701 MSTPCR("tmu1", "peripheral_clk", 0, 11, 0),
716 MSTPCR("flctl0", "peripheral_clk", 0, 10), 702 MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
717 MSTPCR("scif0", "peripheral_clk", 0, 9), 703 MSTPCR("scif0", "peripheral_clk", 0, 9, 0),
718 MSTPCR("scif1", "peripheral_clk", 0, 8), 704 MSTPCR("scif1", "peripheral_clk", 0, 8, 0),
719 MSTPCR("scif2", "peripheral_clk", 0, 7), 705 MSTPCR("scif2", "peripheral_clk", 0, 7, 0),
720 MSTPCR("scif3", "bus_clk", 0, 6), 706 MSTPCR("scif3", "bus_clk", 0, 6, 0),
721 MSTPCR("scif4", "bus_clk", 0, 5), 707 MSTPCR("scif4", "bus_clk", 0, 5, 0),
722 MSTPCR("scif5", "bus_clk", 0, 4), 708 MSTPCR("scif5", "bus_clk", 0, 4, 0),
723 MSTPCR("msiof0", "bus_clk", 0, 2), 709 MSTPCR("msiof0", "bus_clk", 0, 2, 0),
724 MSTPCR("msiof1", "bus_clk", 0, 1), 710 MSTPCR("msiof1", "bus_clk", 0, 1, 0),
725 MSTPCR("meram0", "sh_clk", 0, 0), 711 MSTPCR("meram0", "sh_clk", 0, 0, CLK_ENABLE_ON_INIT),
726 MSTPCR("i2c0", "peripheral_clk", 1, 9), 712 MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
727 MSTPCR("rtc0", "r_clk", 1, 8), 713 MSTPCR("rtc0", "r_clk", 1, 8, 0),
728 MSTPCR("atapi0", "sh_clk", 2, 28), 714 MSTPCR("atapi0", "sh_clk", 2, 28, 0),
729 MSTPCR("adc0", "peripheral_clk", 2, 28), 715 MSTPCR("adc0", "peripheral_clk", 2, 28, 0),
730 MSTPCR("tpu0", "bus_clk", 2, 25), 716 MSTPCR("tpu0", "bus_clk", 2, 25, 0),
731 MSTPCR("irda0", "peripheral_clk", 2, 24), 717 MSTPCR("irda0", "peripheral_clk", 2, 24, 0),
732 MSTPCR("tsif0", "bus_clk", 2, 22), 718 MSTPCR("tsif0", "bus_clk", 2, 22, 0),
733 MSTPCR("icb0", "bus_clk", 2, 21), 719 MSTPCR("icb0", "bus_clk", 2, 21, 0),
734 MSTPCR("sdhi0", "bus_clk", 2, 18), 720 MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
735 MSTPCR("sdhi1", "bus_clk", 2, 17), 721 MSTPCR("sdhi1", "bus_clk", 2, 17, 0),
736 MSTPCR("keysc0", "r_clk", 2, 14), 722 MSTPCR("keysc0", "r_clk", 2, 14, 0),
737 MSTPCR("usb0", "bus_clk", 2, 11), 723 MSTPCR("usb0", "bus_clk", 2, 11, 0),
738 MSTPCR("2dg0", "bus_clk", 2, 10), 724 MSTPCR("2dg0", "bus_clk", 2, 10, 0),
739 MSTPCR("siu0", "bus_clk", 2, 8), 725 MSTPCR("siu0", "bus_clk", 2, 8, 0),
740 MSTPCR("veu1", "bus_clk", 2, 6), 726 MSTPCR("veu1", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT),
741 MSTPCR("vou0", "bus_clk", 2, 5), 727 MSTPCR("vou0", "bus_clk", 2, 5, 0),
742 MSTPCR("beu0", "bus_clk", 2, 4), 728 MSTPCR("beu0", "bus_clk", 2, 4, 0),
743 MSTPCR("ceu0", "bus_clk", 2, 3), 729 MSTPCR("ceu0", "bus_clk", 2, 3, 0),
744 MSTPCR("veu0", "bus_clk", 2, 2), 730 MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
745 MSTPCR("vpu0", "bus_clk", 2, 1), 731 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
746 MSTPCR("lcdc0", "bus_clk", 2, 0), 732 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
747#endif 733#endif
748#if defined(CONFIG_CPU_SUBTYPE_SH7724) 734#if defined(CONFIG_CPU_SUBTYPE_SH7724)
749 /* See Datasheet : Overview -> Block Diagram */ 735 /* See Datasheet : Overview -> Block Diagram */
750 MSTPCR("tlb0", "cpu_clk", 0, 31), 736 MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
751 MSTPCR("ic0", "cpu_clk", 0, 30), 737 MSTPCR("ic0", "cpu_clk", 0, 30, 0),
752 MSTPCR("oc0", "cpu_clk", 0, 29), 738 MSTPCR("oc0", "cpu_clk", 0, 29, 0),
753 MSTPCR("rs0", "bus_clk", 0, 28), 739 MSTPCR("rs0", "bus_clk", 0, 28, 0),
754 MSTPCR("ilmem0", "cpu_clk", 0, 27), 740 MSTPCR("ilmem0", "cpu_clk", 0, 27, 0),
755 MSTPCR("l2c0", "sh_clk", 0, 26), 741 MSTPCR("l2c0", "sh_clk", 0, 26, 0),
756 MSTPCR("fpu0", "cpu_clk", 0, 24), 742 MSTPCR("fpu0", "cpu_clk", 0, 24, 0),
757 MSTPCR("intc0", "peripheral_clk", 0, 22), 743 MSTPCR("intc0", "peripheral_clk", 0, 22, 0),
758 MSTPCR("dmac0", "bus_clk", 0, 21), 744 MSTPCR("dmac0", "bus_clk", 0, 21, 0),
759 MSTPCR("sh0", "sh_clk", 0, 20), 745 MSTPCR("sh0", "sh_clk", 0, 20, 0),
760 MSTPCR("hudi0", "peripheral_clk", 0, 19), 746 MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
761 MSTPCR("ubc0", "cpu_clk", 0, 17), 747 MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
762 MSTPCR("tmu0", "peripheral_clk", 0, 15), 748 MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
763 MSTPCR("cmt0", "r_clk", 0, 14), 749 MSTPCR("cmt0", "r_clk", 0, 14, 0),
764 MSTPCR("rwdt0", "r_clk", 0, 13), 750 MSTPCR("rwdt0", "r_clk", 0, 13, 0),
765 MSTPCR("dmac1", "bus_clk", 0, 12), 751 MSTPCR("dmac1", "bus_clk", 0, 12, 0),
766 MSTPCR("tmu1", "peripheral_clk", 0, 10), 752 MSTPCR("tmu1", "peripheral_clk", 0, 10, 0),
767 MSTPCR("scif0", "peripheral_clk", 0, 9), 753 MSTPCR("scif0", "peripheral_clk", 0, 9, 0),
768 MSTPCR("scif1", "peripheral_clk", 0, 8), 754 MSTPCR("scif1", "peripheral_clk", 0, 8, 0),
769 MSTPCR("scif2", "peripheral_clk", 0, 7), 755 MSTPCR("scif2", "peripheral_clk", 0, 7, 0),
770 MSTPCR("scif3", "bus_clk", 0, 6), 756 MSTPCR("scif3", "bus_clk", 0, 6, 0),
771 MSTPCR("scif4", "bus_clk", 0, 5), 757 MSTPCR("scif4", "bus_clk", 0, 5, 0),
772 MSTPCR("scif5", "bus_clk", 0, 4), 758 MSTPCR("scif5", "bus_clk", 0, 4, 0),
773 MSTPCR("msiof0", "bus_clk", 0, 2), 759 MSTPCR("msiof0", "bus_clk", 0, 2, 0),
774 MSTPCR("msiof1", "bus_clk", 0, 1), 760 MSTPCR("msiof1", "bus_clk", 0, 1, 0),
775 MSTPCR("keysc0", "r_clk", 1, 12), 761 MSTPCR("keysc0", "r_clk", 1, 12, 0),
776 MSTPCR("rtc0", "r_clk", 1, 11), 762 MSTPCR("rtc0", "r_clk", 1, 11, 0),
777 MSTPCR("i2c0", "peripheral_clk", 1, 9), 763 MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
778 MSTPCR("i2c1", "peripheral_clk", 1, 8), 764 MSTPCR("i2c1", "peripheral_clk", 1, 8, 0),
779 MSTPCR("mmc0", "bus_clk", 2, 29), 765 MSTPCR("mmc0", "bus_clk", 2, 29, 0),
780 MSTPCR("eth0", "bus_clk", 2, 28), 766 MSTPCR("eth0", "bus_clk", 2, 28, 0),
781 MSTPCR("atapi0", "bus_clk", 2, 26), 767 MSTPCR("atapi0", "bus_clk", 2, 26, 0),
782 MSTPCR("tpu0", "bus_clk", 2, 25), 768 MSTPCR("tpu0", "bus_clk", 2, 25, 0),
783 MSTPCR("irda0", "peripheral_clk", 2, 24), 769 MSTPCR("irda0", "peripheral_clk", 2, 24, 0),
784 MSTPCR("tsif0", "bus_clk", 2, 22), 770 MSTPCR("tsif0", "bus_clk", 2, 22, 0),
785 MSTPCR("usb1", "bus_clk", 2, 21), 771 MSTPCR("usb1", "bus_clk", 2, 21, 0),
786 MSTPCR("usb0", "bus_clk", 2, 20), 772 MSTPCR("usb0", "bus_clk", 2, 20, 0),
787 MSTPCR("2dg0", "bus_clk", 2, 19), 773 MSTPCR("2dg0", "bus_clk", 2, 19, 0),
788 MSTPCR("sdhi0", "bus_clk", 2, 18), 774 MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
789 MSTPCR("sdhi1", "bus_clk", 2, 17), 775 MSTPCR("sdhi1", "bus_clk", 2, 17, 0),
790 MSTPCR("veu1", "bus_clk", 2, 15), 776 MSTPCR("veu1", "bus_clk", 2, 15, CLK_ENABLE_ON_INIT),
791 MSTPCR("ceu1", "bus_clk", 2, 13), 777 MSTPCR("ceu1", "bus_clk", 2, 13, 0),
792 MSTPCR("beu1", "bus_clk", 2, 12), 778 MSTPCR("beu1", "bus_clk", 2, 12, 0),
793 MSTPCR("2ddmac0", "sh_clk", 2, 10), 779 MSTPCR("2ddmac0", "sh_clk", 2, 10, 0),
794 MSTPCR("spu0", "bus_clk", 2, 9), 780 MSTPCR("spu0", "bus_clk", 2, 9, 0),
795 MSTPCR("jpu0", "bus_clk", 2, 6), 781 MSTPCR("jpu0", "bus_clk", 2, 6, 0),
796 MSTPCR("vou0", "bus_clk", 2, 5), 782 MSTPCR("vou0", "bus_clk", 2, 5, 0),
797 MSTPCR("beu0", "bus_clk", 2, 4), 783 MSTPCR("beu0", "bus_clk", 2, 4, 0),
798 MSTPCR("ceu0", "bus_clk", 2, 3), 784 MSTPCR("ceu0", "bus_clk", 2, 3, 0),
799 MSTPCR("veu0", "bus_clk", 2, 2), 785 MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
800 MSTPCR("vpu0", "bus_clk", 2, 1), 786 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
801 MSTPCR("lcdc0", "bus_clk", 2, 0), 787 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
802#endif 788#endif
803#if defined(CONFIG_CPU_SUBTYPE_SH7343) 789#if defined(CONFIG_CPU_SUBTYPE_SH7343)
804 MSTPCR("uram0", "umem_clk", 0, 28), 790 MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT),
805 MSTPCR("xymem0", "bus_clk", 0, 26), 791 MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT),
806 MSTPCR("tmu0", "peripheral_clk", 0, 15), 792 MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
807 MSTPCR("cmt0", "r_clk", 0, 14), 793 MSTPCR("cmt0", "r_clk", 0, 14, 0),
808 MSTPCR("rwdt0", "r_clk", 0, 13), 794 MSTPCR("rwdt0", "r_clk", 0, 13, 0),
809 MSTPCR("scif0", "peripheral_clk", 0, 7), 795 MSTPCR("scif0", "peripheral_clk", 0, 7, 0),
810 MSTPCR("scif1", "peripheral_clk", 0, 6), 796 MSTPCR("scif1", "peripheral_clk", 0, 6, 0),
811 MSTPCR("scif2", "peripheral_clk", 0, 5), 797 MSTPCR("scif2", "peripheral_clk", 0, 5, 0),
812 MSTPCR("scif3", "peripheral_clk", 0, 4), 798 MSTPCR("scif3", "peripheral_clk", 0, 4, 0),
813 MSTPCR("i2c0", "peripheral_clk", 1, 9), 799 MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
814 MSTPCR("i2c1", "peripheral_clk", 1, 8), 800 MSTPCR("i2c1", "peripheral_clk", 1, 8, 0),
815 MSTPCR("sdhi0", "peripheral_clk", 2, 18), 801 MSTPCR("sdhi0", "peripheral_clk", 2, 18, 0),
816 MSTPCR("keysc0", "r_clk", 2, 14), 802 MSTPCR("keysc0", "r_clk", 2, 14, 0),
817 MSTPCR("usbf0", "peripheral_clk", 2, 11), 803 MSTPCR("usbf0", "peripheral_clk", 2, 11, 0),
818 MSTPCR("siu0", "bus_clk", 2, 8), 804 MSTPCR("siu0", "bus_clk", 2, 8, 0),
819 MSTPCR("jpu0", "bus_clk", 2, 6), 805 MSTPCR("jpu0", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT),
820 MSTPCR("vou0", "bus_clk", 2, 5), 806 MSTPCR("vou0", "bus_clk", 2, 5, 0),
821 MSTPCR("beu0", "bus_clk", 2, 4), 807 MSTPCR("beu0", "bus_clk", 2, 4, 0),
822 MSTPCR("ceu0", "bus_clk", 2, 3), 808 MSTPCR("ceu0", "bus_clk", 2, 3, 0),
823 MSTPCR("veu0", "bus_clk", 2, 2), 809 MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
824 MSTPCR("vpu0", "bus_clk", 2, 1), 810 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
825 MSTPCR("lcdc0", "bus_clk", 2, 0), 811 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
826#endif 812#endif
827#if defined(CONFIG_CPU_SUBTYPE_SH7366) 813#if defined(CONFIG_CPU_SUBTYPE_SH7366)
828 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ 814 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
829 MSTPCR("tlb0", "cpu_clk", 0, 31), 815 MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
830 MSTPCR("ic0", "cpu_clk", 0, 30), 816 MSTPCR("ic0", "cpu_clk", 0, 30, 0),
831 MSTPCR("oc0", "cpu_clk", 0, 29), 817 MSTPCR("oc0", "cpu_clk", 0, 29, 0),
832 MSTPCR("rsmem0", "sh_clk", 0, 28), 818 MSTPCR("rsmem0", "sh_clk", 0, 28, CLK_ENABLE_ON_INIT),
833 MSTPCR("xymem0", "cpu_clk", 0, 26), 819 MSTPCR("xymem0", "cpu_clk", 0, 26, CLK_ENABLE_ON_INIT),
834 MSTPCR("intc30", "peripheral_clk", 0, 23), 820 MSTPCR("intc30", "peripheral_clk", 0, 23, 0),
835 MSTPCR("intc0", "peripheral_clk", 0, 22), 821 MSTPCR("intc0", "peripheral_clk", 0, 22, 0),
836 MSTPCR("dmac0", "bus_clk", 0, 21), 822 MSTPCR("dmac0", "bus_clk", 0, 21, 0),
837 MSTPCR("sh0", "sh_clk", 0, 20), 823 MSTPCR("sh0", "sh_clk", 0, 20, 0),
838 MSTPCR("hudi0", "peripheral_clk", 0, 19), 824 MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
839 MSTPCR("ubc0", "cpu_clk", 0, 17), 825 MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
840 MSTPCR("tmu0", "peripheral_clk", 0, 15), 826 MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
841 MSTPCR("cmt0", "r_clk", 0, 14), 827 MSTPCR("cmt0", "r_clk", 0, 14, 0),
842 MSTPCR("rwdt0", "r_clk", 0, 13), 828 MSTPCR("rwdt0", "r_clk", 0, 13, 0),
843 MSTPCR("flctl0", "peripheral_clk", 0, 10), 829 MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
844 MSTPCR("scif0", "peripheral_clk", 0, 7), 830 MSTPCR("scif0", "peripheral_clk", 0, 7, 0),
845 MSTPCR("scif1", "bus_clk", 0, 6), 831 MSTPCR("scif1", "bus_clk", 0, 6, 0),
846 MSTPCR("scif2", "bus_clk", 0, 5), 832 MSTPCR("scif2", "bus_clk", 0, 5, 0),
847 MSTPCR("msiof0", "peripheral_clk", 0, 2), 833 MSTPCR("msiof0", "peripheral_clk", 0, 2, 0),
848 MSTPCR("sbr0", "peripheral_clk", 0, 1), 834 MSTPCR("sbr0", "peripheral_clk", 0, 1, 0),
849 MSTPCR("i2c0", "peripheral_clk", 1, 9), 835 MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
850 MSTPCR("icb0", "bus_clk", 2, 27), 836 MSTPCR("icb0", "bus_clk", 2, 27, 0),
851 MSTPCR("meram0", "sh_clk", 2, 26), 837 MSTPCR("meram0", "sh_clk", 2, 26, 0),
852 MSTPCR("dacc0", "peripheral_clk", 2, 24), 838 MSTPCR("dacc0", "peripheral_clk", 2, 24, 0),
853 MSTPCR("dacy0", "peripheral_clk", 2, 23), 839 MSTPCR("dacy0", "peripheral_clk", 2, 23, 0),
854 MSTPCR("tsif0", "bus_clk", 2, 22), 840 MSTPCR("tsif0", "bus_clk", 2, 22, 0),
855 MSTPCR("sdhi0", "bus_clk", 2, 18), 841 MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
856 MSTPCR("mmcif0", "bus_clk", 2, 17), 842 MSTPCR("mmcif0", "bus_clk", 2, 17, 0),
857 MSTPCR("usb0", "bus_clk", 2, 11), 843 MSTPCR("usb0", "bus_clk", 2, 11, 0),
858 MSTPCR("siu0", "bus_clk", 2, 8), 844 MSTPCR("siu0", "bus_clk", 2, 8, 0),
859 MSTPCR("veu1", "bus_clk", 2, 7), 845 MSTPCR("veu1", "bus_clk", 2, 7, CLK_ENABLE_ON_INIT),
860 MSTPCR("vou0", "bus_clk", 2, 5), 846 MSTPCR("vou0", "bus_clk", 2, 5, 0),
861 MSTPCR("beu0", "bus_clk", 2, 4), 847 MSTPCR("beu0", "bus_clk", 2, 4, 0),
862 MSTPCR("ceu0", "bus_clk", 2, 3), 848 MSTPCR("ceu0", "bus_clk", 2, 3, 0),
863 MSTPCR("veu0", "bus_clk", 2, 2), 849 MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
864 MSTPCR("vpu0", "bus_clk", 2, 1), 850 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
865 MSTPCR("lcdc0", "bus_clk", 2, 0), 851 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
866#endif 852#endif
867}; 853};
868 854
@@ -897,7 +883,7 @@ struct clk_ops *onchip_ops[] = {
897void __init 883void __init
898arch_init_clk_ops(struct clk_ops **ops, int type) 884arch_init_clk_ops(struct clk_ops **ops, int type)
899{ 885{
900 BUG_ON(type < 0 || type > ARRAY_SIZE(onchip_ops)); 886 BUG_ON(type < 0 || type >= ARRAY_SIZE(onchip_ops));
901 *ops = onchip_ops[type]; 887 *ops = onchip_ops[type];
902} 888}
903 889
@@ -906,6 +892,8 @@ int __init arch_clk_init(void)
906 struct clk *clk; 892 struct clk *clk;
907 int i; 893 int i;
908 894
895 cpg_clk_init();
896
909 clk = clk_get(NULL, "master_clk"); 897 clk = clk_get(NULL, "master_clk");
910 for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) { 898 for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) {
911 pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name); 899 pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name);
@@ -926,7 +914,7 @@ int __init arch_clk_init(void)
926 clk_put(clk); 914 clk_put(clk);
927 } 915 }
928 916
929 clk_recalc_rate(&sh7722_r_clock); /* make sure rate gets propagated */ 917 propagate_rate(&sh7722_r_clock); /* make sure rate gets propagated */
930 918
931 return 0; 919 return 0;
932} 920}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 3177d0d1e06d..370cd47642ef 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -29,33 +29,28 @@ static struct clk_ops sh7763_master_clk_ops = {
29 .init = master_clk_init, 29 .init = master_clk_init,
30}; 30};
31 31
32static void module_clk_recalc(struct clk *clk) 32static unsigned long module_clk_recalc(struct clk *clk)
33{ 33{
34 int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07); 34 int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07);
35 clk->rate = clk->parent->rate / p0fc_divisors[idx]; 35 return clk->parent->rate / p0fc_divisors[idx];
36} 36}
37 37
38static struct clk_ops sh7763_module_clk_ops = { 38static struct clk_ops sh7763_module_clk_ops = {
39 .recalc = module_clk_recalc, 39 .recalc = module_clk_recalc,
40}; 40};
41 41
42static void bus_clk_recalc(struct clk *clk) 42static unsigned long bus_clk_recalc(struct clk *clk)
43{ 43{
44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07); 44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07);
45 clk->rate = clk->parent->rate / bfc_divisors[idx]; 45 return clk->parent->rate / bfc_divisors[idx];
46} 46}
47 47
48static struct clk_ops sh7763_bus_clk_ops = { 48static struct clk_ops sh7763_bus_clk_ops = {
49 .recalc = bus_clk_recalc, 49 .recalc = bus_clk_recalc,
50}; 50};
51 51
52static void cpu_clk_recalc(struct clk *clk)
53{
54 clk->rate = clk->parent->rate;
55}
56
57static struct clk_ops sh7763_cpu_clk_ops = { 52static struct clk_ops sh7763_cpu_clk_ops = {
58 .recalc = cpu_clk_recalc, 53 .recalc = followparent_recalc,
59}; 54};
60 55
61static struct clk_ops *sh7763_clk_ops[] = { 56static struct clk_ops *sh7763_clk_ops[] = {
@@ -71,10 +66,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
71 *ops = sh7763_clk_ops[idx]; 66 *ops = sh7763_clk_ops[idx];
72} 67}
73 68
74static void shyway_clk_recalc(struct clk *clk) 69static unsigned long shyway_clk_recalc(struct clk *clk)
75{ 70{
76 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07); 71 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07);
77 clk->rate = clk->parent->rate / cfc_divisors[idx]; 72 return clk->parent->rate / cfc_divisors[idx];
78} 73}
79 74
80static struct clk_ops sh7763_shyway_clk_ops = { 75static struct clk_ops sh7763_shyway_clk_ops = {
@@ -83,7 +78,7 @@ static struct clk_ops sh7763_shyway_clk_ops = {
83 78
84static struct clk sh7763_shyway_clk = { 79static struct clk sh7763_shyway_clk = {
85 .name = "shyway_clk", 80 .name = "shyway_clk",
86 .flags = CLK_ALWAYS_ENABLED, 81 .flags = CLK_ENABLE_ON_INIT,
87 .ops = &sh7763_shyway_clk_ops, 82 .ops = &sh7763_shyway_clk_ops,
88}; 83};
89 84
@@ -95,31 +90,22 @@ static struct clk *sh7763_onchip_clocks[] = {
95 &sh7763_shyway_clk, 90 &sh7763_shyway_clk,
96}; 91};
97 92
98static int __init sh7763_clk_init(void) 93int __init arch_clk_init(void)
99{ 94{
100 struct clk *clk = clk_get(NULL, "master_clk"); 95 struct clk *clk;
101 int i; 96 int i, ret = 0;
97
98 cpg_clk_init();
102 99
100 clk = clk_get(NULL, "master_clk");
103 for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) { 101 for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) {
104 struct clk *clkp = sh7763_onchip_clocks[i]; 102 struct clk *clkp = sh7763_onchip_clocks[i];
105 103
106 clkp->parent = clk; 104 clkp->parent = clk;
107 clk_register(clkp); 105 ret |= clk_register(clkp);
108 clk_enable(clkp);
109 } 106 }
110 107
111 /*
112 * Now that we have the rest of the clocks registered, we need to
113 * force the parent clock to propagate so that these clocks will
114 * automatically figure out their rate. We cheat by handing the
115 * parent clock its current rate and forcing child propagation.
116 */
117 clk_set_rate(clk, clk_get_rate(clk));
118
119 clk_put(clk); 108 clk_put(clk);
120 109
121 return 0; 110 return ret;
122} 111}
123
124arch_initcall(sh7763_clk_init);
125
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
index 8e236062c721..e0b896769205 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
@@ -28,30 +28,30 @@ static struct clk_ops sh7770_master_clk_ops = {
28 .init = master_clk_init, 28 .init = master_clk_init,
29}; 29};
30 30
31static void module_clk_recalc(struct clk *clk) 31static unsigned long module_clk_recalc(struct clk *clk)
32{ 32{
33 int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f); 33 int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f);
34 clk->rate = clk->parent->rate / pfc_divisors[idx]; 34 return clk->parent->rate / pfc_divisors[idx];
35} 35}
36 36
37static struct clk_ops sh7770_module_clk_ops = { 37static struct clk_ops sh7770_module_clk_ops = {
38 .recalc = module_clk_recalc, 38 .recalc = module_clk_recalc,
39}; 39};
40 40
41static void bus_clk_recalc(struct clk *clk) 41static unsigned long bus_clk_recalc(struct clk *clk)
42{ 42{
43 int idx = (ctrl_inl(FRQCR) & 0x000f); 43 int idx = (ctrl_inl(FRQCR) & 0x000f);
44 clk->rate = clk->parent->rate / bfc_divisors[idx]; 44 return clk->parent->rate / bfc_divisors[idx];
45} 45}
46 46
47static struct clk_ops sh7770_bus_clk_ops = { 47static struct clk_ops sh7770_bus_clk_ops = {
48 .recalc = bus_clk_recalc, 48 .recalc = bus_clk_recalc,
49}; 49};
50 50
51static void cpu_clk_recalc(struct clk *clk) 51static unsigned long cpu_clk_recalc(struct clk *clk)
52{ 52{
53 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f); 53 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f);
54 clk->rate = clk->parent->rate / ifc_divisors[idx]; 54 return clk->parent->rate / ifc_divisors[idx];
55} 55}
56 56
57static struct clk_ops sh7770_cpu_clk_ops = { 57static struct clk_ops sh7770_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index 01f3da619d3d..a249d823578e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -29,30 +29,30 @@ static struct clk_ops sh7780_master_clk_ops = {
29 .init = master_clk_init, 29 .init = master_clk_init,
30}; 30};
31 31
32static void module_clk_recalc(struct clk *clk) 32static unsigned long module_clk_recalc(struct clk *clk)
33{ 33{
34 int idx = (ctrl_inl(FRQCR) & 0x0003); 34 int idx = (ctrl_inl(FRQCR) & 0x0003);
35 clk->rate = clk->parent->rate / pfc_divisors[idx]; 35 return clk->parent->rate / pfc_divisors[idx];
36} 36}
37 37
38static struct clk_ops sh7780_module_clk_ops = { 38static struct clk_ops sh7780_module_clk_ops = {
39 .recalc = module_clk_recalc, 39 .recalc = module_clk_recalc,
40}; 40};
41 41
42static void bus_clk_recalc(struct clk *clk) 42static unsigned long bus_clk_recalc(struct clk *clk)
43{ 43{
44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007); 44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007);
45 clk->rate = clk->parent->rate / bfc_divisors[idx]; 45 return clk->parent->rate / bfc_divisors[idx];
46} 46}
47 47
48static struct clk_ops sh7780_bus_clk_ops = { 48static struct clk_ops sh7780_bus_clk_ops = {
49 .recalc = bus_clk_recalc, 49 .recalc = bus_clk_recalc,
50}; 50};
51 51
52static void cpu_clk_recalc(struct clk *clk) 52static unsigned long cpu_clk_recalc(struct clk *clk)
53{ 53{
54 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001); 54 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001);
55 clk->rate = clk->parent->rate / ifc_divisors[idx]; 55 return clk->parent->rate / ifc_divisors[idx];
56} 56}
57 57
58static struct clk_ops sh7780_cpu_clk_ops = { 58static struct clk_ops sh7780_cpu_clk_ops = {
@@ -72,10 +72,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
72 *ops = sh7780_clk_ops[idx]; 72 *ops = sh7780_clk_ops[idx];
73} 73}
74 74
75static void shyway_clk_recalc(struct clk *clk) 75static unsigned long shyway_clk_recalc(struct clk *clk)
76{ 76{
77 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007); 77 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007);
78 clk->rate = clk->parent->rate / cfc_divisors[idx]; 78 return clk->parent->rate / cfc_divisors[idx];
79} 79}
80 80
81static struct clk_ops sh7780_shyway_clk_ops = { 81static struct clk_ops sh7780_shyway_clk_ops = {
@@ -84,7 +84,7 @@ static struct clk_ops sh7780_shyway_clk_ops = {
84 84
85static struct clk sh7780_shyway_clk = { 85static struct clk sh7780_shyway_clk = {
86 .name = "shyway_clk", 86 .name = "shyway_clk",
87 .flags = CLK_ALWAYS_ENABLED, 87 .flags = CLK_ENABLE_ON_INIT,
88 .ops = &sh7780_shyway_clk_ops, 88 .ops = &sh7780_shyway_clk_ops,
89}; 89};
90 90
@@ -96,31 +96,22 @@ static struct clk *sh7780_onchip_clocks[] = {
96 &sh7780_shyway_clk, 96 &sh7780_shyway_clk,
97}; 97};
98 98
99static int __init sh7780_clk_init(void) 99int __init arch_clk_init(void)
100{ 100{
101 struct clk *clk = clk_get(NULL, "master_clk"); 101 struct clk *clk;
102 int i; 102 int i, ret = 0;
103 103
104 cpg_clk_init();
105
106 clk = clk_get(NULL, "master_clk");
104 for (i = 0; i < ARRAY_SIZE(sh7780_onchip_clocks); i++) { 107 for (i = 0; i < ARRAY_SIZE(sh7780_onchip_clocks); i++) {
105 struct clk *clkp = sh7780_onchip_clocks[i]; 108 struct clk *clkp = sh7780_onchip_clocks[i];
106 109
107 clkp->parent = clk; 110 clkp->parent = clk;
108 clk_register(clkp); 111 ret |= clk_register(clkp);
109 clk_enable(clkp);
110 } 112 }
111 113
112 /*
113 * Now that we have the rest of the clocks registered, we need to
114 * force the parent clock to propagate so that these clocks will
115 * automatically figure out their rate. We cheat by handing the
116 * parent clock its current rate and forcing child propagation.
117 */
118 clk_set_rate(clk, clk_get_rate(clk));
119
120 clk_put(clk); 114 clk_put(clk);
121 115
122 return 0; 116 return ret;
123} 117}
124
125arch_initcall(sh7780_clk_init);
126
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 27fa81bef6a0..a4a9bcbec664 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * SH7785 support for the clock framework 4 * SH7785 support for the clock framework
5 * 5 *
6 * Copyright (C) 2007 Paul Mundt 6 * Copyright (C) 2007 - 2009 Paul Mundt
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -11,152 +11,257 @@
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/cpufreq.h>
14#include <asm/clock.h> 17#include <asm/clock.h>
15#include <asm/freq.h> 18#include <asm/freq.h>
16#include <asm/io.h>
17
18static int ifc_divisors[] = { 1, 2, 4, 6 };
19static int ufc_divisors[] = { 1, 1, 4, 6 };
20static int sfc_divisors[] = { 1, 1, 4, 6 };
21static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18,
22 24, 32, 36, 48, 1, 1, 1, 1 };
23static int mfc_divisors[] = { 1, 1, 4, 6 };
24static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18,
25 24, 32, 36, 48, 1, 1, 1, 1 };
26
27static void master_clk_init(struct clk *clk)
28{
29 clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
30}
31 19
32static struct clk_ops sh7785_master_clk_ops = { 20static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
33 .init = master_clk_init, 21 24, 32, 36, 48 };
22
23static struct clk_div_mult_table cpg_div = {
24 .divisors = div2,
25 .nr_divisors = ARRAY_SIZE(div2),
34}; 26};
35 27
36static void module_clk_recalc(struct clk *clk) 28struct clk_priv {
37{ 29 unsigned int shift;
38 int idx = (ctrl_inl(FRQMR1) & 0x000f); 30
39 clk->rate = clk->parent->rate / pfc_divisors[idx]; 31 /* allowable divisor bitmap */
40} 32 unsigned long div_bitmap;
41 33
42static struct clk_ops sh7785_module_clk_ops = { 34 /* Supportable frequencies + termination entry */
43 .recalc = module_clk_recalc, 35 struct cpufreq_frequency_table freq_table[ARRAY_SIZE(div2)+1];
44}; 36};
45 37
46static void bus_clk_recalc(struct clk *clk) 38#define FRQMR_CLK_DATA(_name, _shift, _div_bitmap) \
47{ 39static struct clk_priv _name##_data = { \
48 int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f); 40 .shift = _shift, \
49 clk->rate = clk->parent->rate / bfc_divisors[idx]; 41 .div_bitmap = _div_bitmap, \
42 \
43 .freq_table[0] = { \
44 .index = 0, \
45 .frequency = CPUFREQ_TABLE_END, \
46 }, \
50} 47}
51 48
52static struct clk_ops sh7785_bus_clk_ops = { 49FRQMR_CLK_DATA(pfc, 0, 0x0f80);
53 .recalc = bus_clk_recalc, 50FRQMR_CLK_DATA(s3fc, 4, 0x0ff0);
54}; 51FRQMR_CLK_DATA(s2fc, 8, 0x0030);
52FRQMR_CLK_DATA(mfc, 12, 0x000c);
53FRQMR_CLK_DATA(bfc, 16, 0x0fe0);
54FRQMR_CLK_DATA(sfc, 20, 0x000c);
55FRQMR_CLK_DATA(ufc, 24, 0x000c);
56FRQMR_CLK_DATA(ifc, 28, 0x000e);
55 57
56static void cpu_clk_recalc(struct clk *clk) 58static unsigned long frqmr_recalc(struct clk *clk)
57{ 59{
58 int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003); 60 struct clk_priv *data = clk->priv;
59 clk->rate = clk->parent->rate / ifc_divisors[idx]; 61 unsigned int idx = (__raw_readl(FRQMR1) >> data->shift) & 0x000f;
62
63 clk_rate_table_build(clk, data->freq_table, ARRAY_SIZE(div2),
64 &cpg_div, &data->div_bitmap);
65
66 return data->freq_table[idx].frequency;
60} 67}
61 68
62static struct clk_ops sh7785_cpu_clk_ops = { 69static long frqmr_round_rate(struct clk *clk, unsigned long rate)
63 .recalc = cpu_clk_recalc, 70{
64}; 71 struct clk_priv *data = clk->priv;
72
73 return clk_rate_table_round(clk, data->freq_table, rate);
74}
65 75
66static struct clk_ops *sh7785_clk_ops[] = { 76static struct clk_ops frqmr_clk_ops = {
67 &sh7785_master_clk_ops, 77 .recalc = frqmr_recalc,
68 &sh7785_module_clk_ops, 78 .round_rate = frqmr_round_rate,
69 &sh7785_bus_clk_ops,
70 &sh7785_cpu_clk_ops,
71}; 79};
72 80
73void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 81static unsigned long pll_recalc(struct clk *clk)
74{ 82{
75 if (idx < ARRAY_SIZE(sh7785_clk_ops)) 83 /*
76 *ops = sh7785_clk_ops[idx]; 84 * XXX: PLL1 multiplier is locked for the default clock mode,
85 * when mode pin detection and configuration support is added,
86 * select the multiplier dynamically.
87 */
88 return clk->parent->rate * 36;
77} 89}
78 90
79static void shyway_clk_recalc(struct clk *clk) 91static struct clk_ops pll_clk_ops = {
80{ 92 .recalc = pll_recalc,
81 int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003); 93};
82 clk->rate = clk->parent->rate / sfc_divisors[idx];
83}
84 94
85static struct clk_ops sh7785_shyway_clk_ops = { 95/*
86 .recalc = shyway_clk_recalc, 96 * Default rate for the root input clock, reset this with clk_set_rate()
97 * from the platform code.
98 */
99static struct clk extal_clk = {
100 .name = "extal",
101 .id = -1,
102 .rate = 33333333,
87}; 103};
88 104
89static struct clk sh7785_shyway_clk = { 105static struct clk pll_clk = {
90 .name = "shyway_clk", 106 .name = "pll_clk",
91 .flags = CLK_ALWAYS_ENABLED, 107 .id = -1,
92 .ops = &sh7785_shyway_clk_ops, 108 .ops = &pll_clk_ops,
109 .parent = &extal_clk,
110 .flags = CLK_ENABLE_ON_INIT,
93}; 111};
94 112
95static void ddr_clk_recalc(struct clk *clk) 113static struct clk cpu_clk = {
96{ 114 .name = "cpu_clk", /* Ick */
97 int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003); 115 .id = -1,
98 clk->rate = clk->parent->rate / mfc_divisors[idx]; 116 .ops = &frqmr_clk_ops,
99} 117 .parent = &pll_clk,
118 .flags = CLK_ENABLE_ON_INIT,
119 .priv = &ifc_data,
120};
100 121
101static struct clk_ops sh7785_ddr_clk_ops = { 122static struct clk shyway_clk = {
102 .recalc = ddr_clk_recalc, 123 .name = "shyway_clk", /* SHck */
124 .id = -1,
125 .ops = &frqmr_clk_ops,
126 .parent = &pll_clk,
127 .flags = CLK_ENABLE_ON_INIT,
128 .priv = &sfc_data,
103}; 129};
104 130
105static struct clk sh7785_ddr_clk = { 131static struct clk peripheral_clk = {
106 .name = "ddr_clk", 132 .name = "peripheral_clk", /* Pck */
107 .flags = CLK_ALWAYS_ENABLED, 133 .id = -1,
108 .ops = &sh7785_ddr_clk_ops, 134 .ops = &frqmr_clk_ops,
135 .parent = &pll_clk,
136 .flags = CLK_ENABLE_ON_INIT,
137 .priv = &pfc_data,
109}; 138};
110 139
111static void ram_clk_recalc(struct clk *clk) 140static struct clk ddr_clk = {
112{ 141 .name = "ddr_clk", /* DDRck */
113 int idx = ((ctrl_inl(FRQMR1) >> 24) & 0x0003); 142 .id = -1,
114 clk->rate = clk->parent->rate / ufc_divisors[idx]; 143 .ops = &frqmr_clk_ops,
115} 144 .parent = &pll_clk,
145 .flags = CLK_ENABLE_ON_INIT,
146 .priv = &mfc_data,
147};
116 148
117static struct clk_ops sh7785_ram_clk_ops = { 149static struct clk bus_clk = {
118 .recalc = ram_clk_recalc, 150 .name = "bus_clk", /* Bck */
151 .id = -1,
152 .ops = &frqmr_clk_ops,
153 .parent = &pll_clk,
154 .flags = CLK_ENABLE_ON_INIT,
155 .priv = &bfc_data,
119}; 156};
120 157
121static struct clk sh7785_ram_clk = { 158static struct clk ga_clk = {
122 .name = "ram_clk", 159 .name = "ga_clk", /* GAck */
123 .flags = CLK_ALWAYS_ENABLED, 160 .id = -1,
124 .ops = &sh7785_ram_clk_ops, 161 .ops = &frqmr_clk_ops,
162 .parent = &pll_clk,
163 .priv = &s2fc_data,
125}; 164};
126 165
127/* 166static struct clk du_clk = {
128 * Additional SH7785-specific on-chip clocks that aren't already part of the 167 .name = "du_clk", /* DUck */
129 * clock framework 168 .id = -1,
130 */ 169 .ops = &frqmr_clk_ops,
131static struct clk *sh7785_onchip_clocks[] = { 170 .parent = &pll_clk,
132 &sh7785_shyway_clk, 171 .priv = &s3fc_data,
133 &sh7785_ddr_clk, 172};
134 &sh7785_ram_clk, 173
174static struct clk umem_clk = {
175 .name = "umem_clk", /* uck */
176 .id = -1,
177 .ops = &frqmr_clk_ops,
178 .parent = &pll_clk,
179 .flags = CLK_ENABLE_ON_INIT,
180 .priv = &ufc_data,
135}; 181};
136 182
137static int __init sh7785_clk_init(void) 183static struct clk *clks[] = {
184 &extal_clk,
185 &pll_clk,
186 &cpu_clk,
187 &shyway_clk,
188 &peripheral_clk,
189 &ddr_clk,
190 &bus_clk,
191 &ga_clk,
192 &du_clk,
193 &umem_clk,
194};
195
196static int mstpcr_clk_enable(struct clk *clk)
138{ 197{
139 struct clk *clk = clk_get(NULL, "master_clk"); 198 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
140 int i; 199 clk->enable_reg);
200 return 0;
201}
141 202
142 for (i = 0; i < ARRAY_SIZE(sh7785_onchip_clocks); i++) { 203static void mstpcr_clk_disable(struct clk *clk)
143 struct clk *clkp = sh7785_onchip_clocks[i]; 204{
205 __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
206 clk->enable_reg);
207}
144 208
145 clkp->parent = clk; 209static struct clk_ops mstpcr_clk_ops = {
146 clk_register(clkp); 210 .enable = mstpcr_clk_enable,
147 clk_enable(clkp); 211 .disable = mstpcr_clk_disable,
148 } 212 .recalc = followparent_recalc,
213};
149 214
150 /* 215#define MSTPCR0 0xffc80030
151 * Now that we have the rest of the clocks registered, we need to 216#define MSTPCR1 0xffc80034
152 * force the parent clock to propagate so that these clocks will
153 * automatically figure out their rate. We cheat by handing the
154 * parent clock its current rate and forcing child propagation.
155 */
156 clk_set_rate(clk, clk_get_rate(clk));
157 217
158 clk_put(clk); 218#define CLK(_name, _id, _parent, _enable_reg, \
219 _enable_bit, _flags) \
220{ \
221 .name = _name, \
222 .id = _id, \
223 .parent = _parent, \
224 .enable_reg = (void __iomem *)_enable_reg, \
225 .enable_bit = _enable_bit, \
226 .flags = _flags, \
227 .ops = &mstpcr_clk_ops, \
228}
159 229
160 return 0; 230static struct clk mstpcr_clks[] = {
231 /* MSTPCR0 */
232 CLK("scif_fck", 5, &peripheral_clk, MSTPCR0, 29, 0),
233 CLK("scif_fck", 4, &peripheral_clk, MSTPCR0, 28, 0),
234 CLK("scif_fck", 3, &peripheral_clk, MSTPCR0, 27, 0),
235 CLK("scif_fck", 2, &peripheral_clk, MSTPCR0, 26, 0),
236 CLK("scif_fck", 1, &peripheral_clk, MSTPCR0, 25, 0),
237 CLK("scif_fck", 0, &peripheral_clk, MSTPCR0, 24, 0),
238 CLK("ssi_fck", 1, &peripheral_clk, MSTPCR0, 21, 0),
239 CLK("ssi_fck", 0, &peripheral_clk, MSTPCR0, 20, 0),
240 CLK("hac_fck", 1, &peripheral_clk, MSTPCR0, 17, 0),
241 CLK("hac_fck", 0, &peripheral_clk, MSTPCR0, 16, 0),
242 CLK("mmcif_fck", -1, &peripheral_clk, MSTPCR0, 13, 0),
243 CLK("flctl_fck", -1, &peripheral_clk, MSTPCR0, 12, 0),
244 CLK("tmu345_fck", -1, &peripheral_clk, MSTPCR0, 9, 0),
245 CLK("tmu012_fck", -1, &peripheral_clk, MSTPCR0, 8, 0),
246 CLK("siof_fck", -1, &peripheral_clk, MSTPCR0, 3, 0),
247 CLK("hspi_fck", -1, &peripheral_clk, MSTPCR0, 2, 0),
248
249 /* MSTPCR1 */
250 CLK("hudi_fck", -1, NULL, MSTPCR1, 19, 0),
251 CLK("ubc_fck", -1, NULL, MSTPCR1, 17, 0),
252 CLK("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
253 CLK("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
254 CLK("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
255};
256
257int __init arch_clk_init(void)
258{
259 int i, ret = 0;
260
261 for (i = 0; i < ARRAY_SIZE(clks); i++)
262 ret |= clk_register(clks[i]);
263 for (i = 0; i < ARRAY_SIZE(mstpcr_clks); i++)
264 ret |= clk_register(&mstpcr_clks[i]);
265
266 return ret;
161} 267}
162arch_initcall(sh7785_clk_init);
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index f84a9c134471..a0e8869071ac 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -36,30 +36,30 @@ static struct clk_ops sh7786_master_clk_ops = {
36 .init = master_clk_init, 36 .init = master_clk_init,
37}; 37};
38 38
39static void module_clk_recalc(struct clk *clk) 39static unsigned long module_clk_recalc(struct clk *clk)
40{ 40{
41 int idx = (ctrl_inl(FRQMR1) & 0x000f); 41 int idx = (ctrl_inl(FRQMR1) & 0x000f);
42 clk->rate = clk->parent->rate / pfc_divisors[idx]; 42 return clk->parent->rate / pfc_divisors[idx];
43} 43}
44 44
45static struct clk_ops sh7786_module_clk_ops = { 45static struct clk_ops sh7786_module_clk_ops = {
46 .recalc = module_clk_recalc, 46 .recalc = module_clk_recalc,
47}; 47};
48 48
49static void bus_clk_recalc(struct clk *clk) 49static unsigned long bus_clk_recalc(struct clk *clk)
50{ 50{
51 int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f); 51 int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
52 clk->rate = clk->parent->rate / bfc_divisors[idx]; 52 return clk->parent->rate / bfc_divisors[idx];
53} 53}
54 54
55static struct clk_ops sh7786_bus_clk_ops = { 55static struct clk_ops sh7786_bus_clk_ops = {
56 .recalc = bus_clk_recalc, 56 .recalc = bus_clk_recalc,
57}; 57};
58 58
59static void cpu_clk_recalc(struct clk *clk) 59static unsigned long cpu_clk_recalc(struct clk *clk)
60{ 60{
61 int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003); 61 int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
62 clk->rate = clk->parent->rate / ifc_divisors[idx]; 62 return clk->parent->rate / ifc_divisors[idx];
63} 63}
64 64
65static struct clk_ops sh7786_cpu_clk_ops = { 65static struct clk_ops sh7786_cpu_clk_ops = {
@@ -79,10 +79,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
79 *ops = sh7786_clk_ops[idx]; 79 *ops = sh7786_clk_ops[idx];
80} 80}
81 81
82static void shyway_clk_recalc(struct clk *clk) 82static unsigned long shyway_clk_recalc(struct clk *clk)
83{ 83{
84 int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003); 84 int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
85 clk->rate = clk->parent->rate / sfc_divisors[idx]; 85 return clk->parent->rate / sfc_divisors[idx];
86} 86}
87 87
88static struct clk_ops sh7786_shyway_clk_ops = { 88static struct clk_ops sh7786_shyway_clk_ops = {
@@ -91,14 +91,14 @@ static struct clk_ops sh7786_shyway_clk_ops = {
91 91
92static struct clk sh7786_shyway_clk = { 92static struct clk sh7786_shyway_clk = {
93 .name = "shyway_clk", 93 .name = "shyway_clk",
94 .flags = CLK_ALWAYS_ENABLED, 94 .flags = CLK_ENABLE_ON_INIT,
95 .ops = &sh7786_shyway_clk_ops, 95 .ops = &sh7786_shyway_clk_ops,
96}; 96};
97 97
98static void ddr_clk_recalc(struct clk *clk) 98static unsigned long ddr_clk_recalc(struct clk *clk)
99{ 99{
100 int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003); 100 int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
101 clk->rate = clk->parent->rate / mfc_divisors[idx]; 101 return clk->parent->rate / mfc_divisors[idx];
102} 102}
103 103
104static struct clk_ops sh7786_ddr_clk_ops = { 104static struct clk_ops sh7786_ddr_clk_ops = {
@@ -107,7 +107,7 @@ static struct clk_ops sh7786_ddr_clk_ops = {
107 107
108static struct clk sh7786_ddr_clk = { 108static struct clk sh7786_ddr_clk = {
109 .name = "ddr_clk", 109 .name = "ddr_clk",
110 .flags = CLK_ALWAYS_ENABLED, 110 .flags = CLK_ENABLE_ON_INIT,
111 .ops = &sh7786_ddr_clk_ops, 111 .ops = &sh7786_ddr_clk_ops,
112}; 112};
113 113
@@ -120,29 +120,22 @@ static struct clk *sh7786_onchip_clocks[] = {
120 &sh7786_ddr_clk, 120 &sh7786_ddr_clk,
121}; 121};
122 122
123static int __init sh7786_clk_init(void) 123int __init arch_clk_init(void)
124{ 124{
125 struct clk *clk = clk_get(NULL, "master_clk"); 125 struct clk *clk;
126 int i; 126 int i, ret = 0;
127 127
128 cpg_clk_init();
129
130 clk = clk_get(NULL, "master_clk");
128 for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) { 131 for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
129 struct clk *clkp = sh7786_onchip_clocks[i]; 132 struct clk *clkp = sh7786_onchip_clocks[i];
130 133
131 clkp->parent = clk; 134 clkp->parent = clk;
132 clk_register(clkp); 135 ret |= clk_register(clkp);
133 clk_enable(clkp);
134 } 136 }
135 137
136 /*
137 * Now that we have the rest of the clocks registered, we need to
138 * force the parent clock to propagate so that these clocks will
139 * automatically figure out their rate. We cheat by handing the
140 * parent clock its current rate and forcing child propagation.
141 */
142 clk_set_rate(clk, clk_get_rate(clk));
143
144 clk_put(clk); 138 clk_put(clk);
145 139
146 return 0; 140 return ret;
147} 141}
148arch_initcall(sh7786_clk_init);
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index c630b29e06a8..23c27d32d982 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -40,30 +40,30 @@ static struct clk_ops shx3_master_clk_ops = {
40 .init = master_clk_init, 40 .init = master_clk_init,
41}; 41};
42 42
43static void module_clk_recalc(struct clk *clk) 43static unsigned long module_clk_recalc(struct clk *clk)
44{ 44{
45 int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK); 45 int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK);
46 clk->rate = clk->parent->rate / pfc_divisors[idx]; 46 return clk->parent->rate / pfc_divisors[idx];
47} 47}
48 48
49static struct clk_ops shx3_module_clk_ops = { 49static struct clk_ops shx3_module_clk_ops = {
50 .recalc = module_clk_recalc, 50 .recalc = module_clk_recalc,
51}; 51};
52 52
53static void bus_clk_recalc(struct clk *clk) 53static unsigned long bus_clk_recalc(struct clk *clk)
54{ 54{
55 int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK); 55 int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK);
56 clk->rate = clk->parent->rate / bfc_divisors[idx]; 56 return clk->parent->rate / bfc_divisors[idx];
57} 57}
58 58
59static struct clk_ops shx3_bus_clk_ops = { 59static struct clk_ops shx3_bus_clk_ops = {
60 .recalc = bus_clk_recalc, 60 .recalc = bus_clk_recalc,
61}; 61};
62 62
63static void cpu_clk_recalc(struct clk *clk) 63static unsigned long cpu_clk_recalc(struct clk *clk)
64{ 64{
65 int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK); 65 int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK);
66 clk->rate = clk->parent->rate / ifc_divisors[idx]; 66 return clk->parent->rate / ifc_divisors[idx];
67} 67}
68 68
69static struct clk_ops shx3_cpu_clk_ops = { 69static struct clk_ops shx3_cpu_clk_ops = {
@@ -83,10 +83,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
83 *ops = shx3_clk_ops[idx]; 83 *ops = shx3_clk_ops[idx];
84} 84}
85 85
86static void shyway_clk_recalc(struct clk *clk) 86static unsigned long shyway_clk_recalc(struct clk *clk)
87{ 87{
88 int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK); 88 int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK);
89 clk->rate = clk->parent->rate / cfc_divisors[idx]; 89 return clk->parent->rate / cfc_divisors[idx];
90} 90}
91 91
92static struct clk_ops shx3_shyway_clk_ops = { 92static struct clk_ops shx3_shyway_clk_ops = {
@@ -95,7 +95,7 @@ static struct clk_ops shx3_shyway_clk_ops = {
95 95
96static struct clk shx3_shyway_clk = { 96static struct clk shx3_shyway_clk = {
97 .name = "shyway_clk", 97 .name = "shyway_clk",
98 .flags = CLK_ALWAYS_ENABLED, 98 .flags = CLK_ENABLE_ON_INIT,
99 .ops = &shx3_shyway_clk_ops, 99 .ops = &shx3_shyway_clk_ops,
100}; 100};
101 101
@@ -107,29 +107,22 @@ static struct clk *shx3_onchip_clocks[] = {
107 &shx3_shyway_clk, 107 &shx3_shyway_clk,
108}; 108};
109 109
110static int __init shx3_clk_init(void) 110int __init arch_clk_init(void)
111{ 111{
112 struct clk *clk = clk_get(NULL, "master_clk"); 112 struct clk *clk;
113 int i; 113 int i, ret = 0;
114 114
115 cpg_clk_init();
116
117 clk = clk_get(NULL, "master_clk");
115 for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) { 118 for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {
116 struct clk *clkp = shx3_onchip_clocks[i]; 119 struct clk *clkp = shx3_onchip_clocks[i];
117 120
118 clkp->parent = clk; 121 clkp->parent = clk;
119 clk_register(clkp); 122 ret |= clk_register(clkp);
120 clk_enable(clkp);
121 } 123 }
122 124
123 /*
124 * Now that we have the rest of the clocks registered, we need to
125 * force the parent clock to propagate so that these clocks will
126 * automatically figure out their rate. We cheat by handing the
127 * parent clock its current rate and forcing child propagation.
128 */
129 clk_set_rate(clk, clk_get_rate(clk));
130
131 clk_put(clk); 125 clk_put(clk);
132 126
133 return 0; 127 return ret;
134} 128}
135arch_initcall(shx3_clk_init);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 51204dc7ca21..6307e087c864 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -318,12 +318,6 @@ static struct platform_device *sh7343_devices[] __initdata = {
318 318
319static int __init sh7343_devices_setup(void) 319static int __init sh7343_devices_setup(void)
320{ 320{
321 clk_always_enable("uram0"); /* URAM */
322 clk_always_enable("xymem0"); /* XYMEM */
323 clk_always_enable("veu0"); /* VEU */
324 clk_always_enable("vpu0"); /* VPU */
325 clk_always_enable("jpu0"); /* JPU */
326
327 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 321 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
328 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 322 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
329 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 323 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 04de0fa85120..318516f6bfad 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -307,12 +307,6 @@ static struct platform_device *sh7366_devices[] __initdata = {
307 307
308static int __init sh7366_devices_setup(void) 308static int __init sh7366_devices_setup(void)
309{ 309{
310 clk_always_enable("rsmem0"); /* RSMEM */
311 clk_always_enable("xymem0"); /* XYMEM */
312 clk_always_enable("veu1"); /* VEU-2 */
313 clk_always_enable("veu0"); /* VEU-1 */
314 clk_always_enable("vpu0"); /* VPU */
315
316 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 310 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
317 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 311 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
318 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 312 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 5d6247fecd63..ea524a2da3e4 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -352,12 +352,6 @@ static struct platform_device *sh7722_devices[] __initdata = {
352 352
353static int __init sh7722_devices_setup(void) 353static int __init sh7722_devices_setup(void)
354{ 354{
355 clk_always_enable("uram0"); /* URAM */
356 clk_always_enable("xymem0"); /* XYMEM */
357 clk_always_enable("veu0"); /* VEU */
358 clk_always_enable("vpu0"); /* VPU */
359 clk_always_enable("jpu0"); /* JPU */
360
361 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 355 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
362 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 356 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
363 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 357 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 1429fc5e4286..04cb4aae7ea7 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -460,11 +460,6 @@ static struct platform_device *sh7723_devices[] __initdata = {
460 460
461static int __init sh7723_devices_setup(void) 461static int __init sh7723_devices_setup(void)
462{ 462{
463 clk_always_enable("meram0"); /* MERAM */
464 clk_always_enable("veu1"); /* VEU2H1 */
465 clk_always_enable("veu0"); /* VEU2H0 */
466 clk_always_enable("vpu0"); /* VPU */
467
468 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 463 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
469 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 464 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
470 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 465 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 852f8104f03a..191f0e2a7e08 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -470,10 +470,6 @@ static struct platform_device *sh7724_devices[] __initdata = {
470 470
471static int __init sh7724_devices_setup(void) 471static int __init sh7724_devices_setup(void)
472{ 472{
473 clk_always_enable("vpu0"); /* VPU */
474 clk_always_enable("veu1"); /* VEU3F1 */
475 clk_always_enable("veu0"); /* VEU3F0 */
476
477 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 473 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
478 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 474 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
479 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 475 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index c91f34c9aa83..f1e0c0d36da7 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -118,7 +118,7 @@ static struct sh_timer_config tmu0_platform_data = {
118 .name = "TMU0", 118 .name = "TMU0",
119 .channel_offset = 0x04, 119 .channel_offset = 0x04,
120 .timer_bit = 0, 120 .timer_bit = 0,
121 .clk = "module_clk", 121 .clk = "peripheral_clk",
122 .clockevent_rating = 200, 122 .clockevent_rating = 200,
123}; 123};
124 124
@@ -149,7 +149,7 @@ static struct sh_timer_config tmu1_platform_data = {
149 .name = "TMU1", 149 .name = "TMU1",
150 .channel_offset = 0x10, 150 .channel_offset = 0x10,
151 .timer_bit = 1, 151 .timer_bit = 1,
152 .clk = "module_clk", 152 .clk = "peripheral_clk",
153 .clocksource_rating = 200, 153 .clocksource_rating = 200,
154}; 154};
155 155
@@ -180,7 +180,7 @@ static struct sh_timer_config tmu2_platform_data = {
180 .name = "TMU2", 180 .name = "TMU2",
181 .channel_offset = 0x1c, 181 .channel_offset = 0x1c,
182 .timer_bit = 2, 182 .timer_bit = 2,
183 .clk = "module_clk", 183 .clk = "peripheral_clk",
184}; 184};
185 185
186static struct resource tmu2_resources[] = { 186static struct resource tmu2_resources[] = {
@@ -210,7 +210,7 @@ static struct sh_timer_config tmu3_platform_data = {
210 .name = "TMU3", 210 .name = "TMU3",
211 .channel_offset = 0x04, 211 .channel_offset = 0x04,
212 .timer_bit = 0, 212 .timer_bit = 0,
213 .clk = "module_clk", 213 .clk = "peripheral_clk",
214}; 214};
215 215
216static struct resource tmu3_resources[] = { 216static struct resource tmu3_resources[] = {
@@ -240,7 +240,7 @@ static struct sh_timer_config tmu4_platform_data = {
240 .name = "TMU4", 240 .name = "TMU4",
241 .channel_offset = 0x10, 241 .channel_offset = 0x10,
242 .timer_bit = 1, 242 .timer_bit = 1,
243 .clk = "module_clk", 243 .clk = "peripheral_clk",
244}; 244};
245 245
246static struct resource tmu4_resources[] = { 246static struct resource tmu4_resources[] = {
@@ -270,7 +270,7 @@ static struct sh_timer_config tmu5_platform_data = {
270 .name = "TMU5", 270 .name = "TMU5",
271 .channel_offset = 0x1c, 271 .channel_offset = 0x1c,
272 .timer_bit = 2, 272 .timer_bit = 2,
273 .clk = "module_clk", 273 .clk = "peripheral_clk",
274}; 274};
275 275
276static struct resource tmu5_resources[] = { 276static struct resource tmu5_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 0feba41d218d..1e86209db284 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -82,7 +82,7 @@ static struct sh_timer_config tmu0_platform_data = {
82 .name = "TMU0", 82 .name = "TMU0",
83 .channel_offset = 0x04, 83 .channel_offset = 0x04,
84 .timer_bit = 0, 84 .timer_bit = 0,
85 .clk = "module_clk", 85 .clk = "peripheral_clk",
86 .clockevent_rating = 200, 86 .clockevent_rating = 200,
87}; 87};
88 88
@@ -113,7 +113,7 @@ static struct sh_timer_config tmu1_platform_data = {
113 .name = "TMU1", 113 .name = "TMU1",
114 .channel_offset = 0x10, 114 .channel_offset = 0x10,
115 .timer_bit = 1, 115 .timer_bit = 1,
116 .clk = "module_clk", 116 .clk = "peripheral_clk",
117 .clocksource_rating = 200, 117 .clocksource_rating = 200,
118}; 118};
119 119
@@ -144,7 +144,7 @@ static struct sh_timer_config tmu2_platform_data = {
144 .name = "TMU2", 144 .name = "TMU2",
145 .channel_offset = 0x1c, 145 .channel_offset = 0x1c,
146 .timer_bit = 2, 146 .timer_bit = 2,
147 .clk = "module_clk", 147 .clk = "peripheral_clk",
148}; 148};
149 149
150static struct resource tmu2_resources[] = { 150static struct resource tmu2_resources[] = {
@@ -174,7 +174,7 @@ static struct sh_timer_config tmu3_platform_data = {
174 .name = "TMU3", 174 .name = "TMU3",
175 .channel_offset = 0x04, 175 .channel_offset = 0x04,
176 .timer_bit = 0, 176 .timer_bit = 0,
177 .clk = "module_clk", 177 .clk = "peripheral_clk",
178}; 178};
179 179
180static struct resource tmu3_resources[] = { 180static struct resource tmu3_resources[] = {
@@ -204,7 +204,7 @@ static struct sh_timer_config tmu4_platform_data = {
204 .name = "TMU4", 204 .name = "TMU4",
205 .channel_offset = 0x10, 205 .channel_offset = 0x10,
206 .timer_bit = 1, 206 .timer_bit = 1,
207 .clk = "module_clk", 207 .clk = "peripheral_clk",
208}; 208};
209 209
210static struct resource tmu4_resources[] = { 210static struct resource tmu4_resources[] = {
@@ -234,7 +234,7 @@ static struct sh_timer_config tmu5_platform_data = {
234 .name = "TMU5", 234 .name = "TMU5",
235 .channel_offset = 0x1c, 235 .channel_offset = 0x1c,
236 .timer_bit = 2, 236 .timer_bit = 2,
237 .clk = "module_clk", 237 .clk = "peripheral_clk",
238}; 238};
239 239
240static struct resource tmu5_resources[] = { 240static struct resource tmu5_resources[] = {
@@ -264,7 +264,7 @@ static struct sh_timer_config tmu6_platform_data = {
264 .name = "TMU6", 264 .name = "TMU6",
265 .channel_offset = 0x04, 265 .channel_offset = 0x04,
266 .timer_bit = 0, 266 .timer_bit = 0,
267 .clk = "module_clk", 267 .clk = "peripheral_clk",
268}; 268};
269 269
270static struct resource tmu6_resources[] = { 270static struct resource tmu6_resources[] = {
@@ -294,7 +294,7 @@ static struct sh_timer_config tmu7_platform_data = {
294 .name = "TMU7", 294 .name = "TMU7",
295 .channel_offset = 0x10, 295 .channel_offset = 0x10,
296 .timer_bit = 1, 296 .timer_bit = 1,
297 .clk = "module_clk", 297 .clk = "peripheral_clk",
298}; 298};
299 299
300static struct resource tmu7_resources[] = { 300static struct resource tmu7_resources[] = {
@@ -324,7 +324,7 @@ static struct sh_timer_config tmu8_platform_data = {
324 .name = "TMU8", 324 .name = "TMU8",
325 .channel_offset = 0x1c, 325 .channel_offset = 0x1c,
326 .timer_bit = 2, 326 .timer_bit = 2,
327 .clk = "module_clk", 327 .clk = "peripheral_clk",
328}; 328};
329 329
330static struct resource tmu8_resources[] = { 330static struct resource tmu8_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index f1df02095062..715e05b431e5 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -18,7 +18,7 @@ static struct sh_timer_config tmu0_platform_data = {
18 .name = "TMU0", 18 .name = "TMU0",
19 .channel_offset = 0x04, 19 .channel_offset = 0x04,
20 .timer_bit = 0, 20 .timer_bit = 0,
21 .clk = "module_clk", 21 .clk = "peripheral_clk",
22 .clockevent_rating = 200, 22 .clockevent_rating = 200,
23}; 23};
24 24
@@ -49,7 +49,7 @@ static struct sh_timer_config tmu1_platform_data = {
49 .name = "TMU1", 49 .name = "TMU1",
50 .channel_offset = 0x10, 50 .channel_offset = 0x10,
51 .timer_bit = 1, 51 .timer_bit = 1,
52 .clk = "module_clk", 52 .clk = "peripheral_clk",
53 .clocksource_rating = 200, 53 .clocksource_rating = 200,
54}; 54};
55 55
@@ -80,7 +80,7 @@ static struct sh_timer_config tmu2_platform_data = {
80 .name = "TMU2", 80 .name = "TMU2",
81 .channel_offset = 0x1c, 81 .channel_offset = 0x1c,
82 .timer_bit = 2, 82 .timer_bit = 2,
83 .clk = "module_clk", 83 .clk = "peripheral_clk",
84}; 84};
85 85
86static struct resource tmu2_resources[] = { 86static struct resource tmu2_resources[] = {
@@ -110,7 +110,7 @@ static struct sh_timer_config tmu3_platform_data = {
110 .name = "TMU3", 110 .name = "TMU3",
111 .channel_offset = 0x04, 111 .channel_offset = 0x04,
112 .timer_bit = 0, 112 .timer_bit = 0,
113 .clk = "module_clk", 113 .clk = "peripheral_clk",
114}; 114};
115 115
116static struct resource tmu3_resources[] = { 116static struct resource tmu3_resources[] = {
@@ -140,7 +140,7 @@ static struct sh_timer_config tmu4_platform_data = {
140 .name = "TMU4", 140 .name = "TMU4",
141 .channel_offset = 0x10, 141 .channel_offset = 0x10,
142 .timer_bit = 1, 142 .timer_bit = 1,
143 .clk = "module_clk", 143 .clk = "peripheral_clk",
144}; 144};
145 145
146static struct resource tmu4_resources[] = { 146static struct resource tmu4_resources[] = {
@@ -170,7 +170,7 @@ static struct sh_timer_config tmu5_platform_data = {
170 .name = "TMU5", 170 .name = "TMU5",
171 .channel_offset = 0x1c, 171 .channel_offset = 0x1c,
172 .timer_bit = 2, 172 .timer_bit = 2,
173 .clk = "module_clk", 173 .clk = "peripheral_clk",
174}; 174};
175 175
176static struct resource tmu5_resources[] = { 176static struct resource tmu5_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index dc5d3e507a21..af561402570b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -20,7 +20,7 @@ static struct sh_timer_config tmu0_platform_data = {
20 .name = "TMU0", 20 .name = "TMU0",
21 .channel_offset = 0x04, 21 .channel_offset = 0x04,
22 .timer_bit = 0, 22 .timer_bit = 0,
23 .clk = "module_clk", 23 .clk = "tmu012_fck",
24 .clockevent_rating = 200, 24 .clockevent_rating = 200,
25}; 25};
26 26
@@ -51,7 +51,7 @@ static struct sh_timer_config tmu1_platform_data = {
51 .name = "TMU1", 51 .name = "TMU1",
52 .channel_offset = 0x10, 52 .channel_offset = 0x10,
53 .timer_bit = 1, 53 .timer_bit = 1,
54 .clk = "module_clk", 54 .clk = "tmu012_fck",
55 .clocksource_rating = 200, 55 .clocksource_rating = 200,
56}; 56};
57 57
@@ -82,7 +82,7 @@ static struct sh_timer_config tmu2_platform_data = {
82 .name = "TMU2", 82 .name = "TMU2",
83 .channel_offset = 0x1c, 83 .channel_offset = 0x1c,
84 .timer_bit = 2, 84 .timer_bit = 2,
85 .clk = "module_clk", 85 .clk = "tmu012_fck",
86}; 86};
87 87
88static struct resource tmu2_resources[] = { 88static struct resource tmu2_resources[] = {
@@ -112,7 +112,7 @@ static struct sh_timer_config tmu3_platform_data = {
112 .name = "TMU3", 112 .name = "TMU3",
113 .channel_offset = 0x04, 113 .channel_offset = 0x04,
114 .timer_bit = 0, 114 .timer_bit = 0,
115 .clk = "module_clk", 115 .clk = "tmu345_fck",
116}; 116};
117 117
118static struct resource tmu3_resources[] = { 118static struct resource tmu3_resources[] = {
@@ -142,7 +142,7 @@ static struct sh_timer_config tmu4_platform_data = {
142 .name = "TMU4", 142 .name = "TMU4",
143 .channel_offset = 0x10, 143 .channel_offset = 0x10,
144 .timer_bit = 1, 144 .timer_bit = 1,
145 .clk = "module_clk", 145 .clk = "tmu345_fck",
146}; 146};
147 147
148static struct resource tmu4_resources[] = { 148static struct resource tmu4_resources[] = {
@@ -172,7 +172,7 @@ static struct sh_timer_config tmu5_platform_data = {
172 .name = "TMU5", 172 .name = "TMU5",
173 .channel_offset = 0x1c, 173 .channel_offset = 0x1c,
174 .timer_bit = 2, 174 .timer_bit = 2,
175 .clk = "module_clk", 175 .clk = "tmu345_fck",
176}; 176};
177 177
178static struct resource tmu5_resources[] = { 178static struct resource tmu5_resources[] = {
@@ -204,31 +204,37 @@ static struct plat_sci_port sci_platform_data[] = {
204 .flags = UPF_BOOT_AUTOCONF, 204 .flags = UPF_BOOT_AUTOCONF,
205 .type = PORT_SCIF, 205 .type = PORT_SCIF,
206 .irqs = { 40, 40, 40, 40 }, 206 .irqs = { 40, 40, 40, 40 },
207 .clk = "scif_fck",
207 }, { 208 }, {
208 .mapbase = 0xffeb0000, 209 .mapbase = 0xffeb0000,
209 .flags = UPF_BOOT_AUTOCONF, 210 .flags = UPF_BOOT_AUTOCONF,
210 .type = PORT_SCIF, 211 .type = PORT_SCIF,
211 .irqs = { 44, 44, 44, 44 }, 212 .irqs = { 44, 44, 44, 44 },
213 .clk = "scif_fck",
212 }, { 214 }, {
213 .mapbase = 0xffec0000, 215 .mapbase = 0xffec0000,
214 .flags = UPF_BOOT_AUTOCONF, 216 .flags = UPF_BOOT_AUTOCONF,
215 .type = PORT_SCIF, 217 .type = PORT_SCIF,
216 .irqs = { 60, 60, 60, 60 }, 218 .irqs = { 60, 60, 60, 60 },
219 .clk = "scif_fck",
217 }, { 220 }, {
218 .mapbase = 0xffed0000, 221 .mapbase = 0xffed0000,
219 .flags = UPF_BOOT_AUTOCONF, 222 .flags = UPF_BOOT_AUTOCONF,
220 .type = PORT_SCIF, 223 .type = PORT_SCIF,
221 .irqs = { 61, 61, 61, 61 }, 224 .irqs = { 61, 61, 61, 61 },
225 .clk = "scif_fck",
222 }, { 226 }, {
223 .mapbase = 0xffee0000, 227 .mapbase = 0xffee0000,
224 .flags = UPF_BOOT_AUTOCONF, 228 .flags = UPF_BOOT_AUTOCONF,
225 .type = PORT_SCIF, 229 .type = PORT_SCIF,
226 .irqs = { 62, 62, 62, 62 }, 230 .irqs = { 62, 62, 62, 62 },
231 .clk = "scif_fck",
227 }, { 232 }, {
228 .mapbase = 0xffef0000, 233 .mapbase = 0xffef0000,
229 .flags = UPF_BOOT_AUTOCONF, 234 .flags = UPF_BOOT_AUTOCONF,
230 .type = PORT_SCIF, 235 .type = PORT_SCIF,
231 .irqs = { 63, 63, 63, 63 }, 236 .irqs = { 63, 63, 63, 63 },
237 .clk = "scif_fck",
232 }, { 238 }, {
233 .flags = 0, 239 .flags = 0,
234 } 240 }
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 2c464bf5a899..93e0d2c017e8 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -75,7 +75,7 @@ static struct sh_timer_config tmu0_platform_data = {
75 .name = "TMU0", 75 .name = "TMU0",
76 .channel_offset = 0x04, 76 .channel_offset = 0x04,
77 .timer_bit = 0, 77 .timer_bit = 0,
78 .clk = "module_clk", 78 .clk = "peripheral_clk",
79 .clockevent_rating = 200, 79 .clockevent_rating = 200,
80}; 80};
81 81
@@ -106,7 +106,7 @@ static struct sh_timer_config tmu1_platform_data = {
106 .name = "TMU1", 106 .name = "TMU1",
107 .channel_offset = 0x10, 107 .channel_offset = 0x10,
108 .timer_bit = 1, 108 .timer_bit = 1,
109 .clk = "module_clk", 109 .clk = "peripheral_clk",
110 .clocksource_rating = 200, 110 .clocksource_rating = 200,
111}; 111};
112 112
@@ -137,7 +137,7 @@ static struct sh_timer_config tmu2_platform_data = {
137 .name = "TMU2", 137 .name = "TMU2",
138 .channel_offset = 0x1c, 138 .channel_offset = 0x1c,
139 .timer_bit = 2, 139 .timer_bit = 2,
140 .clk = "module_clk", 140 .clk = "peripheral_clk",
141}; 141};
142 142
143static struct resource tmu2_resources[] = { 143static struct resource tmu2_resources[] = {
@@ -167,7 +167,7 @@ static struct sh_timer_config tmu3_platform_data = {
167 .name = "TMU3", 167 .name = "TMU3",
168 .channel_offset = 0x04, 168 .channel_offset = 0x04,
169 .timer_bit = 0, 169 .timer_bit = 0,
170 .clk = "module_clk", 170 .clk = "peripheral_clk",
171}; 171};
172 172
173static struct resource tmu3_resources[] = { 173static struct resource tmu3_resources[] = {
@@ -197,7 +197,7 @@ static struct sh_timer_config tmu4_platform_data = {
197 .name = "TMU4", 197 .name = "TMU4",
198 .channel_offset = 0x10, 198 .channel_offset = 0x10,
199 .timer_bit = 1, 199 .timer_bit = 1,
200 .clk = "module_clk", 200 .clk = "peripheral_clk",
201}; 201};
202 202
203static struct resource tmu4_resources[] = { 203static struct resource tmu4_resources[] = {
@@ -227,7 +227,7 @@ static struct sh_timer_config tmu5_platform_data = {
227 .name = "TMU5", 227 .name = "TMU5",
228 .channel_offset = 0x1c, 228 .channel_offset = 0x1c,
229 .timer_bit = 2, 229 .timer_bit = 2,
230 .clk = "module_clk", 230 .clk = "peripheral_clk",
231}; 231};
232 232
233static struct resource tmu5_resources[] = { 233static struct resource tmu5_resources[] = {
@@ -257,7 +257,7 @@ static struct sh_timer_config tmu6_platform_data = {
257 .name = "TMU6", 257 .name = "TMU6",
258 .channel_offset = 0x04, 258 .channel_offset = 0x04,
259 .timer_bit = 0, 259 .timer_bit = 0,
260 .clk = "module_clk", 260 .clk = "peripheral_clk",
261}; 261};
262 262
263static struct resource tmu6_resources[] = { 263static struct resource tmu6_resources[] = {
@@ -287,7 +287,7 @@ static struct sh_timer_config tmu7_platform_data = {
287 .name = "TMU7", 287 .name = "TMU7",
288 .channel_offset = 0x10, 288 .channel_offset = 0x10,
289 .timer_bit = 1, 289 .timer_bit = 1,
290 .clk = "module_clk", 290 .clk = "peripheral_clk",
291}; 291};
292 292
293static struct resource tmu7_resources[] = { 293static struct resource tmu7_resources[] = {
@@ -317,7 +317,7 @@ static struct sh_timer_config tmu8_platform_data = {
317 .name = "TMU8", 317 .name = "TMU8",
318 .channel_offset = 0x1c, 318 .channel_offset = 0x1c,
319 .timer_bit = 2, 319 .timer_bit = 2,
320 .clk = "module_clk", 320 .clk = "peripheral_clk",
321}; 321};
322 322
323static struct resource tmu8_resources[] = { 323static struct resource tmu8_resources[] = {
@@ -347,7 +347,7 @@ static struct sh_timer_config tmu9_platform_data = {
347 .name = "TMU9", 347 .name = "TMU9",
348 .channel_offset = 0x04, 348 .channel_offset = 0x04,
349 .timer_bit = 0, 349 .timer_bit = 0,
350 .clk = "module_clk", 350 .clk = "peripheral_clk",
351}; 351};
352 352
353static struct resource tmu9_resources[] = { 353static struct resource tmu9_resources[] = {
@@ -377,7 +377,7 @@ static struct sh_timer_config tmu10_platform_data = {
377 .name = "TMU10", 377 .name = "TMU10",
378 .channel_offset = 0x10, 378 .channel_offset = 0x10,
379 .timer_bit = 1, 379 .timer_bit = 1,
380 .clk = "module_clk", 380 .clk = "peripheral_clk",
381}; 381};
382 382
383static struct resource tmu10_resources[] = { 383static struct resource tmu10_resources[] = {
@@ -407,7 +407,7 @@ static struct sh_timer_config tmu11_platform_data = {
407 .name = "TMU11", 407 .name = "TMU11",
408 .channel_offset = 0x1c, 408 .channel_offset = 0x1c,
409 .timer_bit = 2, 409 .timer_bit = 2,
410 .clk = "module_clk", 410 .clk = "peripheral_clk",
411}; 411};
412 412
413static struct resource tmu11_resources[] = { 413static struct resource tmu11_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 9d5185b42f13..53c65fd9ccef 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -53,7 +53,7 @@ static struct sh_timer_config tmu0_platform_data = {
53 .name = "TMU0", 53 .name = "TMU0",
54 .channel_offset = 0x04, 54 .channel_offset = 0x04,
55 .timer_bit = 0, 55 .timer_bit = 0,
56 .clk = "module_clk", 56 .clk = "peripheral_clk",
57 .clockevent_rating = 200, 57 .clockevent_rating = 200,
58}; 58};
59 59
@@ -84,7 +84,7 @@ static struct sh_timer_config tmu1_platform_data = {
84 .name = "TMU1", 84 .name = "TMU1",
85 .channel_offset = 0x10, 85 .channel_offset = 0x10,
86 .timer_bit = 1, 86 .timer_bit = 1,
87 .clk = "module_clk", 87 .clk = "peripheral_clk",
88 .clocksource_rating = 200, 88 .clocksource_rating = 200,
89}; 89};
90 90
@@ -115,7 +115,7 @@ static struct sh_timer_config tmu2_platform_data = {
115 .name = "TMU2", 115 .name = "TMU2",
116 .channel_offset = 0x1c, 116 .channel_offset = 0x1c,
117 .timer_bit = 2, 117 .timer_bit = 2,
118 .clk = "module_clk", 118 .clk = "peripheral_clk",
119}; 119};
120 120
121static struct resource tmu2_resources[] = { 121static struct resource tmu2_resources[] = {
@@ -145,7 +145,7 @@ static struct sh_timer_config tmu3_platform_data = {
145 .name = "TMU3", 145 .name = "TMU3",
146 .channel_offset = 0x04, 146 .channel_offset = 0x04,
147 .timer_bit = 0, 147 .timer_bit = 0,
148 .clk = "module_clk", 148 .clk = "peripheral_clk",
149}; 149};
150 150
151static struct resource tmu3_resources[] = { 151static struct resource tmu3_resources[] = {
@@ -175,7 +175,7 @@ static struct sh_timer_config tmu4_platform_data = {
175 .name = "TMU4", 175 .name = "TMU4",
176 .channel_offset = 0x10, 176 .channel_offset = 0x10,
177 .timer_bit = 1, 177 .timer_bit = 1,
178 .clk = "module_clk", 178 .clk = "peripheral_clk",
179}; 179};
180 180
181static struct resource tmu4_resources[] = { 181static struct resource tmu4_resources[] = {
@@ -205,7 +205,7 @@ static struct sh_timer_config tmu5_platform_data = {
205 .name = "TMU5", 205 .name = "TMU5",
206 .channel_offset = 0x1c, 206 .channel_offset = 0x1c,
207 .timer_bit = 2, 207 .timer_bit = 2,
208 .clk = "module_clk", 208 .clk = "peripheral_clk",
209}; 209};
210 210
211static struct resource tmu5_resources[] = { 211static struct resource tmu5_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c
index 5486324880e1..7f864ebc51d3 100644
--- a/arch/sh/kernel/cpu/sh5/clock-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c
@@ -32,30 +32,30 @@ static struct clk_ops sh5_master_clk_ops = {
32 .init = master_clk_init, 32 .init = master_clk_init,
33}; 33};
34 34
35static void module_clk_recalc(struct clk *clk) 35static unsigned long module_clk_recalc(struct clk *clk)
36{ 36{
37 int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007; 37 int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007;
38 clk->rate = clk->parent->rate / ifc_table[idx]; 38 return clk->parent->rate / ifc_table[idx];
39} 39}
40 40
41static struct clk_ops sh5_module_clk_ops = { 41static struct clk_ops sh5_module_clk_ops = {
42 .recalc = module_clk_recalc, 42 .recalc = module_clk_recalc,
43}; 43};
44 44
45static void bus_clk_recalc(struct clk *clk) 45static unsigned long bus_clk_recalc(struct clk *clk)
46{ 46{
47 int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007; 47 int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007;
48 clk->rate = clk->parent->rate / ifc_table[idx]; 48 return clk->parent->rate / ifc_table[idx];
49} 49}
50 50
51static struct clk_ops sh5_bus_clk_ops = { 51static struct clk_ops sh5_bus_clk_ops = {
52 .recalc = bus_clk_recalc, 52 .recalc = bus_clk_recalc,
53}; 53};
54 54
55static void cpu_clk_recalc(struct clk *clk) 55static unsigned long cpu_clk_recalc(struct clk *clk)
56{ 56{
57 int idx = (ctrl_inw(cprc_base) & 0x0007); 57 int idx = (ctrl_inw(cprc_base) & 0x0007);
58 clk->rate = clk->parent->rate / ifc_table[idx]; 58 return clk->parent->rate / ifc_table[idx];
59} 59}
60 60
61static struct clk_ops sh5_cpu_clk_ops = { 61static struct clk_ops sh5_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index 678d69bdebba..f5ff1ac57fc2 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -75,7 +75,7 @@ static struct sh_timer_config tmu0_platform_data = {
75 .name = "TMU0", 75 .name = "TMU0",
76 .channel_offset = 0x04, 76 .channel_offset = 0x04,
77 .timer_bit = 0, 77 .timer_bit = 0,
78 .clk = "module_clk", 78 .clk = "peripheral_clk",
79 .clockevent_rating = 200, 79 .clockevent_rating = 200,
80}; 80};
81 81
@@ -106,7 +106,7 @@ static struct sh_timer_config tmu1_platform_data = {
106 .name = "TMU1", 106 .name = "TMU1",
107 .channel_offset = 0x10, 107 .channel_offset = 0x10,
108 .timer_bit = 1, 108 .timer_bit = 1,
109 .clk = "module_clk", 109 .clk = "peripheral_clk",
110 .clocksource_rating = 200, 110 .clocksource_rating = 200,
111}; 111};
112 112
@@ -137,7 +137,7 @@ static struct sh_timer_config tmu2_platform_data = {
137 .name = "TMU2", 137 .name = "TMU2",
138 .channel_offset = 0x1c, 138 .channel_offset = 0x1c,
139 .timer_bit = 2, 139 .timer_bit = 2,
140 .clk = "module_clk", 140 .clk = "peripheral_clk",
141}; 141};
142 142
143static struct resource tmu2_resources[] = { 143static struct resource tmu2_resources[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 13:44:48 -0500