sh: TLB miss fast-path optimizations.

Handle simple TLB miss faults which can be resolved completely
from the page table in assembler.

Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

2 files changed, 1 insertions, 86 deletions

diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 88e9663fc9fc..6cd6d0045d16 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -20,6 +20,7 @@ config CPU_SH4
         bool
         select CPU_HAS_INTEVT
         select CPU_HAS_SR_RB
+        select CPU_HAS_PTEA if !CPU_SUBTYPE_ST40
 
 config CPU_SH4A
         bool
diff --git a/arch/sh/mm/fault.c b/arch/sh/mm/fault.c
index 128907ef7fcd..123fb80c859d 100644
--- a/arch/sh/mm/fault.c
+++ b/arch/sh/mm/fault.c
@@ -223,89 +223,3 @@ do_sigbus:
         if (!user_mode(regs))
                 goto no_context;
 }
-
-#ifdef CONFIG_SH_STORE_QUEUES
-/*
- * This is a special case for the SH-4 store queues, as pages for this
- * space still need to be faulted in before it's possible to flush the
- * store queue cache for writeout to the remapped region.
- */
-#define P3_ADDR_MAX             (P4SEG_STORE_QUE + 0x04000000)
-#else
-#define P3_ADDR_MAX             P4SEG
-#endif
-
-/*
- * Called with interrupts disabled.
- */
-asmlinkage int __kprobes __do_page_fault(struct pt_regs *regs,
-                                         unsigned long writeaccess,
-                                         unsigned long address)
-{
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
-        pte_t *pte;
-        pte_t entry;
-        struct mm_struct *mm = current->mm;
-        spinlock_t *ptl;
-        int ret = 1;
-
-#ifdef CONFIG_SH_KGDB
-        if (kgdb_nofault && kgdb_bus_err_hook)
-                kgdb_bus_err_hook();
-#endif
-
-        /*
-         * We don't take page faults for P1, P2, and parts of P4, these
-         * are always mapped, whether it be due to legacy behaviour in
-         * 29-bit mode, or due to PMB configuration in 32-bit mode.
-         */
-        if (address >= P3SEG && address < P3_ADDR_MAX) {
-                pgd = pgd_offset_k(address);
-                mm = NULL;
-        } else {
-                if (unlikely(address >= TASK_SIZE || !mm))
-                        return 1;
-
-                pgd = pgd_offset(mm, address);
-        }
-
-        pud = pud_offset(pgd, address);
-        if (pud_none_or_clear_bad(pud))
-                return 1;
-        pmd = pmd_offset(pud, address);
-        if (pmd_none_or_clear_bad(pmd))
-                return 1;
-
-        if (mm)
-                pte = pte_offset_map_lock(mm, pmd, address, &ptl);
-        else
-                pte = pte_offset_kernel(pmd, address);
-
-        entry = *pte;
-        if (unlikely(pte_none(entry) || pte_not_present(entry)))
-                goto unlock;
-        if (unlikely(writeaccess && !pte_write(entry)))
-                goto unlock;
-
-        if (writeaccess)
-                entry = pte_mkdirty(entry);
-        entry = pte_mkyoung(entry);
-
-#ifdef CONFIG_CPU_SH4
-        /*
-         * ITLB is not affected by "ldtlb" instruction.
-         * So, we need to flush the entry by ourselves.
-         */
-        __flush_tlb_page(get_asid(), address & PAGE_MASK);
-#endif
-
-        set_pte(pte, entry);
-        update_mmu_cache(NULL, address, entry);
-        ret = 0;
-unlock:
-        if (mm)
-                pte_unmap_unlock(pte, ptl);
-        return ret;
-}