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authorMark Brown <broonie@opensource.wolfsonmicro.com>2009-11-06 10:46:18 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2009-11-06 10:46:18 -0500
commit330f28f691e9b349e34adcaf82b273cf061bb491 (patch)
treefca3bfe41eff25ef19f576cef1979c68f6521af5 /arch/sh/mm
parentfe3e78e073d25308756f38019956061153267769 (diff)
parent6fc786d5034ed7ce2d43c459211137de6d99dd28 (diff)
Merge branch 'for-2.6.32' into for-2.6.33
Diffstat (limited to 'arch/sh/mm')
-rw-r--r--arch/sh/mm/Kconfig2
-rw-r--r--arch/sh/mm/cache-sh4.c24
-rw-r--r--arch/sh/mm/cache-sh7705.c4
-rw-r--r--arch/sh/mm/cache.c12
-rw-r--r--arch/sh/mm/ioremap_32.c2
-rw-r--r--arch/sh/mm/pmb.c37
6 files changed, 57 insertions, 24 deletions
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 64dc1ad59801..7f7b52f9beba 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -227,7 +227,7 @@ endchoice
227 227
228choice 228choice
229 prompt "HugeTLB page size" 229 prompt "HugeTLB page size"
230 depends on HUGETLB_PAGE && (CPU_SH4 || CPU_SH5) && MMU 230 depends on HUGETLB_PAGE
231 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB 231 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
232 default HUGETLB_PAGE_SIZE_64K 232 default HUGETLB_PAGE_SIZE_64K
233 233
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index b2453bbef4cd..519e2d16cd06 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -26,7 +26,7 @@
26#define MAX_DCACHE_PAGES 64 /* XXX: Tune for ways */ 26#define MAX_DCACHE_PAGES 64 /* XXX: Tune for ways */
27#define MAX_ICACHE_PAGES 32 27#define MAX_ICACHE_PAGES 32
28 28
29static void __flush_cache_4096(unsigned long addr, unsigned long phys, 29static void __flush_cache_one(unsigned long addr, unsigned long phys,
30 unsigned long exec_offset); 30 unsigned long exec_offset);
31 31
32/* 32/*
@@ -43,7 +43,7 @@ static void (*__flush_dcache_segment_fn)(unsigned long, unsigned long) =
43 * Called from kernel/module.c:sys_init_module and routine for a.out format, 43 * Called from kernel/module.c:sys_init_module and routine for a.out format,
44 * signal handler code and kprobes code 44 * signal handler code and kprobes code
45 */ 45 */
46static void sh4_flush_icache_range(void *args) 46static void __uses_jump_to_uncached sh4_flush_icache_range(void *args)
47{ 47{
48 struct flusher_data *data = args; 48 struct flusher_data *data = args;
49 unsigned long start, end; 49 unsigned long start, end;
@@ -89,8 +89,7 @@ static void sh4_flush_icache_range(void *args)
89 local_irq_restore(flags); 89 local_irq_restore(flags);
90} 90}
91 91
92static inline void flush_cache_4096(unsigned long start, 92static inline void flush_cache_one(unsigned long start, unsigned long phys)
93 unsigned long phys)
94{ 93{
95 unsigned long flags, exec_offset = 0; 94 unsigned long flags, exec_offset = 0;
96 95
@@ -103,8 +102,7 @@ static inline void flush_cache_4096(unsigned long start,
103 exec_offset = 0x20000000; 102 exec_offset = 0x20000000;
104 103
105 local_irq_save(flags); 104 local_irq_save(flags);
106 __flush_cache_4096(start | SH_CACHE_ASSOC, 105 __flush_cache_one(start | SH_CACHE_ASSOC, P1SEGADDR(phys), exec_offset);
107 P1SEGADDR(phys), exec_offset);
108 local_irq_restore(flags); 106 local_irq_restore(flags);
109} 107}
110 108
@@ -129,8 +127,8 @@ static void sh4_flush_dcache_page(void *arg)
129 127
130 /* Loop all the D-cache */ 128 /* Loop all the D-cache */
131 n = boot_cpu_data.dcache.n_aliases; 129 n = boot_cpu_data.dcache.n_aliases;
132 for (i = 0; i < n; i++, addr += 4096) 130 for (i = 0; i < n; i++, addr += PAGE_SIZE)
133 flush_cache_4096(addr, phys); 131 flush_cache_one(addr, phys);
134 } 132 }
135 133
136 wmb(); 134 wmb();
@@ -318,11 +316,11 @@ static void sh4_flush_cache_page(void *args)
318 /* We only need to flush D-cache when we have alias */ 316 /* We only need to flush D-cache when we have alias */
319 if ((address^phys) & alias_mask) { 317 if ((address^phys) & alias_mask) {
320 /* Loop 4K of the D-cache */ 318 /* Loop 4K of the D-cache */
321 flush_cache_4096( 319 flush_cache_one(
322 CACHE_OC_ADDRESS_ARRAY | (address & alias_mask), 320 CACHE_OC_ADDRESS_ARRAY | (address & alias_mask),
323 phys); 321 phys);
324 /* Loop another 4K of the D-cache */ 322 /* Loop another 4K of the D-cache */
325 flush_cache_4096( 323 flush_cache_one(
326 CACHE_OC_ADDRESS_ARRAY | (phys & alias_mask), 324 CACHE_OC_ADDRESS_ARRAY | (phys & alias_mask),
327 phys); 325 phys);
328 } 326 }
@@ -337,7 +335,7 @@ static void sh4_flush_cache_page(void *args)
337 * kernel has never executed the code through its identity 335 * kernel has never executed the code through its identity
338 * translation. 336 * translation.
339 */ 337 */
340 flush_cache_4096( 338 flush_cache_one(
341 CACHE_IC_ADDRESS_ARRAY | (address & alias_mask), 339 CACHE_IC_ADDRESS_ARRAY | (address & alias_mask),
342 phys); 340 phys);
343 } 341 }
@@ -393,7 +391,7 @@ static void sh4_flush_cache_range(void *args)
393} 391}
394 392
395/** 393/**
396 * __flush_cache_4096 394 * __flush_cache_one
397 * 395 *
398 * @addr: address in memory mapped cache array 396 * @addr: address in memory mapped cache array
399 * @phys: P1 address to flush (has to match tags if addr has 'A' bit 397 * @phys: P1 address to flush (has to match tags if addr has 'A' bit
@@ -406,7 +404,7 @@ static void sh4_flush_cache_range(void *args)
406 * operation (purge/write-back) is selected by the lower 2 bits of 404 * operation (purge/write-back) is selected by the lower 2 bits of
407 * 'phys'. 405 * 'phys'.
408 */ 406 */
409static void __flush_cache_4096(unsigned long addr, unsigned long phys, 407static void __flush_cache_one(unsigned long addr, unsigned long phys,
410 unsigned long exec_offset) 408 unsigned long exec_offset)
411{ 409{
412 int way_count; 410 int way_count;
diff --git a/arch/sh/mm/cache-sh7705.c b/arch/sh/mm/cache-sh7705.c
index 2cadee2037ac..2601935eb589 100644
--- a/arch/sh/mm/cache-sh7705.c
+++ b/arch/sh/mm/cache-sh7705.c
@@ -78,7 +78,7 @@ static void sh7705_flush_icache_range(void *args)
78/* 78/*
79 * Writeback&Invalidate the D-cache of the page 79 * Writeback&Invalidate the D-cache of the page
80 */ 80 */
81static void __flush_dcache_page(unsigned long phys) 81static void __uses_jump_to_uncached __flush_dcache_page(unsigned long phys)
82{ 82{
83 unsigned long ways, waysize, addrstart; 83 unsigned long ways, waysize, addrstart;
84 unsigned long flags; 84 unsigned long flags;
@@ -144,7 +144,7 @@ static void sh7705_flush_dcache_page(void *arg)
144 __flush_dcache_page(PHYSADDR(page_address(page))); 144 __flush_dcache_page(PHYSADDR(page_address(page)));
145} 145}
146 146
147static void sh7705_flush_cache_all(void *args) 147static void __uses_jump_to_uncached sh7705_flush_cache_all(void *args)
148{ 148{
149 unsigned long flags; 149 unsigned long flags;
150 150
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index 35c37b7f717a..a2dc7f9ecc51 100644
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -128,7 +128,7 @@ void __update_cache(struct vm_area_struct *vma,
128 return; 128 return;
129 129
130 page = pfn_to_page(pfn); 130 page = pfn_to_page(pfn);
131 if (pfn_valid(pfn) && page_mapping(page)) { 131 if (pfn_valid(pfn)) {
132 int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags); 132 int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
133 if (dirty) { 133 if (dirty) {
134 unsigned long addr = (unsigned long)page_address(page); 134 unsigned long addr = (unsigned long)page_address(page);
@@ -265,6 +265,8 @@ static void __init emit_cache_params(void)
265 265
266void __init cpu_cache_init(void) 266void __init cpu_cache_init(void)
267{ 267{
268 unsigned int cache_disabled = !(__raw_readl(CCR) & CCR_CACHE_ENABLE);
269
268 compute_alias(&boot_cpu_data.icache); 270 compute_alias(&boot_cpu_data.icache);
269 compute_alias(&boot_cpu_data.dcache); 271 compute_alias(&boot_cpu_data.dcache);
270 compute_alias(&boot_cpu_data.scache); 272 compute_alias(&boot_cpu_data.scache);
@@ -273,6 +275,13 @@ void __init cpu_cache_init(void)
273 __flush_purge_region = noop__flush_region; 275 __flush_purge_region = noop__flush_region;
274 __flush_invalidate_region = noop__flush_region; 276 __flush_invalidate_region = noop__flush_region;
275 277
278 /*
279 * No flushing is necessary in the disabled cache case so we can
280 * just keep the noop functions in local_flush_..() and __flush_..()
281 */
282 if (unlikely(cache_disabled))
283 goto skip;
284
276 if (boot_cpu_data.family == CPU_FAMILY_SH2) { 285 if (boot_cpu_data.family == CPU_FAMILY_SH2) {
277 extern void __weak sh2_cache_init(void); 286 extern void __weak sh2_cache_init(void);
278 287
@@ -312,5 +321,6 @@ void __init cpu_cache_init(void)
312 sh5_cache_init(); 321 sh5_cache_init();
313 } 322 }
314 323
324skip:
315 emit_cache_params(); 325 emit_cache_params();
316} 326}
diff --git a/arch/sh/mm/ioremap_32.c b/arch/sh/mm/ioremap_32.c
index c3250614e3ae..a86eaa9d75a5 100644
--- a/arch/sh/mm/ioremap_32.c
+++ b/arch/sh/mm/ioremap_32.c
@@ -83,7 +83,7 @@ void __iomem *__ioremap(unsigned long phys_addr, unsigned long size,
83 * 83 *
84 * PMB entries are all pre-faulted. 84 * PMB entries are all pre-faulted.
85 */ 85 */
86 if (unlikely(size >= 0x1000000)) { 86 if (unlikely(phys_addr >= P1SEG)) {
87 unsigned long mapped = pmb_remap(addr, phys_addr, size, flags); 87 unsigned long mapped = pmb_remap(addr, phys_addr, size, flags);
88 88
89 if (likely(mapped)) { 89 if (likely(mapped)) {
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index b1a714a92b14..aade31102112 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -33,6 +33,8 @@
33 33
34#define NR_PMB_ENTRIES 16 34#define NR_PMB_ENTRIES 16
35 35
36static void __pmb_unmap(struct pmb_entry *);
37
36static struct kmem_cache *pmb_cache; 38static struct kmem_cache *pmb_cache;
37static unsigned long pmb_map; 39static unsigned long pmb_map;
38 40
@@ -218,9 +220,10 @@ static struct {
218long pmb_remap(unsigned long vaddr, unsigned long phys, 220long pmb_remap(unsigned long vaddr, unsigned long phys,
219 unsigned long size, unsigned long flags) 221 unsigned long size, unsigned long flags)
220{ 222{
221 struct pmb_entry *pmbp; 223 struct pmb_entry *pmbp, *pmbe;
222 unsigned long wanted; 224 unsigned long wanted;
223 int pmb_flags, i; 225 int pmb_flags, i;
226 long err;
224 227
225 /* Convert typical pgprot value to the PMB equivalent */ 228 /* Convert typical pgprot value to the PMB equivalent */
226 if (flags & _PAGE_CACHABLE) { 229 if (flags & _PAGE_CACHABLE) {
@@ -236,20 +239,22 @@ long pmb_remap(unsigned long vaddr, unsigned long phys,
236 239
237again: 240again:
238 for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++) { 241 for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++) {
239 struct pmb_entry *pmbe;
240 int ret; 242 int ret;
241 243
242 if (size < pmb_sizes[i].size) 244 if (size < pmb_sizes[i].size)
243 continue; 245 continue;
244 246
245 pmbe = pmb_alloc(vaddr, phys, pmb_flags | pmb_sizes[i].flag); 247 pmbe = pmb_alloc(vaddr, phys, pmb_flags | pmb_sizes[i].flag);
246 if (IS_ERR(pmbe)) 248 if (IS_ERR(pmbe)) {
247 return PTR_ERR(pmbe); 249 err = PTR_ERR(pmbe);
250 goto out;
251 }
248 252
249 ret = set_pmb_entry(pmbe); 253 ret = set_pmb_entry(pmbe);
250 if (ret != 0) { 254 if (ret != 0) {
251 pmb_free(pmbe); 255 pmb_free(pmbe);
252 return -EBUSY; 256 err = -EBUSY;
257 goto out;
253 } 258 }
254 259
255 phys += pmb_sizes[i].size; 260 phys += pmb_sizes[i].size;
@@ -264,12 +269,25 @@ again:
264 pmbp->link = pmbe; 269 pmbp->link = pmbe;
265 270
266 pmbp = pmbe; 271 pmbp = pmbe;
272
273 /*
274 * Instead of trying smaller sizes on every iteration
275 * (even if we succeed in allocating space), try using
276 * pmb_sizes[i].size again.
277 */
278 i--;
267 } 279 }
268 280
269 if (size >= 0x1000000) 281 if (size >= 0x1000000)
270 goto again; 282 goto again;
271 283
272 return wanted - size; 284 return wanted - size;
285
286out:
287 if (pmbp)
288 __pmb_unmap(pmbp);
289
290 return err;
273} 291}
274 292
275void pmb_unmap(unsigned long addr) 293void pmb_unmap(unsigned long addr)
@@ -283,12 +301,19 @@ void pmb_unmap(unsigned long addr)
283 if (unlikely(!pmbe)) 301 if (unlikely(!pmbe))
284 return; 302 return;
285 303
304 __pmb_unmap(pmbe);
305}
306
307static void __pmb_unmap(struct pmb_entry *pmbe)
308{
286 WARN_ON(!test_bit(pmbe->entry, &pmb_map)); 309 WARN_ON(!test_bit(pmbe->entry, &pmb_map));
287 310
288 do { 311 do {
289 struct pmb_entry *pmblink = pmbe; 312 struct pmb_entry *pmblink = pmbe;
290 313
291 clear_pmb_entry(pmbe); 314 if (pmbe->entry != PMB_NO_ENTRY)
315 clear_pmb_entry(pmbe);
316
292 pmbe = pmblink->link; 317 pmbe = pmblink->link;
293 318
294 pmb_free(pmblink); 319 pmb_free(pmblink);