diff options
author | Paul Mundt <lethal@linux-sh.org> | 2009-08-14 22:05:42 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2009-08-14 22:05:42 -0400 |
commit | ecba1060583635ab55092072441ff903b5e9a659 (patch) | |
tree | d84dc75eae0b1bb2a2751240783444e2e92ca695 /arch/sh/mm | |
parent | e82da214d2fe3dc2610df966100c4f36bc0fad91 (diff) |
sh: Centralize the CPU cache initialization routines.
This provides a central point for CPU cache initialization routines.
This replaces the antiquated p3_cache_init() method, which the vast
majority of CPUs never cared about.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/mm')
-rw-r--r-- | arch/sh/mm/cache-sh4.c | 2 | ||||
-rw-r--r-- | arch/sh/mm/cache-sh5.c | 2 | ||||
-rw-r--r-- | arch/sh/mm/cache.c | 11 | ||||
-rw-r--r-- | arch/sh/mm/init.c | 2 |
4 files changed, 14 insertions, 3 deletions
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c index 92f87a460a81..df2eb87f1524 100644 --- a/arch/sh/mm/cache-sh4.c +++ b/arch/sh/mm/cache-sh4.c | |||
@@ -94,7 +94,7 @@ static void __init emit_cache_params(void) | |||
94 | /* | 94 | /* |
95 | * SH-4 has virtually indexed and physically tagged cache. | 95 | * SH-4 has virtually indexed and physically tagged cache. |
96 | */ | 96 | */ |
97 | void __init p3_cache_init(void) | 97 | void __init sh4_cache_init(void) |
98 | { | 98 | { |
99 | compute_alias(&boot_cpu_data.icache); | 99 | compute_alias(&boot_cpu_data.icache); |
100 | compute_alias(&boot_cpu_data.dcache); | 100 | compute_alias(&boot_cpu_data.dcache); |
diff --git a/arch/sh/mm/cache-sh5.c b/arch/sh/mm/cache-sh5.c index 28f3c8fb1b99..576cad04b11b 100644 --- a/arch/sh/mm/cache-sh5.c +++ b/arch/sh/mm/cache-sh5.c | |||
@@ -23,7 +23,7 @@ | |||
23 | /* Wired TLB entry for the D-cache */ | 23 | /* Wired TLB entry for the D-cache */ |
24 | static unsigned long long dtlb_cache_slot; | 24 | static unsigned long long dtlb_cache_slot; |
25 | 25 | ||
26 | void __init p3_cache_init(void) | 26 | void __init cpu_cache_init(void) |
27 | { | 27 | { |
28 | /* Reserve a slot for dcache colouring in the DTLB */ | 28 | /* Reserve a slot for dcache colouring in the DTLB */ |
29 | dtlb_cache_slot = sh64_get_wired_dtlb_entry(); | 29 | dtlb_cache_slot = sh64_get_wired_dtlb_entry(); |
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c index f51d0a4eb3ba..659981ffae24 100644 --- a/arch/sh/mm/cache.c +++ b/arch/sh/mm/cache.c | |||
@@ -127,3 +127,14 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr) | |||
127 | __flush_wback_region((void *)addr, PAGE_SIZE); | 127 | __flush_wback_region((void *)addr, PAGE_SIZE); |
128 | } | 128 | } |
129 | } | 129 | } |
130 | |||
131 | void __init cpu_cache_init(void) | ||
132 | { | ||
133 | if ((boot_cpu_data.family == CPU_FAMILY_SH4) || | ||
134 | (boot_cpu_data.family == CPU_FAMILY_SH4A) || | ||
135 | (boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) { | ||
136 | extern void __weak sh4_cache_init(void); | ||
137 | |||
138 | sh4_cache_init(); | ||
139 | } | ||
140 | } | ||
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c index fe532aeaa16d..cf0e9c5146b1 100644 --- a/arch/sh/mm/init.c +++ b/arch/sh/mm/init.c | |||
@@ -230,7 +230,7 @@ void __init mem_init(void) | |||
230 | datasize >> 10, | 230 | datasize >> 10, |
231 | initsize >> 10); | 231 | initsize >> 10); |
232 | 232 | ||
233 | p3_cache_init(); | 233 | cpu_cache_init(); |
234 | 234 | ||
235 | /* Initialize the vDSO */ | 235 | /* Initialize the vDSO */ |
236 | vsyscall_init(); | 236 | vsyscall_init(); |