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authorYoshinori Sato <ysato@users.sourceforge.jp>2008-08-04 03:33:47 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-08-04 03:33:47 -0400
commitcce2d453e4940d3fccd42a6917d01027148e11c3 (patch)
treebf921bfd41e4a40e513a1994d474e03f44089c0e /arch/sh/mm
parent1af446edfe3239b2b731f3458b3c285c397464cc (diff)
SH2(A) cache update
Includes: - SH2 (7619) Writeback support. - SH2A cache handling fix. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/mm')
-rw-r--r--arch/sh/mm/Kconfig1
-rw-r--r--arch/sh/mm/Makefile_3211
-rw-r--r--arch/sh/mm/cache-sh2.c45
-rw-r--r--arch/sh/mm/cache-sh2a.c129
4 files changed, 172 insertions, 14 deletions
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 56d0a7daa34b..9c131cac91a4 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -237,7 +237,6 @@ choice
237 237
238config CACHE_WRITEBACK 238config CACHE_WRITEBACK
239 bool "Write-back" 239 bool "Write-back"
240 depends on CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
241 240
242config CACHE_WRITETHROUGH 241config CACHE_WRITETHROUGH
243 bool "Write-through" 242 bool "Write-through"
diff --git a/arch/sh/mm/Makefile_32 b/arch/sh/mm/Makefile_32
index e295db60b91b..70e0906023cc 100644
--- a/arch/sh/mm/Makefile_32
+++ b/arch/sh/mm/Makefile_32
@@ -5,12 +5,15 @@
5obj-y := init.o extable_32.o consistent.o 5obj-y := init.o extable_32.o consistent.o
6 6
7ifndef CONFIG_CACHE_OFF 7ifndef CONFIG_CACHE_OFF
8obj-$(CONFIG_CPU_SH2) += cache-sh2.o 8cache-$(CONFIG_CPU_SH2) := cache-sh2.o
9obj-$(CONFIG_CPU_SH3) += cache-sh3.o 9cache-$(CONFIG_CPU_SH2A) := cache-sh2a.o
10obj-$(CONFIG_CPU_SH4) += cache-sh4.o 10cache-$(CONFIG_CPU_SH3) := cache-sh3.o
11obj-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o 11cache-$(CONFIG_CPU_SH4) := cache-sh4.o
12cache-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o
12endif 13endif
13 14
15obj-y += $(cache-y)
16
14mmu-y := tlb-nommu.o pg-nommu.o 17mmu-y := tlb-nommu.o pg-nommu.o
15mmu-$(CONFIG_MMU) := fault_32.o tlbflush_32.o ioremap_32.o 18mmu-$(CONFIG_MMU) := fault_32.o tlbflush_32.o ioremap_32.o
16 19
diff --git a/arch/sh/mm/cache-sh2.c b/arch/sh/mm/cache-sh2.c
index 6614033f6be9..c4e80d2b764b 100644
--- a/arch/sh/mm/cache-sh2.c
+++ b/arch/sh/mm/cache-sh2.c
@@ -2,6 +2,7 @@
2 * arch/sh/mm/cache-sh2.c 2 * arch/sh/mm/cache-sh2.c
3 * 3 *
4 * Copyright (C) 2002 Paul Mundt 4 * Copyright (C) 2002 Paul Mundt
5 * Copyright (C) 2008 Yoshinori Sato
5 * 6 *
6 * Released under the terms of the GNU GPL v2.0. 7 * Released under the terms of the GNU GPL v2.0.
7 */ 8 */
@@ -24,8 +25,15 @@ void __flush_wback_region(void *start, int size)
24 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) 25 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
25 & ~(L1_CACHE_BYTES-1); 26 & ~(L1_CACHE_BYTES-1);
26 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 27 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
27 /* FIXME cache purge */ 28 unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0);
28 ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008); 29 int way;
30 for (way = 0; way < 4; way++) {
31 unsigned long data = ctrl_inl(addr | (way << 12));
32 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
33 data &= ~SH_CACHE_UPDATED;
34 ctrl_outl(data, addr | (way << 12));
35 }
36 }
29 } 37 }
30} 38}
31 39
@@ -37,21 +45,40 @@ void __flush_purge_region(void *start, int size)
37 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); 45 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
38 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) 46 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
39 & ~(L1_CACHE_BYTES-1); 47 & ~(L1_CACHE_BYTES-1);
40 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 48
41 ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008); 49 for (v = begin; v < end; v+=L1_CACHE_BYTES)
42 } 50 ctrl_outl((v & CACHE_PHYSADDR_MASK),
51 CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
43} 52}
44 53
45void __flush_invalidate_region(void *start, int size) 54void __flush_invalidate_region(void *start, int size)
46{ 55{
56#ifdef CONFIG_CACHE_WRITEBACK
57 /*
58 * SH-2 does not support individual line invalidation, only a
59 * global invalidate.
60 */
61 unsigned long ccr;
62 unsigned long flags;
63 local_irq_save(flags);
64 jump_to_uncached();
65
66 ccr = ctrl_inl(CCR);
67 ccr |= CCR_CACHE_INVALIDATE;
68 ctrl_outl(ccr, CCR);
69
70 back_to_cached();
71 local_irq_restore(flags);
72#else
47 unsigned long v; 73 unsigned long v;
48 unsigned long begin, end; 74 unsigned long begin, end;
49 75
50 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); 76 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
51 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) 77 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
52 & ~(L1_CACHE_BYTES-1); 78 & ~(L1_CACHE_BYTES-1);
53 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
54 ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008);
55 }
56}
57 79
80 for (v = begin; v < end; v+=L1_CACHE_BYTES)
81 ctrl_outl((v & CACHE_PHYSADDR_MASK),
82 CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
83#endif
84}
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c
new file mode 100644
index 000000000000..62c0c5f35120
--- /dev/null
+++ b/arch/sh/mm/cache-sh2a.c
@@ -0,0 +1,129 @@
1/*
2 * arch/sh/mm/cache-sh2a.c
3 *
4 * Copyright (C) 2008 Yoshinori Sato
5 *
6 * Released under the terms of the GNU GPL v2.0.
7 */
8
9#include <linux/init.h>
10#include <linux/mm.h>
11
12#include <asm/cache.h>
13#include <asm/addrspace.h>
14#include <asm/processor.h>
15#include <asm/cacheflush.h>
16#include <asm/io.h>
17
18void __flush_wback_region(void *start, int size)
19{
20 unsigned long v;
21 unsigned long begin, end;
22 unsigned long flags;
23
24 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
25 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
26 & ~(L1_CACHE_BYTES-1);
27
28 local_irq_save(flags);
29 jump_to_uncached();
30
31 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
32 unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0);
33 int way;
34 for (way = 0; way < 4; way++) {
35 unsigned long data = ctrl_inl(addr | (way << 11));
36 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
37 data &= ~SH_CACHE_UPDATED;
38 ctrl_outl(data, addr | (way << 11));
39 }
40 }
41 }
42
43 back_to_cached();
44 local_irq_restore(flags);
45}
46
47void __flush_purge_region(void *start, int size)
48{
49 unsigned long v;
50 unsigned long begin, end;
51 unsigned long flags;
52
53 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
54 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
55 & ~(L1_CACHE_BYTES-1);
56
57 local_irq_save(flags);
58 jump_to_uncached();
59
60 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
61 ctrl_outl((v & CACHE_PHYSADDR_MASK),
62 CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
63 }
64 back_to_cached();
65 local_irq_restore(flags);
66}
67
68void __flush_invalidate_region(void *start, int size)
69{
70 unsigned long v;
71 unsigned long begin, end;
72 unsigned long flags;
73
74 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
75 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
76 & ~(L1_CACHE_BYTES-1);
77 local_irq_save(flags);
78 jump_to_uncached();
79
80#ifdef CONFIG_CACHE_WRITEBACK
81 ctrl_outl(ctrl_inl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
82 /* I-cache invalidate */
83 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
84 ctrl_outl((v & CACHE_PHYSADDR_MASK),
85 CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
86 }
87#else
88 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
89 ctrl_outl((v & CACHE_PHYSADDR_MASK),
90 CACHE_IC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
91 ctrl_outl((v & CACHE_PHYSADDR_MASK),
92 CACHE_OC_ADDRESS_ARRAY | (v & 0x000003f0) | 0x00000008);
93 }
94#endif
95 back_to_cached();
96 local_irq_restore(flags);
97}
98
99/* WBack O-Cache and flush I-Cache */
100void flush_icache_range(unsigned long start, unsigned long end)
101{
102 unsigned long v;
103 unsigned long flags;
104
105 start = start & ~(L1_CACHE_BYTES-1);
106 end = (end + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1);
107
108 local_irq_save(flags);
109 jump_to_uncached();
110
111 for (v = start; v < end; v+=L1_CACHE_BYTES) {
112 unsigned long addr = (v & 0x000007f0);
113 int way;
114 /* O-Cache writeback */
115 for (way = 0; way < 4; way++) {
116 unsigned long data = ctrl_inl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
117 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
118 data &= ~SH_CACHE_UPDATED;
119 ctrl_outl(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
120 }
121 }
122 /* I-Cache invalidate */
123 ctrl_outl(addr,
124 CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008);
125 }
126
127 back_to_cached();
128 local_irq_restore(flags);
129}