diff options
author | Paul Mundt <lethal@linux-sh.org> | 2010-01-19 01:20:35 -0500 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2010-01-19 01:20:35 -0500 |
commit | bb29c677b366fdf4f6522cd82228a32567aa98c7 (patch) | |
tree | 0235c7477ed635c8c21131b90094d151663ae889 /arch/sh/mm/tlb-urb.c | |
parent | 046581f9623b53f551a93864bb74e15ad2514f0c (diff) |
sh: Split out MMUCR.URB based entry wiring in to shared helper.
Presently this is duplicated between tlb-sh4 and tlb-pteaex. Split the
helpers out in to a generic tlb-urb that can be used by any parts
equipped with MMUCR.URB.
At the same time, move the SH-5 code out-of-line, as we require single
global state for DTLB entry wiring.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/mm/tlb-urb.c')
-rw-r--r-- | arch/sh/mm/tlb-urb.c | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/arch/sh/mm/tlb-urb.c b/arch/sh/mm/tlb-urb.c new file mode 100644 index 000000000000..bb5b9098956d --- /dev/null +++ b/arch/sh/mm/tlb-urb.c | |||
@@ -0,0 +1,81 @@ | |||
1 | /* | ||
2 | * arch/sh/mm/tlb-urb.c | ||
3 | * | ||
4 | * TLB entry wiring helpers for URB-equipped parts. | ||
5 | * | ||
6 | * Copyright (C) 2010 Matt Fleming | ||
7 | * | ||
8 | * This file is subject to the terms and conditions of the GNU General Public | ||
9 | * License. See the file "COPYING" in the main directory of this archive | ||
10 | * for more details. | ||
11 | */ | ||
12 | #include <linux/mm.h> | ||
13 | #include <linux/io.h> | ||
14 | #include <asm/tlb.h> | ||
15 | #include <asm/mmu_context.h> | ||
16 | |||
17 | /* | ||
18 | * Load the entry for 'addr' into the TLB and wire the entry. | ||
19 | */ | ||
20 | void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte) | ||
21 | { | ||
22 | unsigned long status, flags; | ||
23 | int urb; | ||
24 | |||
25 | local_irq_save(flags); | ||
26 | |||
27 | /* Load the entry into the TLB */ | ||
28 | __update_tlb(vma, addr, pte); | ||
29 | |||
30 | /* ... and wire it up. */ | ||
31 | status = __raw_readl(MMUCR); | ||
32 | urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT; | ||
33 | status &= ~MMUCR_URB; | ||
34 | |||
35 | /* | ||
36 | * Make sure we're not trying to wire the last TLB entry slot. | ||
37 | */ | ||
38 | BUG_ON(!--urb); | ||
39 | |||
40 | urb = urb % MMUCR_URB_NENTRIES; | ||
41 | |||
42 | status |= (urb << MMUCR_URB_SHIFT); | ||
43 | __raw_writel(status, MMUCR); | ||
44 | ctrl_barrier(); | ||
45 | |||
46 | local_irq_restore(flags); | ||
47 | } | ||
48 | |||
49 | /* | ||
50 | * Unwire the last wired TLB entry. | ||
51 | * | ||
52 | * It should also be noted that it is not possible to wire and unwire | ||
53 | * TLB entries in an arbitrary order. If you wire TLB entry N, followed | ||
54 | * by entry N+1, you must unwire entry N+1 first, then entry N. In this | ||
55 | * respect, it works like a stack or LIFO queue. | ||
56 | */ | ||
57 | void tlb_unwire_entry(void) | ||
58 | { | ||
59 | unsigned long status, flags; | ||
60 | int urb; | ||
61 | |||
62 | local_irq_save(flags); | ||
63 | |||
64 | status = __raw_readl(MMUCR); | ||
65 | urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT; | ||
66 | status &= ~MMUCR_URB; | ||
67 | |||
68 | /* | ||
69 | * Make sure we're not trying to unwire a TLB entry when none | ||
70 | * have been wired. | ||
71 | */ | ||
72 | BUG_ON(urb++ == MMUCR_URB_NENTRIES); | ||
73 | |||
74 | urb = urb % MMUCR_URB_NENTRIES; | ||
75 | |||
76 | status |= (urb << MMUCR_URB_SHIFT); | ||
77 | __raw_writel(status, MMUCR); | ||
78 | ctrl_barrier(); | ||
79 | |||
80 | local_irq_restore(flags); | ||
81 | } | ||