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authorIngo Molnar <mingo@elte.hu>2009-09-20 14:24:58 -0400
committerIngo Molnar <mingo@elte.hu>2009-09-20 14:25:03 -0400
commitbfefb7a0c6e08736f2d5917c468467f134bf28bb (patch)
tree7aa7084114dc083fe5b4d7b532901bdeb67188e7 /arch/sh/mm/flush-sh4.c
parent8d0cc631f6dd0a9283ceb7d61d8b85ecbcd355ea (diff)
parent78f28b7c555359c67c2a0d23f7436e915329421e (diff)
Merge branch 'linus' into x86/urgent
Merge reason: Bring in changes that the next patch will depend on. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/sh/mm/flush-sh4.c')
-rw-r--r--arch/sh/mm/flush-sh4.c108
1 files changed, 108 insertions, 0 deletions
diff --git a/arch/sh/mm/flush-sh4.c b/arch/sh/mm/flush-sh4.c
new file mode 100644
index 000000000000..cef402678f42
--- /dev/null
+++ b/arch/sh/mm/flush-sh4.c
@@ -0,0 +1,108 @@
1#include <linux/mm.h>
2#include <asm/mmu_context.h>
3#include <asm/cacheflush.h>
4
5/*
6 * Write back the dirty D-caches, but not invalidate them.
7 *
8 * START: Virtual Address (U0, P1, or P3)
9 * SIZE: Size of the region.
10 */
11static void sh4__flush_wback_region(void *start, int size)
12{
13 reg_size_t aligned_start, v, cnt, end;
14
15 aligned_start = register_align(start);
16 v = aligned_start & ~(L1_CACHE_BYTES-1);
17 end = (aligned_start + size + L1_CACHE_BYTES-1)
18 & ~(L1_CACHE_BYTES-1);
19 cnt = (end - v) / L1_CACHE_BYTES;
20
21 while (cnt >= 8) {
22 __ocbwb(v); v += L1_CACHE_BYTES;
23 __ocbwb(v); v += L1_CACHE_BYTES;
24 __ocbwb(v); v += L1_CACHE_BYTES;
25 __ocbwb(v); v += L1_CACHE_BYTES;
26 __ocbwb(v); v += L1_CACHE_BYTES;
27 __ocbwb(v); v += L1_CACHE_BYTES;
28 __ocbwb(v); v += L1_CACHE_BYTES;
29 __ocbwb(v); v += L1_CACHE_BYTES;
30 cnt -= 8;
31 }
32
33 while (cnt) {
34 __ocbwb(v); v += L1_CACHE_BYTES;
35 cnt--;
36 }
37}
38
39/*
40 * Write back the dirty D-caches and invalidate them.
41 *
42 * START: Virtual Address (U0, P1, or P3)
43 * SIZE: Size of the region.
44 */
45static void sh4__flush_purge_region(void *start, int size)
46{
47 reg_size_t aligned_start, v, cnt, end;
48
49 aligned_start = register_align(start);
50 v = aligned_start & ~(L1_CACHE_BYTES-1);
51 end = (aligned_start + size + L1_CACHE_BYTES-1)
52 & ~(L1_CACHE_BYTES-1);
53 cnt = (end - v) / L1_CACHE_BYTES;
54
55 while (cnt >= 8) {
56 __ocbp(v); v += L1_CACHE_BYTES;
57 __ocbp(v); v += L1_CACHE_BYTES;
58 __ocbp(v); v += L1_CACHE_BYTES;
59 __ocbp(v); v += L1_CACHE_BYTES;
60 __ocbp(v); v += L1_CACHE_BYTES;
61 __ocbp(v); v += L1_CACHE_BYTES;
62 __ocbp(v); v += L1_CACHE_BYTES;
63 __ocbp(v); v += L1_CACHE_BYTES;
64 cnt -= 8;
65 }
66 while (cnt) {
67 __ocbp(v); v += L1_CACHE_BYTES;
68 cnt--;
69 }
70}
71
72/*
73 * No write back please
74 */
75static void sh4__flush_invalidate_region(void *start, int size)
76{
77 reg_size_t aligned_start, v, cnt, end;
78
79 aligned_start = register_align(start);
80 v = aligned_start & ~(L1_CACHE_BYTES-1);
81 end = (aligned_start + size + L1_CACHE_BYTES-1)
82 & ~(L1_CACHE_BYTES-1);
83 cnt = (end - v) / L1_CACHE_BYTES;
84
85 while (cnt >= 8) {
86 __ocbi(v); v += L1_CACHE_BYTES;
87 __ocbi(v); v += L1_CACHE_BYTES;
88 __ocbi(v); v += L1_CACHE_BYTES;
89 __ocbi(v); v += L1_CACHE_BYTES;
90 __ocbi(v); v += L1_CACHE_BYTES;
91 __ocbi(v); v += L1_CACHE_BYTES;
92 __ocbi(v); v += L1_CACHE_BYTES;
93 __ocbi(v); v += L1_CACHE_BYTES;
94 cnt -= 8;
95 }
96
97 while (cnt) {
98 __ocbi(v); v += L1_CACHE_BYTES;
99 cnt--;
100 }
101}
102
103void __init sh4__flush_region_init(void)
104{
105 __flush_wback_region = sh4__flush_wback_region;
106 __flush_invalidate_region = sh4__flush_invalidate_region;
107 __flush_purge_region = sh4__flush_purge_region;
108}