aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/mm/cache-sh7705.c
diff options
context:
space:
mode:
authorPaul Mundt <lethal@linux-sh.org>2006-12-24 20:19:56 -0500
committerPaul Mundt <lethal@linux-sh.org>2007-02-12 20:54:45 -0500
commit11c1965687b0a472add948d4240dfe65a2fcb298 (patch)
tree69a71a34591bbdc6339dbe72de36819479f96198 /arch/sh/mm/cache-sh7705.c
parentaec5e0e1c179fac4bbca4007a3f0d3107275a73c (diff)
sh: Fixup cpu_data references for the non-boot CPUs.
There are a lot of bogus cpu_data-> references that only end up working for the boot CPU, convert these to current_cpu_data to fixup SMP. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/mm/cache-sh7705.c')
-rw-r--r--arch/sh/mm/cache-sh7705.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/sh/mm/cache-sh7705.c b/arch/sh/mm/cache-sh7705.c
index 2808b580d984..31f8deb7a158 100644
--- a/arch/sh/mm/cache-sh7705.c
+++ b/arch/sh/mm/cache-sh7705.c
@@ -32,9 +32,9 @@ static inline void cache_wback_all(void)
32{ 32{
33 unsigned long ways, waysize, addrstart; 33 unsigned long ways, waysize, addrstart;
34 34
35 ways = cpu_data->dcache.ways; 35 ways = current_cpu_data.dcache.ways;
36 waysize = cpu_data->dcache.sets; 36 waysize = current_cpu_data.dcache.sets;
37 waysize <<= cpu_data->dcache.entry_shift; 37 waysize <<= current_cpu_data.dcache.entry_shift;
38 38
39 addrstart = CACHE_OC_ADDRESS_ARRAY; 39 addrstart = CACHE_OC_ADDRESS_ARRAY;
40 40
@@ -43,7 +43,7 @@ static inline void cache_wback_all(void)
43 43
44 for (addr = addrstart; 44 for (addr = addrstart;
45 addr < addrstart + waysize; 45 addr < addrstart + waysize;
46 addr += cpu_data->dcache.linesz) { 46 addr += current_cpu_data.dcache.linesz) {
47 unsigned long data; 47 unsigned long data;
48 int v = SH_CACHE_UPDATED | SH_CACHE_VALID; 48 int v = SH_CACHE_UPDATED | SH_CACHE_VALID;
49 49
@@ -53,7 +53,7 @@ static inline void cache_wback_all(void)
53 ctrl_outl(data & ~v, addr); 53 ctrl_outl(data & ~v, addr);
54 } 54 }
55 55
56 addrstart += cpu_data->dcache.way_incr; 56 addrstart += current_cpu_data.dcache.way_incr;
57 } while (--ways); 57 } while (--ways);
58} 58}
59 59
@@ -93,9 +93,9 @@ static void __flush_dcache_page(unsigned long phys)
93 local_irq_save(flags); 93 local_irq_save(flags);
94 jump_to_P2(); 94 jump_to_P2();
95 95
96 ways = cpu_data->dcache.ways; 96 ways = current_cpu_data.dcache.ways;
97 waysize = cpu_data->dcache.sets; 97 waysize = current_cpu_data.dcache.sets;
98 waysize <<= cpu_data->dcache.entry_shift; 98 waysize <<= current_cpu_data.dcache.entry_shift;
99 99
100 addrstart = CACHE_OC_ADDRESS_ARRAY; 100 addrstart = CACHE_OC_ADDRESS_ARRAY;
101 101
@@ -104,7 +104,7 @@ static void __flush_dcache_page(unsigned long phys)
104 104
105 for (addr = addrstart; 105 for (addr = addrstart;
106 addr < addrstart + waysize; 106 addr < addrstart + waysize;
107 addr += cpu_data->dcache.linesz) { 107 addr += current_cpu_data.dcache.linesz) {
108 unsigned long data; 108 unsigned long data;
109 109
110 data = ctrl_inl(addr) & (0x1ffffC00 | SH_CACHE_VALID); 110 data = ctrl_inl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
@@ -114,7 +114,7 @@ static void __flush_dcache_page(unsigned long phys)
114 } 114 }
115 } 115 }
116 116
117 addrstart += cpu_data->dcache.way_incr; 117 addrstart += current_cpu_data.dcache.way_incr;
118 } while (--ways); 118 } while (--ways);
119 119
120 back_to_P1(); 120 back_to_P1();