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authorPaul Mundt <lethal@linux-sh.org>2009-08-14 23:29:49 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-08-14 23:29:49 -0400
commit37443ef3f0406e855e169c87ae3f4ffb4b6ff635 (patch)
treedd57e6fe91e6058b45660b6e4629249a50bc448e /arch/sh/mm/cache-sh5.c
parent916e97834e023f89b31f796b53cc9c7956e7fe17 (diff)
sh: Migrate SH-4 cacheflush ops to function pointers.
This paves the way for allowing individual CPUs to overload the individual flushing routines that they care about without having to depend on weak aliases. SH-4 is converted over initially, as it wires up pretty much everything. The majority of the other CPUs will simply use the default no-op implementation with their own region flushers wired up. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/mm/cache-sh5.c')
-rw-r--r--arch/sh/mm/cache-sh5.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/sh/mm/cache-sh5.c b/arch/sh/mm/cache-sh5.c
index a50d23caf015..a8f5142dc2cf 100644
--- a/arch/sh/mm/cache-sh5.c
+++ b/arch/sh/mm/cache-sh5.c
@@ -20,6 +20,8 @@
20#include <asm/uaccess.h> 20#include <asm/uaccess.h>
21#include <asm/mmu_context.h> 21#include <asm/mmu_context.h>
22 22
23extern void __weak sh4__flush_region_init(void);
24
23/* Wired TLB entry for the D-cache */ 25/* Wired TLB entry for the D-cache */
24static unsigned long long dtlb_cache_slot; 26static unsigned long long dtlb_cache_slot;
25 27
@@ -27,6 +29,8 @@ void __init cpu_cache_init(void)
27{ 29{
28 /* Reserve a slot for dcache colouring in the DTLB */ 30 /* Reserve a slot for dcache colouring in the DTLB */
29 dtlb_cache_slot = sh64_get_wired_dtlb_entry(); 31 dtlb_cache_slot = sh64_get_wired_dtlb_entry();
32
33 sh4__flush_region_init();
30} 34}
31 35
32void __init kmap_coherent_init(void) 36void __init kmap_coherent_init(void)