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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-11 13:08:33 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-11 13:08:33 -0400
commitd3d07d941fd80c173b6d690ded00ee5fb8302e06 (patch)
treef1a82c956e393df9933c8544bb564ef1735384ee /arch/sh/mm/cache-sh5.c
parent6cd8e300b49332eb9eeda45816c711c198d31505 (diff)
parent54ff328b46e58568c4b3350c2fa3223ef862e5a4 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (266 commits) sh: Tie sparseirq in to Kconfig. sh: Wire up sys_rt_tgsigqueueinfo. sh: Fix sys_pwritev() syscall table entry for sh32. sh: Fix sh4a llsc-based cmpxchg() sh: sh7724: Add JPU support sh: sh7724: INTC setting update sh: sh7722 clock framework rewrite sh: sh7366 clock framework rewrite sh: sh7343 clock framework rewrite sh: sh7724 clock framework rewrite V3 sh: sh7723 clock framework rewrite V2 sh: add enable()/disable()/set_rate() to div6 code sh: add AP325RXA mode pin configuration sh: add Migo-R mode pin configuration sh: sh7722 mode pin definitions sh: sh7724 mode pin comments sh: sh7723 mode pin V2 sh: rework mode pin code sh: clock div6 helper code sh: clock div4 frequency table offset fix ...
Diffstat (limited to 'arch/sh/mm/cache-sh5.c')
-rw-r--r--arch/sh/mm/cache-sh5.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/sh/mm/cache-sh5.c b/arch/sh/mm/cache-sh5.c
index 9e277ec7d536..86762092508c 100644
--- a/arch/sh/mm/cache-sh5.c
+++ b/arch/sh/mm/cache-sh5.c
@@ -60,7 +60,7 @@ static inline void sh64_teardown_dtlb_cache_slot(void)
60static inline void sh64_icache_inv_all(void) 60static inline void sh64_icache_inv_all(void)
61{ 61{
62 unsigned long long addr, flag, data; 62 unsigned long long addr, flag, data;
63 unsigned int flags; 63 unsigned long flags;
64 64
65 addr = ICCR0; 65 addr = ICCR0;
66 flag = ICCR0_ICI; 66 flag = ICCR0_ICI;
@@ -172,7 +172,7 @@ static void sh64_icache_inv_user_page_range(struct mm_struct *mm,
172 unsigned long eaddr; 172 unsigned long eaddr;
173 unsigned long after_last_page_start; 173 unsigned long after_last_page_start;
174 unsigned long mm_asid, current_asid; 174 unsigned long mm_asid, current_asid;
175 unsigned long long flags = 0ULL; 175 unsigned long flags = 0;
176 176
177 mm_asid = cpu_asid(smp_processor_id(), mm); 177 mm_asid = cpu_asid(smp_processor_id(), mm);
178 current_asid = get_asid(); 178 current_asid = get_asid();
@@ -236,7 +236,7 @@ static void sh64_icache_inv_user_small_range(struct mm_struct *mm,
236 unsigned long long eaddr = start; 236 unsigned long long eaddr = start;
237 unsigned long long eaddr_end = start + len; 237 unsigned long long eaddr_end = start + len;
238 unsigned long current_asid, mm_asid; 238 unsigned long current_asid, mm_asid;
239 unsigned long long flags; 239 unsigned long flags;
240 unsigned long long epage_start; 240 unsigned long long epage_start;
241 241
242 /* 242 /*
@@ -342,7 +342,7 @@ static void inline sh64_dcache_purge_sets(int sets_to_purge_base, int n_sets)
342 * alloco is a NOP if the cache is write-through. 342 * alloco is a NOP if the cache is write-through.
343 */ 343 */
344 if (test_bit(SH_CACHE_MODE_WT, &(cpu_data->dcache.flags))) 344 if (test_bit(SH_CACHE_MODE_WT, &(cpu_data->dcache.flags)))
345 ctrl_inb(eaddr); 345 __raw_readb((unsigned long)eaddr);
346 } 346 }
347 } 347 }
348 348