diff options
author | Paul Mundt <lethal@linux-sh.org> | 2009-08-21 05:21:07 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2009-08-21 05:21:07 -0400 |
commit | 64a6d72213dd810dd55bd0a503c36150af41c3c3 (patch) | |
tree | 81f2f6e66d3a38f5cb7a27f0a85b365b25469fe4 /arch/sh/mm/cache-sh4.c | |
parent | f26b2a562b46ab186c8383993ab1332673ac4a47 (diff) |
sh: Kill off now redundant local irq disabling.
on_each_cpu() takes care of IRQ and preempt handling, the localized
handling in each of the called functions can be killed off.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/mm/cache-sh4.c')
-rw-r--r-- | arch/sh/mm/cache-sh4.c | 61 |
1 files changed, 26 insertions, 35 deletions
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c index 9201b37c7cca..e3b77f0fa470 100644 --- a/arch/sh/mm/cache-sh4.c +++ b/arch/sh/mm/cache-sh4.c | |||
@@ -48,48 +48,44 @@ static void sh4_flush_icache_range(void *args) | |||
48 | struct flusher_data *data = args; | 48 | struct flusher_data *data = args; |
49 | int icacheaddr; | 49 | int icacheaddr; |
50 | unsigned long start, end; | 50 | unsigned long start, end; |
51 | unsigned long flags, v; | 51 | unsigned long v; |
52 | int i; | 52 | int i; |
53 | 53 | ||
54 | start = data->addr1; | 54 | start = data->addr1; |
55 | end = data->addr2; | 55 | end = data->addr2; |
56 | 56 | ||
57 | /* If there are too many pages then just blow the caches */ | 57 | /* If there are too many pages then just blow the caches */ |
58 | if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) { | 58 | if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) { |
59 | local_flush_cache_all(args); | 59 | local_flush_cache_all(args); |
60 | } else { | 60 | } else { |
61 | /* selectively flush d-cache then invalidate the i-cache */ | 61 | /* selectively flush d-cache then invalidate the i-cache */ |
62 | /* this is inefficient, so only use for small ranges */ | 62 | /* this is inefficient, so only use for small ranges */ |
63 | start &= ~(L1_CACHE_BYTES-1); | 63 | start &= ~(L1_CACHE_BYTES-1); |
64 | end += L1_CACHE_BYTES-1; | 64 | end += L1_CACHE_BYTES-1; |
65 | end &= ~(L1_CACHE_BYTES-1); | 65 | end &= ~(L1_CACHE_BYTES-1); |
66 | 66 | ||
67 | local_irq_save(flags); | 67 | jump_to_uncached(); |
68 | jump_to_uncached(); | 68 | |
69 | 69 | for (v = start; v < end; v+=L1_CACHE_BYTES) { | |
70 | for (v = start; v < end; v+=L1_CACHE_BYTES) { | 70 | __ocbwb(v); |
71 | asm volatile("ocbwb %0" | 71 | |
72 | : /* no output */ | 72 | icacheaddr = CACHE_IC_ADDRESS_ARRAY | |
73 | : "m" (__m(v))); | 73 | (v & cpu_data->icache.entry_mask); |
74 | 74 | ||
75 | icacheaddr = CACHE_IC_ADDRESS_ARRAY | ( | 75 | for (i = 0; i < cpu_data->icache.ways; |
76 | v & cpu_data->icache.entry_mask); | 76 | i++, icacheaddr += cpu_data->icache.way_incr) |
77 | 77 | /* Clear i-cache line valid-bit */ | |
78 | for (i = 0; i < cpu_data->icache.ways; | 78 | ctrl_outl(0, icacheaddr); |
79 | i++, icacheaddr += cpu_data->icache.way_incr) | 79 | } |
80 | /* Clear i-cache line valid-bit */ | ||
81 | ctrl_outl(0, icacheaddr); | ||
82 | } | ||
83 | 80 | ||
84 | back_to_cached(); | 81 | back_to_cached(); |
85 | local_irq_restore(flags); | ||
86 | } | 82 | } |
87 | } | 83 | } |
88 | 84 | ||
89 | static inline void flush_cache_4096(unsigned long start, | 85 | static inline void flush_cache_4096(unsigned long start, |
90 | unsigned long phys) | 86 | unsigned long phys) |
91 | { | 87 | { |
92 | unsigned long flags, exec_offset = 0; | 88 | unsigned long exec_offset = 0; |
93 | 89 | ||
94 | /* | 90 | /* |
95 | * All types of SH-4 require PC to be in P2 to operate on the I-cache. | 91 | * All types of SH-4 require PC to be in P2 to operate on the I-cache. |
@@ -99,10 +95,8 @@ static inline void flush_cache_4096(unsigned long start, | |||
99 | (start < CACHE_OC_ADDRESS_ARRAY)) | 95 | (start < CACHE_OC_ADDRESS_ARRAY)) |
100 | exec_offset = 0x20000000; | 96 | exec_offset = 0x20000000; |
101 | 97 | ||
102 | local_irq_save(flags); | ||
103 | __flush_cache_4096(start | SH_CACHE_ASSOC, | 98 | __flush_cache_4096(start | SH_CACHE_ASSOC, |
104 | P1SEGADDR(phys), exec_offset); | 99 | P1SEGADDR(phys), exec_offset); |
105 | local_irq_restore(flags); | ||
106 | } | 100 | } |
107 | 101 | ||
108 | /* | 102 | /* |
@@ -135,9 +129,8 @@ static void sh4_flush_dcache_page(void *page) | |||
135 | /* TODO: Selective icache invalidation through IC address array.. */ | 129 | /* TODO: Selective icache invalidation through IC address array.. */ |
136 | static void __uses_jump_to_uncached flush_icache_all(void) | 130 | static void __uses_jump_to_uncached flush_icache_all(void) |
137 | { | 131 | { |
138 | unsigned long flags, ccr; | 132 | unsigned long ccr; |
139 | 133 | ||
140 | local_irq_save(flags); | ||
141 | jump_to_uncached(); | 134 | jump_to_uncached(); |
142 | 135 | ||
143 | /* Flush I-cache */ | 136 | /* Flush I-cache */ |
@@ -149,9 +142,7 @@ static void __uses_jump_to_uncached flush_icache_all(void) | |||
149 | * back_to_cached() will take care of the barrier for us, don't add | 142 | * back_to_cached() will take care of the barrier for us, don't add |
150 | * another one! | 143 | * another one! |
151 | */ | 144 | */ |
152 | |||
153 | back_to_cached(); | 145 | back_to_cached(); |
154 | local_irq_restore(flags); | ||
155 | } | 146 | } |
156 | 147 | ||
157 | static inline void flush_dcache_all(void) | 148 | static inline void flush_dcache_all(void) |