diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-02-26 19:54:27 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-02-26 19:54:27 -0500 |
commit | 64d497f55379b1e320a08ec2426468d96f5642ec (patch) | |
tree | 22b9ab3c5e69c5cc2728cbc2ca7fc7623beef8f1 /arch/sh/mm/cache-sh2.c | |
parent | 37d4008484977f60d5d37499a2670c79b214dd46 (diff) | |
parent | b5f5fe80fa98a60daa0fa94512d1599b1e26674c (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (187 commits)
sh: remove dead LED code for migo-r and ms7724se
sh: ecovec build fix for CONFIG_I2C=n
sh: ecovec r-standby support
sh: ms7724se r-standby support
sh: SH-Mobile R-standby register save/restore
clocksource: Fix up a registration/IRQ race in the sh drivers.
sh: ms7724: modify scan_timing for KEYSC
sh: ms7724: Add sh_sir support
sh: mach-ecovec24: Add sh_sir support
sh: wire up SET/GET_UNALIGN_CTL.
sh: allow alignment fault mode to be configured at kernel boot.
sh: sh7724: Update FSI/SPU2 clock
sh: always enable sh7724 vpu_clk and set to 166MHz on Ecovec
sh: add sh7724 kick callback to clk_div4_table
sh: introduce struct clk_div4_table
sh: clock-cpg div4 set_rate() shift fix
sh: Turn on speculative return for SH7785 and SH7786
sh: Merge legacy and dynamic PMB modes.
sh: Use uncached I/O helpers in PMB setup.
sh: Provide uncached I/O helpers.
...
Diffstat (limited to 'arch/sh/mm/cache-sh2.c')
-rw-r--r-- | arch/sh/mm/cache-sh2.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/sh/mm/cache-sh2.c b/arch/sh/mm/cache-sh2.c index 699a71f46327..defcf719f2e8 100644 --- a/arch/sh/mm/cache-sh2.c +++ b/arch/sh/mm/cache-sh2.c | |||
@@ -28,10 +28,10 @@ static void sh2__flush_wback_region(void *start, int size) | |||
28 | unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0); | 28 | unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0); |
29 | int way; | 29 | int way; |
30 | for (way = 0; way < 4; way++) { | 30 | for (way = 0; way < 4; way++) { |
31 | unsigned long data = ctrl_inl(addr | (way << 12)); | 31 | unsigned long data = __raw_readl(addr | (way << 12)); |
32 | if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { | 32 | if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { |
33 | data &= ~SH_CACHE_UPDATED; | 33 | data &= ~SH_CACHE_UPDATED; |
34 | ctrl_outl(data, addr | (way << 12)); | 34 | __raw_writel(data, addr | (way << 12)); |
35 | } | 35 | } |
36 | } | 36 | } |
37 | } | 37 | } |
@@ -47,7 +47,7 @@ static void sh2__flush_purge_region(void *start, int size) | |||
47 | & ~(L1_CACHE_BYTES-1); | 47 | & ~(L1_CACHE_BYTES-1); |
48 | 48 | ||
49 | for (v = begin; v < end; v+=L1_CACHE_BYTES) | 49 | for (v = begin; v < end; v+=L1_CACHE_BYTES) |
50 | ctrl_outl((v & CACHE_PHYSADDR_MASK), | 50 | __raw_writel((v & CACHE_PHYSADDR_MASK), |
51 | CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); | 51 | CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); |
52 | } | 52 | } |
53 | 53 | ||
@@ -63,9 +63,9 @@ static void sh2__flush_invalidate_region(void *start, int size) | |||
63 | local_irq_save(flags); | 63 | local_irq_save(flags); |
64 | jump_to_uncached(); | 64 | jump_to_uncached(); |
65 | 65 | ||
66 | ccr = ctrl_inl(CCR); | 66 | ccr = __raw_readl(CCR); |
67 | ccr |= CCR_CACHE_INVALIDATE; | 67 | ccr |= CCR_CACHE_INVALIDATE; |
68 | ctrl_outl(ccr, CCR); | 68 | __raw_writel(ccr, CCR); |
69 | 69 | ||
70 | back_to_cached(); | 70 | back_to_cached(); |
71 | local_irq_restore(flags); | 71 | local_irq_restore(flags); |
@@ -78,7 +78,7 @@ static void sh2__flush_invalidate_region(void *start, int size) | |||
78 | & ~(L1_CACHE_BYTES-1); | 78 | & ~(L1_CACHE_BYTES-1); |
79 | 79 | ||
80 | for (v = begin; v < end; v+=L1_CACHE_BYTES) | 80 | for (v = begin; v < end; v+=L1_CACHE_BYTES) |
81 | ctrl_outl((v & CACHE_PHYSADDR_MASK), | 81 | __raw_writel((v & CACHE_PHYSADDR_MASK), |
82 | CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); | 82 | CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); |
83 | #endif | 83 | #endif |
84 | } | 84 | } |