Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6

* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (43 commits)
  sh: sh775x/titan fixes for irq header changes.
  sh: update r7780rp defconfig.
  sh: compile fixes for header cleanup.
  sh: Fixup pte_mkhuge() build failure.
  sh: set KBUILD_IMAGE to something sensible.
  sh: show held locks in stack trace with lockdep.
  sh: platform_pata support for R7780RP
  sh: stacktrace/lockdep/irqflags tracing support.
  sh: Fixup movli.l/movco.l atomic ops for gcc4.
  sh: dyntick infrastructure.
  sh: Clock framework tidying.
  sh: Turn off IRQs around get_timer_offset() calls.
  sh: Get the PGD right in oops case with 64-bit PTEs.
  sh: Fix store queue bitmap end.
  sh: More flexible + SH7780 earlyprintk SCIF support.
  sh: Fixup various PAGE_SIZE == 4096 assumptions.
  sh: Fixup 4K irq stacks.
  sh: dma-api channel capability extensions.
  sh: Drop name overload in dma-sh.
  sh: Make dma-isa depend on ISA_DMA_API.
  ...

1 files changed, 38 insertions, 31 deletions

diff --git a/arch/sh/mm/cache-sh2.c b/arch/sh/mm/cache-sh2.c
index 2689cb24ea2b..6614033f6be9 100644
--- a/arch/sh/mm/cache-sh2.c
+++ b/arch/sh/mm/cache-sh2.c
@@ -5,6 +5,7 @@
  *
  * Released under the terms of the GNU GPL v2.0.
  */
+
 #include <linux/init.h>
 #include <linux/mm.h>
 
@@ -14,37 +15,43 @@
 #include <asm/cacheflush.h>
 #include <asm/io.h>
 
-/*
- * Calculate the OC address and set the way bit on the SH-2.
- *
- * We must have already jump_to_P2()'ed prior to calling this
- * function, since we rely on CCR manipulation to do the
- * Right Thing(tm).
- */
-unsigned long __get_oc_addr(unsigned long set, unsigned long way)
+void __flush_wback_region(void *start, int size)
 {
-        unsigned long ccr;
-
-        /*
-         * On SH-2 the way bit isn't tracked in the address field
-         * if we're doing address array access .. instead, we need
-         * to manually switch out the way in the CCR.
-         */
-        ccr = ctrl_inl(CCR);
-        ccr &= ~0x00c0;
-        ccr |= way << cpu_data->dcache.way_shift;
-
-        /*
-         * Despite the number of sets being halved, we end up losing
-         * the first 2 ways to OCRAM instead of the last 2 (if we're
-         * 4-way). As a result, forcibly setting the W1 bit handily
-         * bumps us up 2 ways.
-         */
-        if (ccr & CCR_CACHE_ORA)
-                ccr |= 1 << (cpu_data->dcache.way_shift + 1);
-
-        ctrl_outl(ccr, CCR);
-
-        return CACHE_OC_ADDRESS_ARRAY | (set << cpu_data->dcache.entry_shift);
+        unsigned long v;
+        unsigned long begin, end;
+
+        begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
+        end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+                & ~(L1_CACHE_BYTES-1);
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                /* FIXME cache purge */
+                ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008);
+        }
+}
+
+void __flush_purge_region(void *start, int size)
+{
+        unsigned long v;
+        unsigned long begin, end;
+
+        begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
+        end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+                & ~(L1_CACHE_BYTES-1);
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008);
+        }
+}
+
+void __flush_invalidate_region(void *start, int size)
+{
+        unsigned long v;
+        unsigned long begin, end;
+
+        begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
+        end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+                & ~(L1_CACHE_BYTES-1);
+        for (v = begin; v < end; v+=L1_CACHE_BYTES) {
+                ctrl_outl((v & 0x1ffffc00), (v & 0x00000ff0) | 0x00000008);
+        }
 }