diff options
author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-15 13:01:15 -0500 |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-15 13:01:15 -0500 |
commit | f99c6bb6e2e9c35bd3dc0b1d0faa28bd6970930d (patch) | |
tree | 338721c5084d536208a944567c2dface6a38a994 /arch/sh/mm/cache-debugfs.c | |
parent | e0a04cffa4e97e1e53625e40e70895c882e8972f (diff) | |
parent | 9c57548f17806ffd8e4dc4f7973ce78bbfbc2079 (diff) |
Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (35 commits)
sh: rts7751r2d board updates.
sh: Kill off dead bigsur and ec3104 boards.
sh: Fixup r7780rp pata_platform for devres conversion.
sh: Revert TLB miss fast-path changes that broke PTEA parts.
sh: Compile fix for heartbeat consolidation.
sh: heartbeat consolidation for banked LEDs.
sh: define dma noncoherent API functions.
sh: Missing flush_dcache_all() proto in cacheflush.h.
sh: Kill dead/unused ISA code from __ioremap().
sh: Add cpu-features header to asm/Kbuild.
sh: Move __KERNEL__ up in asm/page.h.
sh: Fix syscall numbering breakage.
sh: dcache write-back for R7780RP PIO.
sh: Switch to local TLB flush variants in additional callsites.
sh: Local TLB flushing variants for SMP prep.
sh: Fixup cpu_data references for the non-boot CPUs.
sh: Use a per-cpu ASID cache.
sh: add SH_CLK_MD Kconfig default.
sh: Fixup SHMIN INTC register definitions.
sh: SH-DMAC compile fixes
...
Diffstat (limited to 'arch/sh/mm/cache-debugfs.c')
-rw-r--r-- | arch/sh/mm/cache-debugfs.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c index 909dcfa8c8c6..de6d2c9aa477 100644 --- a/arch/sh/mm/cache-debugfs.c +++ b/arch/sh/mm/cache-debugfs.c | |||
@@ -46,10 +46,10 @@ static int cache_seq_show(struct seq_file *file, void *iter) | |||
46 | 46 | ||
47 | if (cache_type == CACHE_TYPE_DCACHE) { | 47 | if (cache_type == CACHE_TYPE_DCACHE) { |
48 | base = CACHE_OC_ADDRESS_ARRAY; | 48 | base = CACHE_OC_ADDRESS_ARRAY; |
49 | cache = &cpu_data->dcache; | 49 | cache = ¤t_cpu_data.dcache; |
50 | } else { | 50 | } else { |
51 | base = CACHE_IC_ADDRESS_ARRAY; | 51 | base = CACHE_IC_ADDRESS_ARRAY; |
52 | cache = &cpu_data->icache; | 52 | cache = ¤t_cpu_data.icache; |
53 | } | 53 | } |
54 | 54 | ||
55 | /* | 55 | /* |