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authorMagnus Damm <damm@igel.co.jp>2009-06-10 07:31:16 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-06-11 02:14:28 -0400
commitb621370a3505f8bd42acc41736cae47d5ce8bd06 (patch)
treecca005efbb85ba3f77bf5e34f828d22ae67a1439 /arch/sh/kernel
parentc521dc02034df3681394a30b428bf081cfa22253 (diff)
sh: sh7724 clock framework rewrite V3
This patch contains V3 of the sh7724 clock framework rewrite. The new code makes use of the recently merged div4, div6 and mstp32 helper code. Both extal and fll are supported as input clocks to the pll. The div6 clocks are fed through a divide-by-3 block. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel')
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c85
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c242
3 files changed, 248 insertions, 81 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 25b2833f7446..02a0b17347be 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -27,7 +27,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
27clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o 27clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o
28clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
29clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o 29clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7722.o 30clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
31clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o
32clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 32clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
33 33
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index ccefd7dde78c..5e08504da3a6 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -130,11 +130,7 @@ static void adjust_clocks(int originate, int *l, unsigned long v[],
130 * is quite simple.. 130 * is quite simple..
131 */ 131 */
132 132
133#if defined(CONFIG_CPU_SUBTYPE_SH7724)
134#define STCPLL(frqcr) ((((frqcr >> 24) & 0x3f) + 1) * 2)
135#else
136#define STCPLL(frqcr) (((frqcr >> 24) & 0x1f) + 1) 133#define STCPLL(frqcr) (((frqcr >> 24) & 0x1f) + 1)
137#endif
138 134
139/* 135/*
140 * Instead of having two separate multipliers/divisors set, like this: 136 * Instead of having two separate multipliers/divisors set, like this:
@@ -145,11 +141,7 @@ static void adjust_clocks(int originate, int *l, unsigned long v[],
145 * I created the divisors2 array, which is used to calculate rate like 141 * I created the divisors2 array, which is used to calculate rate like
146 * rate = parent * 2 / divisors2[ divisor ]; 142 * rate = parent * 2 / divisors2[ divisor ];
147*/ 143*/
148#if defined(CONFIG_CPU_SUBTYPE_SH7724)
149static int divisors2[] = { 4, 1, 8, 12, 16, 24, 32, 1, 48, 64, 72, 96, 1, 144 };
150#else
151static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 }; 144static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
152#endif
153 145
154static unsigned long master_clk_recalc(struct clk *clk) 146static unsigned long master_clk_recalc(struct clk *clk)
155{ 147{
@@ -171,17 +163,10 @@ static unsigned long module_clk_recalc(struct clk *clk)
171 return clk->parent->rate / STCPLL(frqcr); 163 return clk->parent->rate / STCPLL(frqcr);
172} 164}
173 165
174#if defined(CONFIG_CPU_SUBTYPE_SH7724)
175#define MASTERDIVS { 12, 16, 24, 30, 32, 36, 48 }
176#define STCMASK 0x3f
177#define DIVCALC(div) (div/2-1)
178#define FRQCRKICK 0x80000000
179#else
180#define MASTERDIVS { 2, 3, 4, 6, 8, 16 } 166#define MASTERDIVS { 2, 3, 4, 6, 8, 16 }
181#define STCMASK 0x1f 167#define STCMASK 0x1f
182#define DIVCALC(div) (div-1) 168#define DIVCALC(div) (div-1)
183#define FRQCRKICK 0x00000000 169#define FRQCRKICK 0x00000000
184#endif
185 170
186static int master_clk_setrate(struct clk *clk, unsigned long rate, int id) 171static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
187{ 172{
@@ -557,8 +542,7 @@ static struct clk sh7722_r_clock = {
557 .rate = 32768, 542 .rate = 32768,
558}; 543};
559 544
560#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\ 545#if !defined(CONFIG_CPU_SUBTYPE_SH7343)
561 !defined(CONFIG_CPU_SUBTYPE_SH7724)
562/* 546/*
563 * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops 547 * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
564 * methods of clk_ops determine which register they should access by 548 * methods of clk_ops determine which register they should access by
@@ -575,10 +559,9 @@ static struct clk sh7722_siu_b_clock = {
575 .arch_flags = SCLKBCR, 559 .arch_flags = SCLKBCR,
576 .ops = &sh7722_siu_clk_ops, 560 .ops = &sh7722_siu_clk_ops,
577}; 561};
578#endif /* CONFIG_CPU_SUBTYPE_SH7343, SH7724 */ 562#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
579 563
580#if defined(CONFIG_CPU_SUBTYPE_SH7722) ||\ 564#if defined(CONFIG_CPU_SUBTYPE_SH7722)
581 defined(CONFIG_CPU_SUBTYPE_SH7724)
582static struct clk sh7722_irda_clock = { 565static struct clk sh7722_irda_clock = {
583 .name = "irda_clk", 566 .name = "irda_clk",
584 .arch_flags = IrDACLKCR, 567 .arch_flags = IrDACLKCR,
@@ -676,61 +659,6 @@ static struct clk sh7722_mstpcr_clocks[] = {
676 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT), 659 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
677 MSTPCR("lcdc0", "bus_clk", 2, 0, 0), 660 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
678#endif 661#endif
679#if defined(CONFIG_CPU_SUBTYPE_SH7724)
680 /* See Datasheet : Overview -> Block Diagram */
681 MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
682 MSTPCR("ic0", "cpu_clk", 0, 30, 0),
683 MSTPCR("oc0", "cpu_clk", 0, 29, 0),
684 MSTPCR("rs0", "bus_clk", 0, 28, 0),
685 MSTPCR("ilmem0", "cpu_clk", 0, 27, 0),
686 MSTPCR("l2c0", "sh_clk", 0, 26, 0),
687 MSTPCR("fpu0", "cpu_clk", 0, 24, 0),
688 MSTPCR("intc0", "peripheral_clk", 0, 22, 0),
689 MSTPCR("dmac0", "bus_clk", 0, 21, 0),
690 MSTPCR("sh0", "sh_clk", 0, 20, 0),
691 MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
692 MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
693 MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
694 MSTPCR("cmt0", "r_clk", 0, 14, 0),
695 MSTPCR("rwdt0", "r_clk", 0, 13, 0),
696 MSTPCR("dmac1", "bus_clk", 0, 12, 0),
697 MSTPCR("tmu1", "peripheral_clk", 0, 10, 0),
698 MSTPCR("scif0", "peripheral_clk", 0, 9, 0),
699 MSTPCR("scif1", "peripheral_clk", 0, 8, 0),
700 MSTPCR("scif2", "peripheral_clk", 0, 7, 0),
701 MSTPCR("scif3", "bus_clk", 0, 6, 0),
702 MSTPCR("scif4", "bus_clk", 0, 5, 0),
703 MSTPCR("scif5", "bus_clk", 0, 4, 0),
704 MSTPCR("msiof0", "bus_clk", 0, 2, 0),
705 MSTPCR("msiof1", "bus_clk", 0, 1, 0),
706 MSTPCR("keysc0", "r_clk", 1, 12, 0),
707 MSTPCR("rtc0", "r_clk", 1, 11, 0),
708 MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
709 MSTPCR("i2c1", "peripheral_clk", 1, 8, 0),
710 MSTPCR("mmc0", "bus_clk", 2, 29, 0),
711 MSTPCR("eth0", "bus_clk", 2, 28, 0),
712 MSTPCR("atapi0", "bus_clk", 2, 26, 0),
713 MSTPCR("tpu0", "bus_clk", 2, 25, 0),
714 MSTPCR("irda0", "peripheral_clk", 2, 24, 0),
715 MSTPCR("tsif0", "bus_clk", 2, 22, 0),
716 MSTPCR("usb1", "bus_clk", 2, 21, 0),
717 MSTPCR("usb0", "bus_clk", 2, 20, 0),
718 MSTPCR("2dg0", "bus_clk", 2, 19, 0),
719 MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
720 MSTPCR("sdhi1", "bus_clk", 2, 17, 0),
721 MSTPCR("veu1", "bus_clk", 2, 15, CLK_ENABLE_ON_INIT),
722 MSTPCR("ceu1", "bus_clk", 2, 13, 0),
723 MSTPCR("beu1", "bus_clk", 2, 12, 0),
724 MSTPCR("2ddmac0", "sh_clk", 2, 10, 0),
725 MSTPCR("spu0", "bus_clk", 2, 9, 0),
726 MSTPCR("jpu0", "bus_clk", 2, 6, 0),
727 MSTPCR("vou0", "bus_clk", 2, 5, 0),
728 MSTPCR("beu0", "bus_clk", 2, 4, 0),
729 MSTPCR("ceu0", "bus_clk", 2, 3, 0),
730 MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
731 MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
732 MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
733#endif
734#if defined(CONFIG_CPU_SUBTYPE_SH7343) 662#if defined(CONFIG_CPU_SUBTYPE_SH7343)
735 MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT), 663 MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT),
736 MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT), 664 MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT),
@@ -802,14 +730,11 @@ static struct clk *sh7722_clocks[] = {
802 &sh7722_sh_clock, 730 &sh7722_sh_clock,
803 &sh7722_peripheral_clock, 731 &sh7722_peripheral_clock,
804 &sh7722_sdram_clock, 732 &sh7722_sdram_clock,
805#if !defined(CONFIG_CPU_SUBTYPE_SH7343) &&\ 733#if !defined(CONFIG_CPU_SUBTYPE_SH7343)
806 !defined(CONFIG_CPU_SUBTYPE_SH7724)
807 &sh7722_siu_a_clock, 734 &sh7722_siu_a_clock,
808 &sh7722_siu_b_clock, 735 &sh7722_siu_b_clock,
809#endif 736#endif
810/* 7724 should support FSI clock */ 737#if defined(CONFIG_CPU_SUBTYPE_SH7722)
811#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
812 defined(CONFIG_CPU_SUBTYPE_SH7724)
813 &sh7722_irda_clock, 738 &sh7722_irda_clock,
814#endif 739#endif
815 &sh7722_video_clock, 740 &sh7722_video_clock,
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
new file mode 100644
index 000000000000..5d5c9b952883
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -0,0 +1,242 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
3 *
4 * SH7724 clock framework support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/clock.h>
25
26/* SH7724 registers */
27#define FRQCRA 0xa4150000
28#define FRQCRB 0xa4150004
29#define VCLKCR 0xa4150048
30#define FCLKACR 0xa4150008
31#define FCLKBCR 0xa415000c
32#define IRDACLKCR 0xa4150018
33#define PLLCR 0xa4150024
34#define MSTPCR0 0xa4150030
35#define MSTPCR1 0xa4150034
36#define MSTPCR2 0xa4150038
37#define SPUCLKCR 0xa415003c
38#define FLLFRQ 0xa4150050
39#define LSTATS 0xa4150060
40
41/* Fixed 32 KHz root clock for RTC and Power Management purposes */
42static struct clk r_clk = {
43 .name = "rclk",
44 .id = -1,
45 .rate = 32768,
46};
47
48/*
49 * Default rate for the root input clock, reset this with clk_set_rate()
50 * from the platform code.
51 */
52struct clk extal_clk = {
53 .name = "extal",
54 .id = -1,
55 .rate = 33333333,
56};
57
58/* The fll multiplies the 32khz r_clk, may be used instead of extal */
59static unsigned long fll_recalc(struct clk *clk)
60{
61 unsigned long mult = 0;
62 unsigned long div = 1;
63
64 if (__raw_readl(PLLCR) & 0x1000)
65 mult = __raw_readl(FLLFRQ) & 0x3ff;
66
67 if (__raw_readl(FLLFRQ) & 0x4000)
68 div = 2;
69
70 return (clk->parent->rate * mult) / div;
71}
72
73static struct clk_ops fll_clk_ops = {
74 .recalc = fll_recalc,
75};
76
77static struct clk fll_clk = {
78 .name = "fll_clk",
79 .id = -1,
80 .ops = &fll_clk_ops,
81 .parent = &r_clk,
82 .flags = CLK_ENABLE_ON_INIT,
83};
84
85static unsigned long pll_recalc(struct clk *clk)
86{
87 unsigned long mult = 1;
88
89 if (__raw_readl(PLLCR) & 0x4000)
90 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
91
92 return clk->parent->rate * mult;
93}
94
95static struct clk_ops pll_clk_ops = {
96 .recalc = pll_recalc,
97};
98
99static struct clk pll_clk = {
100 .name = "pll_clk",
101 .id = -1,
102 .ops = &pll_clk_ops,
103 .flags = CLK_ENABLE_ON_INIT,
104};
105
106/* A fixed divide-by-3 block use by the div6 clocks */
107static unsigned long div3_recalc(struct clk *clk)
108{
109 return clk->parent->rate / 3;
110}
111
112static struct clk_ops div3_clk_ops = {
113 .recalc = div3_recalc,
114};
115
116static struct clk div3_clk = {
117 .name = "div3_clk",
118 .id = -1,
119 .ops = &div3_clk_ops,
120 .parent = &pll_clk,
121};
122
123struct clk *main_clks[] = {
124 &r_clk,
125 &extal_clk,
126 &fll_clk,
127 &pll_clk,
128 &div3_clk,
129};
130
131static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
132
133static struct clk_div_mult_table div4_table = {
134 .divisors = divisors,
135 .nr_divisors = ARRAY_SIZE(divisors),
136};
137
138enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
139
140#define DIV4(_str, _reg, _bit, _mask, _flags) \
141 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
142
143struct clk div4_clks[DIV4_NR] = {
144 [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
145 [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
146 [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
147 [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
148 [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0),
149};
150
151struct clk div6_clks[] = {
152 SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0),
153 SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0),
154 SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0),
155 SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0),
156 SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0),
157};
158
159#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \
160 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT)
161
162static struct clk mstp_clks[] = {
163 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0),
164 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0),
165 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0),
166 MSTP("rs0", &div4_clks[DIV4_B], MSTPCR0, 28, 1, 1, 0),
167 MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0),
168 MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 26, 1, 1, 0),
169 MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0),
170 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 1, 1, 0),
171 MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1),
172 MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0),
173 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0),
174 MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0),
175 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0),
176 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0),
177 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0),
178 MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1),
179 MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
180 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0),
181 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0),
182 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0),
183 MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0),
184 MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0),
185 MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0),
186 MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0),
187 MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0),
188
189 MSTP("keysc0", &r_clk, MSTPCR1, 12, 0, 0, 0),
190 MSTP("rtc0", &r_clk, MSTPCR1, 11, 0, 0, 0),
191 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0),
192 MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0, 1, 0),
193
194 MSTP("mmc0", &div4_clks[DIV4_B], MSTPCR2, 29, 0, 1, 0),
195 MSTP("eth0", &div4_clks[DIV4_B], MSTPCR2, 28, 0, 1, 0),
196 MSTP("atapi0", &div4_clks[DIV4_B], MSTPCR2, 26, 0, 1, 0),
197 MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0),
198 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0),
199 MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0),
200 MSTP("usb1", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1),
201 MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 20, 0, 1, 1),
202 MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 19, 0, 1, 1),
203 MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0),
204 MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0),
205 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 15, 1, 1, 1),
206 MSTP("ceu1", &div4_clks[DIV4_B], MSTPCR2, 13, 0, 1, 1),
207 MSTP("beu1", &div4_clks[DIV4_B], MSTPCR2, 12, 0, 1, 1),
208 MSTP("2ddmac0", &div4_clks[DIV4_SH], MSTPCR2, 10, 0, 1, 1),
209 MSTP("spu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0, 1, 0),
210 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1),
211 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1),
212 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1),
213 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1),
214 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1),
215 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1),
216 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1),
217};
218
219int __init arch_clk_init(void)
220{
221 int k, ret = 0;
222
223 /* autodetect extal or fll configuration */
224 if (__raw_readl(PLLCR) & 0x1000)
225 pll_clk.parent = &fll_clk;
226 else
227 pll_clk.parent = &extal_clk;
228
229 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
230 ret = clk_register(main_clks[k]);
231
232 if (!ret)
233 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
234
235 if (!ret)
236 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
237
238 if (!ret)
239 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
240
241 return ret;
242}