diff options
author | Magnus Damm <damm@opensource.se> | 2010-05-11 05:35:55 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2010-05-13 04:36:34 -0400 |
commit | 59aa69d9c20b1ee15fa26aa6631b555aaef91323 (patch) | |
tree | b95b2d6ad2c09ac6fef4d5b25245e27240f22f59 /arch/sh/kernel | |
parent | 8249a3113094b826c5010d27c8cf07a395be2abc (diff) |
sh: switch sh7366 to clkdev
This patch converts the remaining sh7366 clocks
to use clkdev for lookup. The now unused name
and id from struct clk are also removed.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7366.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c index 4c3a5a583012..7ce5bbcd4084 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c | |||
@@ -37,8 +37,6 @@ | |||
37 | 37 | ||
38 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ | 38 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ |
39 | static struct clk r_clk = { | 39 | static struct clk r_clk = { |
40 | .name = "rclk", | ||
41 | .id = -1, | ||
42 | .rate = 32768, | 40 | .rate = 32768, |
43 | }; | 41 | }; |
44 | 42 | ||
@@ -47,8 +45,6 @@ static struct clk r_clk = { | |||
47 | * from the platform code. | 45 | * from the platform code. |
48 | */ | 46 | */ |
49 | struct clk extal_clk = { | 47 | struct clk extal_clk = { |
50 | .name = "extal", | ||
51 | .id = -1, | ||
52 | .rate = 33333333, | 48 | .rate = 33333333, |
53 | }; | 49 | }; |
54 | 50 | ||
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = { | |||
70 | }; | 66 | }; |
71 | 67 | ||
72 | static struct clk dll_clk = { | 68 | static struct clk dll_clk = { |
73 | .name = "dll_clk", | ||
74 | .id = -1, | ||
75 | .ops = &dll_clk_ops, | 69 | .ops = &dll_clk_ops, |
76 | .parent = &r_clk, | 70 | .parent = &r_clk, |
77 | .flags = CLK_ENABLE_ON_INIT, | 71 | .flags = CLK_ENABLE_ON_INIT, |
@@ -95,8 +89,6 @@ static struct clk_ops pll_clk_ops = { | |||
95 | }; | 89 | }; |
96 | 90 | ||
97 | static struct clk pll_clk = { | 91 | static struct clk pll_clk = { |
98 | .name = "pll_clk", | ||
99 | .id = -1, | ||
100 | .ops = &pll_clk_ops, | 92 | .ops = &pll_clk_ops, |
101 | .flags = CLK_ENABLE_ON_INIT, | 93 | .flags = CLK_ENABLE_ON_INIT, |
102 | }; | 94 | }; |
@@ -203,6 +195,12 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
203 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | 195 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
204 | 196 | ||
205 | static struct clk_lookup lookups[] = { | 197 | static struct clk_lookup lookups[] = { |
198 | /* main clocks */ | ||
199 | CLKDEV_CON_ID("rclk", &r_clk), | ||
200 | CLKDEV_CON_ID("extal", &extal_clk), | ||
201 | CLKDEV_CON_ID("dll_clk", &dll_clk), | ||
202 | CLKDEV_CON_ID("pll_clk", &pll_clk), | ||
203 | |||
206 | /* DIV4 clocks */ | 204 | /* DIV4 clocks */ |
207 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | 205 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), |
208 | CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), | 206 | CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), |