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authorMagnus Damm <damm@igel.co.jp>2008-10-31 07:20:23 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-12-22 04:42:51 -0500
commitf2eb0109fb4268505b0737cfe661542eb6151907 (patch)
treec5de0501660694d28550ac2ab46200431b321e17 /arch/sh/kernel
parent6e88d030a1491ec0f130dc4765d06b22f7db6610 (diff)
sh: sh_mobile mstpcr clocks for sh7366
Add sh7366 mstpcr bits and information about their parent clocks. The datasheet is pretty clear about the clocks on this device. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel')
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c40
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 595afc396224..fc69e18ddd63 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -786,6 +786,46 @@ static struct clk sh7722_mstpcr_clocks[] = {
786 MSTPCR("vpu0", "bus_clk", 2, 1), 786 MSTPCR("vpu0", "bus_clk", 2, 1),
787 MSTPCR("lcdc0", "bus_clk", 2, 0), 787 MSTPCR("lcdc0", "bus_clk", 2, 0),
788#endif 788#endif
789#if defined(CONFIG_CPU_SUBTYPE_SH7366)
790 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
791 MSTPCR("tlb0", "cpu_clk", 0, 31),
792 MSTPCR("ic0", "cpu_clk", 0, 30),
793 MSTPCR("oc0", "cpu_clk", 0, 29),
794 MSTPCR("rsmem0", "sh_clk", 0, 28),
795 MSTPCR("xymem0", "cpu_clk", 0, 26),
796 MSTPCR("intc30", "peripheral_clk", 0, 23),
797 MSTPCR("intc0", "peripheral_clk", 0, 22),
798 MSTPCR("dmac0", "bus_clk", 0, 21),
799 MSTPCR("sh0", "sh_clk", 0, 20),
800 MSTPCR("hudi0", "peripheral_clk", 0, 19),
801 MSTPCR("ubc0", "cpu_clk", 0, 17),
802 MSTPCR("tmu0", "peripheral_clk", 0, 15),
803 MSTPCR("cmt0", "r_clk", 0, 14),
804 MSTPCR("rwdt0", "r_clk", 0, 13),
805 MSTPCR("flctl0", "peripheral_clk", 0, 10),
806 MSTPCR("scif0", "peripheral_clk", 0, 7),
807 MSTPCR("scif1", "bus_clk", 0, 6),
808 MSTPCR("scif2", "bus_clk", 0, 5),
809 MSTPCR("msiof0", "peripheral_clk", 0, 2),
810 MSTPCR("sbr0", "peripheral_clk", 0, 1),
811 MSTPCR("i2c0", "peripheral_clk", 1, 9),
812 MSTPCR("icb0", "bus_clk", 2, 27),
813 MSTPCR("meram0", "sh_clk", 2, 26),
814 MSTPCR("dacc0", "peripheral_clk", 2, 24),
815 MSTPCR("dacy0", "peripheral_clk", 2, 23),
816 MSTPCR("tsif0", "bus_clk", 2, 22),
817 MSTPCR("sdhi0", "bus_clk", 2, 18),
818 MSTPCR("mmcif0", "bus_clk", 2, 17),
819 MSTPCR("usb0", "bus_clk", 2, 11),
820 MSTPCR("siu0", "bus_clk", 2, 8),
821 MSTPCR("veu1", "bus_clk", 2, 7),
822 MSTPCR("vou0", "bus_clk", 2, 5),
823 MSTPCR("beu0", "bus_clk", 2, 4),
824 MSTPCR("ceu0", "bus_clk", 2, 3),
825 MSTPCR("veu0", "bus_clk", 2, 2),
826 MSTPCR("vpu0", "bus_clk", 2, 1),
827 MSTPCR("lcdc0", "bus_clk", 2, 0),
828#endif
789}; 829};
790 830
791static struct clk *sh7722_clocks[] = { 831static struct clk *sh7722_clocks[] = {