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authorPaul Mundt <lethal@linux-sh.org>2006-10-20 02:30:55 -0400
committerPaul Mundt <lethal@linux-sh.org>2006-10-20 02:30:55 -0400
commit66a740572d7bcb18469e71cb014bfed3ff75a773 (patch)
tree7815f5352608159123badd7e3e8a4c0bf921ac11 /arch/sh/kernel
parent709bc44c31db4eeeec7dcf7d3f3fefd057adf7fb (diff)
sh: Convert INTC2 to IRQ table registration.
Currently the INTC2 code contains a fixed IRQ table that it iterates through to set the handler type, we move this in to the CPU subtype setup code instead and allow for submitting the table that way. This drops the ST40 tables, as nothing has been happening with those processors, while converting the only existing users to use the new table directly (SH7760 and SH7780). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel')
-rw-r--r--arch/sh/kernel/cpu/irq/intc2.c164
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c63
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7780.c27
3 files changed, 114 insertions, 140 deletions
diff --git a/arch/sh/kernel/cpu/irq/intc2.c b/arch/sh/kernel/cpu/irq/intc2.c
index 212884adca03..74ca576a7ce5 100644
--- a/arch/sh/kernel/cpu/irq/intc2.c
+++ b/arch/sh/kernel/cpu/irq/intc2.c
@@ -11,10 +11,9 @@
11 * Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780. 11 * Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
12 */ 12 */
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/irq.h> 14#include <linux/irq.h>
15#include <linux/io.h>
16#include <asm/system.h> 16#include <asm/system.h>
17#include <asm/io.h>
18 17
19static void disable_intc2_irq(unsigned int irq) 18static void disable_intc2_irq(unsigned int irq)
20{ 19{
@@ -45,151 +44,36 @@ static struct irq_chip intc2_irq_chip = {
45 * PIO1 which is INTPRI00[19,16] and INTMSK00[13] 44 * PIO1 which is INTPRI00[19,16] and INTMSK00[13]
46 * would be: ^ ^ ^ ^ 45 * would be: ^ ^ ^ ^
47 * | | | | 46 * | | | |
48 * make_intc2_irq(84, 0, 16, 0, 13); 47 * { 84, 0, 16, 0, 13 },
48 *
49 * in the intc2_data table.
49 */ 50 */
50void make_intc2_irq(struct intc2_data *p) 51void make_intc2_irq(struct intc2_data *table, unsigned int nr_irqs)
51{ 52{
52 unsigned int flags; 53 int i;
53 unsigned long ipr;
54
55 disable_irq_nosync(p->irq);
56
57 /* Set the priority level */
58 local_irq_save(flags);
59
60 ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
61 ipr &= ~(0xf << p->ipr_shift);
62 ipr |= p->priority << p->ipr_shift;
63 ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
64
65 local_irq_restore(flags);
66 54
67 set_irq_chip_and_handler_name(p->irq, &intc2_irq_chip, 55 for (i = 0; i < nr_irqs; i++) {
68 handle_level_irq, "level"); 56 unsigned long ipr, flags;
69 set_irq_chip_data(p->irq, p); 57 struct intc2_data *p = table + i;
70 58
71 enable_intc2_irq(p->irq); 59 disable_irq_nosync(p->irq);
72}
73 60
74static struct intc2_data intc2_irq_table[] = { 61 /* Set the priority level */
75#if defined(CONFIG_CPU_SUBTYPE_ST40) 62 local_irq_save(flags);
76 {64, 0, 0, 0, 0, 13}, /* PCI serr */
77 {65, 0, 4, 0, 1, 13}, /* PCI err */
78 {66, 0, 4, 0, 2, 13}, /* PCI ad */
79 {67, 0, 4, 0, 3, 13}, /* PCI pwd down */
80 {72, 0, 8, 0, 5, 13}, /* DMAC INT0 */
81 {73, 0, 8, 0, 6, 13}, /* DMAC INT1 */
82 {74, 0, 8, 0, 7, 13}, /* DMAC INT2 */
83 {75, 0, 8, 0, 8, 13}, /* DMAC INT3 */
84 {76, 0, 8, 0, 9, 13}, /* DMAC INT4 */
85 {78, 0, 8, 0, 11, 13}, /* DMAC ERR */
86 {80, 0, 12, 0, 12, 13}, /* PIO0 */
87 {84, 0, 16, 0, 13, 13}, /* PIO1 */
88 {88, 0, 20, 0, 14, 13}, /* PIO2 */
89 {112, 4, 0, 4, 0, 13}, /* Mailbox */
90 #ifdef CONFIG_CPU_SUBTYPE_ST40GX1
91 {116, 4, 4, 4, 4, 13}, /* SSC0 */
92 {120, 4, 8, 4, 8, 13}, /* IR Blaster */
93 {124, 4, 12, 4, 12, 13}, /* USB host */
94 {128, 4, 16, 4, 16, 13}, /* Video processor BLITTER */
95 {132, 4, 20, 4, 20, 13}, /* UART0 */
96 {134, 4, 20, 4, 22, 13}, /* UART2 */
97 {136, 4, 24, 4, 24, 13}, /* IO_PIO0 */
98 {140, 4, 28, 4, 28, 13}, /* EMPI */
99 {144, 8, 0, 8, 0, 13}, /* MAFE */
100 {148, 8, 4, 8, 4, 13}, /* PWM */
101 {152, 8, 8, 8, 8, 13}, /* SSC1 */
102 {156, 8, 12, 8, 12, 13}, /* IO_PIO1 */
103 {160, 8, 16, 8, 16, 13}, /* USB target */
104 {164, 8, 20, 8, 20, 13}, /* UART1 */
105 {168, 8, 24, 8, 24, 13}, /* Teletext */
106 {172, 8, 28, 8, 28, 13}, /* VideoSync VTG */
107 {173, 8, 28, 8, 29, 13}, /* VideoSync DVP0 */
108 {174, 8, 28, 8, 30, 13}, /* VideoSync DVP1 */
109#endif
110#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
111/*
112 * SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0
113 */
114 /* INTPRIO0 | INTMSK0 */
115 {48, 0, 28, 0, 31, 3}, /* IRQ 4 */
116 {49, 0, 24, 0, 30, 3}, /* IRQ 3 */
117 {50, 0, 20, 0, 29, 3}, /* IRQ 2 */
118 {51, 0, 16, 0, 28, 3}, /* IRQ 1 */
119 /* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */
120 /* INTPRIO4 | INTMSK0 */
121 {56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
122 {57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
123 {58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
124 {59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */
125 {60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */
126 {61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
127 {62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
128 {63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
129 /* INTPRIO8 | INTMSK0 */
130 {52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
131 {53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
132 {54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
133 {55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
134 {64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
135 {65, 8, 24, 0, 16, 3}, /* LCDC */
136 /* 66, 67 unused */
137 {68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
138 {69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
139 {70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
140 /* 71 unused */
141 {72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
142 {73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
143 {74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
144 {75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
145 {76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
146 {77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
147 {78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
148 {79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
149 /* | INTMSK4 */
150 {80, 8, 4, 4, 23, 3}, /* SIM_ERI */
151 {81, 8, 4, 4, 22, 3}, /* SIM_RXI */
152 {82, 8, 4, 4, 21, 3}, /* SIM_TXI */
153 {83, 8, 4, 4, 20, 3}, /* SIM_TEI */
154 {84, 8, 0, 4, 19, 3}, /* HSPII */
155 /* INTPRIOC | INTMSK4 */
156 /* 85-87 unused/reserved */
157 {88, 12, 20, 4, 18, 3}, /* MMCI0 */
158 {89, 12, 20, 4, 17, 3}, /* MMCI1 */
159 {90, 12, 20, 4, 16, 3}, /* MMCI2 */
160 {91, 12, 20, 4, 15, 3}, /* MMCI3 */
161 {92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/
162 /* 93-107 reserved/undocumented */
163 {108,12, 4, 4, 1, 3}, /* ADC */
164 {109,12, 0, 4, 0, 3}, /* CMTI */
165 /* 110-111 reserved/unused */
166#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
167 { TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2},
168 { 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
169 { 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
170 { 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
171 { SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
172 { SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
173 { SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
174 { SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
175 63
176 { SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, 64 ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET +
177 { SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, 65 p->ipr_offset);
178 { SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, 66 ipr &= ~(0xf << p->ipr_shift);
179 { SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY }, 67 ipr |= p->priority << p->ipr_shift;
68 ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET +
69 p->ipr_offset);
180 70
181 { PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY }, 71 local_irq_restore(flags);
182 { PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },
183 { PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },
184 { PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },
185 { PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },
186#endif
187};
188 72
189void __init init_IRQ_intc2(void) 73 set_irq_chip_and_handler_name(p->irq, &intc2_irq_chip,
190{ 74 handle_level_irq, "level");
191 int i; 75 set_irq_chip_data(p->irq, p);
192 76
193 for (i = 0; i < ARRAY_SIZE(intc2_irq_table); i++) 77 enable_intc2_irq(p->irq);
194 make_intc2_irq(intc2_irq_table + i); 78 }
195} 79}
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 97f1c9af35d6..07e5377bf550 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -51,3 +51,66 @@ static int __init sh7760_devices_setup(void)
51 ARRAY_SIZE(sh7760_devices)); 51 ARRAY_SIZE(sh7760_devices));
52} 52}
53__initcall(sh7760_devices_setup); 53__initcall(sh7760_devices_setup);
54
55/*
56 * SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0
57 */
58static struct intc2_data intc2_irq_table[] = {
59 /* INTPRIO0 | INTMSK0 */
60 {48, 0, 28, 0, 31, 3}, /* IRQ 4 */
61 {49, 0, 24, 0, 30, 3}, /* IRQ 3 */
62 {50, 0, 20, 0, 29, 3}, /* IRQ 2 */
63 {51, 0, 16, 0, 28, 3}, /* IRQ 1 */
64 /* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */
65 /* INTPRIO4 | INTMSK0 */
66 {56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
67 {57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
68 {58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
69 {59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */
70 {60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */
71 {61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
72 {62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
73 {63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
74 /* INTPRIO8 | INTMSK0 */
75 {52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
76 {53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
77 {54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
78 {55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
79 {64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
80 {65, 8, 24, 0, 16, 3}, /* LCDC */
81 /* 66, 67 unused */
82 {68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
83 {69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
84 {70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
85 /* 71 unused */
86 {72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
87 {73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
88 {74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
89 {75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
90 {76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
91 {77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
92 {78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
93 {79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
94 /* | INTMSK4 */
95 {80, 8, 4, 4, 23, 3}, /* SIM_ERI */
96 {81, 8, 4, 4, 22, 3}, /* SIM_RXI */
97 {82, 8, 4, 4, 21, 3}, /* SIM_TXI */
98 {83, 8, 4, 4, 20, 3}, /* SIM_TEI */
99 {84, 8, 0, 4, 19, 3}, /* HSPII */
100 /* INTPRIOC | INTMSK4 */
101 /* 85-87 unused/reserved */
102 {88, 12, 20, 4, 18, 3}, /* MMCI0 */
103 {89, 12, 20, 4, 17, 3}, /* MMCI1 */
104 {90, 12, 20, 4, 16, 3}, /* MMCI2 */
105 {91, 12, 20, 4, 15, 3}, /* MMCI3 */
106 {92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/
107 /* 93-107 reserved/undocumented */
108 {108,12, 4, 4, 1, 3}, /* ADC */
109 {109,12, 0, 4, 0, 3}, /* CMTI */
110 /* 110-111 reserved/unused */
111};
112
113void __init init_IRQ_intc2(void)
114{
115 make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
116}
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7780.c b/arch/sh/kernel/cpu/sh4/setup-sh7780.c
index 72493f259edc..814ddb226531 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7780.c
@@ -77,3 +77,30 @@ static int __init sh7780_devices_setup(void)
77 ARRAY_SIZE(sh7780_devices)); 77 ARRAY_SIZE(sh7780_devices));
78} 78}
79__initcall(sh7780_devices_setup); 79__initcall(sh7780_devices_setup);
80
81static struct intc2_data intc2_irq_table[] = {
82 { TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2 },
83 { 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
84 { 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
85 { 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
86 { SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
87 { SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
88 { SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
89 { SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
90
91 { SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
92 { SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
93 { SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
94 { SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
95
96 { PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY },
97 { PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },
98 { PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },
99 { PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },
100 { PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },
101};
102
103void __init init_IRQ_intc2(void)
104{
105 make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
106}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 10:47:23 -0500