Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (266 commits)
  sh: Tie sparseirq in to Kconfig.
  sh: Wire up sys_rt_tgsigqueueinfo.
  sh: Fix sys_pwritev() syscall table entry for sh32.
  sh: Fix sh4a llsc-based cmpxchg()
  sh: sh7724: Add JPU support
  sh: sh7724: INTC setting update
  sh: sh7722 clock framework rewrite
  sh: sh7366 clock framework rewrite
  sh: sh7343 clock framework rewrite
  sh: sh7724 clock framework rewrite V3
  sh: sh7723 clock framework rewrite V2
  sh: add enable()/disable()/set_rate() to div6 code
  sh: add AP325RXA mode pin configuration
  sh: add Migo-R mode pin configuration
  sh: sh7722 mode pin definitions
  sh: sh7724 mode pin comments
  sh: sh7723 mode pin V2
  sh: rework mode pin code
  sh: clock div6 helper code
  sh: clock div4 frequency table offset fix
  ...

90 files changed, 9725 insertions, 3361 deletions

diff --git a/arch/sh/kernel/Makefile_32 b/arch/sh/kernel/Makefile_32
index 82a3a150c00d..9411e3e31e68 100644
--- a/arch/sh/kernel/Makefile_32
+++ b/arch/sh/kernel/Makefile_32
@@ -11,10 +11,10 @@ endif
 
 obj-y   := debugtraps.o idle.o io.o io_generic.o irq.o                  \
            machvec.o process_32.o ptrace_32.o setup.o signal_32.o       \
-           sys_sh.o sys_sh32.o syscalls_32.o time_32.o topology.o       \
+           sys_sh.o sys_sh32.o syscalls_32.o time.o topology.o  \
            traps.o traps_32.o
 
-obj-y                           += cpu/ timers/
+obj-y                           += cpu/
 obj-$(CONFIG_VSYSCALL)          += vsyscall/
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_SH_STANDARD_BIOS)  += sh_bios.o
@@ -32,4 +32,6 @@ obj-$(CONFIG_DYNAMIC_FTRACE)	+= ftrace.o
 obj-$(CONFIG_DUMP_CODE)         += disassemble.o
 obj-$(CONFIG_HIBERNATION)       += swsusp.o
 
+obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)     += localtimer.o
+
 EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/Makefile_64 b/arch/sh/kernel/Makefile_64
index fe425d7f6871..67b9f6c6326b 100644
--- a/arch/sh/kernel/Makefile_64
+++ b/arch/sh/kernel/Makefile_64
@@ -2,19 +2,18 @@ extra-y	:= head_64.o init_task.o vmlinux.lds
 
 obj-y   := debugtraps.o idle.o io.o io_generic.o irq.o machvec.o process_64.o \
            ptrace_64.o setup.o signal_64.o sys_sh.o sys_sh64.o \
-           syscalls_64.o time_64.o topology.o traps.o traps_64.o
+           syscalls_64.o time.o topology.o traps.o traps_64.o
 
-obj-y                           += cpu/ timers/
-obj-$(CONFIG_VSYSCALL)          += vsyscall/
+obj-y                           += cpu/
 obj-$(CONFIG_SMP)               += smp.o
-obj-$(CONFIG_SH_STANDARD_BIOS)  += sh_bios.o
 obj-$(CONFIG_SH_CPU_FREQ)       += cpufreq.o
 obj-$(CONFIG_MODULES)           += sh_ksyms_64.o module.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
-obj-$(CONFIG_KEXEC)             += machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
 obj-$(CONFIG_IO_TRAPPED)        += io_trapped.o
 obj-$(CONFIG_GENERIC_GPIO)      += gpio.o
 
+obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)     += localtimer.o
+
 EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index 2600641a483f..eecad7cbd61e 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -17,5 +17,6 @@ obj-$(CONFIG_ARCH_SHMOBILE)	+= shmobile/
 
 obj-$(CONFIG_UBC_WAKEUP)        += ubc.o
 obj-$(CONFIG_SH_ADC)            += adc.o
+obj-$(CONFIG_SH_CLK_CPG)        += clock-cpg.o
 
 obj-y   += irq/ init.o clock.o
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
new file mode 100644
index 000000000000..275942e58e4f
--- /dev/null
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -0,0 +1,256 @@
+#include <linux/clk.h>
+#include <linux/compiler.h>
+#include <linux/bootmem.h>
+#include <linux/io.h>
+#include <asm/clock.h>
+
+static int sh_clk_mstp32_enable(struct clk *clk)
+{
+        __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
+                     clk->enable_reg);
+        return 0;
+}
+
+static void sh_clk_mstp32_disable(struct clk *clk)
+{
+        __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
+                     clk->enable_reg);
+}
+
+static struct clk_ops sh_clk_mstp32_clk_ops = {
+        .enable         = sh_clk_mstp32_enable,
+        .disable        = sh_clk_mstp32_disable,
+        .recalc         = followparent_recalc,
+};
+
+int __init sh_clk_mstp32_register(struct clk *clks, int nr)
+{
+        struct clk *clkp;
+        int ret = 0;
+        int k;
+
+        for (k = 0; !ret && (k < nr); k++) {
+                clkp = clks + k;
+                clkp->ops = &sh_clk_mstp32_clk_ops;
+                ret |= clk_register(clkp);
+        }
+
+        return ret;
+}
+
+static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
+{
+        return clk_rate_table_round(clk, clk->freq_table, rate);
+}
+
+static int sh_clk_div6_divisors[64] = {
+        1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+        17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
+        33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
+        49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
+};
+
+static struct clk_div_mult_table sh_clk_div6_table = {
+        .divisors = sh_clk_div6_divisors,
+        .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
+};
+
+static unsigned long sh_clk_div6_recalc(struct clk *clk)
+{
+        struct clk_div_mult_table *table = &sh_clk_div6_table;
+        unsigned int idx;
+
+        clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
+                             table, NULL);
+
+        idx = __raw_readl(clk->enable_reg) & 0x003f;
+
+        return clk->freq_table[idx].frequency;
+}
+
+static int sh_clk_div6_set_rate(struct clk *clk,
+                                unsigned long rate, int algo_id)
+{
+        unsigned long value;
+        int idx;
+
+        idx = clk_rate_table_find(clk, clk->freq_table, rate);
+        if (idx < 0)
+                return idx;
+
+        value = __raw_readl(clk->enable_reg);
+        value &= ~0x3f;
+        value |= idx;
+        __raw_writel(value, clk->enable_reg);
+        return 0;
+}
+
+static int sh_clk_div6_enable(struct clk *clk)
+{
+        unsigned long value;
+        int ret;
+
+        ret = sh_clk_div6_set_rate(clk, clk->rate, 0);
+        if (ret == 0) {
+                value = __raw_readl(clk->enable_reg);
+                value &= ~0x100; /* clear stop bit to enable clock */
+                __raw_writel(value, clk->enable_reg);
+        }
+        return ret;
+}
+
+static void sh_clk_div6_disable(struct clk *clk)
+{
+        unsigned long value;
+
+        value = __raw_readl(clk->enable_reg);
+        value |= 0x100; /* stop clock */
+        value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
+        __raw_writel(value, clk->enable_reg);
+}
+
+static struct clk_ops sh_clk_div6_clk_ops = {
+        .recalc         = sh_clk_div6_recalc,
+        .round_rate     = sh_clk_div_round_rate,
+        .set_rate       = sh_clk_div6_set_rate,
+        .enable         = sh_clk_div6_enable,
+        .disable        = sh_clk_div6_disable,
+};
+
+int __init sh_clk_div6_register(struct clk *clks, int nr)
+{
+        struct clk *clkp;
+        void *freq_table;
+        int nr_divs = sh_clk_div6_table.nr_divisors;
+        int freq_table_size = sizeof(struct cpufreq_frequency_table);
+        int ret = 0;
+        int k;
+
+        freq_table_size *= (nr_divs + 1);
+
+        freq_table = alloc_bootmem(freq_table_size * nr);
+        if (!freq_table)
+                return -ENOMEM;
+
+        for (k = 0; !ret && (k < nr); k++) {
+                clkp = clks + k;
+
+                clkp->ops = &sh_clk_div6_clk_ops;
+                clkp->id = -1;
+                clkp->freq_table = freq_table + (k * freq_table_size);
+                clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
+
+                ret = clk_register(clkp);
+        }
+
+        return ret;
+}
+
+static unsigned long sh_clk_div4_recalc(struct clk *clk)
+{
+        struct clk_div_mult_table *table = clk->priv;
+        unsigned int idx;
+
+        clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
+                             table, &clk->arch_flags);
+
+        idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
+
+        return clk->freq_table[idx].frequency;
+}
+
+static struct clk_ops sh_clk_div4_clk_ops = {
+        .recalc         = sh_clk_div4_recalc,
+        .round_rate     = sh_clk_div_round_rate,
+};
+
+int __init sh_clk_div4_register(struct clk *clks, int nr,
+                                struct clk_div_mult_table *table)
+{
+        struct clk *clkp;
+        void *freq_table;
+        int nr_divs = table->nr_divisors;
+        int freq_table_size = sizeof(struct cpufreq_frequency_table);
+        int ret = 0;
+        int k;
+
+        freq_table_size *= (nr_divs + 1);
+
+        freq_table = alloc_bootmem(freq_table_size * nr);
+        if (!freq_table)
+                return -ENOMEM;
+
+        for (k = 0; !ret && (k < nr); k++) {
+                clkp = clks + k;
+
+                clkp->ops = &sh_clk_div4_clk_ops;
+                clkp->id = -1;
+                clkp->priv = table;
+
+                clkp->freq_table = freq_table + (k * freq_table_size);
+                clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
+
+                ret = clk_register(clkp);
+        }
+
+        return ret;
+}
+
+#ifdef CONFIG_SH_CLK_CPG_LEGACY
+static struct clk master_clk = {
+        .name           = "master_clk",
+        .flags          = CLK_ENABLE_ON_INIT,
+        .rate           = CONFIG_SH_PCLK_FREQ,
+};
+
+static struct clk peripheral_clk = {
+        .name           = "peripheral_clk",
+        .parent         = &master_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+static struct clk bus_clk = {
+        .name           = "bus_clk",
+        .parent         = &master_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+static struct clk cpu_clk = {
+        .name           = "cpu_clk",
+        .parent         = &master_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+/*
+ * The ordering of these clocks matters, do not change it.
+ */
+static struct clk *onchip_clocks[] = {
+        &master_clk,
+        &peripheral_clk,
+        &bus_clk,
+        &cpu_clk,
+};
+
+int __init __deprecated cpg_clk_init(void)
+{
+        int i, ret = 0;
+
+        for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
+                struct clk *clk = onchip_clocks[i];
+                arch_init_clk_ops(&clk->ops, i);
+                if (clk->ops)
+                        ret |= clk_register(clk);
+        }
+
+        return ret;
+}
+
+/*
+ * Placeholder for compatability, until the lazy CPUs do this
+ * on their own.
+ */
+int __init __weak arch_clk_init(void)
+{
+        return cpg_clk_init();
+}
+#endif /* CONFIG_SH_CPG_CLK_LEGACY */
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 1dc896483b59..f3a46be2ae81 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -1,15 +1,19 @@
 /*
  * arch/sh/kernel/cpu/clock.c - SuperH clock framework
  *
- *  Copyright (C) 2005, 2006, 2007  Paul Mundt
+ *  Copyright (C) 2005 - 2009  Paul Mundt
  *
  * This clock framework is derived from the OMAP version by:
  *
- *      Copyright (C) 2004 - 2005 Nokia Corporation
+ *      Copyright (C) 2004 - 2008 Nokia Corporation
  *      Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  *
  *  Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
  *
+ *  With clkdev bits:
+ *
+ *      Copyright (C) 2008 Russell King.
+ *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
@@ -19,134 +23,159 @@
 #include <linux/module.h>
 #include <linux/mutex.h>
 #include <linux/list.h>
-#include <linux/kref.h>
 #include <linux/kobject.h>
 #include <linux/sysdev.h>
 #include <linux/seq_file.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
-#include <linux/proc_fs.h>
+#include <linux/debugfs.h>
+#include <linux/cpufreq.h>
 #include <asm/clock.h>
-#include <asm/timer.h>
+#include <asm/machvec.h>
 
 static LIST_HEAD(clock_list);
 static DEFINE_SPINLOCK(clock_lock);
 static DEFINE_MUTEX(clock_list_sem);
 
-/*
- * Each subtype is expected to define the init routines for these clocks,
- * as each subtype (or processor family) will have these clocks at the
- * very least. These are all provided through the CPG, which even some of
- * the more quirky parts (such as ST40, SH4-202, etc.) still have.
- *
- * The processor-specific code is expected to register any additional
- * clock sources that are of interest.
- */
-static struct clk master_clk = {
-        .name           = "master_clk",
-        .flags          = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
-        .rate           = CONFIG_SH_PCLK_FREQ,
-};
+void clk_rate_table_build(struct clk *clk,
+                          struct cpufreq_frequency_table *freq_table,
+                          int nr_freqs,
+                          struct clk_div_mult_table *src_table,
+                          unsigned long *bitmap)
+{
+        unsigned long mult, div;
+        unsigned long freq;
+        int i;
 
-static struct clk module_clk = {
-        .name           = "module_clk",
-        .parent         = &master_clk,
-        .flags          = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
-};
+        for (i = 0; i < nr_freqs; i++) {
+                div = 1;
+                mult = 1;
 
-static struct clk bus_clk = {
-        .name           = "bus_clk",
-        .parent         = &master_clk,
-        .flags          = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
-};
+                if (src_table->divisors && i < src_table->nr_divisors)
+                        div = src_table->divisors[i];
 
-static struct clk cpu_clk = {
-        .name           = "cpu_clk",
-        .parent         = &master_clk,
-        .flags          = CLK_ALWAYS_ENABLED,
-};
+                if (src_table->multipliers && i < src_table->nr_multipliers)
+                        mult = src_table->multipliers[i];
 
-/*
- * The ordering of these clocks matters, do not change it.
- */
-static struct clk *onchip_clocks[] = {
-        &master_clk,
-        &module_clk,
-        &bus_clk,
-        &cpu_clk,
-};
+                if (!div || !mult || (bitmap && !test_bit(i, bitmap)))
+                        freq = CPUFREQ_ENTRY_INVALID;
+                else
+                        freq = clk->parent->rate * mult / div;
 
-static void propagate_rate(struct clk *clk)
+                freq_table[i].index = i;
+                freq_table[i].frequency = freq;
+        }
+
+        /* Termination entry */
+        freq_table[i].index = i;
+        freq_table[i].frequency = CPUFREQ_TABLE_END;
+}
+
+long clk_rate_table_round(struct clk *clk,
+                          struct cpufreq_frequency_table *freq_table,
+                          unsigned long rate)
 {
-        struct clk *clkp;
+        unsigned long rate_error, rate_error_prev = ~0UL;
+        unsigned long rate_best_fit = rate;
+        unsigned long highest, lowest;
+        int i;
+
+        highest = lowest = 0;
+
+        for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
+                unsigned long freq = freq_table[i].frequency;
 
-        list_for_each_entry(clkp, &clock_list, node) {
-                if (likely(clkp->parent != clk))
+                if (freq == CPUFREQ_ENTRY_INVALID)
                         continue;
-                if (likely(clkp->ops && clkp->ops->recalc))
-                        clkp->ops->recalc(clkp);
-                if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
-                        propagate_rate(clkp);
+
+                if (freq > highest)
+                        highest = freq;
+                if (freq < lowest)
+                        lowest = freq;
+
+                rate_error = abs(freq - rate);
+                if (rate_error < rate_error_prev) {
+                        rate_best_fit = freq;
+                        rate_error_prev = rate_error;
+                }
+
+                if (rate_error == 0)
+                        break;
         }
+
+        if (rate >= highest)
+                rate_best_fit = highest;
+        if (rate <= lowest)
+                rate_best_fit = lowest;
+
+        return rate_best_fit;
 }
 
-static int __clk_enable(struct clk *clk)
+int clk_rate_table_find(struct clk *clk,
+                        struct cpufreq_frequency_table *freq_table,
+                        unsigned long rate)
 {
-        /*
-         * See if this is the first time we're enabling the clock, some
-         * clocks that are always enabled still require "special"
-         * initialization. This is especially true if the clock mode
-         * changes and the clock needs to hunt for the proper set of
-         * divisors to use before it can effectively recalc.
-         */
-        if (unlikely(atomic_read(&clk->kref.refcount) == 1))
-                if (clk->ops && clk->ops->init)
-                        clk->ops->init(clk);
+        int i;
 
-        kref_get(&clk->kref);
+        for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
+                unsigned long freq = freq_table[i].frequency;
 
-        if (clk->flags & CLK_ALWAYS_ENABLED)
-                return 0;
+                if (freq == CPUFREQ_ENTRY_INVALID)
+                        continue;
 
-        if (likely(clk->ops && clk->ops->enable))
-                clk->ops->enable(clk);
+                if (freq == rate)
+                        return i;
+        }
 
-        return 0;
+        return -ENOENT;
 }
 
-int clk_enable(struct clk *clk)
+/* Used for clocks that always have same value as the parent clock */
+unsigned long followparent_recalc(struct clk *clk)
 {
-        unsigned long flags;
-        int ret;
-
-        if (!clk)
-                return -EINVAL;
+        return clk->parent ? clk->parent->rate : 0;
+}
 
-        clk_enable(clk->parent);
+int clk_reparent(struct clk *child, struct clk *parent)
+{
+        list_del_init(&child->sibling);
+        if (parent)
+                list_add(&child->sibling, &parent->children);
+        child->parent = parent;
 
-        spin_lock_irqsave(&clock_lock, flags);
-        ret = __clk_enable(clk);
-        spin_unlock_irqrestore(&clock_lock, flags);
+        /* now do the debugfs renaming to reattach the child
+           to the proper parent */
 
-        return ret;
+        return 0;
 }
-EXPORT_SYMBOL_GPL(clk_enable);
 
-static void clk_kref_release(struct kref *kref)
+/* Propagate rate to children */
+void propagate_rate(struct clk *tclk)
 {
-        /* Nothing to do */
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &tclk->children, sibling) {
+                if (clkp->ops && clkp->ops->recalc)
+                        clkp->rate = clkp->ops->recalc(clkp);
+
+                propagate_rate(clkp);
+        }
 }
 
 static void __clk_disable(struct clk *clk)
 {
-        int count = kref_put(&clk->kref, clk_kref_release);
-
-        if (clk->flags & CLK_ALWAYS_ENABLED)
+        if (clk->usecount == 0) {
+                printk(KERN_ERR "Trying disable clock %s with 0 usecount\n",
+                       clk->name);
+                WARN_ON(1);
                 return;
+        }
 
-        if (!count) {   /* count reaches zero, disable the clock */
+        if (!(--clk->usecount)) {
                 if (likely(clk->ops && clk->ops->disable))
                         clk->ops->disable(clk);
+                if (likely(clk->parent))
+                        __clk_disable(clk->parent);
         }
 }
 
@@ -160,28 +189,97 @@ void clk_disable(struct clk *clk)
         spin_lock_irqsave(&clock_lock, flags);
         __clk_disable(clk);
         spin_unlock_irqrestore(&clock_lock, flags);
-
-        clk_disable(clk->parent);
 }
 EXPORT_SYMBOL_GPL(clk_disable);
 
+static int __clk_enable(struct clk *clk)
+{
+        int ret = 0;
+
+        if (clk->usecount++ == 0) {
+                if (clk->parent) {
+                        ret = __clk_enable(clk->parent);
+                        if (unlikely(ret))
+                                goto err;
+                }
+
+                if (clk->ops && clk->ops->enable) {
+                        ret = clk->ops->enable(clk);
+                        if (ret) {
+                                if (clk->parent)
+                                        __clk_disable(clk->parent);
+                                goto err;
+                        }
+                }
+        }
+
+        return ret;
+err:
+        clk->usecount--;
+        return ret;
+}
+
+int clk_enable(struct clk *clk)
+{
+        unsigned long flags;
+        int ret;
+
+        if (!clk)
+                return -EINVAL;
+
+        spin_lock_irqsave(&clock_lock, flags);
+        ret = __clk_enable(clk);
+        spin_unlock_irqrestore(&clock_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+static LIST_HEAD(root_clks);
+
+/**
+ * recalculate_root_clocks - recalculate and propagate all root clocks
+ *
+ * Recalculates all root clocks (clocks with no parent), which if the
+ * clock's .recalc is set correctly, should also propagate their rates.
+ * Called at init.
+ */
+void recalculate_root_clocks(void)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &root_clks, sibling) {
+                if (clkp->ops && clkp->ops->recalc)
+                        clkp->rate = clkp->ops->recalc(clkp);
+                propagate_rate(clkp);
+        }
+}
+
 int clk_register(struct clk *clk)
 {
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        /*
+         * trap out already registered clocks
+         */
+        if (clk->node.next || clk->node.prev)
+                return 0;
+
         mutex_lock(&clock_list_sem);
 
-        list_add(&clk->node, &clock_list);
-        kref_init(&clk->kref);
+        INIT_LIST_HEAD(&clk->children);
+        clk->usecount = 0;
 
-        mutex_unlock(&clock_list_sem);
+        if (clk->parent)
+                list_add(&clk->sibling, &clk->parent->children);
+        else
+                list_add(&clk->sibling, &root_clks);
 
-        if (clk->flags & CLK_ALWAYS_ENABLED) {
-                pr_debug( "Clock '%s' is ALWAYS_ENABLED\n", clk->name);
-                if (clk->ops && clk->ops->init)
-                        clk->ops->init(clk);
-                if (clk->ops && clk->ops->enable)
-                        clk->ops->enable(clk);
-                pr_debug( "Enabled.");
-        }
+        list_add(&clk->node, &clock_list);
+        if (clk->ops && clk->ops->init)
+                clk->ops->init(clk);
+        mutex_unlock(&clock_list_sem);
 
         return 0;
 }
@@ -190,11 +288,21 @@ EXPORT_SYMBOL_GPL(clk_register);
 void clk_unregister(struct clk *clk)
 {
         mutex_lock(&clock_list_sem);
+        list_del(&clk->sibling);
         list_del(&clk->node);
         mutex_unlock(&clock_list_sem);
 }
 EXPORT_SYMBOL_GPL(clk_unregister);
 
+static void clk_enable_init_clocks(void)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &clock_list, node)
+                if (clkp->flags & CLK_ENABLE_ON_INIT)
+                        clk_enable(clkp);
+}
+
 unsigned long clk_get_rate(struct clk *clk)
 {
         return clk->rate;
@@ -210,56 +318,59 @@ EXPORT_SYMBOL_GPL(clk_set_rate);
 int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
 {
         int ret = -EOPNOTSUPP;
+        unsigned long flags;
 
-        if (likely(clk->ops && clk->ops->set_rate)) {
-                unsigned long flags;
+        spin_lock_irqsave(&clock_lock, flags);
 
-                spin_lock_irqsave(&clock_lock, flags);
+        if (likely(clk->ops && clk->ops->set_rate)) {
                 ret = clk->ops->set_rate(clk, rate, algo_id);
-                spin_unlock_irqrestore(&clock_lock, flags);
+                if (ret != 0)
+                        goto out_unlock;
+        } else {
+                clk->rate = rate;
+                ret = 0;
         }
 
-        if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
-                propagate_rate(clk);
+        if (clk->ops && clk->ops->recalc)
+                clk->rate = clk->ops->recalc(clk);
 
-        return ret;
-}
-EXPORT_SYMBOL_GPL(clk_set_rate_ex);
+        propagate_rate(clk);
 
-void clk_recalc_rate(struct clk *clk)
-{
-        if (likely(clk->ops && clk->ops->recalc)) {
-                unsigned long flags;
-
-                spin_lock_irqsave(&clock_lock, flags);
-                clk->ops->recalc(clk);
-                spin_unlock_irqrestore(&clock_lock, flags);
-        }
+out_unlock:
+        spin_unlock_irqrestore(&clock_lock, flags);
 
-        if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
-                propagate_rate(clk);
+        return ret;
 }
-EXPORT_SYMBOL_GPL(clk_recalc_rate);
+EXPORT_SYMBOL_GPL(clk_set_rate_ex);
 
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
+        unsigned long flags;
         int ret = -EINVAL;
-        struct clk *old;
 
         if (!parent || !clk)
                 return ret;
+        if (clk->parent == parent)
+                return 0;
 
-        old = clk->parent;
-        if (likely(clk->ops && clk->ops->set_parent)) {
-                unsigned long flags;
-                spin_lock_irqsave(&clock_lock, flags);
-                ret = clk->ops->set_parent(clk, parent);
-                spin_unlock_irqrestore(&clock_lock, flags);
-                clk->parent = (ret ? old : parent);
-        }
+        spin_lock_irqsave(&clock_lock, flags);
+        if (clk->usecount == 0) {
+                if (clk->ops->set_parent)
+                        ret = clk->ops->set_parent(clk, parent);
+                else
+                        ret = clk_reparent(clk, parent);
+
+                if (ret == 0) {
+                        pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
+                                 clk->name, clk->parent->name, clk->rate);
+                        if (clk->ops->recalc)
+                                clk->rate = clk->ops->recalc(clk);
+                        propagate_rate(clk);
+                }
+        } else
+                ret = -EBUSY;
+        spin_unlock_irqrestore(&clock_lock, flags);
 
-        if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
-                propagate_rate(clk);
         return ret;
 }
 EXPORT_SYMBOL_GPL(clk_set_parent);
@@ -287,14 +398,69 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
 EXPORT_SYMBOL_GPL(clk_round_rate);
 
 /*
+ * Find the correct struct clk for the device and connection ID.
+ * We do slightly fuzzy matching here:
+ *  An entry with a NULL ID is assumed to be a wildcard.
+ *  If an entry has a device ID, it must match
+ *  If an entry has a connection ID, it must match
+ * Then we take the most specific entry - with the following
+ * order of precidence: dev+con > dev only > con only.
+ */
+static struct clk *clk_find(const char *dev_id, const char *con_id)
+{
+        struct clk_lookup *p;
+        struct clk *clk = NULL;
+        int match, best = 0;
+
+        list_for_each_entry(p, &clock_list, node) {
+                match = 0;
+                if (p->dev_id) {
+                        if (!dev_id || strcmp(p->dev_id, dev_id))
+                                continue;
+                        match += 2;
+                }
+                if (p->con_id) {
+                        if (!con_id || strcmp(p->con_id, con_id))
+                                continue;
+                        match += 1;
+                }
+                if (match == 0)
+                        continue;
+
+                if (match > best) {
+                        clk = p->clk;
+                        best = match;
+                }
+        }
+        return clk;
+}
+
+struct clk *clk_get_sys(const char *dev_id, const char *con_id)
+{
+        struct clk *clk;
+
+        mutex_lock(&clock_list_sem);
+        clk = clk_find(dev_id, con_id);
+        mutex_unlock(&clock_list_sem);
+
+        return clk ? clk : ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL_GPL(clk_get_sys);
+
+/*
  * Returns a clock. Note that we first try to use device id on the bus
  * and clock name. If this fails, we try to use clock name only.
  */
 struct clk *clk_get(struct device *dev, const char *id)
 {
+        const char *dev_id = dev ? dev_name(dev) : NULL;
         struct clk *p, *clk = ERR_PTR(-ENOENT);
         int idno;
 
+        clk = clk_get_sys(dev_id, id);
+        if (clk && !IS_ERR(clk))
+                return clk;
+
         if (dev == NULL || dev->bus != &platform_bus_type)
                 idno = -1;
         else
@@ -330,36 +496,6 @@ void clk_put(struct clk *clk)
 }
 EXPORT_SYMBOL_GPL(clk_put);
 
-void __init __attribute__ ((weak))
-arch_init_clk_ops(struct clk_ops **ops, int type)
-{
-}
-
-int __init __attribute__ ((weak))
-arch_clk_init(void)
-{
-        return 0;
-}
-
-static int show_clocks(char *buf, char **start, off_t off,
-                       int len, int *eof, void *data)
-{
-        struct clk *clk;
-        char *p = buf;
-
-        list_for_each_entry_reverse(clk, &clock_list, node) {
-                unsigned long rate = clk_get_rate(clk);
-
-                p += sprintf(p, "%-12s\t: %ld.%02ldMHz\t%s\n", clk->name,
-                             rate / 1000000, (rate % 1000000) / 10000,
-                             ((clk->flags & CLK_ALWAYS_ENABLED) ||
-                              (atomic_read(&clk->kref.refcount) != 1)) ?
-                             "enabled" : "disabled");
-        }
-
-        return p - buf;
-}
-
 #ifdef CONFIG_PM
 static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
 {
@@ -369,20 +505,22 @@ static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
         switch (state.event) {
         case PM_EVENT_ON:
                 /* Resumeing from hibernation */
-                if (prev_state.event == PM_EVENT_FREEZE) {
-                        list_for_each_entry(clkp, &clock_list, node)
-                                if (likely(clkp->ops)) {
-                                        unsigned long rate = clkp->rate;
-
-                                        if (likely(clkp->ops->set_parent))
-                                                clkp->ops->set_parent(clkp,
-                                                        clkp->parent);
-                                        if (likely(clkp->ops->set_rate))
-                                                clkp->ops->set_rate(clkp,
-                                                        rate, NO_CHANGE);
-                                        else if (likely(clkp->ops->recalc))
-                                                clkp->ops->recalc(clkp);
-                                        }
+                if (prev_state.event != PM_EVENT_FREEZE)
+                        break;
+
+                list_for_each_entry(clkp, &clock_list, node) {
+                        if (likely(clkp->ops)) {
+                                unsigned long rate = clkp->rate;
+
+                                if (likely(clkp->ops->set_parent))
+                                        clkp->ops->set_parent(clkp,
+                                                clkp->parent);
+                                if (likely(clkp->ops->set_rate))
+                                        clkp->ops->set_rate(clkp,
+                                                rate, NO_CHANGE);
+                                else if (likely(clkp->ops->recalc))
+                                        clkp->rate = clkp->ops->recalc(clkp);
+                        }
                 }
                 break;
         case PM_EVENT_FREEZE:
@@ -426,34 +564,116 @@ subsys_initcall(clk_sysdev_init);
 
 int __init clk_init(void)
 {
-        int i, ret = 0;
-
-        BUG_ON(!master_clk.rate);
-
-        for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
-                struct clk *clk = onchip_clocks[i];
+        int ret;
 
-                arch_init_clk_ops(&clk->ops, i);
-                ret |= clk_register(clk);
+        ret = arch_clk_init();
+        if (unlikely(ret)) {
+                pr_err("%s: CPU clock registration failed.\n", __func__);
+                return ret;
         }
 
-        ret |= arch_clk_init();
+        if (sh_mv.mv_clk_init) {
+                ret = sh_mv.mv_clk_init();
+                if (unlikely(ret)) {
+                        pr_err("%s: machvec clock initialization failed.\n",
+                               __func__);
+                        return ret;
+                }
+        }
 
         /* Kick the child clocks.. */
-        propagate_rate(&master_clk);
-        propagate_rate(&bus_clk);
+        recalculate_root_clocks();
+
+        /* Enable the necessary init clocks */
+        clk_enable_init_clocks();
 
         return ret;
 }
 
-static int __init clk_proc_init(void)
+/*
+ *      debugfs support to trace clock tree hierarchy and attributes
+ */
+static struct dentry *clk_debugfs_root;
+
+static int clk_debugfs_register_one(struct clk *c)
 {
-        struct proc_dir_entry *p;
-        p = create_proc_read_entry("clocks", S_IRUSR, NULL,
-                                   show_clocks, NULL);
-        if (unlikely(!p))
-                return -EINVAL;
+        int err;
+        struct dentry *d, *child;
+        struct clk *pa = c->parent;
+        char s[255];
+        char *p = s;
+
+        p += sprintf(p, "%s", c->name);
+        if (c->id >= 0)
+                sprintf(p, ":%d", c->id);
+        d = debugfs_create_dir(s, pa ? pa->dentry : clk_debugfs_root);
+        if (!d)
+                return -ENOMEM;
+        c->dentry = d;
+
+        d = debugfs_create_u8("usecount", S_IRUGO, c->dentry, (u8 *)&c->usecount);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        d = debugfs_create_u32("rate", S_IRUGO, c->dentry, (u32 *)&c->rate);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        d = debugfs_create_x32("flags", S_IRUGO, c->dentry, (u32 *)&c->flags);
+        if (!d) {
+                err = -ENOMEM;
+                goto err_out;
+        }
+        return 0;
 
+err_out:
+        d = c->dentry;
+        list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
+                debugfs_remove(child);
+        debugfs_remove(c->dentry);
+        return err;
+}
+
+static int clk_debugfs_register(struct clk *c)
+{
+        int err;
+        struct clk *pa = c->parent;
+
+        if (pa && !pa->dentry) {
+                err = clk_debugfs_register(pa);
+                if (err)
+                        return err;
+        }
+
+        if (!c->dentry) {
+                err = clk_debugfs_register_one(c);
+                if (err)
+                        return err;
+        }
+        return 0;
+}
+
+static int __init clk_debugfs_init(void)
+{
+        struct clk *c;
+        struct dentry *d;
+        int err;
+
+        d = debugfs_create_dir("clock", NULL);
+        if (!d)
+                return -ENOMEM;
+        clk_debugfs_root = d;
+
+        list_for_each_entry(c, &clock_list, node) {
+                err = clk_debugfs_register(c);
+                if (err)
+                        goto err_out;
+        }
         return 0;
+err_out:
+        debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */
+        return err;
 }
-subsys_initcall(clk_proc_init);
+late_initcall(clk_debugfs_init);
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index d29e69c156f0..ad85421099cd 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -62,6 +62,11 @@ static void __init speculative_execution_init(void)
 #define speculative_execution_init()    do { } while (0)
 #endif
 
+/* 2nd-level cache init */
+void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void)
+{
+}
+
 /*
  * Generic first-level cache init
  */
@@ -146,6 +151,8 @@ static void __uses_jump_to_uncached cache_init(void)
         flags &= ~CCR_CACHE_ENABLE;
 #endif
 
+        l2_cache_init();
+
         ctrl_outl(flags, CCR);
         back_to_cached();
 }
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c
index 301b505c4278..6b5d191eec3a 100644
--- a/arch/sh/kernel/cpu/irq/imask.c
+++ b/arch/sh/kernel/cpu/irq/imask.c
@@ -18,38 +18,17 @@
 #include <linux/spinlock.h>
 #include <linux/cache.h>
 #include <linux/irq.h>
+#include <linux/bitmap.h>
 #include <asm/system.h>
 #include <asm/irq.h>
 
 /* Bitmap of IRQ masked */
-static unsigned long imask_mask = 0x7fff;
-static int interrupt_priority = 0;
-
-static void enable_imask_irq(unsigned int irq);
-static void disable_imask_irq(unsigned int irq);
-static void shutdown_imask_irq(unsigned int irq);
-static void mask_and_ack_imask(unsigned int);
-static void end_imask_irq(unsigned int irq);
-
 #define IMASK_PRIORITY  15
 
-static unsigned int startup_imask_irq(unsigned int irq)
-{
-        /* Nothing to do */
-        return 0; /* never anything pending */
-}
+static DECLARE_BITMAP(imask_mask, IMASK_PRIORITY);
+static int interrupt_priority;
 
-static struct hw_interrupt_type imask_irq_type = {
-        .typename = "SR.IMASK",
-        .startup = startup_imask_irq,
-        .shutdown = shutdown_imask_irq,
-        .enable = enable_imask_irq,
-        .disable = disable_imask_irq,
-        .ack = mask_and_ack_imask,
-        .end = end_imask_irq
-};
-
-void static inline set_interrupt_registers(int ip)
+static inline void set_interrupt_registers(int ip)
 {
         unsigned long __dummy;
 
@@ -72,42 +51,31 @@ void static inline set_interrupt_registers(int ip)
                      : "t");
 }
 
-static void disable_imask_irq(unsigned int irq)
+static void mask_imask_irq(unsigned int irq)
 {
-        clear_bit(irq, &imask_mask);
+        clear_bit(irq, imask_mask);
         if (interrupt_priority < IMASK_PRIORITY - irq)
                 interrupt_priority = IMASK_PRIORITY - irq;
-
         set_interrupt_registers(interrupt_priority);
 }
 
-static void enable_imask_irq(unsigned int irq)
+static void unmask_imask_irq(unsigned int irq)
 {
-        set_bit(irq, &imask_mask);
-        interrupt_priority = IMASK_PRIORITY - ffz(imask_mask);
-
+        set_bit(irq, imask_mask);
+        interrupt_priority = IMASK_PRIORITY -
+                find_first_zero_bit(imask_mask, IMASK_PRIORITY);
         set_interrupt_registers(interrupt_priority);
 }
 
-static void mask_and_ack_imask(unsigned int irq)
-{
-        disable_imask_irq(irq);
-}
-
-static void end_imask_irq(unsigned int irq)
-{
-        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
-                enable_imask_irq(irq);
-}
-
-static void shutdown_imask_irq(unsigned int irq)
-{
-        /* Nothing to do */
-}
+static struct irq_chip imask_irq_chip = {
+        .typename       = "SR.IMASK",
+        .mask           = mask_imask_irq,
+        .unmask         = unmask_imask_irq,
+        .mask_ack       = mask_imask_irq,
+};
 
 void make_imask_irq(unsigned int irq)
 {
-        disable_irq_nosync(irq);
-        irq_desc[irq].chip = &imask_irq_type;
-        enable_irq(irq);
+        set_irq_chip_and_handler_name(irq, &imask_irq_chip,
+                                      handle_level_irq, "level");
 }
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c
index 726f0335da76..6c092f1f5557 100644
--- a/arch/sh/kernel/cpu/irq/intc-sh5.c
+++ b/arch/sh/kernel/cpu/irq/intc-sh5.c
@@ -84,7 +84,7 @@ static void disable_intc_irq(unsigned int irq);
 static void mask_and_ack_intc(unsigned int);
 static void end_intc_irq(unsigned int irq);
 
-static struct hw_interrupt_type intc_irq_type = {
+static struct irq_chip intc_irq_type = {
         .typename = "INTC",
         .startup = startup_intc_irq,
         .shutdown = shutdown_intc_irq,
@@ -152,43 +152,13 @@ static void end_intc_irq(unsigned int irq)
         enable_intc_irq(irq);
 }
 
-/* For future use, if we ever support IRLM=0) */
-void make_intc_irq(unsigned int irq)
-{
-        disable_irq_nosync(irq);
-        irq_desc[irq].chip = &intc_irq_type;
-        disable_intc_irq(irq);
-}
-
-#if defined(CONFIG_PROC_FS) && defined(CONFIG_SYSCTL)
-static int IRQ_to_vectorN[NR_INTC_IRQS] = {
-        0x12, 0x15, 0x18, 0x1B, 0x40, 0x41, 0x42, 0x43, /*  0- 7 */
-          -1,   -1,   -1,   -1, 0x50, 0x51, 0x52, 0x53, /*  8-15 */
-        0x54, 0x55, 0x32, 0x33, 0x34, 0x35, 0x36,   -1, /* 16-23 */
-          -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1, /* 24-31 */
-        0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x38, /* 32-39 */
-        0x39, 0x3A, 0x3B,   -1,   -1,   -1,   -1,   -1, /* 40-47 */
-          -1,   -1,   -1,   -1,   -1,   -1,   -1,   -1, /* 48-55 */
-          -1,   -1,   -1,   -1,   -1,   -1,   -1, 0x2B, /* 56-63 */
-
-};
-
-int intc_irq_describe(char* p, int irq)
-{
-        if (irq < NR_INTC_IRQS)
-                return sprintf(p, "(0x%3x)", IRQ_to_vectorN[irq]*0x20);
-        else
-                return 0;
-}
-#endif
-
 void __init plat_irq_setup(void)
 {
         unsigned long long __dummy0, __dummy1=~0x00000000100000f0;
         unsigned long reg;
         int i;
 
-        intc_virt = onchip_remap(INTC_BASE, 1024, "INTC");
+        intc_virt = (unsigned long)ioremap_nocache(INTC_BASE, 1024);
         if (!intc_virt) {
                 panic("Unable to remap INTC\n");
         }
@@ -196,7 +166,7 @@ void __init plat_irq_setup(void)
 
         /* Set default: per-line enable/disable, priority driven ack/eoi */
         for (i = 0; i < NR_INTC_IRQS; i++)
-                irq_desc[i].chip = &intc_irq_type;
+                set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
 
 
         /* Disable all interrupts and set all priorities to 0 to avoid trouble */
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 3eb17ee5540e..808d99a48efb 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -21,6 +21,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/interrupt.h>
+#include <linux/topology.h>
 
 static inline struct ipr_desc *get_ipr_desc(unsigned int irq)
 {
@@ -59,10 +60,18 @@ void register_ipr_controller(struct ipr_desc *desc)
 
         for (i = 0; i < desc->nr_irqs; i++) {
                 struct ipr_data *p = desc->ipr_data + i;
+                struct irq_desc *irq_desc;
 
                 BUG_ON(p->ipr_idx >= desc->nr_offsets);
                 BUG_ON(!desc->ipr_offsets[p->ipr_idx]);
 
+                irq_desc = irq_to_desc_alloc_node(p->irq, numa_node_id());
+                if (unlikely(!irq_desc)) {
+                        printk(KERN_INFO "can not get irq_desc for %d\n",
+                               p->irq);
+                        continue;
+                }
+
                 disable_irq_nosync(p->irq);
                 set_irq_chip_and_handler_name(p->irq, &desc->chip,
                                       handle_level_irq, "level");
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index d2c157917999..4fe863170e31 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -38,32 +38,27 @@ static struct clk_ops sh7619_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FREQCR) & 0x0007);
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh7619_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
+        return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
 }
 
 static struct clk_ops sh7619_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
-{
-        clk->rate = clk->parent->rate;
-}
-
 static struct clk_ops sh7619_cpu_clk_ops = {
-        .recalc         = cpu_clk_recalc,
+        .recalc         = followparent_recalc,
 };
 
 static struct clk_ops *sh7619_clk_ops[] = {
@@ -78,4 +73,3 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
         if (idx < ARRAY_SIZE(sh7619_clk_ops))
                 *ops = sh7619_clk_ops[idx];
 }
-
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 0e32d8e448ca..13798733f2db 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -12,6 +12,8 @@
 #include <linux/init.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
+#include <linux/io.h>
 
 enum {
         UNUSED = 0,
@@ -109,9 +111,75 @@ static struct platform_device eth_device = {
         .resource = eth_resources,
 };
 
+static struct sh_timer_config cmt0_platform_data = {
+        .name = "CMT0",
+        .channel_offset = 0x02,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 125,
+        .clocksource_rating = 0, /* disabled due to code generation issues */
+};
+
+static struct resource cmt0_resources[] = {
+        [0] = {
+                .name   = "CMT0",
+                .start  = 0xf84a0072,
+                .end    = 0xf84a0077,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 86,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt0_device = {
+        .name           = "sh_cmt",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &cmt0_platform_data,
+        },
+        .resource       = cmt0_resources,
+        .num_resources  = ARRAY_SIZE(cmt0_resources),
+};
+
+static struct sh_timer_config cmt1_platform_data = {
+        .name = "CMT1",
+        .channel_offset = 0x08,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 125,
+        .clocksource_rating = 0, /* disabled due to code generation issues */
+};
+
+static struct resource cmt1_resources[] = {
+        [0] = {
+                .name   = "CMT1",
+                .start  = 0xf84a0078,
+                .end    = 0xf84a007d,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 87,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt1_device = {
+        .name           = "sh_cmt",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &cmt1_platform_data,
+        },
+        .resource       = cmt1_resources,
+        .num_resources  = ARRAY_SIZE(cmt1_resources),
+};
+
 static struct platform_device *sh7619_devices[] __initdata = {
         &sci_device,
         &eth_device,
+        &cmt0_device,
+        &cmt1_device,
 };
 
 static int __init sh7619_devices_setup(void)
@@ -125,3 +193,19 @@ void __init plat_irq_setup(void)
 {
         register_intc_controller(&intc_desc);
 }
+
+static struct platform_device *sh7619_early_devices[] __initdata = {
+        &cmt0_device,
+        &cmt1_device,
+};
+
+#define STBCR3 0xf80a0000
+
+void __init plat_early_device_setup(void)
+{
+        /* enable CMT clock */
+        __raw_writeb(__raw_readb(STBCR3) & ~0x10, STBCR3);
+
+        early_platform_add_devices(sh7619_early_devices,
+                                   ARRAY_SIZE(sh7619_early_devices));
+}
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index 4a5e59732334..7814c76159a7 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -34,37 +34,37 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12};
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
+        return 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7201_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FREQCR) & 0x0007);
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh7201_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FREQCR) & 0x0007);
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh7201_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007);
-        clk->rate = clk->parent->rate / ifc_divisors[idx];
+        return clk->parent->rate / ifc_divisors[idx];
 }
 
 static struct clk_ops sh7201_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index fb781329848a..940986965102 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -46,33 +46,28 @@ static struct clk_ops sh7203_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FREQCR) & 0x0007);
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh7203_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FREQCR) & 0x0007);
-        clk->rate = clk->parent->rate / pfc_divisors[idx-2];
+        return clk->parent->rate / pfc_divisors[idx-2];
 }
 
 static struct clk_ops sh7203_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
-{
-        clk->rate = clk->parent->rate;
-}
-
 static struct clk_ops sh7203_cpu_clk_ops = {
-        .recalc         = cpu_clk_recalc,
+        .recalc         = followparent_recalc,
 };
 
 static struct clk_ops *sh7203_clk_ops[] = {
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index 82d7f991ef6b..c2268bdeceeb 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -41,29 +41,29 @@ static struct clk_ops sh7206_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FREQCR) & 0x0007);
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh7206_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
+        return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7206_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FREQCR) & 0x0007);
-        clk->rate = clk->parent->rate / ifc_divisors[idx];
+        return clk->parent->rate / ifc_divisors[idx];
 }
 
 static struct clk_ops sh7206_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index 844293723cfc..869c2da4820b 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
 
 enum {
         UNUSED = 0,
@@ -24,7 +25,7 @@ enum {
 
         SCIF0, SCIF1,
 
-        MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5
+        MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5,
         MTU2_TGI3B, MTU2_TGI3C,
 
         /* interrupt groups */
@@ -113,6 +114,99 @@ static struct intc_mask_reg mask_registers[] __initdata = {
 static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
+static struct sh_timer_config mtu2_0_platform_data = {
+        .name = "MTU2_0",
+        .channel_offset = -0x80,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource mtu2_0_resources[] = {
+        [0] = {
+                .name   = "MTU2_0",
+                .start  = 0xff801300,
+                .end    = 0xff801326,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 228,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mtu2_0_device = {
+        .name           = "sh_mtu2",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &mtu2_0_platform_data,
+        },
+        .resource       = mtu2_0_resources,
+        .num_resources  = ARRAY_SIZE(mtu2_0_resources),
+};
+
+static struct sh_timer_config mtu2_1_platform_data = {
+        .name = "MTU2_1",
+        .channel_offset = -0x100,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource mtu2_1_resources[] = {
+        [0] = {
+                .name   = "MTU2_1",
+                .start  = 0xff801380,
+                .end    = 0xff801390,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 234,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mtu2_1_device = {
+        .name           = "sh_mtu2",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &mtu2_1_platform_data,
+        },
+        .resource       = mtu2_1_resources,
+        .num_resources  = ARRAY_SIZE(mtu2_1_resources),
+};
+
+static struct sh_timer_config mtu2_2_platform_data = {
+        .name = "MTU2_2",
+        .channel_offset = 0x80,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource mtu2_2_resources[] = {
+        [0] = {
+                .name   = "MTU2_2",
+                .start  = 0xff801000,
+                .end    = 0xff80100a,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 240,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mtu2_2_device = {
+        .name           = "sh_mtu2",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &mtu2_2_platform_data,
+        },
+        .resource       = mtu2_2_resources,
+        .num_resources  = ARRAY_SIZE(mtu2_2_resources),
+};
+
 static struct plat_sci_port sci_platform_data[] = {
         {
                 .mapbase        = 0xff804000,
@@ -134,6 +228,9 @@ static struct platform_device sci_device = {
 
 static struct platform_device *mxg_devices[] __initdata = {
         &sci_device,
+        &mtu2_0_device,
+        &mtu2_1_device,
+        &mtu2_2_device,
 };
 
 static int __init mxg_devices_setup(void)
@@ -147,3 +244,15 @@ void __init plat_irq_setup(void)
 {
         register_intc_controller(&intc_desc);
 }
+
+static struct platform_device *mxg_early_devices[] __initdata = {
+        &mtu2_0_device,
+        &mtu2_1_device,
+        &mtu2_2_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(mxg_early_devices,
+                                   ARRAY_SIZE(mxg_early_devices));
+}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 00f42f9e3f5c..d8febe128066 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -12,6 +12,8 @@
 #include <linux/init.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
+#include <linux/io.h>
 
 enum {
         UNUSED = 0,
@@ -249,9 +251,105 @@ static struct platform_device rtc_device = {
         .resource       = rtc_resources,
 };
 
+static struct sh_timer_config mtu2_0_platform_data = {
+        .name = "MTU2_0",
+        .channel_offset = -0x80,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource mtu2_0_resources[] = {
+        [0] = {
+                .name   = "MTU2_0",
+                .start  = 0xfffe4300,
+                .end    = 0xfffe4326,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 108,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mtu2_0_device = {
+        .name           = "sh_mtu2",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &mtu2_0_platform_data,
+        },
+        .resource       = mtu2_0_resources,
+        .num_resources  = ARRAY_SIZE(mtu2_0_resources),
+};
+
+static struct sh_timer_config mtu2_1_platform_data = {
+        .name = "MTU2_1",
+        .channel_offset = -0x100,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource mtu2_1_resources[] = {
+        [0] = {
+                .name   = "MTU2_1",
+                .start  = 0xfffe4380,
+                .end    = 0xfffe4390,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 116,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mtu2_1_device = {
+        .name           = "sh_mtu2",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &mtu2_1_platform_data,
+        },
+        .resource       = mtu2_1_resources,
+        .num_resources  = ARRAY_SIZE(mtu2_1_resources),
+};
+
+static struct sh_timer_config mtu2_2_platform_data = {
+        .name = "MTU2_2",
+        .channel_offset = 0x80,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource mtu2_2_resources[] = {
+        [0] = {
+                .name   = "MTU2_2",
+                .start  = 0xfffe4000,
+                .end    = 0xfffe400a,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 124,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mtu2_2_device = {
+        .name           = "sh_mtu2",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &mtu2_2_platform_data,
+        },
+        .resource       = mtu2_2_resources,
+        .num_resources  = ARRAY_SIZE(mtu2_2_resources),
+};
+
 static struct platform_device *sh7201_devices[] __initdata = {
         &sci_device,
         &rtc_device,
+        &mtu2_0_device,
+        &mtu2_1_device,
+        &mtu2_2_device,
 };
 
 static int __init sh7201_devices_setup(void)
@@ -265,3 +363,20 @@ void __init plat_irq_setup(void)
 {
         register_intc_controller(&intc_desc);
 }
+
+static struct platform_device *sh7201_early_devices[] __initdata = {
+        &mtu2_0_device,
+        &mtu2_1_device,
+        &mtu2_2_device,
+};
+
+#define STBCR3 0xfffe0408
+
+void __init plat_early_device_setup(void)
+{
+        /* enable MTU2 clock */
+        __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
+
+        early_platform_add_devices(sh7201_early_devices,
+                                   ARRAY_SIZE(sh7201_early_devices));
+}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index 820dfb2e8656..62e3039d2398 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -11,6 +11,8 @@
 #include <linux/init.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
+#include <linux/io.h>
 
 enum {
         UNUSED = 0,
@@ -205,6 +207,132 @@ static struct platform_device sci_device = {
         },
 };
 
+static struct sh_timer_config cmt0_platform_data = {
+        .name = "CMT0",
+        .channel_offset = 0x02,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 125,
+        .clocksource_rating = 0, /* disabled due to code generation issues */
+};
+
+static struct resource cmt0_resources[] = {
+        [0] = {
+                .name   = "CMT0",
+                .start  = 0xfffec002,
+                .end    = 0xfffec007,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 142,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt0_device = {
+        .name           = "sh_cmt",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &cmt0_platform_data,
+        },
+        .resource       = cmt0_resources,
+        .num_resources  = ARRAY_SIZE(cmt0_resources),
+};
+
+static struct sh_timer_config cmt1_platform_data = {
+        .name = "CMT1",
+        .channel_offset = 0x08,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 125,
+        .clocksource_rating = 0, /* disabled due to code generation issues */
+};
+
+static struct resource cmt1_resources[] = {
+        [0] = {
+                .name   = "CMT1",
+                .start  = 0xfffec008,
+                .end    = 0xfffec00d,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 143,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt1_device = {
+        .name           = "sh_cmt",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &cmt1_platform_data,
+        },
+        .resource       = cmt1_resources,
+        .num_resources  = ARRAY_SIZE(cmt1_resources),
+};
+
+static struct sh_timer_config mtu2_0_platform_data = {
+        .name = "MTU2_0",
+        .channel_offset = -0x80,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource mtu2_0_resources[] = {
+        [0] = {
+                .name   = "MTU2_0",
+                .start  = 0xfffe4300,
+                .end    = 0xfffe4326,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 146,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mtu2_0_device = {
+        .name           = "sh_mtu2",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &mtu2_0_platform_data,
+        },
+        .resource       = mtu2_0_resources,
+        .num_resources  = ARRAY_SIZE(mtu2_0_resources),
+};
+
+static struct sh_timer_config mtu2_1_platform_data = {
+        .name = "MTU2_1",
+        .channel_offset = -0x100,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource mtu2_1_resources[] = {
+        [0] = {
+                .name   = "MTU2_1",
+                .start  = 0xfffe4380,
+                .end    = 0xfffe4390,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 153,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mtu2_1_device = {
+        .name           = "sh_mtu2",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &mtu2_1_platform_data,
+        },
+        .resource       = mtu2_1_resources,
+        .num_resources  = ARRAY_SIZE(mtu2_1_resources),
+};
+
 static struct resource rtc_resources[] = {
         [0] = {
                 .start  = 0xffff2000,
@@ -227,6 +355,10 @@ static struct platform_device rtc_device = {
 
 static struct platform_device *sh7203_devices[] __initdata = {
         &sci_device,
+        &cmt0_device,
+        &cmt1_device,
+        &mtu2_0_device,
+        &mtu2_1_device,
         &rtc_device,
 };
 
@@ -241,3 +373,25 @@ void __init plat_irq_setup(void)
 {
         register_intc_controller(&intc_desc);
 }
+
+static struct platform_device *sh7203_early_devices[] __initdata = {
+        &cmt0_device,
+        &cmt1_device,
+        &mtu2_0_device,
+        &mtu2_1_device,
+};
+
+#define STBCR3 0xfffe0408
+#define STBCR4 0xfffe040c
+
+void __init plat_early_device_setup(void)
+{
+        /* enable CMT clock */
+        __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
+
+        /* enable MTU2 clock */
+        __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
+
+        early_platform_add_devices(sh7203_early_devices,
+                                   ARRAY_SIZE(sh7203_early_devices));
+}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index c46a8355726d..3e6f3d7a58be 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -12,6 +12,8 @@
 #include <linux/init.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
+#include <linux/io.h>
 
 enum {
         UNUSED = 0,
@@ -165,8 +167,170 @@ static struct platform_device sci_device = {
         },
 };
 
+static struct sh_timer_config cmt0_platform_data = {
+        .name = "CMT0",
+        .channel_offset = 0x02,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 125,
+        .clocksource_rating = 0, /* disabled due to code generation issues */
+};
+
+static struct resource cmt0_resources[] = {
+        [0] = {
+                .name   = "CMT0",
+                .start  = 0xfffec002,
+                .end    = 0xfffec007,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 140,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt0_device = {
+        .name           = "sh_cmt",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &cmt0_platform_data,
+        },
+        .resource       = cmt0_resources,
+        .num_resources  = ARRAY_SIZE(cmt0_resources),
+};
+
+static struct sh_timer_config cmt1_platform_data = {
+        .name = "CMT1",
+        .channel_offset = 0x08,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 125,
+        .clocksource_rating = 0, /* disabled due to code generation issues */
+};
+
+static struct resource cmt1_resources[] = {
+        [0] = {
+                .name   = "CMT1",
+                .start  = 0xfffec008,
+                .end    = 0xfffec00d,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 144,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt1_device = {
+        .name           = "sh_cmt",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &cmt1_platform_data,
+        },
+        .resource       = cmt1_resources,
+        .num_resources  = ARRAY_SIZE(cmt1_resources),
+};
+
+static struct sh_timer_config mtu2_0_platform_data = {
+        .name = "MTU2_0",
+        .channel_offset = -0x80,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource mtu2_0_resources[] = {
+        [0] = {
+                .name   = "MTU2_0",
+                .start  = 0xfffe4300,
+                .end    = 0xfffe4326,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 156,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mtu2_0_device = {
+        .name           = "sh_mtu2",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &mtu2_0_platform_data,
+        },
+        .resource       = mtu2_0_resources,
+        .num_resources  = ARRAY_SIZE(mtu2_0_resources),
+};
+
+static struct sh_timer_config mtu2_1_platform_data = {
+        .name = "MTU2_1",
+        .channel_offset = -0x100,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource mtu2_1_resources[] = {
+        [0] = {
+                .name   = "MTU2_1",
+                .start  = 0xfffe4380,
+                .end    = 0xfffe4390,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 164,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mtu2_1_device = {
+        .name           = "sh_mtu2",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &mtu2_1_platform_data,
+        },
+        .resource       = mtu2_1_resources,
+        .num_resources  = ARRAY_SIZE(mtu2_1_resources),
+};
+
+static struct sh_timer_config mtu2_2_platform_data = {
+        .name = "MTU2_2",
+        .channel_offset = 0x80,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource mtu2_2_resources[] = {
+        [0] = {
+                .name   = "MTU2_2",
+                .start  = 0xfffe4000,
+                .end    = 0xfffe400a,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 180,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mtu2_2_device = {
+        .name           = "sh_mtu2",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &mtu2_2_platform_data,
+        },
+        .resource       = mtu2_2_resources,
+        .num_resources  = ARRAY_SIZE(mtu2_2_resources),
+};
+
 static struct platform_device *sh7206_devices[] __initdata = {
         &sci_device,
+        &cmt0_device,
+        &cmt1_device,
+        &mtu2_0_device,
+        &mtu2_1_device,
+        &mtu2_2_device,
 };
 
 static int __init sh7206_devices_setup(void)
@@ -180,3 +344,26 @@ void __init plat_irq_setup(void)
 {
         register_intc_controller(&intc_desc);
 }
+
+static struct platform_device *sh7206_early_devices[] __initdata = {
+        &cmt0_device,
+        &cmt1_device,
+        &mtu2_0_device,
+        &mtu2_1_device,
+        &mtu2_2_device,
+};
+
+#define STBCR3 0xfffe0408
+#define STBCR4 0xfffe040c
+
+void __init plat_early_device_setup(void)
+{
+        /* enable CMT clock */
+        __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
+
+        /* enable MTU2 clock */
+        __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
+
+        early_platform_add_devices(sh7206_early_devices,
+                                   ARRAY_SIZE(sh7206_early_devices));
+}
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh3.c b/arch/sh/kernel/cpu/sh3/clock-sh3.c
index c3c945958baf..27b8738f0b09 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh3.c
@@ -38,36 +38,36 @@ static struct clk_ops sh3_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int frqcr = ctrl_inw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh3_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int frqcr = ctrl_inw(FRQCR);
         int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
 
-        clk->rate = clk->parent->rate / stc_multipliers[idx];
+        return clk->parent->rate / stc_multipliers[idx];
 }
 
 static struct clk_ops sh3_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int frqcr = ctrl_inw(FRQCR);
         int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
 
-        clk->rate = clk->parent->rate / ifc_divisors[idx];
+        return clk->parent->rate / ifc_divisors[idx];
 }
 
 static struct clk_ops sh3_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7705.c b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
index dfdbf3277fd7..0ca8f2c3646c 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
@@ -39,30 +39,30 @@ static struct clk_ops sh7705_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int idx = ctrl_inw(FRQCR) & 0x0003;
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh7705_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8;
-        clk->rate = clk->parent->rate / stc_multipliers[idx];
+        return clk->parent->rate / stc_multipliers[idx];
 }
 
 static struct clk_ops sh7705_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4;
-        clk->rate = clk->parent->rate / ifc_divisors[idx];
+        return clk->parent->rate / ifc_divisors[idx];
 }
 
 static struct clk_ops sh7705_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7706.c b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
index 0cf96f9833bc..4bf7887d310a 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7706.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
@@ -34,36 +34,36 @@ static struct clk_ops sh7706_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int frqcr = ctrl_inw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh7706_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int frqcr = ctrl_inw(FRQCR);
         int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
 
-        clk->rate = clk->parent->rate / stc_multipliers[idx];
+        return clk->parent->rate / stc_multipliers[idx];
 }
 
 static struct clk_ops sh7706_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int frqcr = ctrl_inw(FRQCR);
         int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
 
-        clk->rate = clk->parent->rate / ifc_divisors[idx];
+        return clk->parent->rate / ifc_divisors[idx];
 }
 
 static struct clk_ops sh7706_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7709.c b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
index b791a29fdb62..fa30b6017730 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
@@ -41,12 +41,12 @@ static struct clk_ops sh7709_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int frqcr = ctrl_inw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh7709_module_clk_ops = {
@@ -56,25 +56,25 @@ static struct clk_ops sh7709_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int frqcr = ctrl_inw(FRQCR);
         int idx = (frqcr & 0x0080) ?
                 ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1;
 
-        clk->rate = clk->parent->rate * stc_multipliers[idx];
+        return clk->parent->rate * stc_multipliers[idx];
 }
 
 static struct clk_ops sh7709_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int frqcr = ctrl_inw(FRQCR);
         int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
 
-        clk->rate = clk->parent->rate / ifc_divisors[idx];
+        return clk->parent->rate / ifc_divisors[idx];
 }
 
 static struct clk_ops sh7709_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7710.c b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
index 4744c50ec449..030a58ba18a5 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
@@ -33,30 +33,30 @@ static struct clk_ops sh7710_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FRQCR) & 0x0007);
-        clk->rate = clk->parent->rate / md_table[idx];
+        return clk->parent->rate / md_table[idx];
 }
 
 static struct clk_ops sh7710_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FRQCR) & 0x0700) >> 8;
-        clk->rate = clk->parent->rate / md_table[idx];
+        return clk->parent->rate / md_table[idx];
 }
 
 static struct clk_ops sh7710_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FRQCR) & 0x0070) >> 4;
-        clk->rate = clk->parent->rate / md_table[idx];
+        return clk->parent->rate / md_table[idx];
 }
 
 static struct clk_ops sh7710_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7712.c b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
index 54f54df51ef0..6428ee6c77ed 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7712.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
@@ -33,24 +33,24 @@ static struct clk_ops sh7712_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int frqcr = ctrl_inw(FRQCR);
         int idx = frqcr & 0x0007;
 
-        clk->rate = clk->parent->rate / divisors[idx];
+        return clk->parent->rate / divisors[idx];
 }
 
 static struct clk_ops sh7712_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int frqcr = ctrl_inw(FRQCR);
         int idx = (frqcr & 0x0030) >> 4;
 
-        clk->rate = clk->parent->rate / divisors[idx];
+        return clk->parent->rate / divisors[idx];
 }
 
 static struct clk_ops sh7712_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 63b67badd67e..88f742fed9ed 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -13,6 +13,7 @@
 #include <linux/irq.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
 #include <asm/rtc.h>
 
 enum {
@@ -116,7 +117,102 @@ static struct platform_device rtc_device = {
         },
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x02,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xfffffe94,
+                .end    = 0xfffffe9f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0xe,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xfffffea0,
+                .end    = 0xfffffeab,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1a,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xfffffeac,
+                .end    = 0xfffffebb,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
 static struct platform_device *sh7705_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
         &sci_device,
         &rtc_device,
 };
@@ -128,6 +224,18 @@ static int __init sh7705_devices_setup(void)
 }
 __initcall(sh7705_devices_setup);
 
+static struct platform_device *sh7705_early_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7705_early_devices,
+                                   ARRAY_SIZE(sh7705_early_devices));
+}
+
 void __init plat_irq_setup(void)
 {
         register_intc_controller(&intc_desc);
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index a74f960b5e79..c56306798584 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
 
 enum {
         UNUSED = 0,
@@ -144,7 +145,102 @@ static struct platform_device sci_device = {
         },
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x02,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xfffffe94,
+                .end    = 0xfffffe9f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0xe,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xfffffea0,
+                .end    = 0xfffffeab,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1a,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xfffffeac,
+                .end    = 0xfffffebb,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
 static struct platform_device *sh770x_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
         &sci_device,
         &rtc_device,
 };
@@ -156,6 +252,18 @@ static int __init sh770x_devices_setup(void)
 }
 __initcall(sh770x_devices_setup);
 
+static struct platform_device *sh770x_early_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh770x_early_devices,
+                                   ARRAY_SIZE(sh770x_early_devices));
+}
+
 void __init plat_irq_setup(void)
 {
         register_intc_controller(&intc_desc);
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 335098b66e2f..efa76c8148f4 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -13,6 +13,7 @@
 #include <linux/irq.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
 #include <asm/rtc.h>
 
 enum {
@@ -120,7 +121,102 @@ static struct platform_device sci_device = {
         },
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x02,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xa412fe94,
+                .end    = 0xa412fe9f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0xe,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xa412fea0,
+                .end    = 0xa412feab,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1a,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xa412feac,
+                .end    = 0xa412feb5,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
 static struct platform_device *sh7710_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
         &sci_device,
         &rtc_device,
 };
@@ -132,6 +228,18 @@ static int __init sh7710_devices_setup(void)
 }
 __initcall(sh7710_devices_setup);
 
+static struct platform_device *sh7710_early_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7710_early_devices,
+                                   ARRAY_SIZE(sh7710_early_devices));
+}
+
 void __init plat_irq_setup(void)
 {
         register_intc_controller(&intc_desc);
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 003874a2fd2a..5b2107798edb 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -18,6 +18,7 @@
 #include <linux/serial.h>
 #include <linux/io.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
 #include <asm/rtc.h>
 
 static struct resource rtc_resources[] = {
@@ -123,7 +124,259 @@ static struct platform_device usbf_device = {
         .resource       = usbf_resources,
 };
 
+static struct sh_timer_config cmt0_platform_data = {
+        .name = "CMT0",
+        .channel_offset = 0x10,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 125,
+        .clocksource_rating = 125,
+};
+
+static struct resource cmt0_resources[] = {
+        [0] = {
+                .name   = "CMT0",
+                .start  = 0x044a0010,
+                .end    = 0x044a001b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 104,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt0_device = {
+        .name           = "sh_cmt",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &cmt0_platform_data,
+        },
+        .resource       = cmt0_resources,
+        .num_resources  = ARRAY_SIZE(cmt0_resources),
+};
+
+static struct sh_timer_config cmt1_platform_data = {
+        .name = "CMT1",
+        .channel_offset = 0x20,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+};
+
+static struct resource cmt1_resources[] = {
+        [0] = {
+                .name   = "CMT1",
+                .start  = 0x044a0020,
+                .end    = 0x044a002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 104,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt1_device = {
+        .name           = "sh_cmt",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &cmt1_platform_data,
+        },
+        .resource       = cmt1_resources,
+        .num_resources  = ARRAY_SIZE(cmt1_resources),
+};
+
+static struct sh_timer_config cmt2_platform_data = {
+        .name = "CMT2",
+        .channel_offset = 0x30,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource cmt2_resources[] = {
+        [0] = {
+                .name   = "CMT2",
+                .start  = 0x044a0030,
+                .end    = 0x044a003b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 104,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt2_device = {
+        .name           = "sh_cmt",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &cmt2_platform_data,
+        },
+        .resource       = cmt2_resources,
+        .num_resources  = ARRAY_SIZE(cmt2_resources),
+};
+
+static struct sh_timer_config cmt3_platform_data = {
+        .name = "CMT3",
+        .channel_offset = 0x40,
+        .timer_bit = 3,
+        .clk = "peripheral_clk",
+};
+
+static struct resource cmt3_resources[] = {
+        [0] = {
+                .name   = "CMT3",
+                .start  = 0x044a0040,
+                .end    = 0x044a004b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 104,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt3_device = {
+        .name           = "sh_cmt",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &cmt3_platform_data,
+        },
+        .resource       = cmt3_resources,
+        .num_resources  = ARRAY_SIZE(cmt3_resources),
+};
+
+static struct sh_timer_config cmt4_platform_data = {
+        .name = "CMT4",
+        .channel_offset = 0x50,
+        .timer_bit = 4,
+        .clk = "peripheral_clk",
+};
+
+static struct resource cmt4_resources[] = {
+        [0] = {
+                .name   = "CMT4",
+                .start  = 0x044a0050,
+                .end    = 0x044a005b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 104,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt4_device = {
+        .name           = "sh_cmt",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &cmt4_platform_data,
+        },
+        .resource       = cmt4_resources,
+        .num_resources  = ARRAY_SIZE(cmt4_resources),
+};
+
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x02,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xa412fe94,
+                .end    = 0xa412fe9f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0xe,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xa412fea0,
+                .end    = 0xa412feab,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1a,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xa412feac,
+                .end    = 0xa412feb5,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
 static struct platform_device *sh7720_devices[] __initdata = {
+        &cmt0_device,
+        &cmt1_device,
+        &cmt2_device,
+        &cmt3_device,
+        &cmt4_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
         &rtc_device,
         &sci_device,
         &usb_ohci_device,
@@ -137,6 +390,23 @@ static int __init sh7720_devices_setup(void)
 }
 __initcall(sh7720_devices_setup);
 
+static struct platform_device *sh7720_early_devices[] __initdata = {
+        &cmt0_device,
+        &cmt1_device,
+        &cmt2_device,
+        &cmt3_device,
+        &cmt4_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7720_early_devices,
+                                   ARRAY_SIZE(sh7720_early_devices));
+}
+
 enum {
         UNUSED = 0,
 
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index a33429463e96..21421e34e7d5 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -21,10 +21,10 @@
 static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 };
 static int frqcr3_values[]   = { 0, 1, 2, 3, 4, 5, 6  };
 
-static void emi_clk_recalc(struct clk *clk)
+static unsigned long emi_clk_recalc(struct clk *clk)
 {
         int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007;
-        clk->rate = clk->parent->rate / frqcr3_divisors[idx];
+        return clk->parent->rate / frqcr3_divisors[idx];
 }
 
 static inline int frqcr3_lookup(struct clk *clk, unsigned long rate)
@@ -46,14 +46,14 @@ static struct clk_ops sh4202_emi_clk_ops = {
 
 static struct clk sh4202_emi_clk = {
         .name           = "emi_clk",
-        .flags          = CLK_ALWAYS_ENABLED,
+        .flags          = CLK_ENABLE_ON_INIT,
         .ops            = &sh4202_emi_clk_ops,
 };
 
-static void femi_clk_recalc(struct clk *clk)
+static unsigned long femi_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007;
-        clk->rate = clk->parent->rate / frqcr3_divisors[idx];
+        return clk->parent->rate / frqcr3_divisors[idx];
 }
 
 static struct clk_ops sh4202_femi_clk_ops = {
@@ -62,7 +62,7 @@ static struct clk_ops sh4202_femi_clk_ops = {
 
 static struct clk sh4202_femi_clk = {
         .name           = "femi_clk",
-        .flags          = CLK_ALWAYS_ENABLED,
+        .flags          = CLK_ENABLE_ON_INIT,
         .ops            = &sh4202_femi_clk_ops,
 };
 
@@ -90,10 +90,10 @@ static void shoc_clk_init(struct clk *clk)
         WARN_ON(i == ARRAY_SIZE(frqcr3_divisors));      /* Undefined clock */
 }
 
-static void shoc_clk_recalc(struct clk *clk)
+static unsigned long shoc_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007;
-        clk->rate = clk->parent->rate / frqcr3_divisors[idx];
+        return clk->parent->rate / frqcr3_divisors[idx];
 }
 
 static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
@@ -140,7 +140,7 @@ static struct clk_ops sh4202_shoc_clk_ops = {
 
 static struct clk sh4202_shoc_clk = {
         .name           = "shoc_clk",
-        .flags          = CLK_ALWAYS_ENABLED,
+        .flags          = CLK_ENABLE_ON_INIT,
         .ops            = &sh4202_shoc_clk_ops,
 };
 
@@ -150,31 +150,22 @@ static struct clk *sh4202_onchip_clocks[] = {
         &sh4202_shoc_clk,
 };
 
-static int __init sh4202_clk_init(void)
+int __init arch_clk_init(void)
 {
-        struct clk *clk = clk_get(NULL, "master_clk");
-        int i;
+        struct clk *clk;
+        int i, ret = 0;
+
+        cpg_clk_init();
 
+        clk = clk_get(NULL, "master_clk");
         for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) {
                 struct clk *clkp = sh4202_onchip_clocks[i];
 
                 clkp->parent = clk;
-                clk_register(clkp);
-                clk_enable(clkp);
+                ret |= clk_register(clkp);
         }
 
-        /*
-         * Now that we have the rest of the clocks registered, we need to
-         * force the parent clock to propagate so that these clocks will
-         * automatically figure out their rate. We cheat by handing the
-         * parent clock its current rate and forcing child propagation.
-         */
-        clk_set_rate(clk, clk_get_rate(clk));
-
         clk_put(clk);
 
-        return 0;
+        return ret;
 }
-
-arch_initcall(sh4202_clk_init);
-
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4.c b/arch/sh/kernel/cpu/sh4/clock-sh4.c
index dca9f87a12d6..73294d9cd049 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4.c
@@ -35,30 +35,30 @@ static struct clk_ops sh4_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FRQCR) & 0x0007);
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh4_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FRQCR) >> 3) & 0x0007;
-        clk->rate = clk->parent->rate / bfc_divisors[idx];
+        return clk->parent->rate / bfc_divisors[idx];
 }
 
 static struct clk_ops sh4_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(FRQCR) >> 6) & 0x0007;
-        clk->rate = clk->parent->rate / ifc_divisors[idx];
+        return clk->parent->rate / ifc_divisors[idx];
 }
 
 static struct clk_ops sh4_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 91e3677ae09d..6c78d0a9c857 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -60,12 +60,18 @@ int __init detect_cpu_and_cache_system(void)
                 if ((cvr & 0x10000000) == 0)
                         boot_cpu_data.flags |= CPU_HAS_DSP;
 
-                boot_cpu_data.flags |= CPU_HAS_LLSC;
+                boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER;
                 boot_cpu_data.cut_major = pvr & 0x7f;
+
+                boot_cpu_data.icache.ways = 4;
+                boot_cpu_data.dcache.ways = 4;
+        } else {
+                /* And some SH-4 defaults.. */
+                boot_cpu_data.flags |= CPU_HAS_PTEA;
         }
 
         /* FPU detection works for everyone */
-        if ((cvr & 0x20000000) == 1)
+        if ((cvr & 0x20000000))
                 boot_cpu_data.flags |= CPU_HAS_FPU;
 
         /* Mask off the upper chip ID */
@@ -78,25 +84,20 @@ int __init detect_cpu_and_cache_system(void)
         switch (pvr) {
         case 0x205:
                 boot_cpu_data.type = CPU_SH7750;
-                boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
-                                   CPU_HAS_PERF_COUNTER;
+                boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
+                                       CPU_HAS_PERF_COUNTER;
                 break;
         case 0x206:
                 boot_cpu_data.type = CPU_SH7750S;
-                boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
-                                   CPU_HAS_PERF_COUNTER;
+                boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
+                                       CPU_HAS_PERF_COUNTER;
                 break;
         case 0x1100:
                 boot_cpu_data.type = CPU_SH7751;
-                boot_cpu_data.flags |= CPU_HAS_FPU;
                 break;
         case 0x2001:
         case 0x2004:
                 boot_cpu_data.type = CPU_SH7770;
-                boot_cpu_data.icache.ways = 4;
-                boot_cpu_data.dcache.ways = 4;
-
-                boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
                 break;
         case 0x2006:
         case 0x200A:
@@ -107,45 +108,26 @@ int __init detect_cpu_and_cache_system(void)
                 else
                         boot_cpu_data.type = CPU_SH7780;
 
-                boot_cpu_data.icache.ways = 4;
-                boot_cpu_data.dcache.ways = 4;
-
-                boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
-                                   CPU_HAS_LLSC;
                 break;
         case 0x3000:
         case 0x3003:
         case 0x3009:
                 boot_cpu_data.type = CPU_SH7343;
-                boot_cpu_data.icache.ways = 4;
-                boot_cpu_data.dcache.ways = 4;
-                boot_cpu_data.flags |= CPU_HAS_LLSC;
                 break;
         case 0x3004:
         case 0x3007:
                 boot_cpu_data.type = CPU_SH7785;
-                boot_cpu_data.icache.ways = 4;
-                boot_cpu_data.dcache.ways = 4;
-                boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
-                                          CPU_HAS_LLSC;
                 break;
         case 0x4004:
                 boot_cpu_data.type = CPU_SH7786;
-                boot_cpu_data.icache.ways = 4;
-                boot_cpu_data.dcache.ways = 4;
-                boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
-                        CPU_HAS_LLSC | CPU_HAS_PTEAEX;
+                boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
                 break;
         case 0x3008:
-                boot_cpu_data.icache.ways = 4;
-                boot_cpu_data.dcache.ways = 4;
-                boot_cpu_data.flags |= CPU_HAS_LLSC;
-
                 switch (prr) {
                 case 0x50:
                 case 0x51:
                         boot_cpu_data.type = CPU_SH7723;
-                        boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE;
+                        boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
                         break;
                 case 0x70:
                         boot_cpu_data.type = CPU_SH7366;
@@ -156,13 +138,13 @@ int __init detect_cpu_and_cache_system(void)
                         break;
                 }
                 break;
+        case 0x300b:
+                boot_cpu_data.type = CPU_SH7724;
+                boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
+                break;
         case 0x4000:    /* 1st cut */
         case 0x4001:    /* 2nd cut */
                 boot_cpu_data.type = CPU_SHX3;
-                boot_cpu_data.icache.ways = 4;
-                boot_cpu_data.dcache.ways = 4;
-                boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
-                                          CPU_HAS_LLSC;
                 break;
         case 0x700:
                 boot_cpu_data.type = CPU_SH4_501;
@@ -173,7 +155,6 @@ int __init detect_cpu_and_cache_system(void)
                 boot_cpu_data.type = CPU_SH4_202;
                 boot_cpu_data.icache.ways = 2;
                 boot_cpu_data.dcache.ways = 2;
-                boot_cpu_data.flags |= CPU_HAS_FPU;
                 break;
         case 0x500 ... 0x501:
                 switch (prr) {
@@ -191,18 +172,12 @@ int __init detect_cpu_and_cache_system(void)
                 boot_cpu_data.icache.ways = 2;
                 boot_cpu_data.dcache.ways = 2;
 
-                boot_cpu_data.flags |= CPU_HAS_FPU;
-
                 break;
         default:
                 boot_cpu_data.type = CPU_SH_NONE;
                 break;
         }
 
-#ifdef CONFIG_CPU_HAS_PTEA
-        boot_cpu_data.flags |= CPU_HAS_PTEA;
-#endif
-
         /*
          * On anything that's not a direct-mapped cache, look to the CVR
          * for I/D-cache specifics.
@@ -222,43 +197,48 @@ int __init detect_cpu_and_cache_system(void)
         }
 
         /*
-         * Setup the L2 cache desc
-         *
          * SH-4A's have an optional PIPT L2.
          */
         if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
-                /* Bug if we can't decode the L2 info */
-                BUG_ON(!(cvr & 0xf));
-
-                /* Silicon and specifications have clearly never met.. */
-                cvr ^= 0xf;
-
                 /*
-                 * Size calculation is much more sensible
-                 * than it is for the L1.
-                 *
-                 * Sizes are 128KB, 258KB, 512KB, and 1MB.
+                 * Verify that it really has something hooked up, this
+                 * is the safety net for CPUs that have optional L2
+                 * support yet do not implement it.
                  */
-                size = (cvr & 0xf) << 17;
-
-                BUG_ON(!size);
-
-                boot_cpu_data.scache.way_incr           = (1 << 16);
-                boot_cpu_data.scache.entry_shift        = 5;
-                boot_cpu_data.scache.ways               = 4;
-                boot_cpu_data.scache.linesz             = L1_CACHE_BYTES;
-
-                boot_cpu_data.scache.entry_mask =
-                        (boot_cpu_data.scache.way_incr -
-                         boot_cpu_data.scache.linesz);
-
-                boot_cpu_data.scache.sets       = size /
-                        (boot_cpu_data.scache.linesz *
-                         boot_cpu_data.scache.ways);
-
-                boot_cpu_data.scache.way_size   =
-                        (boot_cpu_data.scache.sets *
-                         boot_cpu_data.scache.linesz);
+                if ((cvr & 0xf) == 0)
+                        boot_cpu_data.flags &= ~CPU_HAS_L2_CACHE;
+                else {
+                        /*
+                         * Silicon and specifications have clearly never
+                         * met..
+                         */
+                        cvr ^= 0xf;
+
+                        /*
+                         * Size calculation is much more sensible
+                         * than it is for the L1.
+                         *
+                         * Sizes are 128KB, 258KB, 512KB, and 1MB.
+                         */
+                        size = (cvr & 0xf) << 17;
+
+                        boot_cpu_data.scache.way_incr           = (1 << 16);
+                        boot_cpu_data.scache.entry_shift        = 5;
+                        boot_cpu_data.scache.ways               = 4;
+                        boot_cpu_data.scache.linesz             = L1_CACHE_BYTES;
+
+                        boot_cpu_data.scache.entry_mask =
+                                (boot_cpu_data.scache.way_incr -
+                                 boot_cpu_data.scache.linesz);
+
+                        boot_cpu_data.scache.sets       = size /
+                                (boot_cpu_data.scache.linesz *
+                                 boot_cpu_data.scache.ways);
+
+                        boot_cpu_data.scache.way_size   =
+                                (boot_cpu_data.scache.sets *
+                                 boot_cpu_data.scache.linesz);
+                }
         }
 
         return 0;
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index 7371abf64f80..6d088d123591 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -2,6 +2,7 @@
  * SH4-202 Setup
  *
  *  Copyright (C) 2006  Paul Mundt
+ *  Copyright (C) 2009  Magnus Damm
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -11,6 +12,8 @@
 #include <linux/init.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
+#include <linux/io.h>
 
 static struct plat_sci_port sci_platform_data[] = {
         {
@@ -31,8 +34,103 @@ static struct platform_device sci_device = {
         },
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffd80008,
+                .end    = 0xffd80013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffd80014,
+                .end    = 0xffd8001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffd80020,
+                .end    = 0xffd8002f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
 static struct platform_device *sh4202_devices[] __initdata = {
         &sci_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
 };
 
 static int __init sh4202_devices_setup(void)
@@ -42,7 +140,71 @@ static int __init sh4202_devices_setup(void)
 }
 __initcall(sh4202_devices_setup);
 
+static struct platform_device *sh4202_early_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh4202_early_devices,
+                                   ARRAY_SIZE(sh4202_early_devices));
+}
+
+enum {
+        UNUSED = 0,
+
+        /* interrupt sources */
+        IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
+        HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT,
+};
+
+static struct intc_vect vectors[] __initdata = {
+        INTC_VECT(HUDI, 0x600),
+        INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
+        INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
+        INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
+        INTC_VECT(RTC, 0x4c0),
+        INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
+        INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
+        INTC_VECT(WDT, 0x560),
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+        { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
+        { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
+        { 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } },
+        { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL,
+                         NULL, prio_registers, NULL);
+
+static struct intc_vect vectors_irlm[] __initdata = {
+        INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
+        INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
+};
+
+static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL,
+                         NULL, prio_registers, NULL);
+
 void __init plat_irq_setup(void)
 {
-        /* do nothing - all IRL interrupts are handled by the board code */
+        register_intc_controller(&intc_desc);
+}
+
+#define INTC_ICR        0xffd00000UL
+#define INTC_ICR_IRLM   (1<<7)
+
+void __init plat_irq_setup_pins(int mode)
+{
+        switch (mode) {
+        case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
+                ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
+                register_intc_controller(&intc_desc_irlm);
+                break;
+        default:
+                BUG();
+        }
 }
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index a1c80d909cd6..851672d15cf4 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/serial.h>
 #include <linux/io.h>
+#include <linux/sh_timer.h>
 #include <linux/serial_sci.h>
 
 static struct resource rtc_resources[] = {
@@ -60,9 +61,177 @@ static struct platform_device sci_device = {
         },
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffd80008,
+                .end    = 0xffd80013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffd80014,
+                .end    = 0xffd8001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffd80020,
+                .end    = 0xffd8002f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
+/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
+#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
+        defined(CONFIG_CPU_SUBTYPE_SH7751) || \
+        defined(CONFIG_CPU_SUBTYPE_SH7751R)
+
+static struct sh_timer_config tmu3_platform_data = {
+        .name = "TMU3",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu3_resources[] = {
+        [0] = {
+                .name   = "TMU3",
+                .start  = 0xfe100008,
+                .end    = 0xfe100013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 72,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu3_device = {
+        .name           = "sh_tmu",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &tmu3_platform_data,
+        },
+        .resource       = tmu3_resources,
+        .num_resources  = ARRAY_SIZE(tmu3_resources),
+};
+
+static struct sh_timer_config tmu4_platform_data = {
+        .name = "TMU4",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu4_resources[] = {
+        [0] = {
+                .name   = "TMU4",
+                .start  = 0xfe100014,
+                .end    = 0xfe10001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 76,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu4_device = {
+        .name           = "sh_tmu",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &tmu4_platform_data,
+        },
+        .resource       = tmu4_resources,
+        .num_resources  = ARRAY_SIZE(tmu4_resources),
+};
+
+#endif
+
 static struct platform_device *sh7750_devices[] __initdata = {
         &rtc_device,
         &sci_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
+        defined(CONFIG_CPU_SUBTYPE_SH7751) || \
+        defined(CONFIG_CPU_SUBTYPE_SH7751R)
+        &tmu3_device,
+        &tmu4_device,
+#endif
 };
 
 static int __init sh7750_devices_setup(void)
@@ -72,6 +241,24 @@ static int __init sh7750_devices_setup(void)
 }
 __initcall(sh7750_devices_setup);
 
+static struct platform_device *sh7750_early_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
+        defined(CONFIG_CPU_SUBTYPE_SH7751) || \
+        defined(CONFIG_CPU_SUBTYPE_SH7751R)
+        &tmu3_device,
+        &tmu4_device,
+#endif
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7750_early_devices,
+                                   ARRAY_SIZE(sh7750_early_devices));
+}
+
 enum {
         UNUSED = 0,
 
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index d9bdc931ac09..5b822519bd90 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -10,6 +10,7 @@
 #include <linux/platform_device.h>
 #include <linux/init.h>
 #include <linux/serial.h>
+#include <linux/sh_timer.h>
 #include <linux/serial_sci.h>
 #include <linux/io.h>
 
@@ -18,10 +19,7 @@ enum {
 
         /* interrupt sources */
         IRL0, IRL1, IRL2, IRL3,
-        HUDI, GPIOI,
-        DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
-        DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
-        DMAC_DMAE,
+        HUDI, GPIOI, DMAC,
         IRQ4, IRQ5, IRQ6, IRQ7,
         HCAN20, HCAN21,
         SSI0, SSI1,
@@ -36,21 +34,20 @@ enum {
         HSPI,
         MMCIF0, MMCIF1, MMCIF2, MMCIF3,
         MFI, ADC, CMT,
-        TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
-        WDT,
-        REF_RCMI, REF_ROVI,
+        TMU0, TMU1, TMU2,
+        WDT, REF,
 
         /* interrupt groups */
-        DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF,
+        DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF,
 };
 
 static struct intc_vect vectors[] __initdata = {
         INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
-        INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
-        INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
-        INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
-        INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
-        INTC_VECT(DMAC_DMAE, 0x6c0),
+        INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
+        INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
+        INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
+        INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
+        INTC_VECT(DMAC, 0x6c0),
         INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
         INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
         INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
@@ -74,23 +71,18 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
         INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
-        INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
+        INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
         INTC_VECT(WDT, 0x560),
-        INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
+        INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
 };
 
 static struct intc_group groups[] __initdata = {
-        INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
-                   DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
-                   DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
         INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
         INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
         INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
         INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
         INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
-        INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
-        INTC_GROUP(REF, REF_RCMI, REF_ROVI),
 };
 
 static struct intc_mask_reg mask_registers[] __initdata = {
@@ -168,8 +160,104 @@ static struct platform_device sci_device = {
         },
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffd80008,
+                .end    = 0xffd80013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffd80014,
+                .end    = 0xffd8001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffd80020,
+                .end    = 0xffd8002f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
+
 static struct platform_device *sh7760_devices[] __initdata = {
         &sci_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
 };
 
 static int __init sh7760_devices_setup(void)
@@ -179,6 +267,18 @@ static int __init sh7760_devices_setup(void)
 }
 __initcall(sh7760_devices_setup);
 
+static struct platform_device *sh7760_early_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7760_early_devices,
+                                   ARRAY_SIZE(sh7760_early_devices));
+}
+
 #define INTC_ICR        0xffd00000UL
 #define INTC_ICR_IRLM   (1 << 7)
 
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 1a92361feeb9..96ea09ca8cc1 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7786)	+= setup-sh7786.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7343)        += setup-sh7343.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7722)        += setup-sh7722.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7723)        += setup-sh7723.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7724)        += setup-sh7724.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7366)        += setup-sh7366.o
 obj-$(CONFIG_CPU_SUBTYPE_SHX3)          += setup-shx3.o
 
@@ -23,15 +24,17 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7770)	:= clock-sh7770.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7780)      := clock-sh7780.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7785)      := clock-sh7785.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7786)      := clock-sh7786.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7343)      := clock-sh7722.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7343)      := clock-sh7343.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7722)      := clock-sh7722.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7723)      := clock-sh7722.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7366)      := clock-sh7722.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7723)      := clock-sh7723.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7724)      := clock-sh7724.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7366)      := clock-sh7366.o
 clock-$(CONFIG_CPU_SUBTYPE_SHX3)        := clock-shx3.o
 
 # Pinmux setup
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7722)     := pinmux-sh7722.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7723)     := pinmux-sh7723.o
+pinmux-$(CONFIG_CPU_SUBTYPE_SH7724)     := pinmux-sh7724.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7785)     := pinmux-sh7785.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7786)     := pinmux-sh7786.o
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
new file mode 100644
index 000000000000..0ee3ee861252
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -0,0 +1,211 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+ *
+ * SH7343 clock framework support
+ *
+ * Copyright (C) 2009 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/clock.h>
+
+/* SH7343 registers */
+#define FRQCR           0xa4150000
+#define VCLKCR          0xa4150004
+#define SCLKACR         0xa4150008
+#define SCLKBCR         0xa415000c
+#define PLLCR           0xa4150024
+#define MSTPCR0         0xa4150030
+#define MSTPCR1         0xa4150034
+#define MSTPCR2         0xa4150038
+#define DLLFRQ          0xa4150050
+
+/* Fixed 32 KHz root clock for RTC and Power Management purposes */
+static struct clk r_clk = {
+        .name           = "rclk",
+        .id             = -1,
+        .rate           = 32768,
+};
+
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+struct clk extal_clk = {
+        .name           = "extal",
+        .id             = -1,
+        .rate           = 33333333,
+};
+
+/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
+static unsigned long dll_recalc(struct clk *clk)
+{
+        unsigned long mult;
+
+        if (__raw_readl(PLLCR) & 0x1000)
+                mult = __raw_readl(DLLFRQ);
+        else
+                mult = 0;
+
+        return clk->parent->rate * mult;
+}
+
+static struct clk_ops dll_clk_ops = {
+        .recalc         = dll_recalc,
+};
+
+static struct clk dll_clk = {
+        .name           = "dll_clk",
+        .id             = -1,
+        .ops            = &dll_clk_ops,
+        .parent         = &r_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (__raw_readl(PLLCR) & 0x4000)
+                mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
+
+        return clk->parent->rate * mult;
+}
+
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+};
+
+static struct clk pll_clk = {
+        .name           = "pll_clk",
+        .id             = -1,
+        .ops            = &pll_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+struct clk *main_clks[] = {
+        &r_clk,
+        &extal_clk,
+        &dll_clk,
+        &pll_clk,
+};
+
+static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
+static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
+
+static struct clk_div_mult_table div4_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+        .multipliers = multipliers,
+        .nr_multipliers = ARRAY_SIZE(multipliers),
+};
+
+enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
+       DIV4_SIUA, DIV4_SIUB, DIV4_NR };
+
+#define DIV4(_str, _reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
+        [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
+        [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
+};
+
+struct clk div6_clks[] = {
+        SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
+};
+
+#define MSTP(_str, _parent, _reg, _bit, _flags) \
+  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
+
+static struct clk mstp_clks[] = {
+        MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
+        MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
+        MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
+        MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
+        MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
+        MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
+        MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
+        MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
+        MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
+        MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
+        MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
+        MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
+        MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
+        MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
+        MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
+        MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
+        MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
+        MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
+        MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
+        MSTP("scif3", &div4_clks[DIV4_P], MSTPCR0, 4, 0),
+        MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0),
+        MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
+        MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
+
+        MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
+        MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0),
+
+        MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0),
+        MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
+        MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
+        MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
+        MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0),
+        MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
+        MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0),
+        MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0),
+        MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
+        MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
+        MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
+        MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
+        MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
+        MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
+        MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
+        MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
+        MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
+};
+
+int __init arch_clk_init(void)
+{
+        int k, ret = 0;
+
+        /* autodetect extal or dll configuration */
+        if (__raw_readl(PLLCR) & 0x1000)
+                pll_clk.parent = &dll_clk;
+        else
+                pll_clk.parent = &extal_clk;
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+
+        return ret;
+}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
new file mode 100644
index 000000000000..a95ebaba095c
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -0,0 +1,211 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+ *
+ * SH7366 clock framework support
+ *
+ * Copyright (C) 2009 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/clock.h>
+
+/* SH7366 registers */
+#define FRQCR           0xa4150000
+#define VCLKCR          0xa4150004
+#define SCLKACR         0xa4150008
+#define SCLKBCR         0xa415000c
+#define PLLCR           0xa4150024
+#define MSTPCR0         0xa4150030
+#define MSTPCR1         0xa4150034
+#define MSTPCR2         0xa4150038
+#define DLLFRQ          0xa4150050
+
+/* Fixed 32 KHz root clock for RTC and Power Management purposes */
+static struct clk r_clk = {
+        .name           = "rclk",
+        .id             = -1,
+        .rate           = 32768,
+};
+
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+struct clk extal_clk = {
+        .name           = "extal",
+        .id             = -1,
+        .rate           = 33333333,
+};
+
+/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
+static unsigned long dll_recalc(struct clk *clk)
+{
+        unsigned long mult;
+
+        if (__raw_readl(PLLCR) & 0x1000)
+                mult = __raw_readl(DLLFRQ);
+        else
+                mult = 0;
+
+        return clk->parent->rate * mult;
+}
+
+static struct clk_ops dll_clk_ops = {
+        .recalc         = dll_recalc,
+};
+
+static struct clk dll_clk = {
+        .name           = "dll_clk",
+        .id             = -1,
+        .ops            = &dll_clk_ops,
+        .parent         = &r_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+        unsigned long div = 1;
+
+        if (__raw_readl(PLLCR) & 0x4000)
+                mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
+        else
+                div = 2;
+
+        return (clk->parent->rate * mult) / div;
+}
+
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+};
+
+static struct clk pll_clk = {
+        .name           = "pll_clk",
+        .id             = -1,
+        .ops            = &pll_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+struct clk *main_clks[] = {
+        &r_clk,
+        &extal_clk,
+        &dll_clk,
+        &pll_clk,
+};
+
+static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
+static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
+
+static struct clk_div_mult_table div4_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+        .multipliers = multipliers,
+        .nr_multipliers = ARRAY_SIZE(multipliers),
+};
+
+enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
+       DIV4_SIUA, DIV4_SIUB, DIV4_NR };
+
+#define DIV4(_str, _reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
+        [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
+        [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
+        [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
+};
+
+struct clk div6_clks[] = {
+        SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
+};
+
+#define MSTP(_str, _parent, _reg, _bit, _flags) \
+  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
+
+static struct clk mstp_clks[] = {
+        /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
+        MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
+        MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
+        MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
+        MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
+        MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
+        MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
+        MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
+        MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
+        MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
+        MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
+        MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
+        MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
+        MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
+        MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
+        MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
+        MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
+        MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
+        MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
+        MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
+        MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
+        MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
+
+        MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
+
+        MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0),
+        MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0),
+        MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
+        MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0),
+        MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0),
+        MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
+        MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
+        MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
+        MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0),
+        MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
+        MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
+        MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
+        MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
+        MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
+        MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
+        MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
+};
+
+int __init arch_clk_init(void)
+{
+        int k, ret = 0;
+
+        /* autodetect extal or dll configuration */
+        if (__raw_readl(PLLCR) & 0x1000)
+                pll_clk.parent = &dll_clk;
+        else
+                pll_clk.parent = &extal_clk;
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+
+        return ret;
+}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 0e174af21874..40f859354f79 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -1,844 +1,197 @@
 /*
  * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
  *
- * SH7343, SH7722, SH7723 & SH7366 support for the clock framework
+ * SH7722 clock framework support
  *
- * Copyright (c) 2006-2007 Nomad Global Solutions Inc
- * Based on code for sh7343 by Paul Mundt
+ * Copyright (C) 2009 Magnus Damm
  *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <linux/errno.h>
-#include <linux/stringify.h>
 #include <asm/clock.h>
-#include <asm/freq.h>
-
-#define N  (-1)
-#define NM (-2)
-#define ROUND_NEAREST 0
-#define ROUND_DOWN -1
-#define ROUND_UP   +1
-
-static int adjust_algos[][3] = {
-        {},     /* NO_CHANGE */
-        { NM, N, 1 },   /* N:1, N:1 */
-        { 3, 2, 2 },    /* 3:2:2 */
-        { 5, 2, 2 },    /* 5:2:2 */
-        { N, 1, 1 },    /* N:1:1 */
-
-        { N, 1 },       /* N:1 */
 
-        { N, 1 },       /* N:1 */
-        { 3, 2 },
-        { 4, 3 },
-        { 5, 4 },
-
-        { N, 1 }
+/* SH7722 registers */
+#define FRQCR           0xa4150000
+#define VCLKCR          0xa4150004
+#define SCLKACR         0xa4150008
+#define SCLKBCR         0xa415000c
+#define IRDACLKCR       0xa4150018
+#define PLLCR           0xa4150024
+#define MSTPCR0         0xa4150030
+#define MSTPCR1         0xa4150034
+#define MSTPCR2         0xa4150038
+#define DLLFRQ          0xa4150050
+
+/* Fixed 32 KHz root clock for RTC and Power Management purposes */
+static struct clk r_clk = {
+        .name           = "rclk",
+        .id             = -1,
+        .rate           = 32768,
 };
 
-static unsigned long adjust_pair_of_clocks(unsigned long r1, unsigned long r2,
-                        int m1, int m2, int round_flag)
-{
-        unsigned long rem, div;
-        int the_one = 0;
-
-        pr_debug( "Actual values: r1 = %ld\n", r1);
-        pr_debug( "...............r2 = %ld\n", r2);
-
-        if (m1 == m2) {
-                r2 = r1;
-                pr_debug( "setting equal rates: r2 now %ld\n", r2);
-        } else if ((m2 == N  && m1 == 1) ||
-                   (m2 == NM && m1 == N)) { /* N:1 or NM:N */
-                pr_debug( "Setting rates as 1:N (N:N*M)\n");
-                rem = r2 % r1;
-                pr_debug( "...remainder = %ld\n", rem);
-                if (rem) {
-                        div = r2 / r1;
-                        pr_debug( "...div = %ld\n", div);
-                        switch (round_flag) {
-                        case ROUND_NEAREST:
-                                the_one = rem >= r1/2 ? 1 : 0; break;
-                        case ROUND_UP:
-                                the_one = 1; break;
-                        case ROUND_DOWN:
-                                the_one = 0; break;
-                        }
-
-                        r2 = r1 * (div + the_one);
-                        pr_debug( "...setting r2 to %ld\n", r2);
-                }
-        } else if ((m2 == 1  && m1 == N) ||
-                   (m2 == N && m1 == NM)) { /* 1:N or N:NM */
-                pr_debug( "Setting rates as N:1 (N*M:N)\n");
-                rem = r1 % r2;
-                pr_debug( "...remainder = %ld\n", rem);
-                if (rem) {
-                        div = r1 / r2;
-                        pr_debug( "...div = %ld\n", div);
-                        switch (round_flag) {
-                        case ROUND_NEAREST:
-                                the_one = rem > r2/2 ? 1 : 0; break;
-                        case ROUND_UP:
-                                the_one = 0; break;
-                        case ROUND_DOWN:
-                                the_one = 1; break;
-                        }
-
-                        r2 = r1 / (div + the_one);
-                        pr_debug( "...setting r2 to %ld\n", r2);
-                }
-        } else { /* value:value */
-                pr_debug( "Setting rates as %d:%d\n", m1, m2);
-                div = r1 / m1;
-                r2 = div * m2;
-                pr_debug( "...div = %ld\n", div);
-                pr_debug( "...setting r2 to %ld\n", r2);
-        }
-
-        return r2;
-}
-
-static void adjust_clocks(int originate, int *l, unsigned long v[],
-                          int n_in_line)
-{
-        int x;
-
-        pr_debug( "Go down from %d...\n", originate);
-        /* go up recalculation clocks */
-        for (x = originate; x>0; x -- )
-                v[x-1] = adjust_pair_of_clocks(v[x], v[x-1],
-                                        l[x], l[x-1],
-                                        ROUND_UP);
-
-        pr_debug( "Go up from %d...\n", originate);
-        /* go down recalculation clocks */
-        for (x = originate; x<n_in_line - 1; x ++ )
-                v[x+1] = adjust_pair_of_clocks(v[x], v[x+1],
-                                        l[x], l[x+1],
-                                        ROUND_UP);
-}
-
-
 /*
- * SH7722 uses a common set of multipliers and divisors, so this
- * is quite simple..
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
  */
-
-/*
- * Instead of having two separate multipliers/divisors set, like this:
- *
- * static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
- * static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
- *
- * I created the divisors2 array, which is used to calculate rate like
- *   rate = parent * 2 / divisors2[ divisor ];
-*/
-static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
-
-static void master_clk_recalc(struct clk *clk)
-{
-        unsigned frqcr = ctrl_inl(FRQCR);
-
-        clk->rate = CONFIG_SH_PCLK_FREQ * (((frqcr >> 24) & 0x1f) + 1);
-}
-
-static void master_clk_init(struct clk *clk)
-{
-        clk->parent = NULL;
-        clk->flags |= CLK_RATE_PROPAGATES;
-        clk->rate = CONFIG_SH_PCLK_FREQ;
-        master_clk_recalc(clk);
-}
-
-
-static void module_clk_recalc(struct clk *clk)
-{
-        unsigned long frqcr = ctrl_inl(FRQCR);
-
-        clk->rate = clk->parent->rate / (((frqcr >> 24) & 0x1f) + 1);
-}
-
-static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
-{
-        int div = rate / clk->rate;
-        int master_divs[] = { 2, 3, 4, 6, 8, 16 };
-        int index;
-        unsigned long frqcr;
-
-        for (index = 1; index < ARRAY_SIZE(master_divs); index++)
-                if (div >= master_divs[index - 1] && div < master_divs[index])
-                        break;
-
-        if (index >= ARRAY_SIZE(master_divs))
-                index = ARRAY_SIZE(master_divs);
-        div = master_divs[index - 1];
-
-        frqcr = ctrl_inl(FRQCR);
-        frqcr &= ~(0xF << 24);
-        frqcr |= ( (div-1) << 24);
-        ctrl_outl(frqcr, FRQCR);
-
-        return 0;
-}
-
-static struct clk_ops sh7722_master_clk_ops = {
-        .init = master_clk_init,
-        .recalc = master_clk_recalc,
-        .set_rate = master_clk_setrate,
-};
-
-static struct clk_ops sh7722_module_clk_ops = {
-       .recalc = module_clk_recalc,
-};
-
-struct frqcr_context {
-        unsigned mask;
-        unsigned shift;
-};
-
-struct frqcr_context sh7722_get_clk_context(const char *name)
-{
-        struct frqcr_context ctx = { 0, };
-
-        if (!strcmp(name, "peripheral_clk")) {
-                ctx.shift = 0;
-                ctx.mask = 0xF;
-        } else if (!strcmp(name, "sdram_clk")) {
-                ctx.shift = 4;
-                ctx.mask = 0xF;
-        } else if (!strcmp(name, "bus_clk")) {
-                ctx.shift = 8;
-                ctx.mask = 0xF;
-        } else if (!strcmp(name, "sh_clk")) {
-                ctx.shift = 12;
-                ctx.mask = 0xF;
-        } else if (!strcmp(name, "umem_clk")) {
-                ctx.shift = 16;
-                ctx.mask = 0xF;
-        } else if (!strcmp(name, "cpu_clk")) {
-                ctx.shift = 20;
-                ctx.mask = 7;
-        }
-        return ctx;
-}
-
-/**
- * sh7722_find_div_index - find divisor for setting rate
- *
- * All sh7722 clocks use the same set of multipliers/divisors. This function
- * chooses correct divisor to set the rate of clock with parent clock that
- * generates frequency of 'parent_rate'
- *
- * @parent_rate: rate of parent clock
- * @rate: requested rate to be set
- */
-static int sh7722_find_div_index(unsigned long parent_rate, unsigned rate)
-{
-        unsigned div2 = parent_rate * 2 / rate;
-        int index;
-
-        if (rate > parent_rate)
-                return -EINVAL;
-
-        for (index = 1; index < ARRAY_SIZE(divisors2); index++) {
-                if (div2 > divisors2[index - 1] && div2 <= divisors2[index])
-                        break;
-        }
-        if (index >= ARRAY_SIZE(divisors2))
-                index = ARRAY_SIZE(divisors2) - 1;
-        return index;
-}
-
-static void sh7722_frqcr_recalc(struct clk *clk)
-{
-        struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
-        unsigned long frqcr = ctrl_inl(FRQCR);
-        int index;
-
-        index = (frqcr >> ctx.shift) & ctx.mask;
-        clk->rate = clk->parent->rate * 2 / divisors2[index];
-}
-
-static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
-                                 int algo_id)
-{
-        struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
-        unsigned long parent_rate = clk->parent->rate;
-        int div;
-        unsigned long frqcr;
-        int err = 0;
-
-        /* pretty invalid */
-        if (parent_rate < rate)
-                return -EINVAL;
-
-        /* look for multiplier/divisor pair */
-        div = sh7722_find_div_index(parent_rate, rate);
-        if (div<0)
-                return div;
-
-        /* calculate new value of clock rate */
-        clk->rate = parent_rate * 2 / divisors2[div];
-        frqcr = ctrl_inl(FRQCR);
-
-        /* FIXME: adjust as algo_id specifies */
-        if (algo_id != NO_CHANGE) {
-                int originator;
-                char *algo_group_1[] = { "cpu_clk", "umem_clk", "sh_clk" };
-                char *algo_group_2[] = { "sh_clk", "bus_clk" };
-                char *algo_group_3[] = { "sh_clk", "sdram_clk" };
-                char *algo_group_4[] = { "bus_clk", "peripheral_clk" };
-                char *algo_group_5[] = { "cpu_clk", "peripheral_clk" };
-                char **algo_current = NULL;
-                /* 3 is the maximum number of clocks in relation */
-                struct clk *ck[3];
-                unsigned long values[3]; /* the same comment as above */
-                int part_length = -1;
-                int i;
-
-                /*
-                 * all the steps below only required if adjustion was
-                 * requested
-                 */
-                if (algo_id == IUS_N1_N1 ||
-                    algo_id == IUS_322 ||
-                    algo_id == IUS_522 ||
-                    algo_id == IUS_N11) {
-                        algo_current = algo_group_1;
-                        part_length = 3;
-                }
-                if (algo_id == SB_N1) {
-                        algo_current = algo_group_2;
-                        part_length = 2;
-                }
-                if (algo_id == SB3_N1 ||
-                    algo_id == SB3_32 ||
-                    algo_id == SB3_43 ||
-                    algo_id == SB3_54) {
-                        algo_current = algo_group_3;
-                        part_length = 2;
-                }
-                if (algo_id == BP_N1) {
-                        algo_current = algo_group_4;
-                        part_length = 2;
-                }
-                if (algo_id == IP_N1) {
-                        algo_current = algo_group_5;
-                        part_length = 2;
-                }
-                if (!algo_current)
-                        goto incorrect_algo_id;
-
-                originator = -1;
-                for (i = 0; i < part_length; i ++ ) {
-                        if (originator >= 0 && !strcmp(clk->name,
-                                                       algo_current[i]))
-                                originator = i;
-                        ck[i] = clk_get(NULL, algo_current[i]);
-                        values[i] = clk_get_rate(ck[i]);
-                }
-
-                if (originator >= 0)
-                        adjust_clocks(originator, adjust_algos[algo_id],
-                                      values, part_length);
-
-                for (i = 0; i < part_length; i ++ ) {
-                        struct frqcr_context part_ctx;
-                        int part_div;
-
-                        if (likely(!err)) {
-                                part_div = sh7722_find_div_index(parent_rate,
-                                                                rate);
-                                if (part_div > 0) {
-                                        part_ctx = sh7722_get_clk_context(
-                                                                ck[i]->name);
-                                        frqcr &= ~(part_ctx.mask <<
-                                                   part_ctx.shift);
-                                        frqcr |= part_div << part_ctx.shift;
-                                } else
-                                        err = part_div;
-                        }
-
-                        ck[i]->ops->recalc(ck[i]);
-                        clk_put(ck[i]);
-                }
-        }
-
-        /* was there any error during recalculation ? If so, bail out.. */
-        if (unlikely(err!=0))
-                goto out_err;
-
-        /* clear FRQCR bits */
-        frqcr &= ~(ctx.mask << ctx.shift);
-        frqcr |= div << ctx.shift;
-
-        /* ...and perform actual change */
-        ctrl_outl(frqcr, FRQCR);
-        return 0;
-
-incorrect_algo_id:
-        return -EINVAL;
-out_err:
-        return err;
-}
-
-static long sh7722_frqcr_round_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk->parent->rate;
-        int div;
-
-        /* look for multiplier/divisor pair */
-        div = sh7722_find_div_index(parent_rate, rate);
-        if (div < 0)
-                return clk->rate;
-
-        /* calculate new value of clock rate */
-        return parent_rate * 2 / divisors2[div];
-}
-
-static struct clk_ops sh7722_frqcr_clk_ops = {
-        .recalc = sh7722_frqcr_recalc,
-        .set_rate = sh7722_frqcr_set_rate,
-        .round_rate = sh7722_frqcr_round_rate,
+struct clk extal_clk = {
+        .name           = "extal",
+        .id             = -1,
+        .rate           = 33333333,
 };
 
-/*
- * clock ops methods for SIU A/B and IrDA clock
- *
- */
-
-#ifndef CONFIG_CPU_SUBTYPE_SH7343
-
-static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
-{
-        unsigned long r;
-        int div;
-
-        r = ctrl_inl(clk->arch_flags);
-        div = sh7722_find_div_index(clk->parent->rate, rate);
-        if (div < 0)
-                return div;
-        r = (r & ~0xF) | div;
-        ctrl_outl(r, clk->arch_flags);
-        return 0;
-}
-
-static void sh7722_siu_recalc(struct clk *clk)
-{
-        unsigned long r;
-
-        r = ctrl_inl(clk->arch_flags);
-        clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF];
-}
-
-static int sh7722_siu_start_stop(struct clk *clk, int enable)
+/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
+static unsigned long dll_recalc(struct clk *clk)
 {
-        unsigned long r;
+        unsigned long mult;
 
-        r = ctrl_inl(clk->arch_flags);
-        if (enable)
-                ctrl_outl(r & ~(1 << 8), clk->arch_flags);
+        if (__raw_readl(PLLCR) & 0x1000)
+                mult = __raw_readl(DLLFRQ);
         else
-                ctrl_outl(r | (1 << 8), clk->arch_flags);
-        return 0;
-}
-
-static void sh7722_siu_enable(struct clk *clk)
-{
-        sh7722_siu_start_stop(clk, 1);
-}
+                mult = 0;
 
-static void sh7722_siu_disable(struct clk *clk)
-{
-        sh7722_siu_start_stop(clk, 0);
+        return clk->parent->rate * mult;
 }
 
-static struct clk_ops sh7722_siu_clk_ops = {
-        .recalc = sh7722_siu_recalc,
-        .set_rate = sh7722_siu_set_rate,
-        .enable = sh7722_siu_enable,
-        .disable = sh7722_siu_disable,
+static struct clk_ops dll_clk_ops = {
+        .recalc         = dll_recalc,
 };
 
-#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
-
-static void sh7722_video_enable(struct clk *clk)
-{
-        unsigned long r;
-
-        r = ctrl_inl(VCLKCR);
-        ctrl_outl( r & ~(1<<8), VCLKCR);
-}
-
-static void sh7722_video_disable(struct clk *clk)
-{
-        unsigned long r;
-
-        r = ctrl_inl(VCLKCR);
-        ctrl_outl( r | (1<<8), VCLKCR);
-}
+static struct clk dll_clk = {
+        .name           = "dll_clk",
+        .id             = -1,
+        .ops            = &dll_clk_ops,
+        .parent         = &r_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
 
-static int sh7722_video_set_rate(struct clk *clk, unsigned long rate,
-                                 int algo_id)
+static unsigned long pll_recalc(struct clk *clk)
 {
-        unsigned long r;
-
-        r = ctrl_inl(VCLKCR);
-        r &= ~0x3F;
-        r |= ((clk->parent->rate / rate - 1) & 0x3F);
-        ctrl_outl(r, VCLKCR);
-        return 0;
-}
+        unsigned long mult = 1;
+        unsigned long div = 1;
 
-static void sh7722_video_recalc(struct clk *clk)
-{
-        unsigned long r;
+        if (__raw_readl(PLLCR) & 0x4000)
+                mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
+        else
+                div = 2;
 
-        r = ctrl_inl(VCLKCR);
-        clk->rate = clk->parent->rate / ((r & 0x3F) + 1);
+        return (clk->parent->rate * mult) / div;
 }
 
-static struct clk_ops sh7722_video_clk_ops = {
-        .recalc = sh7722_video_recalc,
-        .set_rate = sh7722_video_set_rate,
-        .enable = sh7722_video_enable,
-        .disable = sh7722_video_disable,
-};
-/*
- * and at last, clock definitions themselves
- */
-static struct clk sh7722_umem_clock = {
-        .name = "umem_clk",
-        .ops = &sh7722_frqcr_clk_ops,
-        .flags = CLK_RATE_PROPAGATES,
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
 };
 
-static struct clk sh7722_sh_clock = {
-        .name = "sh_clk",
-        .ops = &sh7722_frqcr_clk_ops,
-        .flags = CLK_RATE_PROPAGATES,
+static struct clk pll_clk = {
+        .name           = "pll_clk",
+        .id             = -1,
+        .ops            = &pll_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
 };
 
-static struct clk sh7722_peripheral_clock = {
-        .name = "peripheral_clk",
-        .ops = &sh7722_frqcr_clk_ops,
-        .flags = CLK_RATE_PROPAGATES,
+struct clk *main_clks[] = {
+        &r_clk,
+        &extal_clk,
+        &dll_clk,
+        &pll_clk,
 };
 
-static struct clk sh7722_sdram_clock = {
-        .name = "sdram_clk",
-        .ops = &sh7722_frqcr_clk_ops,
-};
+static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
+static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 
-static struct clk sh7722_r_clock = {
-        .name = "r_clk",
-        .rate = 32768,
-        .flags = CLK_RATE_PROPAGATES,
+static struct clk_div_mult_table div4_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+        .multipliers = multipliers,
+        .nr_multipliers = ARRAY_SIZE(multipliers),
 };
 
-#ifndef CONFIG_CPU_SUBTYPE_SH7343
-
-/*
- * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
- * methods of clk_ops determine which register they should access by
- * examining clk->name field
- */
-static struct clk sh7722_siu_a_clock = {
-        .name = "siu_a_clk",
-        .arch_flags = SCLKACR,
-        .ops = &sh7722_siu_clk_ops,
-};
+enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
+       DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };
 
-static struct clk sh7722_siu_b_clock = {
-        .name = "siu_b_clk",
-        .arch_flags = SCLKBCR,
-        .ops = &sh7722_siu_clk_ops,
-};
+#define DIV4(_str, _reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7722)
-static struct clk sh7722_irda_clock = {
-        .name = "irda_clk",
-        .arch_flags = IrDACLKCR,
-        .ops = &sh7722_siu_clk_ops,
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
+        [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
+        [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
+        [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
+        [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
 };
-#endif
-#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
 
-static struct clk sh7722_video_clock = {
-        .name = "video_clk",
-        .ops = &sh7722_video_clk_ops,
+struct clk div6_clks[] = {
+        SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
 };
 
-#define MSTPCR_ARCH_FLAGS(reg, bit) (((reg) << 8) | (bit))
-#define MSTPCR_ARCH_FLAGS_REG(value) ((value) >> 8)
-#define MSTPCR_ARCH_FLAGS_BIT(value) ((value) & 0xff)
-
-static int sh7722_mstpcr_start_stop(struct clk *clk, int enable)
-{
-        unsigned long bit = MSTPCR_ARCH_FLAGS_BIT(clk->arch_flags);
-        unsigned long reg;
-        unsigned long r;
-
-        switch(MSTPCR_ARCH_FLAGS_REG(clk->arch_flags)) {
-        case 0:
-                reg = MSTPCR0;
-                break;
-        case 1:
-                reg = MSTPCR1;
-                break;
-        case 2:
-                reg = MSTPCR2;
-                break;
-        default:
-                return -EINVAL;
-        }  
-
-        r = ctrl_inl(reg);
-
-        if (enable)
-                r &= ~(1 << bit);
-        else
-                r |= (1 << bit);
+#define MSTP(_str, _parent, _reg, _bit, _flags) \
+  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
 
-        ctrl_outl(r, reg);
-        return 0;
-}
+static struct clk mstp_clks[] = {
+        MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
+        MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
+        MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
+        MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
+        MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
+        MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
+        MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
+        MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
+        MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
 
-static void sh7722_mstpcr_enable(struct clk *clk)
-{
-        sh7722_mstpcr_start_stop(clk, 1);
-}
+        MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
+        MSTP("rtc0", &r_clk, MSTPCR1, 8, 0),
 
-static void sh7722_mstpcr_disable(struct clk *clk)
-{
-        sh7722_mstpcr_start_stop(clk, 0);
-}
-
-static void sh7722_mstpcr_recalc(struct clk *clk)
-{
-        if (clk->parent)
-                clk->rate = clk->parent->rate;
-}
-
-static struct clk_ops sh7722_mstpcr_clk_ops = {
-        .enable = sh7722_mstpcr_enable,
-        .disable = sh7722_mstpcr_disable,
-        .recalc = sh7722_mstpcr_recalc,
-};
-
-#define MSTPCR(_name, _parent, regnr, bitnr) \
-{                                               \
-        .name = _name,                          \
-        .arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr),  \
-        .ops = (void *)_parent,         \
-}
-
-static struct clk sh7722_mstpcr_clocks[] = {
-#if defined(CONFIG_CPU_SUBTYPE_SH7722)
-        MSTPCR("uram0", "umem_clk", 0, 28),
-        MSTPCR("xymem0", "bus_clk", 0, 26),
-        MSTPCR("tmu0", "peripheral_clk", 0, 15),
-        MSTPCR("cmt0", "r_clk", 0, 14),
-        MSTPCR("rwdt0", "r_clk", 0, 13),
-        MSTPCR("flctl0", "peripheral_clk", 0, 10),
-        MSTPCR("scif0", "peripheral_clk", 0, 7),
-        MSTPCR("scif1", "peripheral_clk", 0, 6),
-        MSTPCR("scif2", "peripheral_clk", 0, 5),
-        MSTPCR("i2c0", "peripheral_clk", 1, 9),
-        MSTPCR("rtc0", "r_clk", 1, 8),
-        MSTPCR("sdhi0", "peripheral_clk", 2, 18),
-        MSTPCR("keysc0", "r_clk", 2, 14),
-        MSTPCR("usbf0", "peripheral_clk", 2, 11),
-        MSTPCR("2dg0", "bus_clk", 2, 9),
-        MSTPCR("siu0", "bus_clk", 2, 8),
-        MSTPCR("vou0", "bus_clk", 2, 5),
-        MSTPCR("jpu0", "bus_clk", 2, 6),
-        MSTPCR("beu0", "bus_clk", 2, 4),
-        MSTPCR("ceu0", "bus_clk", 2, 3),
-        MSTPCR("veu0", "bus_clk", 2, 2),
-        MSTPCR("vpu0", "bus_clk", 2, 1),
-        MSTPCR("lcdc0", "bus_clk", 2, 0),
-#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7723)
-        /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
-        MSTPCR("tlb0", "cpu_clk", 0, 31),
-        MSTPCR("ic0", "cpu_clk", 0, 30),
-        MSTPCR("oc0", "cpu_clk", 0, 29),
-        MSTPCR("l2c0", "sh_clk", 0, 28),
-        MSTPCR("ilmem0", "cpu_clk", 0, 27),
-        MSTPCR("fpu0", "cpu_clk", 0, 24),
-        MSTPCR("intc0", "cpu_clk", 0, 22),
-        MSTPCR("dmac0", "bus_clk", 0, 21),
-        MSTPCR("sh0", "sh_clk", 0, 20),
-        MSTPCR("hudi0", "peripheral_clk", 0, 19),
-        MSTPCR("ubc0", "cpu_clk", 0, 17),
-        MSTPCR("tmu0", "peripheral_clk", 0, 15),
-        MSTPCR("cmt0", "r_clk", 0, 14),
-        MSTPCR("rwdt0", "r_clk", 0, 13),
-        MSTPCR("dmac1", "bus_clk", 0, 12),
-        MSTPCR("tmu1", "peripheral_clk", 0, 11),
-        MSTPCR("flctl0", "peripheral_clk", 0, 10),
-        MSTPCR("scif0", "peripheral_clk", 0, 9),
-        MSTPCR("scif1", "peripheral_clk", 0, 8),
-        MSTPCR("scif2", "peripheral_clk", 0, 7),
-        MSTPCR("scif3", "bus_clk", 0, 6),
-        MSTPCR("scif4", "bus_clk", 0, 5),
-        MSTPCR("scif5", "bus_clk", 0, 4),
-        MSTPCR("msiof0", "bus_clk", 0, 2),
-        MSTPCR("msiof1", "bus_clk", 0, 1),
-        MSTPCR("meram0", "sh_clk", 0, 0),
-        MSTPCR("i2c0", "peripheral_clk", 1, 9),
-        MSTPCR("rtc0", "r_clk", 1, 8),
-        MSTPCR("atapi0", "sh_clk", 2, 28),
-        MSTPCR("adc0", "peripheral_clk", 2, 28),
-        MSTPCR("tpu0", "bus_clk", 2, 25),
-        MSTPCR("irda0", "peripheral_clk", 2, 24),
-        MSTPCR("tsif0", "bus_clk", 2, 22),
-        MSTPCR("icb0", "bus_clk", 2, 21),
-        MSTPCR("sdhi0", "bus_clk", 2, 18),
-        MSTPCR("sdhi1", "bus_clk", 2, 17),
-        MSTPCR("keysc0", "r_clk", 2, 14),
-        MSTPCR("usb0", "bus_clk", 2, 11),
-        MSTPCR("2dg0", "bus_clk", 2, 10),
-        MSTPCR("siu0", "bus_clk", 2, 8),
-        MSTPCR("veu1", "bus_clk", 2, 6),
-        MSTPCR("vou0", "bus_clk", 2, 5),
-        MSTPCR("beu0", "bus_clk", 2, 4),
-        MSTPCR("ceu0", "bus_clk", 2, 3),
-        MSTPCR("veu0", "bus_clk", 2, 2),
-        MSTPCR("vpu0", "bus_clk", 2, 1),
-        MSTPCR("lcdc0", "bus_clk", 2, 0),
-#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7343)
-        MSTPCR("uram0", "umem_clk", 0, 28),
-        MSTPCR("xymem0", "bus_clk", 0, 26),
-        MSTPCR("tmu0", "peripheral_clk", 0, 15),
-        MSTPCR("cmt0", "r_clk", 0, 14),
-        MSTPCR("rwdt0", "r_clk", 0, 13),
-        MSTPCR("scif0", "peripheral_clk", 0, 7),
-        MSTPCR("scif1", "peripheral_clk", 0, 6),
-        MSTPCR("scif2", "peripheral_clk", 0, 5),
-        MSTPCR("scif3", "peripheral_clk", 0, 4),
-        MSTPCR("i2c0", "peripheral_clk", 1, 9),
-        MSTPCR("i2c1", "peripheral_clk", 1, 8),
-        MSTPCR("sdhi0", "peripheral_clk", 2, 18),
-        MSTPCR("keysc0", "r_clk", 2, 14),
-        MSTPCR("usbf0", "peripheral_clk", 2, 11),
-        MSTPCR("siu0", "bus_clk", 2, 8),
-        MSTPCR("jpu0", "bus_clk", 2, 6),
-        MSTPCR("vou0", "bus_clk", 2, 5),
-        MSTPCR("beu0", "bus_clk", 2, 4),
-        MSTPCR("ceu0", "bus_clk", 2, 3),
-        MSTPCR("veu0", "bus_clk", 2, 2),
-        MSTPCR("vpu0", "bus_clk", 2, 1),
-        MSTPCR("lcdc0", "bus_clk", 2, 0),
-#endif
-#if defined(CONFIG_CPU_SUBTYPE_SH7366)
-        /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
-        MSTPCR("tlb0", "cpu_clk", 0, 31),
-        MSTPCR("ic0", "cpu_clk", 0, 30),
-        MSTPCR("oc0", "cpu_clk", 0, 29),
-        MSTPCR("rsmem0", "sh_clk", 0, 28),
-        MSTPCR("xymem0", "cpu_clk", 0, 26),
-        MSTPCR("intc30", "peripheral_clk", 0, 23),
-        MSTPCR("intc0", "peripheral_clk", 0, 22),
-        MSTPCR("dmac0", "bus_clk", 0, 21),
-        MSTPCR("sh0", "sh_clk", 0, 20),
-        MSTPCR("hudi0", "peripheral_clk", 0, 19),
-        MSTPCR("ubc0", "cpu_clk", 0, 17),
-        MSTPCR("tmu0", "peripheral_clk", 0, 15),
-        MSTPCR("cmt0", "r_clk", 0, 14),
-        MSTPCR("rwdt0", "r_clk", 0, 13),
-        MSTPCR("flctl0", "peripheral_clk", 0, 10),
-        MSTPCR("scif0", "peripheral_clk", 0, 7),
-        MSTPCR("scif1", "bus_clk", 0, 6),
-        MSTPCR("scif2", "bus_clk", 0, 5),
-        MSTPCR("msiof0", "peripheral_clk", 0, 2),
-        MSTPCR("sbr0", "peripheral_clk", 0, 1),
-        MSTPCR("i2c0", "peripheral_clk", 1, 9),
-        MSTPCR("icb0", "bus_clk", 2, 27),
-        MSTPCR("meram0", "sh_clk", 2, 26),
-        MSTPCR("dacc0", "peripheral_clk", 2, 24),
-        MSTPCR("dacy0", "peripheral_clk", 2, 23),
-        MSTPCR("tsif0", "bus_clk", 2, 22),
-        MSTPCR("sdhi0", "bus_clk", 2, 18),
-        MSTPCR("mmcif0", "bus_clk", 2, 17),
-        MSTPCR("usb0", "bus_clk", 2, 11),
-        MSTPCR("siu0", "bus_clk", 2, 8),
-        MSTPCR("veu1", "bus_clk", 2, 7),
-        MSTPCR("vou0", "bus_clk", 2, 5),
-        MSTPCR("beu0", "bus_clk", 2, 4),
-        MSTPCR("ceu0", "bus_clk", 2, 3),
-        MSTPCR("veu0", "bus_clk", 2, 2),
-        MSTPCR("vpu0", "bus_clk", 2, 1),
-        MSTPCR("lcdc0", "bus_clk", 2, 0),
-#endif
-};
-
-static struct clk *sh7722_clocks[] = {
-        &sh7722_umem_clock,
-        &sh7722_sh_clock,
-        &sh7722_peripheral_clock,
-        &sh7722_sdram_clock,
-#ifndef CONFIG_CPU_SUBTYPE_SH7343
-        &sh7722_siu_a_clock,
-        &sh7722_siu_b_clock,
-#if defined(CONFIG_CPU_SUBTYPE_SH7722)
-        &sh7722_irda_clock,
-#endif
-#endif
-        &sh7722_video_clock,
+        MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
+        MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
+        MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
+        MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 9, 0),
+        MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
+        MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
+        MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
+        MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
+        MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
+        MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
+        MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
+        MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
 };
 
-/*
- * init in order: master, module, bus, cpu
- */
-struct clk_ops *onchip_ops[] = {
-        &sh7722_master_clk_ops,
-        &sh7722_module_clk_ops,
-        &sh7722_frqcr_clk_ops,
-        &sh7722_frqcr_clk_ops,
-};
-
-void __init
-arch_init_clk_ops(struct clk_ops **ops, int type)
-{
-        BUG_ON(type < 0 || type > ARRAY_SIZE(onchip_ops));
-        *ops = onchip_ops[type];
-}
-
 int __init arch_clk_init(void)
 {
-        struct clk *clk;
-        int i;
+        int k, ret = 0;
+
+        /* autodetect extal or dll configuration */
+        if (__raw_readl(PLLCR) & 0x1000)
+                pll_clk.parent = &dll_clk;
+        else
+                pll_clk.parent = &extal_clk;
 
-        clk = clk_get(NULL, "master_clk");
-        for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) {
-                pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name);
-                sh7722_clocks[i]->parent = clk;
-                clk_register(sh7722_clocks[i]);
-        }
-        clk_put(clk);
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
 
-        clk_register(&sh7722_r_clock);
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 
-        for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr_clocks); i++) {
-                pr_debug( "Registering mstpcr clock '%s'\n",
-                          sh7722_mstpcr_clocks[i].name);
-                clk = clk_get(NULL, (void *) sh7722_mstpcr_clocks[i].ops);
-                sh7722_mstpcr_clocks[i].parent = clk;
-                sh7722_mstpcr_clocks[i].ops = &sh7722_mstpcr_clk_ops;
-                clk_register(&sh7722_mstpcr_clocks[i]);
-                clk_put(clk);
-        }
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
 
-        clk_recalc_rate(&sh7722_r_clock); /* make sure rate gets propagated */
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
 
-        return 0;
+        return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
new file mode 100644
index 000000000000..e67c2678b8ae
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -0,0 +1,222 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+ *
+ * SH7723 clock framework support
+ *
+ * Copyright (C) 2009 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/clock.h>
+
+/* SH7723 registers */
+#define FRQCR           0xa4150000
+#define VCLKCR          0xa4150004
+#define SCLKACR         0xa4150008
+#define SCLKBCR         0xa415000c
+#define IRDACLKCR       0xa4150018
+#define PLLCR           0xa4150024
+#define MSTPCR0         0xa4150030
+#define MSTPCR1         0xa4150034
+#define MSTPCR2         0xa4150038
+#define DLLFRQ          0xa4150050
+
+/* Fixed 32 KHz root clock for RTC and Power Management purposes */
+static struct clk r_clk = {
+        .name           = "rclk",
+        .id             = -1,
+        .rate           = 32768,
+};
+
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+struct clk extal_clk = {
+        .name           = "extal",
+        .id             = -1,
+        .rate           = 33333333,
+};
+
+/* The dll multiplies the 32khz r_clk, may be used instead of extal */
+static unsigned long dll_recalc(struct clk *clk)
+{
+        unsigned long mult;
+
+        if (__raw_readl(PLLCR) & 0x1000)
+                mult = __raw_readl(DLLFRQ);
+        else
+                mult = 0;
+
+        return clk->parent->rate * mult;
+}
+
+static struct clk_ops dll_clk_ops = {
+        .recalc         = dll_recalc,
+};
+
+static struct clk dll_clk = {
+        .name           = "dll_clk",
+        .id             = -1,
+        .ops            = &dll_clk_ops,
+        .parent         = &r_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+        unsigned long div = 1;
+
+        if (__raw_readl(PLLCR) & 0x4000)
+                mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
+        else
+                div = 2;
+
+        return (clk->parent->rate * mult) / div;
+}
+
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+};
+
+static struct clk pll_clk = {
+        .name           = "pll_clk",
+        .id             = -1,
+        .ops            = &pll_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+struct clk *main_clks[] = {
+        &r_clk,
+        &extal_clk,
+        &dll_clk,
+        &pll_clk,
+};
+
+static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
+static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
+
+static struct clk_div_mult_table div4_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+        .multipliers = multipliers,
+        .nr_multipliers = ARRAY_SIZE(multipliers),
+};
+
+enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
+       DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };
+
+#define DIV4(_str, _reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
+        [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
+        [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
+        [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
+        [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
+        [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
+};
+
+struct clk div6_clks[] = {
+        SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
+};
+
+#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \
+  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT)
+
+static struct clk mstp_clks[] = {
+        /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
+        MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0),
+        MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0),
+        MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0),
+        MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 28, 1, 1, 0),
+        MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0),
+        MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0),
+        MSTP("intc0", &div4_clks[DIV4_I], MSTPCR0, 22, 1, 1, 0),
+        MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1),
+        MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0),
+        MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0),
+        MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0),
+        MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0),
+        MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0),
+        MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0),
+        MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1),
+        MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 11, 0, 1, 0),
+        MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
+        MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0),
+        MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0),
+        MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0),
+        MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0),
+        MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0),
+        MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0),
+        MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0),
+        MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0),
+        MSTP("meram0", &div4_clks[DIV4_SH], MSTPCR0, 0, 1, 1, 0),
+
+        MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0),
+        MSTP("rtc0", &r_clk, MSTPCR1, 8, 0, 0, 0),
+
+        MSTP("atapi0", &div4_clks[DIV4_SH], MSTPCR2, 28, 0, 1, 0),
+        MSTP("adc0", &div4_clks[DIV4_P], MSTPCR2, 27, 0, 1, 0),
+        MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0),
+        MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0),
+        MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0),
+        MSTP("icb0", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1),
+        MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0),
+        MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0),
+        MSTP("keysc0", &r_clk, MSTPCR2, 14, 0, 0, 0),
+        MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 11, 0, 1, 0),
+        MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 10, 0, 1, 1),
+        MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0, 1, 0),
+        MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1),
+        MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1),
+        MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1),
+        MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1),
+        MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1),
+        MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1),
+        MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1),
+};
+
+int __init arch_clk_init(void)
+{
+        int k, ret = 0;
+
+        /* autodetect extal or dll configuration */
+        if (__raw_readl(PLLCR) & 0x1000)
+                pll_clk.parent = &dll_clk;
+        else
+                pll_clk.parent = &extal_clk;
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+
+        return ret;
+}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
new file mode 100644
index 000000000000..5d5c9b952883
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -0,0 +1,242 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+ *
+ * SH7724 clock framework support
+ *
+ * Copyright (C) 2009 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/clock.h>
+
+/* SH7724 registers */
+#define FRQCRA          0xa4150000
+#define FRQCRB          0xa4150004
+#define VCLKCR          0xa4150048
+#define FCLKACR         0xa4150008
+#define FCLKBCR         0xa415000c
+#define IRDACLKCR       0xa4150018
+#define PLLCR           0xa4150024
+#define MSTPCR0         0xa4150030
+#define MSTPCR1         0xa4150034
+#define MSTPCR2         0xa4150038
+#define SPUCLKCR        0xa415003c
+#define FLLFRQ          0xa4150050
+#define LSTATS          0xa4150060
+
+/* Fixed 32 KHz root clock for RTC and Power Management purposes */
+static struct clk r_clk = {
+        .name           = "rclk",
+        .id             = -1,
+        .rate           = 32768,
+};
+
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+struct clk extal_clk = {
+        .name           = "extal",
+        .id             = -1,
+        .rate           = 33333333,
+};
+
+/* The fll multiplies the 32khz r_clk, may be used instead of extal */
+static unsigned long fll_recalc(struct clk *clk)
+{
+        unsigned long mult = 0;
+        unsigned long div = 1;
+
+        if (__raw_readl(PLLCR) & 0x1000)
+                mult = __raw_readl(FLLFRQ) & 0x3ff;
+
+        if (__raw_readl(FLLFRQ) & 0x4000)
+                div = 2;
+
+        return (clk->parent->rate * mult) / div;
+}
+
+static struct clk_ops fll_clk_ops = {
+        .recalc         = fll_recalc,
+};
+
+static struct clk fll_clk = {
+        .name           = "fll_clk",
+        .id             = -1,
+        .ops            = &fll_clk_ops,
+        .parent         = &r_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (__raw_readl(PLLCR) & 0x4000)
+                mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
+
+        return clk->parent->rate * mult;
+}
+
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+};
+
+static struct clk pll_clk = {
+        .name           = "pll_clk",
+        .id             = -1,
+        .ops            = &pll_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+/* A fixed divide-by-3 block use by the div6 clocks */
+static unsigned long div3_recalc(struct clk *clk)
+{
+        return clk->parent->rate / 3;
+}
+
+static struct clk_ops div3_clk_ops = {
+        .recalc         = div3_recalc,
+};
+
+static struct clk div3_clk = {
+        .name           = "div3_clk",
+        .id             = -1,
+        .ops            = &div3_clk_ops,
+        .parent         = &pll_clk,
+};
+
+struct clk *main_clks[] = {
+        &r_clk,
+        &extal_clk,
+        &fll_clk,
+        &pll_clk,
+        &div3_clk,
+};
+
+static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
+
+static struct clk_div_mult_table div4_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
+
+#define DIV4(_str, _reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
+        [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0),
+};
+
+struct clk div6_clks[] = {
+        SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0),
+        SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0),
+        SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0),
+        SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0),
+        SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0),
+};
+
+#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \
+  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT)
+
+static struct clk mstp_clks[] = {
+        MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0),
+        MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0),
+        MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0),
+        MSTP("rs0", &div4_clks[DIV4_B], MSTPCR0, 28, 1, 1, 0),
+        MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0),
+        MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 26, 1, 1, 0),
+        MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0),
+        MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 1, 1, 0),
+        MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1),
+        MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0),
+        MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0),
+        MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0),
+        MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0),
+        MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0),
+        MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0),
+        MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1),
+        MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
+        MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0),
+        MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0),
+        MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0),
+        MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0),
+        MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0),
+        MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0),
+        MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0),
+        MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0),
+
+        MSTP("keysc0", &r_clk, MSTPCR1, 12, 0, 0, 0),
+        MSTP("rtc0", &r_clk, MSTPCR1, 11, 0, 0, 0),
+        MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0),
+        MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0, 1, 0),
+
+        MSTP("mmc0", &div4_clks[DIV4_B], MSTPCR2, 29, 0, 1, 0),
+        MSTP("eth0", &div4_clks[DIV4_B], MSTPCR2, 28, 0, 1, 0),
+        MSTP("atapi0", &div4_clks[DIV4_B], MSTPCR2, 26, 0, 1, 0),
+        MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0),
+        MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0),
+        MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0),
+        MSTP("usb1", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1),
+        MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 20, 0, 1, 1),
+        MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 19, 0, 1, 1),
+        MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0),
+        MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0),
+        MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 15, 1, 1, 1),
+        MSTP("ceu1", &div4_clks[DIV4_B], MSTPCR2, 13, 0, 1, 1),
+        MSTP("beu1", &div4_clks[DIV4_B], MSTPCR2, 12, 0, 1, 1),
+        MSTP("2ddmac0", &div4_clks[DIV4_SH], MSTPCR2, 10, 0, 1, 1),
+        MSTP("spu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0, 1, 0),
+        MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1),
+        MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1),
+        MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1),
+        MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1),
+        MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1),
+        MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1),
+        MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1),
+};
+
+int __init arch_clk_init(void)
+{
+        int k, ret = 0;
+
+        /* autodetect extal or fll configuration */
+        if (__raw_readl(PLLCR) & 0x1000)
+                pll_clk.parent = &fll_clk;
+        else
+                pll_clk.parent = &extal_clk;
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+
+        return ret;
+}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 3177d0d1e06d..370cd47642ef 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -29,33 +29,28 @@ static struct clk_ops sh7763_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07);
-        clk->rate = clk->parent->rate / p0fc_divisors[idx];
+        return clk->parent->rate / p0fc_divisors[idx];
 }
 
 static struct clk_ops sh7763_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07);
-        clk->rate = clk->parent->rate / bfc_divisors[idx];
+        return clk->parent->rate / bfc_divisors[idx];
 }
 
 static struct clk_ops sh7763_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
-{
-        clk->rate = clk->parent->rate;
-}
-
 static struct clk_ops sh7763_cpu_clk_ops = {
-        .recalc         = cpu_clk_recalc,
+        .recalc         = followparent_recalc,
 };
 
 static struct clk_ops *sh7763_clk_ops[] = {
@@ -71,10 +66,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
                 *ops = sh7763_clk_ops[idx];
 }
 
-static void shyway_clk_recalc(struct clk *clk)
+static unsigned long shyway_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07);
-        clk->rate = clk->parent->rate / cfc_divisors[idx];
+        return clk->parent->rate / cfc_divisors[idx];
 }
 
 static struct clk_ops sh7763_shyway_clk_ops = {
@@ -83,7 +78,7 @@ static struct clk_ops sh7763_shyway_clk_ops = {
 
 static struct clk sh7763_shyway_clk = {
         .name           = "shyway_clk",
-        .flags          = CLK_ALWAYS_ENABLED,
+        .flags          = CLK_ENABLE_ON_INIT,
         .ops            = &sh7763_shyway_clk_ops,
 };
 
@@ -95,31 +90,22 @@ static struct clk *sh7763_onchip_clocks[] = {
         &sh7763_shyway_clk,
 };
 
-static int __init sh7763_clk_init(void)
+int __init arch_clk_init(void)
 {
-        struct clk *clk = clk_get(NULL, "master_clk");
-        int i;
+        struct clk *clk;
+        int i, ret = 0;
+
+        cpg_clk_init();
 
+        clk = clk_get(NULL, "master_clk");
         for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) {
                 struct clk *clkp = sh7763_onchip_clocks[i];
 
                 clkp->parent = clk;
-                clk_register(clkp);
-                clk_enable(clkp);
+                ret |= clk_register(clkp);
         }
 
-        /*
-         * Now that we have the rest of the clocks registered, we need to
-         * force the parent clock to propagate so that these clocks will
-         * automatically figure out their rate. We cheat by handing the
-         * parent clock its current rate and forcing child propagation.
-         */
-        clk_set_rate(clk, clk_get_rate(clk));
-
         clk_put(clk);
 
-        return 0;
+        return ret;
 }
-
-arch_initcall(sh7763_clk_init);
-
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
index 8e236062c721..e0b896769205 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
@@ -28,30 +28,30 @@ static struct clk_ops sh7770_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f);
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh7770_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inl(FRQCR) & 0x000f);
-        clk->rate = clk->parent->rate / bfc_divisors[idx];
+        return clk->parent->rate / bfc_divisors[idx];
 }
 
 static struct clk_ops sh7770_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f);
-        clk->rate = clk->parent->rate / ifc_divisors[idx];
+        return clk->parent->rate / ifc_divisors[idx];
 }
 
 static struct clk_ops sh7770_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index 01f3da619d3d..a249d823578e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -29,30 +29,30 @@ static struct clk_ops sh7780_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inl(FRQCR) & 0x0003);
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh7780_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007);
-        clk->rate = clk->parent->rate / bfc_divisors[idx];
+        return clk->parent->rate / bfc_divisors[idx];
 }
 
 static struct clk_ops sh7780_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001);
-        clk->rate = clk->parent->rate / ifc_divisors[idx];
+        return clk->parent->rate / ifc_divisors[idx];
 }
 
 static struct clk_ops sh7780_cpu_clk_ops = {
@@ -72,10 +72,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
                 *ops = sh7780_clk_ops[idx];
 }
 
-static void shyway_clk_recalc(struct clk *clk)
+static unsigned long shyway_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007);
-        clk->rate = clk->parent->rate / cfc_divisors[idx];
+        return clk->parent->rate / cfc_divisors[idx];
 }
 
 static struct clk_ops sh7780_shyway_clk_ops = {
@@ -84,7 +84,7 @@ static struct clk_ops sh7780_shyway_clk_ops = {
 
 static struct clk sh7780_shyway_clk = {
         .name           = "shyway_clk",
-        .flags          = CLK_ALWAYS_ENABLED,
+        .flags          = CLK_ENABLE_ON_INIT,
         .ops            = &sh7780_shyway_clk_ops,
 };
 
@@ -96,31 +96,22 @@ static struct clk *sh7780_onchip_clocks[] = {
         &sh7780_shyway_clk,
 };
 
-static int __init sh7780_clk_init(void)
+int __init arch_clk_init(void)
 {
-        struct clk *clk = clk_get(NULL, "master_clk");
-        int i;
+        struct clk *clk;
+        int i, ret = 0;
 
+        cpg_clk_init();
+
+        clk = clk_get(NULL, "master_clk");
         for (i = 0; i < ARRAY_SIZE(sh7780_onchip_clocks); i++) {
                 struct clk *clkp = sh7780_onchip_clocks[i];
 
                 clkp->parent = clk;
-                clk_register(clkp);
-                clk_enable(clkp);
+                ret |= clk_register(clkp);
         }
 
-        /*
-         * Now that we have the rest of the clocks registered, we need to
-         * force the parent clock to propagate so that these clocks will
-         * automatically figure out their rate. We cheat by handing the
-         * parent clock its current rate and forcing child propagation.
-         */
-        clk_set_rate(clk, clk_get_rate(clk));
-
         clk_put(clk);
 
-        return 0;
+        return ret;
 }
-
-arch_initcall(sh7780_clk_init);
-
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 27fa81bef6a0..73abfbf2f16d 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -3,7 +3,7 @@
  *
  * SH7785 support for the clock framework
  *
- *  Copyright (C) 2007  Paul Mundt
+ *  Copyright (C) 2007 - 2009  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -11,152 +11,116 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/cpufreq.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
-#include <asm/io.h>
-
-static int ifc_divisors[] = { 1, 2, 4, 6 };
-static int ufc_divisors[] = { 1, 1, 4, 6 };
-static int sfc_divisors[] = { 1, 1, 4, 6 };
-static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18,
-                             24, 32, 36, 48, 1, 1, 1, 1 };
-static int mfc_divisors[] = { 1, 1, 4, 6 };
-static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18,
-                              24, 32, 36, 48, 1, 1, 1, 1 };
-
-static void master_clk_init(struct clk *clk)
-{
-        clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
-}
+#include <cpu/sh7785.h>
 
-static struct clk_ops sh7785_master_clk_ops = {
-        .init           = master_clk_init,
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk extal_clk = {
+        .name           = "extal",
+        .id             = -1,
+        .rate           = 33333333,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long pll_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQMR1) & 0x000f);
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
-}
+        int multiplier;
 
-static struct clk_ops sh7785_module_clk_ops = {
-        .recalc         = module_clk_recalc,
-};
+        multiplier = test_mode_pin(MODE_PIN4) ? 36 : 72;
 
-static void bus_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
-        clk->rate = clk->parent->rate / bfc_divisors[idx];
+        return clk->parent->rate * multiplier;
 }
 
-static struct clk_ops sh7785_bus_clk_ops = {
-        .recalc         = bus_clk_recalc,
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
-        clk->rate = clk->parent->rate / ifc_divisors[idx];
-}
-
-static struct clk_ops sh7785_cpu_clk_ops = {
-        .recalc         = cpu_clk_recalc,
+static struct clk pll_clk = {
+        .name           = "pll_clk",
+        .id             = -1,
+        .ops            = &pll_clk_ops,
+        .parent         = &extal_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
 };
 
-static struct clk_ops *sh7785_clk_ops[] = {
-        &sh7785_master_clk_ops,
-        &sh7785_module_clk_ops,
-        &sh7785_bus_clk_ops,
-        &sh7785_cpu_clk_ops,
+static struct clk *clks[] = {
+        &extal_clk,
+        &pll_clk,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
-{
-        if (idx < ARRAY_SIZE(sh7785_clk_ops))
-                *ops = sh7785_clk_ops[idx];
-}
-
-static void shyway_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
-        clk->rate = clk->parent->rate / sfc_divisors[idx];
-}
+static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
+                               24, 32, 36, 48 };
 
-static struct clk_ops sh7785_shyway_clk_ops = {
-        .recalc         = shyway_clk_recalc,
+static struct clk_div_mult_table div4_table = {
+        .divisors = div2,
+        .nr_divisors = ARRAY_SIZE(div2),
 };
 
-static struct clk sh7785_shyway_clk = {
-        .name           = "shyway_clk",
-        .flags          = CLK_ALWAYS_ENABLED,
-        .ops            = &sh7785_shyway_clk_ops,
+enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
+        DIV4_DU, DIV4_P, DIV4_NR };
+
+#define DIV4(_str, _bit, _mask, _flags) \
+  SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
+
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0),
+        [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0),
+        [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0),
+        [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT),
+        [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT),
+        [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT),
 };
 
-static void ddr_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
-        clk->rate = clk->parent->rate / mfc_divisors[idx];
-}
-
-static struct clk_ops sh7785_ddr_clk_ops = {
-        .recalc         = ddr_clk_recalc,
-};
-
-static struct clk sh7785_ddr_clk = {
-        .name           = "ddr_clk",
-        .flags          = CLK_ALWAYS_ENABLED,
-        .ops            = &sh7785_ddr_clk_ops,
-};
-
-static void ram_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 24) & 0x0003);
-        clk->rate = clk->parent->rate / ufc_divisors[idx];
-}
-
-static struct clk_ops sh7785_ram_clk_ops = {
-        .recalc         = ram_clk_recalc,
+#define MSTPCR0         0xffc80030
+#define MSTPCR1         0xffc80034
+
+static struct clk mstp_clks[] = {
+        /* MSTPCR0 */
+        SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
+        SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
+        SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
+        SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
+        SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
+        SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
+        SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
+        SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
+        SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
+        SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
+        SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0),
+        SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0),
+        SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
+        SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
+        SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0),
+        SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
+
+        /* MSTPCR1 */
+        SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0),
+        SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0),
+        SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
+        SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
+        SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
 };
 
-static struct clk sh7785_ram_clk = {
-        .name           = "ram_clk",
-        .flags          = CLK_ALWAYS_ENABLED,
-        .ops            = &sh7785_ram_clk_ops,
-};
-
-/*
- * Additional SH7785-specific on-chip clocks that aren't already part of the
- * clock framework
- */
-static struct clk *sh7785_onchip_clocks[] = {
-        &sh7785_shyway_clk,
-        &sh7785_ddr_clk,
-        &sh7785_ram_clk,
-};
-
-static int __init sh7785_clk_init(void)
+int __init arch_clk_init(void)
 {
-        struct clk *clk = clk_get(NULL, "master_clk");
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(sh7785_onchip_clocks); i++) {
-                struct clk *clkp = sh7785_onchip_clocks[i];
-
-                clkp->parent = clk;
-                clk_register(clkp);
-                clk_enable(clkp);
-        }
+        int i, ret = 0;
 
-        /*
-         * Now that we have the rest of the clocks registered, we need to
-         * force the parent clock to propagate so that these clocks will
-         * automatically figure out their rate. We cheat by handing the
-         * parent clock its current rate and forcing child propagation.
-         */
-        clk_set_rate(clk, clk_get_rate(clk));
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                ret |= clk_register(clks[i]);
 
-        clk_put(clk);
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
+                                           &div4_table);
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
 
-        return 0;
+        return ret;
 }
-arch_initcall(sh7785_clk_init);
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index f84a9c134471..a0e8869071ac 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -36,30 +36,30 @@ static struct clk_ops sh7786_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inl(FRQMR1) & 0x000f);
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh7786_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
-        clk->rate = clk->parent->rate / bfc_divisors[idx];
+        return clk->parent->rate / bfc_divisors[idx];
 }
 
 static struct clk_ops sh7786_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
-        clk->rate = clk->parent->rate / ifc_divisors[idx];
+        return clk->parent->rate / ifc_divisors[idx];
 }
 
 static struct clk_ops sh7786_cpu_clk_ops = {
@@ -79,10 +79,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
                 *ops = sh7786_clk_ops[idx];
 }
 
-static void shyway_clk_recalc(struct clk *clk)
+static unsigned long shyway_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
-        clk->rate = clk->parent->rate / sfc_divisors[idx];
+        return clk->parent->rate / sfc_divisors[idx];
 }
 
 static struct clk_ops sh7786_shyway_clk_ops = {
@@ -91,14 +91,14 @@ static struct clk_ops sh7786_shyway_clk_ops = {
 
 static struct clk sh7786_shyway_clk = {
         .name           = "shyway_clk",
-        .flags          = CLK_ALWAYS_ENABLED,
+        .flags          = CLK_ENABLE_ON_INIT,
         .ops            = &sh7786_shyway_clk_ops,
 };
 
-static void ddr_clk_recalc(struct clk *clk)
+static unsigned long ddr_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
-        clk->rate = clk->parent->rate / mfc_divisors[idx];
+        return clk->parent->rate / mfc_divisors[idx];
 }
 
 static struct clk_ops sh7786_ddr_clk_ops = {
@@ -107,7 +107,7 @@ static struct clk_ops sh7786_ddr_clk_ops = {
 
 static struct clk sh7786_ddr_clk = {
         .name           = "ddr_clk",
-        .flags          = CLK_ALWAYS_ENABLED,
+        .flags          = CLK_ENABLE_ON_INIT,
         .ops            = &sh7786_ddr_clk_ops,
 };
 
@@ -120,29 +120,22 @@ static struct clk *sh7786_onchip_clocks[] = {
         &sh7786_ddr_clk,
 };
 
-static int __init sh7786_clk_init(void)
+int __init arch_clk_init(void)
 {
-        struct clk *clk = clk_get(NULL, "master_clk");
-        int i;
+        struct clk *clk;
+        int i, ret = 0;
 
+        cpg_clk_init();
+
+        clk = clk_get(NULL, "master_clk");
         for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
                 struct clk *clkp = sh7786_onchip_clocks[i];
 
                 clkp->parent = clk;
-                clk_register(clkp);
-                clk_enable(clkp);
+                ret |= clk_register(clkp);
         }
 
-        /*
-         * Now that we have the rest of the clocks registered, we need to
-         * force the parent clock to propagate so that these clocks will
-         * automatically figure out their rate. We cheat by handing the
-         * parent clock its current rate and forcing child propagation.
-         */
-        clk_set_rate(clk, clk_get_rate(clk));
-
         clk_put(clk);
 
-        return 0;
+        return ret;
 }
-arch_initcall(sh7786_clk_init);
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index c630b29e06a8..23c27d32d982 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -40,30 +40,30 @@ static struct clk_ops shx3_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK);
-        clk->rate = clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops shx3_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK);
-        clk->rate = clk->parent->rate / bfc_divisors[idx];
+        return clk->parent->rate / bfc_divisors[idx];
 }
 
 static struct clk_ops shx3_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK);
-        clk->rate = clk->parent->rate / ifc_divisors[idx];
+        return clk->parent->rate / ifc_divisors[idx];
 }
 
 static struct clk_ops shx3_cpu_clk_ops = {
@@ -83,10 +83,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
                 *ops = shx3_clk_ops[idx];
 }
 
-static void shyway_clk_recalc(struct clk *clk)
+static unsigned long shyway_clk_recalc(struct clk *clk)
 {
         int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK);
-        clk->rate = clk->parent->rate / cfc_divisors[idx];
+        return clk->parent->rate / cfc_divisors[idx];
 }
 
 static struct clk_ops shx3_shyway_clk_ops = {
@@ -95,7 +95,7 @@ static struct clk_ops shx3_shyway_clk_ops = {
 
 static struct clk shx3_shyway_clk = {
         .name           = "shyway_clk",
-        .flags          = CLK_ALWAYS_ENABLED,
+        .flags          = CLK_ENABLE_ON_INIT,
         .ops            = &shx3_shyway_clk_ops,
 };
 
@@ -107,29 +107,22 @@ static struct clk *shx3_onchip_clocks[] = {
         &shx3_shyway_clk,
 };
 
-static int __init shx3_clk_init(void)
+int __init arch_clk_init(void)
 {
-        struct clk *clk = clk_get(NULL, "master_clk");
-        int i;
+        struct clk *clk;
+        int i, ret = 0;
 
+        cpg_clk_init();
+
+        clk = clk_get(NULL, "master_clk");
         for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {
                 struct clk *clkp = shx3_onchip_clocks[i];
 
                 clkp->parent = clk;
-                clk_register(clkp);
-                clk_enable(clkp);
+                ret |= clk_register(clkp);
         }
 
-        /*
-         * Now that we have the rest of the clocks registered, we need to
-         * force the parent clock to propagate so that these clocks will
-         * automatically figure out their rate. We cheat by handing the
-         * parent clock its current rate and forcing child propagation.
-         */
-        clk_set_rate(clk, clk_get_rate(clk));
-
         clk_put(clk);
 
-        return 0;
+        return ret;
 }
-arch_initcall(shx3_clk_init);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
new file mode 100644
index 000000000000..1af0f9586379
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
@@ -0,0 +1,2230 @@
+/*
+ * SH7724 Pinmux
+ *
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ *
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * Based on SH7723 Pinmux
+ *  Copyright (C) 2008  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <cpu/sh7724.h>
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+        PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
+        PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+        PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
+        PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
+        PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
+        PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+        PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
+        PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
+        PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
+        PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
+        PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
+                              PTG5_DATA, PTG4_DATA,
+        PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
+        PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
+        PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
+        PTJ7_DATA, PTJ6_DATA, PTJ5_DATA,
+        PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
+        PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
+        PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
+        PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+        PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
+        PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+        PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
+        PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
+        PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
+        PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
+        PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
+        PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
+        PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
+                   PTS6_DATA, PTS5_DATA, PTS4_DATA,
+        PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
+        PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
+        PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
+        PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
+        PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
+        PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
+        PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
+        PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
+        PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
+        PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
+        PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
+        PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
+        PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
+        PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
+        PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
+        PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
+        PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
+        PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
+        PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
+        PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
+        PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
+        PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
+        PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN,
+        PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
+        PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
+        PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
+        PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
+        PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
+        PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
+        PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
+        PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
+        PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
+        PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
+        PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
+        PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
+        PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
+        PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
+        PTQ7_IN, PTQ6_IN, PTQ5_IN, PTQ4_IN,
+        PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
+        PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
+        PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
+                 PTS6_IN, PTS5_IN, PTS4_IN,
+        PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
+        PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN,
+        PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
+        PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
+        PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
+        PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
+        PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
+        PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
+        PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
+        PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
+        PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
+        PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
+        PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
+        PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
+        PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
+        PINMUX_INPUT_END,
+
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
+        PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
+        PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU,
+        PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU,
+        PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU,
+        PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU,
+        PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
+        PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
+        PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU,
+        PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
+        PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU,
+        PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU,
+        PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
+        PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
+        PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
+        PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU,
+        PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
+        PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU,
+        PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU,
+        PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
+        PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU,
+        PTN7_IN_PU, PTN6_IN_PU, PTN5_IN_PU, PTN4_IN_PU,
+        PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU,
+        PTQ7_IN_PU, PTQ6_IN_PU, PTQ5_IN_PU, PTQ4_IN_PU,
+        PTQ3_IN_PU, PTQ2_IN_PU, PTQ1_IN_PU, PTQ0_IN_PU,
+        PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU,
+        PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU,
+                    PTS6_IN_PU, PTS5_IN_PU, PTS4_IN_PU,
+        PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU,
+        PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU,
+        PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
+        PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
+        PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
+        PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
+        PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU,
+        PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU,
+        PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU,
+        PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
+        PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
+        PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
+        PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
+        PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU,
+        PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU,
+        PINMUX_INPUT_PULLUP_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
+        PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
+        PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
+        PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
+        PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
+        PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
+        PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
+        PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
+        PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT,
+        PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
+        PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
+        PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
+                            PTG5_OUT, PTG4_OUT,
+        PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
+        PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
+        PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
+        PTJ7_OUT, PTJ6_OUT, PTJ5_OUT,
+        PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
+        PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
+        PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
+        PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
+        PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
+        PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
+        PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
+        PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
+        PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
+        PTQ7_OUT, PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
+        PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
+        PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
+                            PTR1_OUT, PTR0_OUT,
+                  PTS6_OUT, PTS5_OUT, PTS4_OUT,
+        PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
+        PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT,
+        PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
+        PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
+        PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
+        PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
+        PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
+        PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
+        PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
+        PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
+        PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
+        PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
+        PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
+        PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
+        PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
+        PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
+        PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
+        PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
+        PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
+        PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
+        PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
+        PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
+        PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN,
+        PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
+        PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
+        PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
+                          PTG5_FN, PTG4_FN,
+        PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
+        PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
+        PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
+        PTJ7_FN, PTJ6_FN, PTJ5_FN,
+        PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
+        PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
+        PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
+        PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN,
+        PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
+        PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
+        PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
+        PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN,
+        PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
+        PTQ7_FN, PTQ6_FN, PTQ5_FN, PTQ4_FN,
+        PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
+        PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
+        PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
+                 PTS6_FN, PTS5_FN, PTS4_FN,
+        PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
+        PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN,
+        PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
+        PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
+        PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
+        PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
+        PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
+        PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
+        PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
+        PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
+        PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
+        PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
+        PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
+        PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
+        PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
+
+
+        PSA15_0, PSA15_1,
+        PSA14_0, PSA14_1,
+        PSA13_0, PSA13_1,
+        PSA12_0, PSA12_1,
+        PSA10_0, PSA10_1,
+        PSA9_0,  PSA9_1,
+        PSA8_0,  PSA8_1,
+        PSA7_0,  PSA7_1,
+        PSA6_0,  PSA6_1,
+        PSA5_0,  PSA5_1,
+        PSA3_0,  PSA3_1,
+        PSA2_0,  PSA2_1,
+        PSA1_0,  PSA1_1,
+        PSA0_0,  PSA0_1,
+
+        PSB14_0, PSB14_1,
+        PSB13_0, PSB13_1,
+        PSB12_0, PSB12_1,
+        PSB11_0, PSB11_1,
+        PSB10_0, PSB10_1,
+        PSB9_0,  PSB9_1,
+        PSB8_0,  PSB8_1,
+        PSB7_0,  PSB7_1,
+        PSB6_0,  PSB6_1,
+        PSB5_0,  PSB5_1,
+        PSB4_0,  PSB4_1,
+        PSB3_0,  PSB3_1,
+        PSB2_0,  PSB2_1,
+        PSB1_0,  PSB1_1,
+        PSB0_0,  PSB0_1,
+
+        PSC15_0, PSC15_1,
+        PSC14_0, PSC14_1,
+        PSC13_0, PSC13_1,
+        PSC12_0, PSC12_1,
+        PSC11_0, PSC11_1,
+        PSC10_0, PSC10_1,
+        PSC9_0,  PSC9_1,
+        PSC8_0,  PSC8_1,
+        PSC7_0,  PSC7_1,
+        PSC6_0,  PSC6_1,
+        PSC5_0,  PSC5_1,
+        PSC4_0,  PSC4_1,
+        PSC2_0,  PSC2_1,
+        PSC1_0,  PSC1_1,
+        PSC0_0,  PSC0_1,
+
+        PSD15_0, PSD15_1,
+        PSD14_0, PSD14_1,
+        PSD13_0, PSD13_1,
+        PSD12_0, PSD12_1,
+        PSD11_0, PSD11_1,
+        PSD10_0, PSD10_1,
+        PSD9_0,  PSD9_1,
+        PSD8_0,  PSD8_1,
+        PSD7_0,  PSD7_1,
+        PSD6_0,  PSD6_1,
+        PSD5_0,  PSD5_1,
+        PSD4_0,  PSD4_1,
+        PSD3_0,  PSD3_1,
+        PSD2_0,  PSD2_1,
+        PSD1_0,  PSD1_1,
+        PSD0_0,  PSD0_1,
+
+        PSE15_0, PSE15_1,
+        PSE14_0, PSE14_1,
+        PSE13_0, PSE13_1,
+        PSE12_0, PSE12_1,
+        PSE11_0, PSE11_1,
+        PSE10_0, PSE10_1,
+        PSE9_0,  PSE9_1,
+        PSE8_0,  PSE8_1,
+        PSE7_0,  PSE7_1,
+        PSE6_0,  PSE6_1,
+        PSE5_0,  PSE5_1,
+        PSE4_0,  PSE4_1,
+        PSE3_0,  PSE3_1,
+        PSE2_0,  PSE2_1,
+        PSE1_0,  PSE1_1,
+        PSE0_0,  PSE0_1,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+        /*PTA*/
+        D23_MARK,       KEYOUT2_MARK,           IDED15_MARK,
+        D22_MARK,       KEYOUT1_MARK,           IDED14_MARK,
+        D21_MARK,       KEYOUT0_MARK,           IDED13_MARK,
+        D20_MARK,       KEYIN4_MARK,            IDED12_MARK,
+        D19_MARK,       KEYIN3_MARK,            IDED11_MARK,
+        D18_MARK,       KEYIN2_MARK,            IDED10_MARK,
+        D17_MARK,       KEYIN1_MARK,            IDED9_MARK,
+        D16_MARK,       KEYIN0_MARK,            IDED8_MARK,
+
+        /*PTB*/
+        D31_MARK,       TPUTO1_MARK,            IDEA1_MARK,
+        D30_MARK,       TPUTO0_MARK,            IDEA0_MARK,
+        D29_MARK,                               IODREQ_MARK,
+        D28_MARK,                               IDECS0_MARK,
+        D27_MARK,                               IDECS1_MARK,
+        D26_MARK,       KEYOUT5_IN5_MARK,       IDEIORD_MARK,
+        D25_MARK,       KEYOUT4_IN6_MARK,       IDEIOWR_MARK,
+        D24_MARK,       KEYOUT3_MARK,           IDEINT_MARK,
+
+        /*PTC*/
+        LCDD7_MARK,
+        LCDD6_MARK,
+        LCDD5_MARK,
+        LCDD4_MARK,
+        LCDD3_MARK,
+        LCDD2_MARK,
+        LCDD1_MARK,
+        LCDD0_MARK,
+
+        /*PTD*/
+        LCDD15_MARK,
+        LCDD14_MARK,
+        LCDD13_MARK,
+        LCDD12_MARK,
+        LCDD11_MARK,
+        LCDD10_MARK,
+        LCDD9_MARK,
+        LCDD8_MARK,
+
+        /*PTE*/
+        FSIMCKB_MARK,
+        FSIMCKA_MARK,
+        LCDD21_MARK,    SCIF2_L_TXD_MARK,
+        LCDD20_MARK,    SCIF4_SCK_MARK,
+        LCDD19_MARK,    SCIF4_RXD_MARK,
+        LCDD18_MARK,    SCIF4_TXD_MARK,
+        LCDD17_MARK,
+        LCDD16_MARK,
+
+        /*PTF*/
+        LCDVSYN_MARK,
+        LCDDISP_MARK,   LCDRS_MARK,
+        LCDHSYN_MARK,   LCDCS_MARK,
+        LCDDON_MARK,
+        LCDDCK_MARK,    LCDWR_MARK,
+        LCDVEPWC_MARK,  SCIF0_TXD_MARK,
+        LCDD23_MARK,    SCIF2_L_SCK_MARK,
+        LCDD22_MARK,    SCIF2_L_RXD_MARK,
+
+        /*PTG*/
+        AUDCK_MARK,
+        AUDSYNC_MARK,
+        AUDATA3_MARK,
+        AUDATA2_MARK,
+        AUDATA1_MARK,
+        AUDATA0_MARK,
+
+        /*PTH*/
+        VIO0_VD_MARK,
+        VIO0_CLK_MARK,
+        VIO0_D7_MARK,
+        VIO0_D6_MARK,
+        VIO0_D5_MARK,
+        VIO0_D4_MARK,
+        VIO0_D3_MARK,
+        VIO0_D2_MARK,
+
+        /*PTJ*/
+        PDSTATUS_MARK,
+        STATUS2_MARK,
+        STATUS0_MARK,
+        A25_MARK,               BS_MARK,
+        A24_MARK,
+        A23_MARK,
+        A22_MARK,
+
+        /*PTK*/
+        VIO1_D5_MARK,   VIO0_D13_MARK,  IDED5_MARK,
+        VIO1_D4_MARK,   VIO0_D12_MARK,  IDED4_MARK,
+        VIO1_D3_MARK,   VIO0_D11_MARK,  IDED3_MARK,
+        VIO1_D2_MARK,   VIO0_D10_MARK,  IDED2_MARK,
+        VIO1_D1_MARK,   VIO0_D9_MARK,   IDED1_MARK,
+        VIO1_D0_MARK,   VIO0_D8_MARK,   IDED0_MARK,
+        VIO0_FLD_MARK,
+        VIO0_HD_MARK,
+
+        /*PTL*/
+        DV_D5_MARK,     SCIF3_V_SCK_MARK,       RMII_RXD0_MARK,
+        DV_D4_MARK,     SCIF3_V_RXD_MARK,       RMII_RXD1_MARK,
+        DV_D3_MARK,     SCIF3_V_TXD_MARK,       RMII_REF_CLK_MARK,
+        DV_D2_MARK,     SCIF1_SCK_MARK,         RMII_TX_EN_MARK,
+        DV_D1_MARK,     SCIF1_RXD_MARK,         RMII_TXD0_MARK,
+        DV_D0_MARK,     SCIF1_TXD_MARK,         RMII_TXD1_MARK,
+        DV_D15_MARK,
+        DV_D14_MARK,    MSIOF0_MCK_MARK,
+
+        /*PTM*/
+        DV_D13_MARK,    MSIOF0_TSCK_MARK,
+        DV_D12_MARK,    MSIOF0_RXD_MARK,
+        DV_D11_MARK,    MSIOF0_TXD_MARK,
+        DV_D10_MARK,    MSIOF0_TSYNC_MARK,
+        DV_D9_MARK,     MSIOF0_SS1_MARK,        MSIOF0_RSCK_MARK,
+        DV_D8_MARK,     MSIOF0_SS2_MARK,        MSIOF0_RSYNC_MARK,
+        LCDVCPWC_MARK,  SCIF0_RXD_MARK,
+        LCDRD_MARK,     SCIF0_SCK_MARK,
+
+        /*PTN*/
+        VIO0_D1_MARK,
+        VIO0_D0_MARK,
+        DV_CLKI_MARK,
+        DV_CLK_MARK,    SCIF2_V_SCK_MARK,
+        DV_VSYNC_MARK,  SCIF2_V_RXD_MARK,
+        DV_HSYNC_MARK,  SCIF2_V_TXD_MARK,
+        DV_D7_MARK,     SCIF3_V_CTS_MARK,       RMII_RX_ER_MARK,
+        DV_D6_MARK,     SCIF3_V_RTS_MARK,       RMII_CRS_DV_MARK,
+
+        /*PTQ*/
+        D7_MARK,
+        D6_MARK,
+        D5_MARK,
+        D4_MARK,
+        D3_MARK,
+        D2_MARK,
+        D1_MARK,
+        D0_MARK,
+
+        /*PTR*/
+        CS6B_CE1B_MARK,
+        CS6A_CE2B_MARK,
+        CS5B_CE1A_MARK,
+        CS5A_CE2A_MARK,
+        IOIS16_MARK,            LCDLCLK_MARK,
+        WAIT_MARK,
+        WE3_ICIOWR_MARK,        TPUTO3_MARK,    TPUTI3_MARK,
+        WE2_ICIORD_MARK,        TPUTO2_MARK,    IDEA2_MARK,
+
+        /*PTS*/
+        VIO_CKO_MARK,
+        VIO1_FLD_MARK,  TPUTI2_MARK,            IDEIORDY_MARK,
+        VIO1_HD_MARK,   SCIF5_SCK_MARK,
+        VIO1_VD_MARK,   SCIF5_RXD_MARK,
+        VIO1_CLK_MARK,  SCIF5_TXD_MARK,
+        VIO1_D7_MARK,   VIO0_D15_MARK,          IDED7_MARK,
+        VIO1_D6_MARK,   VIO0_D14_MARK,          IDED6_MARK,
+
+        /*PTT*/
+        D15_MARK,
+        D14_MARK,
+        D13_MARK,
+        D12_MARK,
+        D11_MARK,
+        D10_MARK,
+        D9_MARK,
+        D8_MARK,
+
+        /*PTU*/
+        DMAC_DACK0_MARK,
+        DMAC_DREQ0_MARK,
+        FSIOASD_MARK,
+        FSIIABCK_MARK,
+        FSIIALRCK_MARK,
+        FSIOABCK_MARK,
+        FSIOALRCK_MARK,
+        CLKAUDIOAO_MARK,
+
+        /*PTV*/
+        FSIIBSD_MARK,           MSIOF1_SS2_MARK,        MSIOF1_RSYNC_MARK,
+        FSIOBSD_MARK,           MSIOF1_SS1_MARK,        MSIOF1_RSCK_MARK,
+        FSIIBBCK_MARK,          MSIOF1_RXD_MARK,
+        FSIIBLRCK_MARK,         MSIOF1_TSYNC_MARK,
+        FSIOBBCK_MARK,          MSIOF1_TSCK_MARK,
+        FSIOBLRCK_MARK,         MSIOF1_TXD_MARK,
+        CLKAUDIOBO_MARK,        MSIOF1_MCK_MARK,
+        FSIIASD_MARK,
+
+        /*PTW*/
+        MMC_D7_MARK,            SDHI1CD_MARK,           IODACK_MARK,
+        MMC_D6_MARK,            SDHI1WP_MARK,           IDERST_MARK,
+        MMC_D5_MARK,            SDHI1D3_MARK,           EXBUF_ENB_MARK,
+        MMC_D4_MARK,            SDHI1D2_MARK,           DIRECTION_MARK,
+        MMC_D3_MARK,            SDHI1D1_MARK,
+        MMC_D2_MARK,            SDHI1D0_MARK,
+        MMC_D1_MARK,            SDHI1CMD_MARK,
+        MMC_D0_MARK,            SDHI1CLK_MARK,
+
+        /*PTX*/
+        DMAC_DACK1_MARK,        IRDA_OUT_MARK,
+        DMAC_DREQ1_MARK,        IRDA_IN_MARK,
+        TSIF_TS0_SDAT_MARK,                             LNKSTA_MARK,
+        TSIF_TS0_SCK_MARK,                              MDIO_MARK,
+        TSIF_TS0_SDEN_MARK,                             MDC_MARK,
+        TSIF_TS0_SPSYNC_MARK,
+        MMC_CLK_MARK,
+        MMC_CMD_MARK,
+
+        /*PTY*/
+        SDHI0CD_MARK,
+        SDHI0WP_MARK,
+        SDHI0D3_MARK,
+        SDHI0D2_MARK,
+        SDHI0D1_MARK,
+        SDHI0D0_MARK,
+        SDHI0CMD_MARK,
+        SDHI0CLK_MARK,
+
+        /*PTZ*/
+        INTC_IRQ7_MARK,         SCIF3_I_CTS_MARK,
+        INTC_IRQ6_MARK,         SCIF3_I_RTS_MARK,
+        INTC_IRQ5_MARK,         SCIF3_I_SCK_MARK,
+        INTC_IRQ4_MARK,         SCIF3_I_RXD_MARK,
+        INTC_IRQ3_MARK,         SCIF3_I_TXD_MARK,
+        INTC_IRQ2_MARK,
+        INTC_IRQ1_MARK,
+        INTC_IRQ0_MARK,
+        PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+        /* PTA GPIO */
+        PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
+        PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
+        PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU),
+        PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU),
+        PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU),
+        PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU),
+        PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU),
+        PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU),
+
+        /* PTB GPIO */
+        PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU),
+        PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU),
+        PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU),
+        PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU),
+        PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU),
+        PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU),
+        PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU),
+        PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU),
+
+        /* PTC GPIO */
+        PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU),
+        PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU),
+        PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU),
+        PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU),
+        PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU),
+        PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU),
+        PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU),
+        PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU),
+
+        /* PTD GPIO */
+        PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU),
+        PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU),
+        PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU),
+        PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU),
+        PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU),
+        PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU),
+        PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU),
+        PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU),
+
+        /* PTE GPIO */
+        PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT, PTE7_IN_PU),
+        PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT, PTE6_IN_PU),
+        PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT, PTE5_IN_PU),
+        PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU),
+        PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU),
+        PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU),
+        PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU),
+        PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU),
+
+        /* PTF GPIO */
+        PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT, PTF7_IN_PU),
+        PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT, PTF6_IN_PU),
+        PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT, PTF5_IN_PU),
+        PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT, PTF4_IN_PU),
+        PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT, PTF3_IN_PU),
+        PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT, PTF2_IN_PU),
+        PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT, PTF1_IN_PU),
+        PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU),
+
+        /* PTG GPIO */
+        PINMUX_DATA(PTG5_DATA, PTG5_OUT),
+        PINMUX_DATA(PTG4_DATA, PTG4_OUT),
+        PINMUX_DATA(PTG3_DATA, PTG3_OUT),
+        PINMUX_DATA(PTG2_DATA, PTG2_OUT),
+        PINMUX_DATA(PTG1_DATA, PTG1_OUT),
+        PINMUX_DATA(PTG0_DATA, PTG0_OUT),
+
+        /* PTH GPIO */
+        PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT, PTH7_IN_PU),
+        PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU),
+        PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU),
+        PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU),
+        PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU),
+        PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU),
+        PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU),
+        PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU),
+
+        /* PTJ GPIO */
+        PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
+        PINMUX_DATA(PTJ6_DATA, PTJ6_OUT),
+        PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
+        PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU),
+        PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU),
+        PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU),
+        PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU),
+
+        /* PTK GPIO */
+        PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT, PTK7_IN_PU),
+        PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT, PTK6_IN_PU),
+        PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT, PTK5_IN_PU),
+        PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT, PTK4_IN_PU),
+        PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU),
+        PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU),
+        PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU),
+        PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU),
+
+        /* PTL GPIO */
+        PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU),
+        PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU),
+        PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU),
+        PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU),
+        PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU),
+        PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT, PTL2_IN_PU),
+        PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT, PTL1_IN_PU),
+        PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT, PTL0_IN_PU),
+
+        /* PTM GPIO */
+        PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU),
+        PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU),
+        PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU),
+        PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU),
+        PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU),
+        PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU),
+        PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU),
+        PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU),
+
+        /* PTN GPIO */
+        PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT, PTN7_IN_PU),
+        PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT, PTN6_IN_PU),
+        PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT, PTN5_IN_PU),
+        PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT, PTN4_IN_PU),
+        PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT, PTN3_IN_PU),
+        PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT, PTN2_IN_PU),
+        PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT, PTN1_IN_PU),
+        PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT, PTN0_IN_PU),
+
+        /* PTQ GPIO */
+        PINMUX_DATA(PTQ7_DATA, PTQ7_IN, PTQ7_OUT, PTQ7_IN_PU),
+        PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT, PTQ6_IN_PU),
+        PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT, PTQ5_IN_PU),
+        PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT, PTQ4_IN_PU),
+        PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT, PTQ3_IN_PU),
+        PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT, PTQ2_IN_PU),
+        PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT, PTQ1_IN_PU),
+        PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT, PTQ0_IN_PU),
+
+        /* PTR GPIO */
+        PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU),
+        PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU),
+        PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU),
+        PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU),
+        PINMUX_DATA(PTR3_DATA, PTR3_IN,           PTR3_IN_PU),
+        PINMUX_DATA(PTR2_DATA, PTR2_IN,           PTR2_IN_PU),
+        PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU),
+        PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU),
+
+        /* PTS GPIO */
+        PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT, PTS6_IN_PU),
+        PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT, PTS5_IN_PU),
+        PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU),
+        PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU),
+        PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU),
+        PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU),
+        PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU),
+
+        /* PTT GPIO */
+        PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT, PTT7_IN_PU),
+        PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT, PTT6_IN_PU),
+        PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT, PTT5_IN_PU),
+        PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU),
+        PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU),
+        PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU),
+        PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU),
+        PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU),
+
+        /* PTU GPIO */
+        PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT, PTU7_IN_PU),
+        PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT, PTU6_IN_PU),
+        PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT, PTU5_IN_PU),
+        PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU),
+        PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU),
+        PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU),
+        PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU),
+        PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU),
+
+        /* PTV GPIO */
+        PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT, PTV7_IN_PU),
+        PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT, PTV6_IN_PU),
+        PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT, PTV5_IN_PU),
+        PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU),
+        PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU),
+        PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU),
+        PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU),
+        PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU),
+
+        /* PTW GPIO */
+        PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT, PTW7_IN_PU),
+        PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT, PTW6_IN_PU),
+        PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT, PTW5_IN_PU),
+        PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT, PTW4_IN_PU),
+        PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT, PTW3_IN_PU),
+        PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT, PTW2_IN_PU),
+        PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT, PTW1_IN_PU),
+        PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT, PTW0_IN_PU),
+
+        /* PTX GPIO */
+        PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT, PTX7_IN_PU),
+        PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT, PTX6_IN_PU),
+        PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT, PTX5_IN_PU),
+        PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT, PTX4_IN_PU),
+        PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT, PTX3_IN_PU),
+        PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT, PTX2_IN_PU),
+        PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT, PTX1_IN_PU),
+        PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT, PTX0_IN_PU),
+
+        /* PTY GPIO */
+        PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT, PTY7_IN_PU),
+        PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT, PTY6_IN_PU),
+        PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT, PTY5_IN_PU),
+        PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT, PTY4_IN_PU),
+        PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT, PTY3_IN_PU),
+        PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT, PTY2_IN_PU),
+        PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT, PTY1_IN_PU),
+        PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT, PTY0_IN_PU),
+
+        /* PTZ GPIO */
+        PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT, PTZ7_IN_PU),
+        PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT, PTZ6_IN_PU),
+        PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT, PTZ5_IN_PU),
+        PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT, PTZ4_IN_PU),
+        PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT, PTZ3_IN_PU),
+        PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT, PTZ2_IN_PU),
+        PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT, PTZ1_IN_PU),
+        PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT, PTZ0_IN_PU),
+
+        /* PTA FN */
+        PINMUX_DATA(D23_MARK,   PSA15_0, PSA14_0, PTA7_FN),
+        PINMUX_DATA(D22_MARK,   PSA15_0, PSA14_0, PTA6_FN),
+        PINMUX_DATA(D21_MARK,   PSA15_0, PSA14_0, PTA5_FN),
+        PINMUX_DATA(D20_MARK,   PSA15_0, PSA14_0, PTA4_FN),
+        PINMUX_DATA(D19_MARK,   PSA15_0, PSA14_0, PTA3_FN),
+        PINMUX_DATA(D18_MARK,   PSA15_0, PSA14_0, PTA2_FN),
+        PINMUX_DATA(D17_MARK,   PSA15_0, PSA14_0, PTA1_FN),
+        PINMUX_DATA(D16_MARK,   PSA15_0, PSA14_0, PTA0_FN),
+
+        PINMUX_DATA(KEYOUT2_MARK,       PSA15_0, PSA14_1, PTA7_FN),
+        PINMUX_DATA(KEYOUT1_MARK,       PSA15_0, PSA14_1, PTA6_FN),
+        PINMUX_DATA(KEYOUT0_MARK,       PSA15_0, PSA14_1, PTA5_FN),
+        PINMUX_DATA(KEYIN4_MARK,        PSA15_0, PSA14_1, PTA4_FN),
+        PINMUX_DATA(KEYIN3_MARK,        PSA15_0, PSA14_1, PTA3_FN),
+        PINMUX_DATA(KEYIN2_MARK,        PSA15_0, PSA14_1, PTA2_FN),
+        PINMUX_DATA(KEYIN1_MARK,        PSA15_0, PSA14_1, PTA1_FN),
+        PINMUX_DATA(KEYIN0_MARK,        PSA15_0, PSA14_1, PTA0_FN),
+
+        PINMUX_DATA(IDED15_MARK,        PSA15_1, PSA14_0, PTA7_FN),
+        PINMUX_DATA(IDED14_MARK,        PSA15_1, PSA14_0, PTA6_FN),
+        PINMUX_DATA(IDED13_MARK,        PSA15_1, PSA14_0, PTA5_FN),
+        PINMUX_DATA(IDED12_MARK,        PSA15_1, PSA14_0, PTA4_FN),
+        PINMUX_DATA(IDED11_MARK,        PSA15_1, PSA14_0, PTA3_FN),
+        PINMUX_DATA(IDED10_MARK,        PSA15_1, PSA14_0, PTA2_FN),
+        PINMUX_DATA(IDED9_MARK,         PSA15_1, PSA14_0, PTA1_FN),
+        PINMUX_DATA(IDED8_MARK,         PSA15_1, PSA14_0, PTA0_FN),
+
+        /* PTB FN */
+        PINMUX_DATA(D31_MARK,           PSE15_0, PSE14_0, PTB7_FN),
+        PINMUX_DATA(D30_MARK,           PSE15_0, PSE14_0, PTB6_FN),
+        PINMUX_DATA(D29_MARK,           PSE11_0,          PTB5_FN),
+        PINMUX_DATA(D28_MARK,           PSE11_0,          PTB4_FN),
+        PINMUX_DATA(D27_MARK,           PSE11_0,          PTB3_FN),
+        PINMUX_DATA(D26_MARK,           PSA15_0, PSA14_0, PTB2_FN),
+        PINMUX_DATA(D25_MARK,           PSA15_0, PSA14_0, PTB1_FN),
+        PINMUX_DATA(D24_MARK,           PSA15_0, PSA14_0, PTB0_FN),
+
+        PINMUX_DATA(IDEA1_MARK,         PSE15_1, PSE14_0, PTB7_FN),
+        PINMUX_DATA(IDEA0_MARK,         PSE15_1, PSE14_0, PTB6_FN),
+        PINMUX_DATA(IODREQ_MARK,        PSE11_1,          PTB5_FN),
+        PINMUX_DATA(IDECS0_MARK,        PSE11_1,          PTB4_FN),
+        PINMUX_DATA(IDECS1_MARK,        PSE11_1,          PTB3_FN),
+        PINMUX_DATA(IDEIORD_MARK,       PSA15_1, PSA14_0, PTB2_FN),
+        PINMUX_DATA(IDEIOWR_MARK,       PSA15_1, PSA14_0, PTB1_FN),
+        PINMUX_DATA(IDEINT_MARK,        PSA15_1, PSA14_0, PTB0_FN),
+
+        PINMUX_DATA(TPUTO1_MARK,        PSE15_0, PSE14_1, PTB7_FN),
+        PINMUX_DATA(TPUTO0_MARK,        PSE15_0, PSE14_1, PTB6_FN),
+
+        PINMUX_DATA(KEYOUT5_IN5_MARK,   PSA15_0, PSA14_1, PTB2_FN),
+        PINMUX_DATA(KEYOUT4_IN6_MARK,   PSA15_0, PSA14_1, PTB1_FN),
+        PINMUX_DATA(KEYOUT3_MARK,       PSA15_0, PSA14_1, PTB0_FN),
+
+        /* PTC FN */
+        PINMUX_DATA(LCDD7_MARK, PSD5_0, PTC7_FN),
+        PINMUX_DATA(LCDD6_MARK, PSD5_0, PTC6_FN),
+        PINMUX_DATA(LCDD5_MARK, PSD5_0, PTC5_FN),
+        PINMUX_DATA(LCDD4_MARK, PSD5_0, PTC4_FN),
+        PINMUX_DATA(LCDD3_MARK, PSD5_0, PTC3_FN),
+        PINMUX_DATA(LCDD2_MARK, PSD5_0, PTC2_FN),
+        PINMUX_DATA(LCDD1_MARK, PSD5_0, PTC1_FN),
+        PINMUX_DATA(LCDD0_MARK, PSD5_0, PTC0_FN),
+
+        /* PTD FN */
+        PINMUX_DATA(LCDD15_MARK, PSD5_0, PTD7_FN),
+        PINMUX_DATA(LCDD14_MARK, PSD5_0, PTD6_FN),
+        PINMUX_DATA(LCDD13_MARK, PSD5_0, PTD5_FN),
+        PINMUX_DATA(LCDD12_MARK, PSD5_0, PTD4_FN),
+        PINMUX_DATA(LCDD11_MARK, PSD5_0, PTD3_FN),
+        PINMUX_DATA(LCDD10_MARK, PSD5_0, PTD2_FN),
+        PINMUX_DATA(LCDD9_MARK,  PSD5_0, PTD1_FN),
+        PINMUX_DATA(LCDD8_MARK,  PSD5_0, PTD0_FN),
+
+        /* PTE FN */
+        PINMUX_DATA(FSIMCKB_MARK, PTE7_FN),
+        PINMUX_DATA(FSIMCKA_MARK, PTE6_FN),
+
+        PINMUX_DATA(LCDD21_MARK,        PSC5_0, PSC4_0, PTE5_FN),
+        PINMUX_DATA(LCDD20_MARK,        PSD3_0, PSD2_0, PTE4_FN),
+        PINMUX_DATA(LCDD19_MARK,        PSA3_0, PSA2_0, PTE3_FN),
+        PINMUX_DATA(LCDD18_MARK,        PSA3_0, PSA2_0, PTE2_FN),
+        PINMUX_DATA(LCDD17_MARK,        PSD5_0,         PTE1_FN),
+        PINMUX_DATA(LCDD16_MARK,        PSD5_0,         PTE0_FN),
+
+        PINMUX_DATA(SCIF2_L_TXD_MARK,   PSC5_0, PSC4_1, PTE5_FN),
+        PINMUX_DATA(SCIF4_SCK_MARK,     PSD3_0, PSD2_1, PTE4_FN),
+        PINMUX_DATA(SCIF4_RXD_MARK,     PSA3_0, PSA2_1, PTE3_FN),
+        PINMUX_DATA(SCIF4_TXD_MARK,     PSA3_0, PSA2_1, PTE2_FN),
+
+        /* PTF FN */
+        PINMUX_DATA(LCDVSYN_MARK,       PSD8_0,          PTF7_FN),
+        PINMUX_DATA(LCDDISP_MARK,       PSD10_0, PSD9_0, PTF6_FN),
+        PINMUX_DATA(LCDHSYN_MARK,       PSD10_0, PSD9_0, PTF5_FN),
+        PINMUX_DATA(LCDDON_MARK,        PSD8_0,          PTF4_FN),
+        PINMUX_DATA(LCDDCK_MARK,        PSD10_0, PSD9_0, PTF3_FN),
+        PINMUX_DATA(LCDVEPWC_MARK,      PSA6_0,          PTF2_FN),
+        PINMUX_DATA(LCDD23_MARK,        PSC7_0,  PSC6_0, PTF1_FN),
+        PINMUX_DATA(LCDD22_MARK,        PSC5_0,  PSC4_0, PTF0_FN),
+
+        PINMUX_DATA(LCDRS_MARK,         PSD10_0, PSD9_1, PTF6_FN),
+        PINMUX_DATA(LCDCS_MARK,         PSD10_0, PSD9_1, PTF5_FN),
+        PINMUX_DATA(LCDWR_MARK,         PSD10_0, PSD9_1, PTF3_FN),
+
+        PINMUX_DATA(SCIF0_TXD_MARK,     PSA6_1,          PTF2_FN),
+        PINMUX_DATA(SCIF2_L_SCK_MARK,   PSC7_0,  PSC6_1, PTF1_FN),
+        PINMUX_DATA(SCIF2_L_RXD_MARK,   PSC5_0,  PSC4_1, PTF0_FN),
+
+        /* PTG FN */
+        PINMUX_DATA(AUDCK_MARK,   PTG5_FN),
+        PINMUX_DATA(AUDSYNC_MARK, PTG4_FN),
+        PINMUX_DATA(AUDATA3_MARK, PTG3_FN),
+        PINMUX_DATA(AUDATA2_MARK, PTG2_FN),
+        PINMUX_DATA(AUDATA1_MARK, PTG1_FN),
+        PINMUX_DATA(AUDATA0_MARK, PTG0_FN),
+
+        /* PTH FN */
+        PINMUX_DATA(VIO0_VD_MARK,  PTH7_FN),
+        PINMUX_DATA(VIO0_CLK_MARK, PTH6_FN),
+        PINMUX_DATA(VIO0_D7_MARK,  PTH5_FN),
+        PINMUX_DATA(VIO0_D6_MARK,  PTH4_FN),
+        PINMUX_DATA(VIO0_D5_MARK,  PTH3_FN),
+        PINMUX_DATA(VIO0_D4_MARK,  PTH2_FN),
+        PINMUX_DATA(VIO0_D3_MARK,  PTH1_FN),
+        PINMUX_DATA(VIO0_D2_MARK,  PTH0_FN),
+
+        /* PTJ FN */
+        PINMUX_DATA(PDSTATUS_MARK,      PTJ7_FN),
+        PINMUX_DATA(STATUS2_MARK,       PTJ6_FN),
+        PINMUX_DATA(STATUS0_MARK,       PTJ5_FN),
+        PINMUX_DATA(A25_MARK,           PSA8_0, PTJ3_FN),
+        PINMUX_DATA(BS_MARK,            PSA8_1, PTJ3_FN),
+        PINMUX_DATA(A24_MARK,           PTJ2_FN),
+        PINMUX_DATA(A23_MARK,           PTJ1_FN),
+        PINMUX_DATA(A22_MARK,           PTJ0_FN),
+
+        /* PTK FN */
+        PINMUX_DATA(VIO1_D5_MARK,       PSB7_0, PSB6_0, PTK7_FN),
+        PINMUX_DATA(VIO1_D4_MARK,       PSB7_0, PSB6_0, PTK6_FN),
+        PINMUX_DATA(VIO1_D3_MARK,       PSB7_0, PSB6_0, PTK5_FN),
+        PINMUX_DATA(VIO1_D2_MARK,       PSB7_0, PSB6_0, PTK4_FN),
+        PINMUX_DATA(VIO1_D1_MARK,       PSB7_0, PSB6_0, PTK3_FN),
+        PINMUX_DATA(VIO1_D0_MARK,       PSB7_0, PSB6_0, PTK2_FN),
+
+        PINMUX_DATA(VIO0_D13_MARK,      PSB7_0, PSB6_1, PTK7_FN),
+        PINMUX_DATA(VIO0_D12_MARK,      PSB7_0, PSB6_1, PTK6_FN),
+        PINMUX_DATA(VIO0_D11_MARK,      PSB7_0, PSB6_1, PTK5_FN),
+        PINMUX_DATA(VIO0_D10_MARK,      PSB7_0, PSB6_1, PTK4_FN),
+        PINMUX_DATA(VIO0_D9_MARK,       PSB7_0, PSB6_1, PTK3_FN),
+        PINMUX_DATA(VIO0_D8_MARK,       PSB7_0, PSB6_1, PTK2_FN),
+
+        PINMUX_DATA(IDED5_MARK,         PSB7_1, PSB6_0, PTK7_FN),
+        PINMUX_DATA(IDED4_MARK,         PSB7_1, PSB6_0, PTK6_FN),
+        PINMUX_DATA(IDED3_MARK,         PSB7_1, PSB6_0, PTK5_FN),
+        PINMUX_DATA(IDED2_MARK,         PSB7_1, PSB6_0, PTK4_FN),
+        PINMUX_DATA(IDED1_MARK,         PSB7_1, PSB6_0, PTK3_FN),
+        PINMUX_DATA(IDED0_MARK,         PSB7_1, PSB6_0, PTK2_FN),
+
+        PINMUX_DATA(VIO0_FLD_MARK,      PTK1_FN),
+        PINMUX_DATA(VIO0_HD_MARK,       PTK0_FN),
+
+        /* PTL FN */
+        PINMUX_DATA(DV_D5_MARK,         PSB9_0, PSB8_0, PTL7_FN),
+        PINMUX_DATA(DV_D4_MARK,         PSB9_0, PSB8_0, PTL6_FN),
+        PINMUX_DATA(DV_D3_MARK,         PSE7_0, PSE6_0, PTL5_FN),
+        PINMUX_DATA(DV_D2_MARK,         PSC9_0, PSC8_0, PTL4_FN),
+        PINMUX_DATA(DV_D1_MARK,         PSC9_0, PSC8_0, PTL3_FN),
+        PINMUX_DATA(DV_D0_MARK,         PSC9_0, PSC8_0, PTL2_FN),
+        PINMUX_DATA(DV_D15_MARK,        PSD4_0,         PTL1_FN),
+        PINMUX_DATA(DV_D14_MARK,        PSE5_0, PSE4_0, PTL0_FN),
+
+        PINMUX_DATA(SCIF3_V_SCK_MARK,   PSB9_0, PSB8_1, PTL7_FN),
+        PINMUX_DATA(SCIF3_V_RXD_MARK,   PSB9_0, PSB8_1, PTL6_FN),
+        PINMUX_DATA(SCIF3_V_TXD_MARK,   PSE7_0, PSE6_1, PTL5_FN),
+        PINMUX_DATA(SCIF1_SCK_MARK,     PSC9_0, PSC8_1, PTL4_FN),
+        PINMUX_DATA(SCIF1_RXD_MARK,     PSC9_0, PSC8_1, PTL3_FN),
+        PINMUX_DATA(SCIF1_TXD_MARK,     PSC9_0, PSC8_1, PTL2_FN),
+
+        PINMUX_DATA(RMII_RXD0_MARK,     PSB9_1, PSB8_0, PTL7_FN),
+        PINMUX_DATA(RMII_RXD1_MARK,     PSB9_1, PSB8_0, PTL6_FN),
+        PINMUX_DATA(RMII_REF_CLK_MARK,  PSE7_1, PSE6_0, PTL5_FN),
+        PINMUX_DATA(RMII_TX_EN_MARK,    PSC9_1, PSC8_0, PTL4_FN),
+        PINMUX_DATA(RMII_TXD0_MARK,     PSC9_1, PSC8_0, PTL3_FN),
+        PINMUX_DATA(RMII_TXD1_MARK,     PSC9_1, PSC8_0, PTL2_FN),
+
+        PINMUX_DATA(MSIOF0_MCK_MARK,    PSE5_0, PSE4_1, PTL0_FN),
+
+        /* PTM FN */
+        PINMUX_DATA(DV_D13_MARK,        PSC13_0, PSC12_0, PTM7_FN),
+        PINMUX_DATA(DV_D12_MARK,        PSC13_0, PSC12_0, PTM6_FN),
+        PINMUX_DATA(DV_D11_MARK,        PSC13_0, PSC12_0, PTM5_FN),
+        PINMUX_DATA(DV_D10_MARK,        PSC13_0, PSC12_0, PTM4_FN),
+        PINMUX_DATA(DV_D9_MARK,         PSC11_0, PSC10_0, PTM3_FN),
+        PINMUX_DATA(DV_D8_MARK,         PSC11_0, PSC10_0, PTM2_FN),
+
+        PINMUX_DATA(MSIOF0_TSCK_MARK,   PSC13_0, PSC12_1, PTM7_FN),
+        PINMUX_DATA(MSIOF0_RXD_MARK,    PSC13_0, PSC12_1, PTM6_FN),
+        PINMUX_DATA(MSIOF0_TXD_MARK,    PSC13_0, PSC12_1, PTM5_FN),
+        PINMUX_DATA(MSIOF0_TSYNC_MARK,  PSC13_0, PSC12_1, PTM4_FN),
+        PINMUX_DATA(MSIOF0_SS1_MARK,    PSC11_0, PSC10_1, PTM3_FN),
+        PINMUX_DATA(MSIOF0_RSCK_MARK,   PSC11_1, PSC10_0, PTM3_FN),
+        PINMUX_DATA(MSIOF0_SS2_MARK,    PSC11_0, PSC10_1, PTM2_FN),
+        PINMUX_DATA(MSIOF0_RSYNC_MARK,  PSC11_1, PSC10_0, PTM2_FN),
+
+        PINMUX_DATA(LCDVCPWC_MARK,      PSA6_0, PTM1_FN),
+        PINMUX_DATA(LCDRD_MARK,         PSA7_0, PTM0_FN),
+
+        PINMUX_DATA(SCIF0_RXD_MARK,     PSA6_1, PTM1_FN),
+        PINMUX_DATA(SCIF0_SCK_MARK,     PSA7_1, PTM0_FN),
+
+        /* PTN FN */
+        PINMUX_DATA(VIO0_D1_MARK,       PTN7_FN),
+        PINMUX_DATA(VIO0_D0_MARK,       PTN6_FN),
+
+        PINMUX_DATA(DV_CLKI_MARK,       PSD11_0,          PTN5_FN),
+        PINMUX_DATA(DV_CLK_MARK,        PSD13_0, PSD12_0, PTN4_FN),
+        PINMUX_DATA(DV_VSYNC_MARK,      PSD15_0, PSD14_0, PTN3_FN),
+        PINMUX_DATA(DV_HSYNC_MARK,      PSB5_0,  PSB4_0,  PTN2_FN),
+        PINMUX_DATA(DV_D7_MARK,         PSB3_0,  PSB2_0,  PTN1_FN),
+        PINMUX_DATA(DV_D6_MARK,         PSB1_0,  PSB0_0,  PTN0_FN),
+
+        PINMUX_DATA(SCIF2_V_SCK_MARK,   PSD13_0, PSD12_1, PTN4_FN),
+        PINMUX_DATA(SCIF2_V_RXD_MARK,   PSD15_0, PSD14_1, PTN3_FN),
+        PINMUX_DATA(SCIF2_V_TXD_MARK,   PSB5_0,  PSB4_1,  PTN2_FN),
+        PINMUX_DATA(SCIF3_V_CTS_MARK,   PSB3_0,  PSB2_1,  PTN1_FN),
+        PINMUX_DATA(SCIF3_V_RTS_MARK,   PSB1_0,  PSB0_1,  PTN0_FN),
+
+        PINMUX_DATA(RMII_RX_ER_MARK,    PSB3_1, PSB2_0, PTN1_FN),
+        PINMUX_DATA(RMII_CRS_DV_MARK,   PSB1_1, PSB0_0, PTN0_FN),
+
+        /* PTQ FN */
+        PINMUX_DATA(D7_MARK, PTQ7_FN),
+        PINMUX_DATA(D6_MARK, PTQ6_FN),
+        PINMUX_DATA(D5_MARK, PTQ5_FN),
+        PINMUX_DATA(D4_MARK, PTQ4_FN),
+        PINMUX_DATA(D3_MARK, PTQ3_FN),
+        PINMUX_DATA(D2_MARK, PTQ2_FN),
+        PINMUX_DATA(D1_MARK, PTQ1_FN),
+        PINMUX_DATA(D0_MARK, PTQ0_FN),
+
+        /* PTR FN */
+        PINMUX_DATA(CS6B_CE1B_MARK,                     PTR7_FN),
+        PINMUX_DATA(CS6A_CE2B_MARK,                     PTR6_FN),
+        PINMUX_DATA(CS5B_CE1A_MARK,                     PTR5_FN),
+        PINMUX_DATA(CS5A_CE2A_MARK,                     PTR4_FN),
+        PINMUX_DATA(IOIS16_MARK,        PSA5_0,         PTR3_FN),
+        PINMUX_DATA(WAIT_MARK,                          PTR2_FN),
+        PINMUX_DATA(WE3_ICIOWR_MARK,    PSA1_0, PSA0_0, PTR1_FN),
+        PINMUX_DATA(WE2_ICIORD_MARK,    PSD1_0, PSD0_0, PTR0_FN),
+
+        PINMUX_DATA(LCDLCLK_MARK,       PSA5_1,         PTR3_FN),
+
+        PINMUX_DATA(IDEA2_MARK,         PSD1_1, PSD0_0, PTR0_FN),
+
+        PINMUX_DATA(TPUTO3_MARK,        PSA1_0, PSA0_1, PTR1_FN),
+        PINMUX_DATA(TPUTI3_MARK,        PSA1_1, PSA0_0, PTR1_FN),
+        PINMUX_DATA(TPUTO2_MARK,        PSD1_0, PSD0_1, PTR0_FN),
+
+        /* PTS FN */
+        PINMUX_DATA(VIO_CKO_MARK,       PTS6_FN),
+
+        PINMUX_DATA(TPUTI2_MARK,        PSE9_0, PSE8_1, PTS5_FN),
+
+        PINMUX_DATA(IDEIORDY_MARK,      PSE9_1, PSE8_0, PTS5_FN),
+
+        PINMUX_DATA(VIO1_FLD_MARK,      PSE9_0, PSE8_0, PTS5_FN),
+        PINMUX_DATA(VIO1_HD_MARK,       PSA10_0,        PTS4_FN),
+        PINMUX_DATA(VIO1_VD_MARK,       PSA9_0,         PTS3_FN),
+        PINMUX_DATA(VIO1_CLK_MARK,      PSA9_0,         PTS2_FN),
+        PINMUX_DATA(VIO1_D7_MARK,       PSB7_0, PSB6_0, PTS1_FN),
+        PINMUX_DATA(VIO1_D6_MARK,       PSB7_0, PSB6_0, PTS0_FN),
+
+        PINMUX_DATA(SCIF5_SCK_MARK,     PSA10_1, PTS4_FN),
+        PINMUX_DATA(SCIF5_RXD_MARK,     PSA9_1,  PTS3_FN),
+        PINMUX_DATA(SCIF5_TXD_MARK,     PSA9_1,  PTS2_FN),
+
+        PINMUX_DATA(VIO0_D15_MARK,      PSB7_0, PSB6_1, PTS1_FN),
+        PINMUX_DATA(VIO0_D14_MARK,      PSB7_0, PSB6_1, PTS0_FN),
+
+        PINMUX_DATA(IDED7_MARK,         PSB7_1, PSB6_0, PTS1_FN),
+        PINMUX_DATA(IDED6_MARK,         PSB7_1, PSB6_0, PTS0_FN),
+
+        /* PTT FN */
+        PINMUX_DATA(D15_MARK, PTT7_FN),
+        PINMUX_DATA(D14_MARK, PTT6_FN),
+        PINMUX_DATA(D13_MARK, PTT5_FN),
+        PINMUX_DATA(D12_MARK, PTT4_FN),
+        PINMUX_DATA(D11_MARK, PTT3_FN),
+        PINMUX_DATA(D10_MARK, PTT2_FN),
+        PINMUX_DATA(D9_MARK,  PTT1_FN),
+        PINMUX_DATA(D8_MARK,  PTT0_FN),
+
+        /* PTU FN */
+        PINMUX_DATA(DMAC_DACK0_MARK, PTU7_FN),
+        PINMUX_DATA(DMAC_DREQ0_MARK, PTU6_FN),
+
+        PINMUX_DATA(FSIOASD_MARK,       PSE1_0, PTU5_FN),
+        PINMUX_DATA(FSIIABCK_MARK,      PSE1_0, PTU4_FN),
+        PINMUX_DATA(FSIIALRCK_MARK,     PSE1_0, PTU3_FN),
+        PINMUX_DATA(FSIOABCK_MARK,      PSE1_0, PTU2_FN),
+        PINMUX_DATA(FSIOALRCK_MARK,     PSE1_0, PTU1_FN),
+        PINMUX_DATA(CLKAUDIOAO_MARK,    PSE0_0, PTU0_FN),
+
+        /* PTV FN */
+        PINMUX_DATA(FSIIBSD_MARK,       PSD7_0,  PSD6_0,  PTV7_FN),
+        PINMUX_DATA(FSIOBSD_MARK,       PSD7_0,  PSD6_0,  PTV6_FN),
+        PINMUX_DATA(FSIIBBCK_MARK,      PSC15_0, PSC14_0, PTV5_FN),
+        PINMUX_DATA(FSIIBLRCK_MARK,     PSC15_0, PSC14_0, PTV4_FN),
+        PINMUX_DATA(FSIOBBCK_MARK,      PSC15_0, PSC14_0, PTV3_FN),
+        PINMUX_DATA(FSIOBLRCK_MARK,     PSC15_0, PSC14_0, PTV2_FN),
+        PINMUX_DATA(CLKAUDIOBO_MARK,    PSE3_0,  PSE2_0,  PTV1_FN),
+        PINMUX_DATA(FSIIASD_MARK,       PSE10_0,          PTV0_FN),
+
+        PINMUX_DATA(MSIOF1_SS2_MARK,    PSD7_0,  PSD6_1,  PTV7_FN),
+        PINMUX_DATA(MSIOF1_RSYNC_MARK,  PSD7_1,  PSD6_0,  PTV7_FN),
+        PINMUX_DATA(MSIOF1_SS1_MARK,    PSD7_0,  PSD6_1,  PTV6_FN),
+        PINMUX_DATA(MSIOF1_RSCK_MARK,   PSD7_1,  PSD6_0,  PTV6_FN),
+        PINMUX_DATA(MSIOF1_RXD_MARK,    PSC15_0, PSC14_1, PTV5_FN),
+        PINMUX_DATA(MSIOF1_TSYNC_MARK,  PSC15_0, PSC14_1, PTV4_FN),
+        PINMUX_DATA(MSIOF1_TSCK_MARK,   PSC15_0, PSC14_1, PTV3_FN),
+        PINMUX_DATA(MSIOF1_TXD_MARK,    PSC15_0, PSC14_1, PTV2_FN),
+        PINMUX_DATA(MSIOF1_MCK_MARK,    PSE3_0,  PSE2_1,  PTV1_FN),
+
+        /* PTW FN */
+        PINMUX_DATA(MMC_D7_MARK,        PSE13_0, PSE12_0, PTW7_FN),
+        PINMUX_DATA(MMC_D6_MARK,        PSE13_0, PSE12_0, PTW6_FN),
+        PINMUX_DATA(MMC_D5_MARK,        PSE13_0, PSE12_0, PTW5_FN),
+        PINMUX_DATA(MMC_D4_MARK,        PSE13_0, PSE12_0, PTW4_FN),
+        PINMUX_DATA(MMC_D3_MARK,        PSA13_0,          PTW3_FN),
+        PINMUX_DATA(MMC_D2_MARK,        PSA13_0,          PTW2_FN),
+        PINMUX_DATA(MMC_D1_MARK,        PSA13_0,          PTW1_FN),
+        PINMUX_DATA(MMC_D0_MARK,        PSA13_0,          PTW0_FN),
+
+        PINMUX_DATA(SDHI1CD_MARK,       PSE13_0, PSE12_1, PTW7_FN),
+        PINMUX_DATA(SDHI1WP_MARK,       PSE13_0, PSE12_1, PTW6_FN),
+        PINMUX_DATA(SDHI1D3_MARK,       PSE13_0, PSE12_1, PTW5_FN),
+        PINMUX_DATA(SDHI1D2_MARK,       PSE13_0, PSE12_1, PTW4_FN),
+        PINMUX_DATA(SDHI1D1_MARK,       PSA13_1,          PTW3_FN),
+        PINMUX_DATA(SDHI1D0_MARK,       PSA13_1,          PTW2_FN),
+        PINMUX_DATA(SDHI1CMD_MARK,      PSA13_1,          PTW1_FN),
+        PINMUX_DATA(SDHI1CLK_MARK,      PSA13_1,          PTW0_FN),
+
+        PINMUX_DATA(IODACK_MARK,        PSE13_1, PSE12_0, PTW7_FN),
+        PINMUX_DATA(IDERST_MARK,        PSE13_1, PSE12_0, PTW6_FN),
+        PINMUX_DATA(EXBUF_ENB_MARK,     PSE13_1, PSE12_0, PTW5_FN),
+        PINMUX_DATA(DIRECTION_MARK,     PSE13_1, PSE12_0, PTW4_FN),
+
+        /* PTX FN */
+        PINMUX_DATA(DMAC_DACK1_MARK,    PSA12_0, PTX7_FN),
+        PINMUX_DATA(DMAC_DREQ1_MARK,    PSA12_0, PTX6_FN),
+
+        PINMUX_DATA(IRDA_OUT_MARK,      PSA12_1, PTX7_FN),
+        PINMUX_DATA(IRDA_IN_MARK,       PSA12_1, PTX6_FN),
+
+        PINMUX_DATA(TSIF_TS0_SDAT_MARK, PSC0_0, PTX5_FN),
+        PINMUX_DATA(TSIF_TS0_SCK_MARK,  PSC1_0, PTX4_FN),
+        PINMUX_DATA(TSIF_TS0_SDEN_MARK, PSC2_0, PTX3_FN),
+        PINMUX_DATA(TSIF_TS0_SPSYNC_MARK,       PTX2_FN),
+
+        PINMUX_DATA(LNKSTA_MARK,        PSC0_1, PTX5_FN),
+        PINMUX_DATA(MDIO_MARK,          PSC1_1, PTX4_FN),
+        PINMUX_DATA(MDC_MARK,           PSC2_1, PTX3_FN),
+
+        PINMUX_DATA(MMC_CLK_MARK, PTX1_FN),
+        PINMUX_DATA(MMC_CMD_MARK, PTX0_FN),
+
+        /* PTY FN */
+        PINMUX_DATA(SDHI0CD_MARK,  PTY7_FN),
+        PINMUX_DATA(SDHI0WP_MARK,  PTY6_FN),
+        PINMUX_DATA(SDHI0D3_MARK,  PTY5_FN),
+        PINMUX_DATA(SDHI0D2_MARK,  PTY4_FN),
+        PINMUX_DATA(SDHI0D1_MARK,  PTY3_FN),
+        PINMUX_DATA(SDHI0D0_MARK,  PTY2_FN),
+        PINMUX_DATA(SDHI0CMD_MARK, PTY1_FN),
+        PINMUX_DATA(SDHI0CLK_MARK, PTY0_FN),
+
+        /* PTZ FN */
+        PINMUX_DATA(INTC_IRQ7_MARK,     PSB10_0, PTZ7_FN),
+        PINMUX_DATA(INTC_IRQ6_MARK,     PSB11_0, PTZ6_FN),
+        PINMUX_DATA(INTC_IRQ5_MARK,     PSB12_0, PTZ5_FN),
+        PINMUX_DATA(INTC_IRQ4_MARK,     PSB13_0, PTZ4_FN),
+        PINMUX_DATA(INTC_IRQ3_MARK,     PSB14_0, PTZ3_FN),
+        PINMUX_DATA(INTC_IRQ2_MARK,              PTZ2_FN),
+        PINMUX_DATA(INTC_IRQ1_MARK,              PTZ1_FN),
+        PINMUX_DATA(INTC_IRQ0_MARK,              PTZ0_FN),
+
+        PINMUX_DATA(SCIF3_I_CTS_MARK,   PSB10_1, PTZ7_FN),
+        PINMUX_DATA(SCIF3_I_RTS_MARK,   PSB11_1, PTZ6_FN),
+        PINMUX_DATA(SCIF3_I_SCK_MARK,   PSB12_1, PTZ5_FN),
+        PINMUX_DATA(SCIF3_I_RXD_MARK,   PSB13_1, PTZ4_FN),
+        PINMUX_DATA(SCIF3_I_TXD_MARK,   PSB14_1, PTZ3_FN),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+        /* PTA */
+        PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
+        PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
+        PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
+        PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
+        PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
+        PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
+        PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
+        PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
+
+        /* PTB */
+        PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
+        PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
+        PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
+        PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
+        PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
+        PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
+        PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
+        PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
+
+        /* PTC */
+        PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
+        PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
+        PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
+        PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
+        PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
+        PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
+        PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
+        PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
+
+        /* PTD */
+        PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
+        PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
+        PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
+        PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
+        PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
+        PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
+        PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
+        PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
+
+        /* PTE */
+        PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
+        PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
+        PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
+        PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
+        PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
+        PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
+        PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
+        PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
+
+        /* PTF */
+        PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
+        PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
+        PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
+        PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
+        PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
+        PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
+        PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
+        PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
+
+        /* PTG */
+        PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
+        PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
+        PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
+        PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
+        PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
+        PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
+
+        /* PTH */
+        PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
+        PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
+        PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
+        PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
+        PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
+        PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
+        PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
+        PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
+
+        /* PTJ */
+        PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
+        PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
+        PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
+        PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
+        PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
+        PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
+        PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
+
+        /* PTK */
+        PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
+        PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
+        PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
+        PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
+        PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
+        PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
+        PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
+        PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
+
+        /* PTL */
+        PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
+        PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
+        PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
+        PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
+        PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
+        PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
+        PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
+        PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
+
+        /* PTM */
+        PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
+        PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
+        PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
+        PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
+        PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
+        PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
+        PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
+        PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
+
+        /* PTN */
+        PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
+        PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
+        PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
+        PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
+        PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
+        PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
+        PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
+        PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
+
+        /* PTQ */
+        PINMUX_GPIO(GPIO_PTQ7, PTQ7_DATA),
+        PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
+        PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
+        PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
+        PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
+        PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
+        PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
+        PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
+
+        /* PTR */
+        PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
+        PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
+        PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
+        PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
+        PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
+        PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
+        PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
+        PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
+
+        /* PTS */
+        PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
+        PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
+        PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
+        PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
+        PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
+        PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
+        PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
+
+        /* PTT */
+        PINMUX_GPIO(GPIO_PTT7, PTT7_DATA),
+        PINMUX_GPIO(GPIO_PTT6, PTT6_DATA),
+        PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
+        PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
+        PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
+        PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
+        PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
+        PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
+
+        /* PTU */
+        PINMUX_GPIO(GPIO_PTU7, PTU7_DATA),
+        PINMUX_GPIO(GPIO_PTU6, PTU6_DATA),
+        PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
+        PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
+        PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
+        PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
+        PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
+        PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
+
+        /* PTV */
+        PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
+        PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
+        PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
+        PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
+        PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
+        PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
+        PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
+        PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
+
+        /* PTW */
+        PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
+        PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
+        PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
+        PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
+        PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
+        PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
+        PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
+        PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
+
+        /* PTX */
+        PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
+        PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
+        PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
+        PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
+        PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
+        PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
+        PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
+        PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
+
+        /* PTY */
+        PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
+        PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
+        PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
+        PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
+        PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
+        PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
+        PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
+        PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
+
+        /* PTZ */
+        PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
+        PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
+        PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
+        PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
+        PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
+        PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
+        PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
+        PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
+
+        /* BSC */
+        PINMUX_GPIO(GPIO_FN_D31,        D31_MARK),
+        PINMUX_GPIO(GPIO_FN_D30,        D30_MARK),
+        PINMUX_GPIO(GPIO_FN_D29,        D29_MARK),
+        PINMUX_GPIO(GPIO_FN_D28,        D28_MARK),
+        PINMUX_GPIO(GPIO_FN_D27,        D27_MARK),
+        PINMUX_GPIO(GPIO_FN_D26,        D26_MARK),
+        PINMUX_GPIO(GPIO_FN_D25,        D25_MARK),
+        PINMUX_GPIO(GPIO_FN_D24,        D24_MARK),
+        PINMUX_GPIO(GPIO_FN_D23,        D23_MARK),
+        PINMUX_GPIO(GPIO_FN_D22,        D22_MARK),
+        PINMUX_GPIO(GPIO_FN_D21,        D21_MARK),
+        PINMUX_GPIO(GPIO_FN_D20,        D20_MARK),
+        PINMUX_GPIO(GPIO_FN_D19,        D19_MARK),
+        PINMUX_GPIO(GPIO_FN_D18,        D18_MARK),
+        PINMUX_GPIO(GPIO_FN_D17,        D17_MARK),
+        PINMUX_GPIO(GPIO_FN_D16,        D16_MARK),
+        PINMUX_GPIO(GPIO_FN_D15,        D15_MARK),
+        PINMUX_GPIO(GPIO_FN_D14,        D14_MARK),
+        PINMUX_GPIO(GPIO_FN_D13,        D13_MARK),
+        PINMUX_GPIO(GPIO_FN_D12,        D12_MARK),
+        PINMUX_GPIO(GPIO_FN_D11,        D11_MARK),
+        PINMUX_GPIO(GPIO_FN_D10,        D10_MARK),
+        PINMUX_GPIO(GPIO_FN_D9,         D9_MARK),
+        PINMUX_GPIO(GPIO_FN_D8,         D8_MARK),
+        PINMUX_GPIO(GPIO_FN_D7,         D7_MARK),
+        PINMUX_GPIO(GPIO_FN_D6,         D6_MARK),
+        PINMUX_GPIO(GPIO_FN_D5,         D5_MARK),
+        PINMUX_GPIO(GPIO_FN_D4,         D4_MARK),
+        PINMUX_GPIO(GPIO_FN_D3,         D3_MARK),
+        PINMUX_GPIO(GPIO_FN_D2,         D2_MARK),
+        PINMUX_GPIO(GPIO_FN_D1,         D1_MARK),
+        PINMUX_GPIO(GPIO_FN_D0,         D0_MARK),
+        PINMUX_GPIO(GPIO_FN_A25,        A25_MARK),
+        PINMUX_GPIO(GPIO_FN_A24,        A24_MARK),
+        PINMUX_GPIO(GPIO_FN_A23,        A23_MARK),
+        PINMUX_GPIO(GPIO_FN_A22,        A22_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6B_CE1B,  CS6B_CE1B_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6A_CE2B,  CS6A_CE2B_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5B_CE1A,  CS5B_CE1A_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5A_CE2A,  CS5A_CE2A_MARK),
+        PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK),
+        PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK),
+        PINMUX_GPIO(GPIO_FN_IOIS16,     IOIS16_MARK),
+        PINMUX_GPIO(GPIO_FN_WAIT,       WAIT_MARK),
+        PINMUX_GPIO(GPIO_FN_BS,         BS_MARK),
+
+        /* KEYSC */
+        PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5,        KEYOUT5_IN5_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6,        KEYOUT4_IN6_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN4,             KEYIN4_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN3,             KEYIN3_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN2,             KEYIN2_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN1,             KEYIN1_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYIN0,             KEYIN0_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT3,            KEYOUT3_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT2,            KEYOUT2_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT1,            KEYOUT1_MARK),
+        PINMUX_GPIO(GPIO_FN_KEYOUT0,            KEYOUT0_MARK),
+
+        /* ATAPI */
+        PINMUX_GPIO(GPIO_FN_IDED15,     IDED15_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED14,     IDED14_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED13,     IDED13_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED12,     IDED12_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED11,     IDED11_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED10,     IDED10_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED9,      IDED9_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED8,      IDED8_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED7,      IDED7_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED6,      IDED6_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED5,      IDED5_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED4,      IDED4_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED3,      IDED3_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED2,      IDED2_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED1,      IDED1_MARK),
+        PINMUX_GPIO(GPIO_FN_IDED0,      IDED0_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEA2,      IDEA2_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEA1,      IDEA1_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEA0,      IDEA0_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEIOWR,    IDEIOWR_MARK),
+        PINMUX_GPIO(GPIO_FN_IODREQ,     IODREQ_MARK),
+        PINMUX_GPIO(GPIO_FN_IDECS0,     IDECS0_MARK),
+        PINMUX_GPIO(GPIO_FN_IDECS1,     IDECS1_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEIORD,    IDEIORD_MARK),
+        PINMUX_GPIO(GPIO_FN_DIRECTION,  DIRECTION_MARK),
+        PINMUX_GPIO(GPIO_FN_EXBUF_ENB,  EXBUF_ENB_MARK),
+        PINMUX_GPIO(GPIO_FN_IDERST,     IDERST_MARK),
+        PINMUX_GPIO(GPIO_FN_IODACK,     IODACK_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEINT,     IDEINT_MARK),
+        PINMUX_GPIO(GPIO_FN_IDEIORDY,   IDEIORDY_MARK),
+
+        /* TPU */
+        PINMUX_GPIO(GPIO_FN_TPUTO3,     TPUTO3_MARK),
+        PINMUX_GPIO(GPIO_FN_TPUTO2,     TPUTO2_MARK),
+        PINMUX_GPIO(GPIO_FN_TPUTO1,     TPUTO1_MARK),
+        PINMUX_GPIO(GPIO_FN_TPUTO0,     TPUTO0_MARK),
+        PINMUX_GPIO(GPIO_FN_TPUTI3,     TPUTI3_MARK),
+        PINMUX_GPIO(GPIO_FN_TPUTI2,     TPUTI2_MARK),
+
+        /* LCDC */
+        PINMUX_GPIO(GPIO_FN_LCDD23,     LCDD23_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD22,     LCDD22_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD21,     LCDD21_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD20,     LCDD20_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD19,     LCDD19_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD18,     LCDD18_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD17,     LCDD17_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD16,     LCDD16_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD15,     LCDD15_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD14,     LCDD14_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD13,     LCDD13_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD12,     LCDD12_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD11,     LCDD11_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD10,     LCDD10_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD9,      LCDD9_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD8,      LCDD8_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD7,      LCDD7_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD6,      LCDD6_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD5,      LCDD5_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD4,      LCDD4_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD3,      LCDD3_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD2,      LCDD2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD1,      LCDD1_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDD0,      LCDD0_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVSYN,    LCDVSYN_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDDISP,    LCDDISP_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDRS,      LCDRS_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDHSYN,    LCDHSYN_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDCS,      LCDCS_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDDON,     LCDDON_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDDCK,     LCDDCK_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDWR,      LCDWR_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVEPWC,   LCDVEPWC_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDVCPWC,   LCDVCPWC_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDRD,      LCDRD_MARK),
+        PINMUX_GPIO(GPIO_FN_LCDLCLK,    LCDLCLK_MARK),
+
+        /* SCIF0 */
+        PINMUX_GPIO(GPIO_FN_SCIF0_TXD,  SCIF0_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_RXD,  SCIF0_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF0_SCK,  SCIF0_SCK_MARK),
+
+        /* SCIF1 */
+        PINMUX_GPIO(GPIO_FN_SCIF1_SCK,  SCIF1_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_RXD,  SCIF1_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF1_TXD,  SCIF1_TXD_MARK),
+
+        /* SCIF2 */
+        PINMUX_GPIO(GPIO_FN_SCIF2_L_TXD,        SCIF2_L_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_L_SCK,        SCIF2_L_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_L_RXD,        SCIF2_L_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_V_TXD,        SCIF2_V_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_V_SCK,        SCIF2_V_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF2_V_RXD,        SCIF2_V_RXD_MARK),
+
+        /* SCIF3 */
+        PINMUX_GPIO(GPIO_FN_SCIF3_V_SCK,        SCIF3_V_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_V_RXD,        SCIF3_V_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_V_TXD,        SCIF3_V_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_V_CTS,        SCIF3_V_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_V_RTS,        SCIF3_V_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_I_SCK,        SCIF3_I_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_I_RXD,        SCIF3_I_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_I_TXD,        SCIF3_I_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_I_CTS,        SCIF3_I_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF3_I_RTS,        SCIF3_I_RTS_MARK),
+
+        /* SCIF4 */
+        PINMUX_GPIO(GPIO_FN_SCIF4_SCK,  SCIF4_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF4_RXD,  SCIF4_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF4_TXD,  SCIF4_TXD_MARK),
+
+        /* SCIF5 */
+        PINMUX_GPIO(GPIO_FN_SCIF5_SCK,  SCIF5_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF5_RXD,  SCIF5_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SCIF5_TXD,  SCIF5_TXD_MARK),
+
+        /* FSI */
+        PINMUX_GPIO(GPIO_FN_FSIMCKB,    FSIMCKB_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIMCKA,    FSIMCKA_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIOASD,    FSIOASD_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIIABCK,   FSIIABCK_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIIALRCK,  FSIIALRCK_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIOABCK,   FSIOABCK_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIOALRCK,  FSIOALRCK_MARK),
+        PINMUX_GPIO(GPIO_FN_CLKAUDIOAO, CLKAUDIOAO_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIIBSD,    FSIIBSD_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIOBSD,    FSIOBSD_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIIBBCK,   FSIIBBCK_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIIBLRCK,  FSIIBLRCK_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIOBBCK,   FSIOBBCK_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIOBLRCK,  FSIOBLRCK_MARK),
+        PINMUX_GPIO(GPIO_FN_CLKAUDIOBO, CLKAUDIOBO_MARK),
+        PINMUX_GPIO(GPIO_FN_FSIIASD,    FSIIASD_MARK),
+
+        /* AUD */
+        PINMUX_GPIO(GPIO_FN_AUDCK,      AUDCK_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDSYNC,    AUDSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA3,    AUDATA3_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA2,    AUDATA2_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA1,    AUDATA1_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA0,    AUDATA0_MARK),
+
+        /* VIO */
+        PINMUX_GPIO(GPIO_FN_VIO_CKO,    VIO_CKO_MARK),
+
+        /* VIO0 */
+        PINMUX_GPIO(GPIO_FN_VIO0_D15,   VIO0_D15_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D14,   VIO0_D14_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D13,   VIO0_D13_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D12,   VIO0_D12_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D11,   VIO0_D11_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D10,   VIO0_D10_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D9,    VIO0_D9_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D8,    VIO0_D8_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D7,    VIO0_D7_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D6,    VIO0_D6_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D5,    VIO0_D5_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D4,    VIO0_D4_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D3,    VIO0_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D2,    VIO0_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D1,    VIO0_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_D0,    VIO0_D0_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_VD,    VIO0_VD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_CLK,   VIO0_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_FLD,   VIO0_FLD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO0_HD,    VIO0_HD_MARK),
+
+        /* VIO1 */
+        PINMUX_GPIO(GPIO_FN_VIO1_D7,    VIO1_D7_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D6,    VIO1_D6_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D5,    VIO1_D5_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D4,    VIO1_D4_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D3,    VIO1_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D2,    VIO1_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D1,    VIO1_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_D0,    VIO1_D0_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_FLD,   VIO1_FLD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_HD,    VIO1_HD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_VD,    VIO1_VD_MARK),
+        PINMUX_GPIO(GPIO_FN_VIO1_CLK,   VIO1_CLK_MARK),
+
+        /* Eth */
+        PINMUX_GPIO(GPIO_FN_RMII_RXD0,          RMII_RXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_RXD1,          RMII_RXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_TXD0,          RMII_TXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_TXD1,          RMII_TXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_REF_CLK,       RMII_REF_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_TX_EN,         RMII_TX_EN_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_RX_ER,         RMII_RX_ER_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII_CRS_DV,        RMII_CRS_DV_MARK),
+        PINMUX_GPIO(GPIO_FN_LNKSTA,             LNKSTA_MARK),
+        PINMUX_GPIO(GPIO_FN_MDIO,               MDIO_MARK),
+        PINMUX_GPIO(GPIO_FN_MDC,                MDC_MARK),
+
+        /* System */
+        PINMUX_GPIO(GPIO_FN_PDSTATUS,   PDSTATUS_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS2,    STATUS2_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS0,    STATUS0_MARK),
+
+        /* VOU */
+        PINMUX_GPIO(GPIO_FN_DV_D15,     DV_D15_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D14,     DV_D14_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D13,     DV_D13_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D12,     DV_D12_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D11,     DV_D11_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D10,     DV_D10_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D9,      DV_D9_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D8,      DV_D8_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D7,      DV_D7_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D6,      DV_D6_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D5,      DV_D5_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D4,      DV_D4_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D3,      DV_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D2,      DV_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D1,      DV_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_D0,      DV_D0_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_CLKI,    DV_CLKI_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_CLK,     DV_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_VSYNC,   DV_VSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_HSYNC,   DV_HSYNC_MARK),
+
+        /* MSIOF0 */
+        PINMUX_GPIO(GPIO_FN_MSIOF0_RXD,         MSIOF0_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_TXD,         MSIOF0_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_MCK,         MSIOF0_MCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_TSCK,        MSIOF0_TSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_SS1,         MSIOF0_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_SS2,         MSIOF0_SS2_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_TSYNC,       MSIOF0_TSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_RSCK,        MSIOF0_RSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF0_RSYNC,       MSIOF0_RSYNC_MARK),
+
+        /* MSIOF1 */
+        PINMUX_GPIO(GPIO_FN_MSIOF1_RXD,         MSIOF1_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_TXD,         MSIOF1_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_MCK,         MSIOF1_MCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK,        MSIOF1_TSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_SS1,         MSIOF1_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_SS2,         MSIOF1_SS2_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC,       MSIOF1_TSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK,        MSIOF1_RSCK_MARK),
+        PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC,       MSIOF1_RSYNC_MARK),
+
+        /* DMAC */
+        PINMUX_GPIO(GPIO_FN_DMAC_DACK0, DMAC_DACK0_MARK),
+        PINMUX_GPIO(GPIO_FN_DMAC_DREQ0, DMAC_DREQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_DMAC_DACK1, DMAC_DACK1_MARK),
+        PINMUX_GPIO(GPIO_FN_DMAC_DREQ1, DMAC_DREQ1_MARK),
+
+        /* SDHI0 */
+        PINMUX_GPIO(GPIO_FN_SDHI0CD,    SDHI0CD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0WP,    SDHI0WP_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0CMD,   SDHI0CMD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0CLK,   SDHI0CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D3,    SDHI0D3_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D2,    SDHI0D2_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D1,    SDHI0D1_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI0D0,    SDHI0D0_MARK),
+
+        /* SDHI1 */
+        PINMUX_GPIO(GPIO_FN_SDHI1CD,    SDHI1CD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1WP,    SDHI1WP_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1CMD,   SDHI1CMD_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1CLK,   SDHI1CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1D3,    SDHI1D3_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1D2,    SDHI1D2_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1D1,    SDHI1D1_MARK),
+        PINMUX_GPIO(GPIO_FN_SDHI1D0,    SDHI1D0_MARK),
+
+        /* MMC */
+        PINMUX_GPIO(GPIO_FN_MMC_D7,     MMC_D7_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D6,     MMC_D6_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D5,     MMC_D5_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D4,     MMC_D4_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D3,     MMC_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D2,     MMC_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D1,     MMC_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_D0,     MMC_D0_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_CLK,    MMC_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_MMC_CMD,    MMC_CMD_MARK),
+
+        /* IrDA */
+        PINMUX_GPIO(GPIO_FN_IRDA_OUT,   IRDA_OUT_MARK),
+        PINMUX_GPIO(GPIO_FN_IRDA_IN,    IRDA_IN_MARK),
+
+        /* TSIF */
+        PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDAT,      TSIF_TS0_SDAT_MARK),
+        PINMUX_GPIO(GPIO_FN_TSIF_TS0_SCK,       TSIF_TS0_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDEN,      TSIF_TS0_SDEN_MARK),
+        PINMUX_GPIO(GPIO_FN_TSIF_TS0_SPSYNC,    TSIF_TS0_SPSYNC_MARK),
+
+        /* IRQ */
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ7,  INTC_IRQ7_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ6,  INTC_IRQ6_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ5,  INTC_IRQ5_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ4,  INTC_IRQ4_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ3,  INTC_IRQ3_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ2,  INTC_IRQ2_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ1,  INTC_IRQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_INTC_IRQ0,  INTC_IRQ0_MARK),
+ };
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
+                PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
+                PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
+                PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN,
+                PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN,
+                PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN,
+                PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN,
+                PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN,
+                PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN }
+        },
+        { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
+                PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN,
+                PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN,
+                PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN,
+                PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN,
+                PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN,
+                PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN,
+                PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN,
+                PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN }
+        },
+        { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
+                PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN,
+                PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN,
+                PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN,
+                PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN,
+                PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN,
+                PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN,
+                PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN,
+                PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN }
+        },
+        { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
+                PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN,
+                PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN,
+                PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN,
+                PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN,
+                PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN,
+                PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN,
+                PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN,
+                PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN }
+        },
+        { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
+                PTE7_FN, PTE7_OUT, PTE7_IN_PU, PTE7_IN,
+                PTE6_FN, PTE6_OUT, PTE6_IN_PU, PTE6_IN,
+                PTE5_FN, PTE5_OUT, PTE5_IN_PU, PTE5_IN,
+                PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN,
+                PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN,
+                PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN,
+                PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN,
+                PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN }
+        },
+        { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
+                PTF7_FN, PTF7_OUT, PTF7_IN_PU, PTF7_IN,
+                PTF6_FN, PTF6_OUT, PTF6_IN_PU, PTF6_IN,
+                PTF5_FN, PTF5_OUT, PTF5_IN_PU, PTF5_IN,
+                PTF4_FN, PTF4_OUT, PTF4_IN_PU, PTF4_IN,
+                PTF3_FN, PTF3_OUT, PTF3_IN_PU, PTF3_IN,
+                PTF2_FN, PTF2_OUT, PTF2_IN_PU, PTF2_IN,
+                PTF1_FN, PTF1_OUT, PTF1_IN_PU, PTF1_IN,
+                PTF0_FN, PTF0_OUT, PTF0_IN_PU, PTF0_IN }
+        },
+        { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PTG5_FN, PTG5_OUT, 0, 0,
+                PTG4_FN, PTG4_OUT, 0, 0,
+                PTG3_FN, PTG3_OUT, 0, 0,
+                PTG2_FN, PTG2_OUT, 0, 0,
+                PTG1_FN, PTG1_OUT, 0, 0,
+                PTG0_FN, PTG0_OUT, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
+                PTH7_FN, PTH7_OUT, PTH7_IN_PU, PTH7_IN,
+                PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN,
+                PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN,
+                PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN,
+                PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN,
+                PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN,
+                PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN,
+                PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN }
+        },
+        { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
+                PTJ7_FN, PTJ7_OUT, 0, 0,
+                PTJ6_FN, PTJ6_OUT, 0, 0,
+                PTJ5_FN, PTJ5_OUT, 0, 0,
+                0, 0, 0, 0,
+                PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN,
+                PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN,
+                PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN,
+                PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN }
+        },
+        { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
+                PTK7_FN, PTK7_OUT, PTK7_IN_PU, PTK7_IN,
+                PTK6_FN, PTK6_OUT, PTK6_IN_PU, PTK6_IN,
+                PTK5_FN, PTK5_OUT, PTK5_IN_PU, PTK5_IN,
+                PTK4_FN, PTK4_OUT, PTK4_IN_PU, PTK4_IN,
+                PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN,
+                PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN,
+                PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN,
+                PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN }
+        },
+        { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
+                PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN,
+                PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN,
+                PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN,
+                PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN,
+                PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN,
+                PTL2_FN, PTL2_OUT, PTL2_IN_PU, PTL2_IN,
+                PTL1_FN, PTL1_OUT, PTL1_IN_PU, PTL1_IN,
+                PTL0_FN, PTL0_OUT, PTL0_IN_PU, PTL0_IN }
+        },
+        { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
+                PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN,
+                PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN,
+                PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN,
+                PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN,
+                PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN,
+                PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN,
+                PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN,
+                PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN }
+        },
+        { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
+                PTN7_FN, PTN7_OUT, PTN7_IN_PU, PTN7_IN,
+                PTN6_FN, PTN6_OUT, PTN6_IN_PU, PTN6_IN,
+                PTN5_FN, PTN5_OUT, PTN5_IN_PU, PTN5_IN,
+                PTN4_FN, PTN4_OUT, PTN4_IN_PU, PTN4_IN,
+                PTN3_FN, PTN3_OUT, PTN3_IN_PU, PTN3_IN,
+                PTN2_FN, PTN2_OUT, PTN2_IN_PU, PTN2_IN,
+                PTN1_FN, PTN1_OUT, PTN1_IN_PU, PTN1_IN,
+                PTN0_FN, PTN0_OUT, PTN0_IN_PU, PTN0_IN }
+        },
+        { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
+                PTQ7_FN, PTQ7_OUT, PTQ7_IN_PU, PTQ7_IN,
+                PTQ6_FN, PTQ6_OUT, PTQ6_IN_PU, PTQ6_IN,
+                PTQ5_FN, PTQ5_OUT, PTQ5_IN_PU, PTQ5_IN,
+                PTQ4_FN, PTQ4_OUT, PTQ4_IN_PU, PTQ4_IN,
+                PTQ3_FN, PTQ3_OUT, PTQ3_IN_PU, PTQ3_IN,
+                PTQ2_FN, PTQ2_OUT, PTQ2_IN_PU, PTQ2_IN,
+                PTQ1_FN, PTQ1_OUT, PTQ1_IN_PU, PTQ1_IN,
+                PTQ0_FN, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN }
+        },
+        { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
+                PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN,
+                PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN,
+                PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN,
+                PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN,
+                PTR3_FN, 0,        PTR3_IN_PU, PTR3_IN,
+                PTR2_FN, 0,        PTR2_IN_PU, PTR2_IN,
+                PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN,
+                PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN }
+        },
+        { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) {
+                0, 0, 0, 0,
+                PTS6_FN, PTS6_OUT, PTS6_IN_PU, PTS6_IN,
+                PTS5_FN, PTS5_OUT, PTS5_IN_PU, PTS5_IN,
+                PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN,
+                PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN,
+                PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN,
+                PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN,
+                PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN }
+        },
+        { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
+                PTT7_FN, PTT7_OUT, PTT7_IN_PU, PTT7_IN,
+                PTT6_FN, PTT6_OUT, PTT6_IN_PU, PTT6_IN,
+                PTT5_FN, PTT5_OUT, PTT5_IN_PU, PTT5_IN,
+                PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN,
+                PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN,
+                PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN,
+                PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN,
+                PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN }
+        },
+        { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
+                PTU7_FN, PTU7_OUT, PTU7_IN_PU, PTU7_IN,
+                PTU6_FN, PTU6_OUT, PTU6_IN_PU, PTU6_IN,
+                PTU5_FN, PTU5_OUT, PTU5_IN_PU, PTU5_IN,
+                PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN,
+                PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN,
+                PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN,
+                PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN,
+                PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN }
+        },
+        { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
+                PTV7_FN, PTV7_OUT, PTV7_IN_PU, PTV7_IN,
+                PTV6_FN, PTV6_OUT, PTV6_IN_PU, PTV6_IN,
+                PTV5_FN, PTV5_OUT, PTV5_IN_PU, PTV5_IN,
+                PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN,
+                PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN,
+                PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN,
+                PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN,
+                PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN }
+        },
+        { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
+                PTW7_FN, PTW7_OUT, PTW7_IN_PU, PTW7_IN,
+                PTW6_FN, PTW6_OUT, PTW6_IN_PU, PTW6_IN,
+                PTW5_FN, PTW5_OUT, PTW5_IN_PU, PTW5_IN,
+                PTW4_FN, PTW4_OUT, PTW4_IN_PU, PTW4_IN,
+                PTW3_FN, PTW3_OUT, PTW3_IN_PU, PTW3_IN,
+                PTW2_FN, PTW2_OUT, PTW2_IN_PU, PTW2_IN,
+                PTW1_FN, PTW1_OUT, PTW1_IN_PU, PTW1_IN,
+                PTW0_FN, PTW0_OUT, PTW0_IN_PU, PTW0_IN }
+        },
+        { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
+                PTX7_FN, PTX7_OUT, PTX7_IN_PU, PTX7_IN,
+                PTX6_FN, PTX6_OUT, PTX6_IN_PU, PTX6_IN,
+                PTX5_FN, PTX5_OUT, PTX5_IN_PU, PTX5_IN,
+                PTX4_FN, PTX4_OUT, PTX4_IN_PU, PTX4_IN,
+                PTX3_FN, PTX3_OUT, PTX3_IN_PU, PTX3_IN,
+                PTX2_FN, PTX2_OUT, PTX2_IN_PU, PTX2_IN,
+                PTX1_FN, PTX1_OUT, PTX1_IN_PU, PTX1_IN,
+                PTX0_FN, PTX0_OUT, PTX0_IN_PU, PTX0_IN }
+        },
+        { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
+                PTY7_FN, PTY7_OUT, PTY7_IN_PU, PTY7_IN,
+                PTY6_FN, PTY6_OUT, PTY6_IN_PU, PTY6_IN,
+                PTY5_FN, PTY5_OUT, PTY5_IN_PU, PTY5_IN,
+                PTY4_FN, PTY4_OUT, PTY4_IN_PU, PTY4_IN,
+                PTY3_FN, PTY3_OUT, PTY3_IN_PU, PTY3_IN,
+                PTY2_FN, PTY2_OUT, PTY2_IN_PU, PTY2_IN,
+                PTY1_FN, PTY1_OUT, PTY1_IN_PU, PTY1_IN,
+                PTY0_FN, PTY0_OUT, PTY0_IN_PU, PTY0_IN }
+        },
+        { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
+                PTZ7_FN, PTZ7_OUT, PTZ7_IN_PU, PTZ7_IN,
+                PTZ6_FN, PTZ6_OUT, PTZ6_IN_PU, PTZ6_IN,
+                PTZ5_FN, PTZ5_OUT, PTZ5_IN_PU, PTZ5_IN,
+                PTZ4_FN, PTZ4_OUT, PTZ4_IN_PU, PTZ4_IN,
+                PTZ3_FN, PTZ3_OUT, PTZ3_IN_PU, PTZ3_IN,
+                PTZ2_FN, PTZ2_OUT, PTZ2_IN_PU, PTZ2_IN,
+                PTZ1_FN, PTZ1_OUT, PTZ1_IN_PU, PTZ1_IN,
+                PTZ0_FN, PTZ0_OUT, PTZ0_IN_PU, PTZ0_IN }
+        },
+        { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) {
+                PSA15_0, PSA15_1,
+                PSA14_0, PSA14_1,
+                PSA13_0, PSA13_1,
+                PSA12_0, PSA12_1,
+                0, 0,
+                PSA10_0, PSA10_1,
+                PSA9_0,  PSA9_1,
+                PSA8_0,  PSA8_1,
+                PSA7_0,  PSA7_1,
+                PSA6_0,  PSA6_1,
+                PSA5_0,  PSA5_1,
+                0, 0,
+                PSA3_0,  PSA3_1,
+                PSA2_0,  PSA2_1,
+                PSA1_0,  PSA1_1,
+                PSA0_0,  PSA0_1}
+        },
+        { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) {
+                0, 0,
+                PSB14_0, PSB14_1,
+                PSB13_0, PSB13_1,
+                PSB12_0, PSB12_1,
+                PSB11_0, PSB11_1,
+                PSB10_0, PSB10_1,
+                PSB9_0,  PSB9_1,
+                PSB8_0,  PSB8_1,
+                PSB7_0,  PSB7_1,
+                PSB6_0,  PSB6_1,
+                PSB5_0,  PSB5_1,
+                PSB4_0,  PSB4_1,
+                PSB3_0,  PSB3_1,
+                PSB2_0,  PSB2_1,
+                PSB1_0,  PSB1_1,
+                PSB0_0,  PSB0_1}
+        },
+        { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) {
+                PSC15_0, PSC15_1,
+                PSC14_0, PSC14_1,
+                PSC13_0, PSC13_1,
+                PSC12_0, PSC12_1,
+                PSC11_0, PSC11_1,
+                PSC10_0, PSC10_1,
+                PSC9_0,  PSC9_1,
+                PSC8_0,  PSC8_1,
+                PSC7_0,  PSC7_1,
+                PSC6_0,  PSC6_1,
+                PSC5_0,  PSC5_1,
+                PSC4_0,  PSC4_1,
+                0, 0,
+                PSC2_0,  PSC2_1,
+                PSC1_0,  PSC1_1,
+                PSC0_0,  PSC0_1}
+        },
+        { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) {
+                PSD15_0, PSD15_1,
+                PSD14_0, PSD14_1,
+                PSD13_0, PSD13_1,
+                PSD12_0, PSD12_1,
+                PSD11_0, PSD11_1,
+                PSD10_0, PSD10_1,
+                PSD9_0,  PSD9_1,
+                PSD8_0,  PSD8_1,
+                PSD7_0,  PSD7_1,
+                PSD6_0,  PSD6_1,
+                PSD5_0,  PSD5_1,
+                PSD4_0,  PSD4_1,
+                PSD3_0,  PSD3_1,
+                PSD2_0,  PSD2_1,
+                PSD1_0,  PSD1_1,
+                PSD0_0,  PSD0_1}
+        },
+        { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) {
+                PSE15_0, PSE15_1,
+                PSE14_0, PSE14_1,
+                PSE13_0, PSE13_1,
+                PSE12_0, PSE12_1,
+                PSE11_0, PSE11_1,
+                PSE10_0, PSE10_1,
+                PSE9_0,  PSE9_1,
+                PSE8_0,  PSE8_1,
+                PSE7_0,  PSE7_1,
+                PSE6_0,  PSE6_1,
+                PSE5_0,  PSE5_1,
+                PSE4_0,  PSE4_1,
+                PSE3_0,  PSE3_1,
+                PSE2_0,  PSE2_1,
+                PSE1_0,  PSE1_1,
+                PSE0_0,  PSE0_1}
+        },
+        {}
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
+                PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+                PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
+        },
+        { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
+                PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+                PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
+        },
+        { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
+                PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
+                PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
+        },
+        { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
+                PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+                PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
+        },
+        { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
+                PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
+                PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
+        },
+        { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
+                PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
+                PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
+        },
+        { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
+                0,         0,         PTG5_DATA, PTG4_DATA,
+                PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
+        },
+        { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
+                PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
+                PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
+        },
+        { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
+                PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
+                PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
+        },
+        { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
+                PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
+                PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
+        },
+        { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
+                PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+                PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
+        },
+        { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
+                PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+                PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
+        },
+        { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
+                PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
+                PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
+        },
+        { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
+                PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
+                PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
+        },
+        { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
+                PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
+                PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
+        },
+        { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
+                0,         PTS6_DATA, PTS5_DATA, PTS4_DATA,
+                PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
+        },
+        { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
+                PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
+                PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
+        },
+        { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
+                PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
+                PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
+        },
+        { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
+                PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
+                PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
+        },
+        { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
+                PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
+                PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
+        },
+        { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
+                PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
+                PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
+        },
+        { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
+                PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
+                PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
+        },
+        { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
+                PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
+                PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
+        },
+        { },
+};
+
+static struct pinmux_info sh7724_pinmux_info = {
+        .name = "sh7724_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PTA7,
+        .last_gpio = GPIO_FN_INTC_IRQ0,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+static int __init plat_pinmux_setup(void)
+{
+        return register_pinmux(&sh7724_pinmux_info);
+}
+arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index c1549382c87c..6307e087c864 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -12,7 +12,7 @@
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
 #include <linux/uio_driver.h>
-#include <linux/sh_cmt.h>
+#include <linux/sh_timer.h>
 #include <asm/clock.h>
 
 static struct resource iic0_resources[] = {
@@ -141,7 +141,7 @@ static struct platform_device jpu_device = {
         .num_resources  = ARRAY_SIZE(jpu_resources),
 };
 
-static struct sh_cmt_config cmt_platform_data = {
+static struct sh_timer_config cmt_platform_data = {
         .name = "CMT",
         .channel_offset = 0x60,
         .timer_bit = 5,
@@ -173,27 +173,123 @@ static struct platform_device cmt_device = {
         .num_resources  = ARRAY_SIZE(cmt_resources),
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "tmu0",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffd80008,
+                .end    = 0xffd80013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "tmu0",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffd80014,
+                .end    = 0xffd8001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "tmu0",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffd80020,
+                .end    = 0xffd8002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
 static struct plat_sci_port sci_platform_data[] = {
         {
                 .mapbase        = 0xffe00000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 80, 80, 80, 80 },
+                .clk            = "scif0",
         }, {
                 .mapbase        = 0xffe10000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 81, 81, 81, 81 },
+                .clk            = "scif1",
         }, {
                 .mapbase        = 0xffe20000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 82, 82, 82, 82 },
+                .clk            = "scif2",
         }, {
                 .mapbase        = 0xffe30000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 83, 83, 83, 83 },
+                .clk            = "scif3",
         }, {
                 .flags = 0,
         }
@@ -209,6 +305,9 @@ static struct platform_device sci_device = {
 
 static struct platform_device *sh7343_devices[] __initdata = {
         &cmt_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
         &iic0_device,
         &iic1_device,
         &sci_device,
@@ -219,12 +318,6 @@ static struct platform_device *sh7343_devices[] __initdata = {
 
 static int __init sh7343_devices_setup(void)
 {
-        clk_always_enable("uram0"); /* URAM */
-        clk_always_enable("xymem0"); /* XYMEM */
-        clk_always_enable("veu0"); /* VEU */
-        clk_always_enable("vpu0"); /* VPU */
-        clk_always_enable("jpu0"); /* JPU */
-
         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
@@ -234,6 +327,19 @@ static int __init sh7343_devices_setup(void)
 }
 __initcall(sh7343_devices_setup);
 
+static struct platform_device *sh7343_early_devices[] __initdata = {
+        &cmt_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7343_early_devices,
+                                   ARRAY_SIZE(sh7343_early_devices));
+}
+
 enum {
         UNUSED = 0,
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 93ecf8ed5c6c..318516f6bfad 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -14,7 +14,7 @@
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
 #include <linux/uio_driver.h>
-#include <linux/sh_cmt.h>
+#include <linux/sh_timer.h>
 #include <asm/clock.h>
 
 static struct resource iic_resources[] = {
@@ -148,7 +148,7 @@ static struct platform_device veu1_device = {
         .num_resources  = ARRAY_SIZE(veu1_resources),
 };
 
-static struct sh_cmt_config cmt_platform_data = {
+static struct sh_timer_config cmt_platform_data = {
         .name = "CMT",
         .channel_offset = 0x60,
         .timer_bit = 5,
@@ -180,12 +180,105 @@ static struct platform_device cmt_device = {
         .num_resources  = ARRAY_SIZE(cmt_resources),
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "tmu0",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffd80008,
+                .end    = 0xffd80013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "tmu0",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffd80014,
+                .end    = 0xffd8001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "tmu0",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffd80020,
+                .end    = 0xffd8002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
 static struct plat_sci_port sci_platform_data[] = {
         {
                 .mapbase        = 0xffe00000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 80, 80, 80, 80 },
+                .clk            = "scif0",
         }, {
                 .flags = 0,
         }
@@ -201,6 +294,9 @@ static struct platform_device sci_device = {
 
 static struct platform_device *sh7366_devices[] __initdata = {
         &cmt_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
         &iic_device,
         &sci_device,
         &usb_host_device,
@@ -211,12 +307,6 @@ static struct platform_device *sh7366_devices[] __initdata = {
 
 static int __init sh7366_devices_setup(void)
 {
-        clk_always_enable("rsmem0"); /* RSMEM */
-        clk_always_enable("xymem0"); /* XYMEM */
-        clk_always_enable("veu1"); /* VEU-2 */
-        clk_always_enable("veu0"); /* VEU-1 */
-        clk_always_enable("vpu0"); /* VPU */
-
         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
@@ -226,6 +316,19 @@ static int __init sh7366_devices_setup(void)
 }
 __initcall(sh7366_devices_setup);
 
+static struct platform_device *sh7366_early_devices[] __initdata = {
+        &cmt_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7366_early_devices,
+                                   ARRAY_SIZE(sh7366_early_devices));
+}
+
 enum {
         UNUSED=0,
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 406747f07dc0..ea524a2da3e4 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -13,7 +13,7 @@
 #include <linux/serial_sci.h>
 #include <linux/mm.h>
 #include <linux/uio_driver.h>
-#include <linux/sh_cmt.h>
+#include <linux/sh_timer.h>
 #include <asm/clock.h>
 #include <asm/mmzone.h>
 
@@ -177,13 +177,13 @@ static struct platform_device jpu_device = {
         .num_resources  = ARRAY_SIZE(jpu_resources),
 };
 
-static struct sh_cmt_config cmt_platform_data = {
+static struct sh_timer_config cmt_platform_data = {
         .name = "CMT",
         .channel_offset = 0x60,
         .timer_bit = 5,
         .clk = "cmt0",
         .clockevent_rating = 125,
-        .clocksource_rating = 200,
+        .clocksource_rating = 125,
 };
 
 static struct resource cmt_resources[] = {
@@ -209,24 +209,119 @@ static struct platform_device cmt_device = {
         .num_resources  = ARRAY_SIZE(cmt_resources),
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "tmu0",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffd80008,
+                .end    = 0xffd80013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "tmu0",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffd80014,
+                .end    = 0xffd8001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "tmu0",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffd80020,
+                .end    = 0xffd8002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
 static struct plat_sci_port sci_platform_data[] = {
         {
                 .mapbase        = 0xffe00000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 80, 80, 80, 80 },
+                .clk            = "scif0",
         },
         {
                 .mapbase        = 0xffe10000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 81, 81, 81, 81 },
+                .clk            = "scif1",
         },
         {
                 .mapbase        = 0xffe20000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 82, 82, 82, 82 },
+                .clk            = "scif2",
         },
         {
                 .flags = 0,
@@ -243,6 +338,9 @@ static struct platform_device sci_device = {
 
 static struct platform_device *sh7722_devices[] __initdata = {
         &cmt_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
         &rtc_device,
         &usbf_device,
         &iic_device,
@@ -254,12 +352,6 @@ static struct platform_device *sh7722_devices[] __initdata = {
 
 static int __init sh7722_devices_setup(void)
 {
-        clk_always_enable("uram0"); /* URAM */
-        clk_always_enable("xymem0"); /* XYMEM */
-        clk_always_enable("veu0"); /* VEU */
-        clk_always_enable("vpu0"); /* VPU */
-        clk_always_enable("jpu0"); /* JPU */
-
         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
@@ -269,6 +361,19 @@ static int __init sh7722_devices_setup(void)
 }
 __initcall(sh7722_devices_setup);
 
+static struct platform_device *sh7722_early_devices[] __initdata = {
+        &cmt_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7722_early_devices,
+                                   ARRAY_SIZE(sh7722_early_devices));
+}
+
 enum {
         UNUSED=0,
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index a800466b938c..d8f4a13aeff9 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -13,7 +13,8 @@
 #include <linux/mm.h>
 #include <linux/serial_sci.h>
 #include <linux/uio_driver.h>
-#include <linux/sh_cmt.h>
+#include <linux/sh_timer.h>
+#include <linux/io.h>
 #include <asm/clock.h>
 #include <asm/mmzone.h>
 
@@ -101,13 +102,13 @@ static struct platform_device veu1_device = {
         .num_resources  = ARRAY_SIZE(veu1_resources),
 };
 
-static struct sh_cmt_config cmt_platform_data = {
+static struct sh_timer_config cmt_platform_data = {
         .name = "CMT",
         .channel_offset = 0x60,
         .timer_bit = 5,
         .clk = "cmt0",
         .clockevent_rating = 125,
-        .clocksource_rating = 200,
+        .clocksource_rating = 125,
 };
 
 static struct resource cmt_resources[] = {
@@ -133,37 +134,225 @@ static struct platform_device cmt_device = {
         .num_resources  = ARRAY_SIZE(cmt_resources),
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "tmu0",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffd80008,
+                .end    = 0xffd80013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "tmu0",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffd80014,
+                .end    = 0xffd8001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "tmu0",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffd80020,
+                .end    = 0xffd8002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
+static struct sh_timer_config tmu3_platform_data = {
+        .name = "TMU3",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "tmu1",
+};
+
+static struct resource tmu3_resources[] = {
+        [0] = {
+                .name   = "TMU3",
+                .start  = 0xffd90008,
+                .end    = 0xffd90013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 57,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu3_device = {
+        .name           = "sh_tmu",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &tmu3_platform_data,
+        },
+        .resource       = tmu3_resources,
+        .num_resources  = ARRAY_SIZE(tmu3_resources),
+};
+
+static struct sh_timer_config tmu4_platform_data = {
+        .name = "TMU4",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "tmu1",
+};
+
+static struct resource tmu4_resources[] = {
+        [0] = {
+                .name   = "TMU4",
+                .start  = 0xffd90014,
+                .end    = 0xffd9001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 58,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu4_device = {
+        .name           = "sh_tmu",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &tmu4_platform_data,
+        },
+        .resource       = tmu4_resources,
+        .num_resources  = ARRAY_SIZE(tmu4_resources),
+};
+
+static struct sh_timer_config tmu5_platform_data = {
+        .name = "TMU5",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "tmu1",
+};
+
+static struct resource tmu5_resources[] = {
+        [0] = {
+                .name   = "TMU5",
+                .start  = 0xffd90020,
+                .end    = 0xffd9002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 57,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu5_device = {
+        .name           = "sh_tmu",
+        .id             = 5,
+        .dev = {
+                .platform_data  = &tmu5_platform_data,
+        },
+        .resource       = tmu5_resources,
+        .num_resources  = ARRAY_SIZE(tmu5_resources),
+};
+
 static struct plat_sci_port sci_platform_data[] = {
         {
                 .mapbase        = 0xffe00000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 80, 80, 80, 80 },
+                .clk            = "scif0",
         },{
                 .mapbase        = 0xffe10000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 81, 81, 81, 81 },
+                .clk            = "scif1",
         },{
                 .mapbase        = 0xffe20000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 82, 82, 82, 82 },
+                .clk            = "scif2",
         },{
                 .mapbase        = 0xa4e30000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIFA,
                 .irqs           = { 56, 56, 56, 56 },
+                .clk            = "scif3",
         },{
                 .mapbase        = 0xa4e40000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIFA,
                 .irqs           = { 88, 88, 88, 88 },
+                .clk            = "scif4",
         },{
                 .mapbase        = 0xa4e50000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIFA,
                 .irqs           = { 109, 109, 109, 109 },
+                .clk            = "scif5",
         }, {
                 .flags = 0,
         }
@@ -255,6 +444,12 @@ static struct platform_device iic_device = {
 
 static struct platform_device *sh7723_devices[] __initdata = {
         &cmt_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
         &sci_device,
         &rtc_device,
         &iic_device,
@@ -266,11 +461,6 @@ static struct platform_device *sh7723_devices[] __initdata = {
 
 static int __init sh7723_devices_setup(void)
 {
-        clk_always_enable("meram0"); /* MERAM */
-        clk_always_enable("veu1"); /* VEU2H1 */
-        clk_always_enable("veu0"); /* VEU2H0 */
-        clk_always_enable("vpu0"); /* VPU */
-
         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
@@ -280,6 +470,31 @@ static int __init sh7723_devices_setup(void)
 }
 __initcall(sh7723_devices_setup);
 
+static struct platform_device *sh7723_early_devices[] __initdata = {
+        &cmt_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7723_early_devices,
+                                   ARRAY_SIZE(sh7723_early_devices));
+}
+
+#define RAMCR_CACHE_L2FC        0x0002
+#define RAMCR_CACHE_L2E         0x0001
+#define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
+void __uses_jump_to_uncached l2_cache_init(void)
+{
+        /* Enable L2 cache */
+        ctrl_outl(L2_CACHE_ENABLE, RAMCR);
+}
+
 enum {
         UNUSED=0,
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
new file mode 100644
index 000000000000..e5ac9eb11c63
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -0,0 +1,786 @@
+/*
+ * SH7724 Setup
+ *
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ *
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * Based on SH7723 Setup
+ * Copyright (C) 2008  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/mm.h>
+#include <linux/serial_sci.h>
+#include <linux/uio_driver.h>
+#include <linux/sh_timer.h>
+#include <linux/io.h>
+#include <asm/clock.h>
+#include <asm/mmzone.h>
+
+/* Serial */
+static struct plat_sci_port sci_platform_data[] = {
+        {
+                .mapbase        = 0xffe00000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 80, 80, 80, 80 },
+                .clk            = "scif0",
+        }, {
+                .mapbase        = 0xffe10000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 81, 81, 81, 81 },
+                .clk            = "scif1",
+        }, {
+                .mapbase        = 0xffe20000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIF,
+                .irqs           = { 82, 82, 82, 82 },
+                .clk            = "scif2",
+        }, {
+                .mapbase        = 0xa4e30000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIFA,
+                .irqs           = { 56, 56, 56, 56 },
+                .clk            = "scif3",
+        }, {
+                .mapbase        = 0xa4e40000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIFA,
+                .irqs           = { 88, 88, 88, 88 },
+                .clk            = "scif4",
+        }, {
+                .mapbase        = 0xa4e50000,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .type           = PORT_SCIFA,
+                .irqs           = { 109, 109, 109, 109 },
+                .clk            = "scif5",
+        }, {
+                .flags = 0,
+        }
+};
+
+static struct platform_device sci_device = {
+        .name           = "sh-sci",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = sci_platform_data,
+        },
+};
+
+/* RTC */
+static struct resource rtc_resources[] = {
+        [0] = {
+                .start  = 0xa465fec0,
+                .end    = 0xa465fec0 + 0x58 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        [1] = {
+                /* Period IRQ */
+                .start  = 69,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* Carry IRQ */
+                .start  = 70,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                /* Alarm IRQ */
+                .start  = 68,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device rtc_device = {
+        .name           = "sh-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(rtc_resources),
+        .resource       = rtc_resources,
+};
+
+/* I2C0 */
+static struct resource iic0_resources[] = {
+        [0] = {
+                .name   = "IIC0",
+                .start  = 0x04470000,
+                .end    = 0x04470018 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 96,
+                .end    = 99,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device iic0_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 0, /* "i2c0" clock */
+        .num_resources  = ARRAY_SIZE(iic0_resources),
+        .resource       = iic0_resources,
+};
+
+/* I2C1 */
+static struct resource iic1_resources[] = {
+        [0] = {
+                .name   = "IIC1",
+                .start  = 0x04750000,
+                .end    = 0x04750018 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 92,
+                .end    = 95,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device iic1_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 1, /* "i2c1" clock */
+        .num_resources  = ARRAY_SIZE(iic1_resources),
+        .resource       = iic1_resources,
+};
+
+/* VPU */
+static struct uio_info vpu_platform_data = {
+        .name = "VPU5F",
+        .version = "0",
+        .irq = 60,
+};
+
+static struct resource vpu_resources[] = {
+        [0] = {
+                .name   = "VPU",
+                .start  = 0xfe900000,
+                .end    = 0xfe902807,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device vpu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &vpu_platform_data,
+        },
+        .resource       = vpu_resources,
+        .num_resources  = ARRAY_SIZE(vpu_resources),
+};
+
+/* VEU0 */
+static struct uio_info veu0_platform_data = {
+        .name = "VEU3F0",
+        .version = "0",
+        .irq = 83,
+};
+
+static struct resource veu0_resources[] = {
+        [0] = {
+                .name   = "VEU3F0",
+                .start  = 0xfe920000,
+                .end    = 0xfe9200cb - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device veu0_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &veu0_platform_data,
+        },
+        .resource       = veu0_resources,
+        .num_resources  = ARRAY_SIZE(veu0_resources),
+};
+
+/* VEU1 */
+static struct uio_info veu1_platform_data = {
+        .name = "VEU3F1",
+        .version = "0",
+        .irq = 54,
+};
+
+static struct resource veu1_resources[] = {
+        [0] = {
+                .name   = "VEU3F1",
+                .start  = 0xfe924000,
+                .end    = 0xfe9240cb - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device veu1_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &veu1_platform_data,
+        },
+        .resource       = veu1_resources,
+        .num_resources  = ARRAY_SIZE(veu1_resources),
+};
+
+static struct sh_timer_config cmt_platform_data = {
+        .name = "CMT",
+        .channel_offset = 0x60,
+        .timer_bit = 5,
+        .clk = "cmt0",
+        .clockevent_rating = 125,
+        .clocksource_rating = 200,
+};
+
+static struct resource cmt_resources[] = {
+        [0] = {
+                .name   = "CMT",
+                .start  = 0x044a0060,
+                .end    = 0x044a006b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 104,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt_device = {
+        .name           = "sh_cmt",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &cmt_platform_data,
+        },
+        .resource       = cmt_resources,
+        .num_resources  = ARRAY_SIZE(cmt_resources),
+};
+
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "tmu0",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffd80008,
+                .end    = 0xffd80013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "tmu0",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffd80014,
+                .end    = 0xffd8001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "tmu0",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffd80020,
+                .end    = 0xffd8002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
+
+static struct sh_timer_config tmu3_platform_data = {
+        .name = "TMU3",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "tmu1",
+};
+
+static struct resource tmu3_resources[] = {
+        [0] = {
+                .name   = "TMU3",
+                .start  = 0xffd90008,
+                .end    = 0xffd90013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 57,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu3_device = {
+        .name           = "sh_tmu",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &tmu3_platform_data,
+        },
+        .resource       = tmu3_resources,
+        .num_resources  = ARRAY_SIZE(tmu3_resources),
+};
+
+static struct sh_timer_config tmu4_platform_data = {
+        .name = "TMU4",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "tmu1",
+};
+
+static struct resource tmu4_resources[] = {
+        [0] = {
+                .name   = "TMU4",
+                .start  = 0xffd90014,
+                .end    = 0xffd9001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 58,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu4_device = {
+        .name           = "sh_tmu",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &tmu4_platform_data,
+        },
+        .resource       = tmu4_resources,
+        .num_resources  = ARRAY_SIZE(tmu4_resources),
+};
+
+static struct sh_timer_config tmu5_platform_data = {
+        .name = "TMU5",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "tmu1",
+};
+
+static struct resource tmu5_resources[] = {
+        [0] = {
+                .name   = "TMU5",
+                .start  = 0xffd90020,
+                .end    = 0xffd9002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 57,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu5_device = {
+        .name           = "sh_tmu",
+        .id             = 5,
+        .dev = {
+                .platform_data  = &tmu5_platform_data,
+        },
+        .resource       = tmu5_resources,
+        .num_resources  = ARRAY_SIZE(tmu5_resources),
+};
+
+/* JPU */
+static struct uio_info jpu_platform_data = {
+        .name = "JPU",
+        .version = "0",
+        .irq = 27,
+};
+
+static struct resource jpu_resources[] = {
+        [0] = {
+                .name   = "JPU",
+                .start  = 0xfe980000,
+                .end    = 0xfe9902d3,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device jpu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &jpu_platform_data,
+        },
+        .resource       = jpu_resources,
+        .num_resources  = ARRAY_SIZE(jpu_resources),
+};
+
+static struct platform_device *sh7724_devices[] __initdata = {
+        &cmt_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
+        &sci_device,
+        &rtc_device,
+        &iic0_device,
+        &iic1_device,
+        &vpu_device,
+        &veu0_device,
+        &veu1_device,
+        &jpu_device,
+};
+
+static int __init sh7724_devices_setup(void)
+{
+        platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
+        platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
+        platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
+        platform_resource_setup_memory(&jpu_device,  "jpu",  2 << 20);
+
+        return platform_add_devices(sh7724_devices,
+                                    ARRAY_SIZE(sh7724_devices));
+}
+device_initcall(sh7724_devices_setup);
+
+static struct platform_device *sh7724_early_devices[] __initdata = {
+        &cmt_device,
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7724_early_devices,
+                                   ARRAY_SIZE(sh7724_early_devices));
+}
+
+#define RAMCR_CACHE_L2FC        0x0002
+#define RAMCR_CACHE_L2E         0x0001
+#define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
+void __uses_jump_to_uncached l2_cache_init(void)
+{
+        /* Enable L2 cache */
+        ctrl_outl(L2_CACHE_ENABLE, RAMCR);
+}
+
+enum {
+        UNUSED = 0,
+
+        /* interrupt sources */
+        IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+        HUDI,
+        DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
+        _2DG_TRI, _2DG_INI, _2DG_CEI,
+        DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
+        VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
+        SCIFA3,
+        VPU,
+        TPU,
+        CEU1,
+        BEU1,
+        USB0, USB1,
+        ATAPI,
+        RTC_ATI, RTC_PRI, RTC_CUI,
+        DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
+        DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
+        KEYSC,
+        SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
+        VEU0,
+        MSIOF_MSIOFI0, MSIOF_MSIOFI1,
+        SPU_SPUI0, SPU_SPUI1,
+        SCIFA4,
+        ICB,
+        ETHI,
+        I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
+        I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
+        SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3,
+        CMT,
+        TSIF,
+        FSI,
+        SCIFA5,
+        TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
+        IRDA,
+        SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
+        JPU,
+        _2DDMAC,
+        MMC_MMC2I, MMC_MMC3I,
+        LCDC,
+        TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
+
+        /* interrupt groups */
+        DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
+        DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
+};
+
+static struct intc_vect vectors[] __initdata = {
+        INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
+        INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
+        INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
+        INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
+
+        INTC_VECT(DMAC1A_DEI0, 0x700),
+        INTC_VECT(DMAC1A_DEI1, 0x720),
+        INTC_VECT(DMAC1A_DEI2, 0x740),
+        INTC_VECT(DMAC1A_DEI3, 0x760),
+
+        INTC_VECT(_2DG_TRI, 0x780),
+        INTC_VECT(_2DG_INI, 0x7A0),
+        INTC_VECT(_2DG_CEI, 0x7C0),
+
+        INTC_VECT(DMAC0A_DEI0, 0x800),
+        INTC_VECT(DMAC0A_DEI1, 0x820),
+        INTC_VECT(DMAC0A_DEI2, 0x840),
+        INTC_VECT(DMAC0A_DEI3, 0x860),
+
+        INTC_VECT(VIO_CEU0, 0x880),
+        INTC_VECT(VIO_BEU0, 0x8A0),
+        INTC_VECT(VIO_VEU1, 0x8C0),
+        INTC_VECT(VIO_VOU,  0x8E0),
+
+        INTC_VECT(SCIFA3, 0x900),
+        INTC_VECT(VPU,    0x980),
+        INTC_VECT(TPU,    0x9A0),
+        INTC_VECT(CEU1,   0x9E0),
+        INTC_VECT(BEU1,   0xA00),
+        INTC_VECT(USB0,   0xA20),
+        INTC_VECT(USB1,   0xA40),
+        INTC_VECT(ATAPI,  0xA60),
+
+        INTC_VECT(RTC_ATI, 0xA80),
+        INTC_VECT(RTC_PRI, 0xAA0),
+        INTC_VECT(RTC_CUI, 0xAC0),
+
+        INTC_VECT(DMAC1B_DEI4, 0xB00),
+        INTC_VECT(DMAC1B_DEI5, 0xB20),
+        INTC_VECT(DMAC1B_DADERR, 0xB40),
+
+        INTC_VECT(DMAC0B_DEI4, 0xB80),
+        INTC_VECT(DMAC0B_DEI5, 0xBA0),
+        INTC_VECT(DMAC0B_DADERR, 0xBC0),
+
+        INTC_VECT(KEYSC,      0xBE0),
+        INTC_VECT(SCIF_SCIF0, 0xC00),
+        INTC_VECT(SCIF_SCIF1, 0xC20),
+        INTC_VECT(SCIF_SCIF2, 0xC40),
+        INTC_VECT(VEU0,       0xC60),
+        INTC_VECT(MSIOF_MSIOFI0, 0xC80),
+        INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
+        INTC_VECT(SPU_SPUI0, 0xCC0),
+        INTC_VECT(SPU_SPUI1, 0xCE0),
+        INTC_VECT(SCIFA4,    0xD00),
+
+        INTC_VECT(ICB,  0xD20),
+        INTC_VECT(ETHI, 0xD60),
+
+        INTC_VECT(I2C1_ALI, 0xD80),
+        INTC_VECT(I2C1_TACKI, 0xDA0),
+        INTC_VECT(I2C1_WAITI, 0xDC0),
+        INTC_VECT(I2C1_DTEI, 0xDE0),
+
+        INTC_VECT(I2C0_ALI, 0xE00),
+        INTC_VECT(I2C0_TACKI, 0xE20),
+        INTC_VECT(I2C0_WAITI, 0xE40),
+        INTC_VECT(I2C0_DTEI, 0xE60),
+
+        INTC_VECT(SDHI0_SDHII0, 0xE80),
+        INTC_VECT(SDHI0_SDHII1, 0xEA0),
+        INTC_VECT(SDHI0_SDHII2, 0xEC0),
+        INTC_VECT(SDHI0_SDHII3, 0xEE0),
+
+        INTC_VECT(CMT,    0xF00),
+        INTC_VECT(TSIF,   0xF20),
+        INTC_VECT(FSI,    0xF80),
+        INTC_VECT(SCIFA5, 0xFA0),
+
+        INTC_VECT(TMU0_TUNI0, 0x400),
+        INTC_VECT(TMU0_TUNI1, 0x420),
+        INTC_VECT(TMU0_TUNI2, 0x440),
+
+        INTC_VECT(IRDA,    0x480),
+
+        INTC_VECT(SDHI1_SDHII0, 0x4E0),
+        INTC_VECT(SDHI1_SDHII1, 0x500),
+        INTC_VECT(SDHI1_SDHII2, 0x520),
+
+        INTC_VECT(JPU, 0x560),
+        INTC_VECT(_2DDMAC, 0x4A0),
+
+        INTC_VECT(MMC_MMC2I, 0x5A0),
+        INTC_VECT(MMC_MMC3I, 0x5C0),
+
+        INTC_VECT(LCDC, 0xF40),
+
+        INTC_VECT(TMU1_TUNI0, 0x920),
+        INTC_VECT(TMU1_TUNI1, 0x940),
+        INTC_VECT(TMU1_TUNI2, 0x960),
+};
+
+static struct intc_group groups[] __initdata = {
+        INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
+        INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
+        INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
+        INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
+        INTC_GROUP(USB, USB0, USB1),
+        INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
+        INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
+        INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
+        INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
+        INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
+        INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3),
+        INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
+        INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
+        INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
+};
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+        { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
+          { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
+            0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
+        { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
+          { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
+            DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
+        { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
+          { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
+        { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
+          { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
+            SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
+        { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
+          { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
+            JPU, 0, 0, LCDC } },
+        { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
+          { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
+            VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
+        { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
+          { 0, 0, ICB, SCIFA4,
+            CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
+        { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
+          { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
+            I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
+        { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
+          { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
+            0, 0, SCIFA5, FSI } },
+        { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
+          { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
+        { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
+          { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
+            0, RTC_CUI, RTC_PRI, RTC_ATI } },
+        { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
+          { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
+            0, TPU, 0, TSIF } },
+        { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
+          { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
+        { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+        { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
+                                             TMU0_TUNI2, IRDA } },
+        { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
+        { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
+                                             TMU1_TUNI2, SPU } },
+        { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
+        { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
+        { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
+        { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
+                                             SCIF_SCIF2, VEU0 } },
+        { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
+                                             I2C1, I2C0 } },
+        { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
+        { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
+        { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
+        { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
+        { 0xa4140010, 0, 32, 4, /* INTPRI00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_sense_reg sense_registers[] __initdata = {
+        { 0xa414001c, 16, 2, /* ICR1 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_mask_reg ack_registers[] __initdata = {
+        { 0xa4140024, 0, 8, /* INTREQ00 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
+                             mask_registers, prio_registers, sense_registers,
+                             ack_registers);
+
+void __init plat_irq_setup(void)
+{
+        register_intc_controller(&intc_desc);
+}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index bdf0f61ae1ed..f1e0c0d36da7 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -12,6 +12,7 @@
 #include <linux/platform_device.h>
 #include <linux/init.h>
 #include <linux/serial.h>
+#include <linux/sh_timer.h>
 #include <linux/io.h>
 #include <linux/serial_sci.h>
 
@@ -113,7 +114,195 @@ static struct platform_device usbf_device = {
         .resource       = usbf_resources,
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffd80008,
+                .end    = 0xffd80013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 28,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffd80014,
+                .end    = 0xffd8001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 29,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffd80020,
+                .end    = 0xffd8002f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 30,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
+static struct sh_timer_config tmu3_platform_data = {
+        .name = "TMU3",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu3_resources[] = {
+        [0] = {
+                .name   = "TMU3",
+                .start  = 0xffd88008,
+                .end    = 0xffd88013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 96,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu3_device = {
+        .name           = "sh_tmu",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &tmu3_platform_data,
+        },
+        .resource       = tmu3_resources,
+        .num_resources  = ARRAY_SIZE(tmu3_resources),
+};
+
+static struct sh_timer_config tmu4_platform_data = {
+        .name = "TMU4",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu4_resources[] = {
+        [0] = {
+                .name   = "TMU4",
+                .start  = 0xffd88014,
+                .end    = 0xffd8801f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 97,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu4_device = {
+        .name           = "sh_tmu",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &tmu4_platform_data,
+        },
+        .resource       = tmu4_resources,
+        .num_resources  = ARRAY_SIZE(tmu4_resources),
+};
+
+static struct sh_timer_config tmu5_platform_data = {
+        .name = "TMU5",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu5_resources[] = {
+        [0] = {
+                .name   = "TMU5",
+                .start  = 0xffd88020,
+                .end    = 0xffd8802b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 98,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu5_device = {
+        .name           = "sh_tmu",
+        .id             = 5,
+        .dev = {
+                .platform_data  = &tmu5_platform_data,
+        },
+        .resource       = tmu5_resources,
+        .num_resources  = ARRAY_SIZE(tmu5_resources),
+};
+
 static struct platform_device *sh7763_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
         &rtc_device,
         &sci_device,
         &usb_ohci_device,
@@ -127,6 +316,21 @@ static int __init sh7763_devices_setup(void)
 }
 __initcall(sh7763_devices_setup);
 
+static struct platform_device *sh7763_early_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7763_early_devices,
+                                   ARRAY_SIZE(sh7763_early_devices));
+}
+
 enum {
         UNUSED = 0,
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index b73578ee295d..1e86209db284 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -11,6 +11,8 @@
 #include <linux/init.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
+#include <linux/io.h>
 
 static struct plat_sci_port sci_platform_data[] = {
         {
@@ -76,7 +78,288 @@ static struct platform_device sci_device = {
         },
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffd80008,
+                .end    = 0xffd80013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffd80014,
+                .end    = 0xffd8001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffd80020,
+                .end    = 0xffd8002f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
+static struct sh_timer_config tmu3_platform_data = {
+        .name = "TMU3",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu3_resources[] = {
+        [0] = {
+                .name   = "TMU3",
+                .start  = 0xffd81008,
+                .end    = 0xffd81013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 19,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu3_device = {
+        .name           = "sh_tmu",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &tmu3_platform_data,
+        },
+        .resource       = tmu3_resources,
+        .num_resources  = ARRAY_SIZE(tmu3_resources),
+};
+
+static struct sh_timer_config tmu4_platform_data = {
+        .name = "TMU4",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu4_resources[] = {
+        [0] = {
+                .name   = "TMU4",
+                .start  = 0xffd81014,
+                .end    = 0xffd8101f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 20,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu4_device = {
+        .name           = "sh_tmu",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &tmu4_platform_data,
+        },
+        .resource       = tmu4_resources,
+        .num_resources  = ARRAY_SIZE(tmu4_resources),
+};
+
+static struct sh_timer_config tmu5_platform_data = {
+        .name = "TMU5",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu5_resources[] = {
+        [0] = {
+                .name   = "TMU5",
+                .start  = 0xffd81020,
+                .end    = 0xffd8102f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 21,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu5_device = {
+        .name           = "sh_tmu",
+        .id             = 5,
+        .dev = {
+                .platform_data  = &tmu5_platform_data,
+        },
+        .resource       = tmu5_resources,
+        .num_resources  = ARRAY_SIZE(tmu5_resources),
+};
+
+static struct sh_timer_config tmu6_platform_data = {
+        .name = "TMU6",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu6_resources[] = {
+        [0] = {
+                .name   = "TMU6",
+                .start  = 0xffd82008,
+                .end    = 0xffd82013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 22,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu6_device = {
+        .name           = "sh_tmu",
+        .id             = 6,
+        .dev = {
+                .platform_data  = &tmu6_platform_data,
+        },
+        .resource       = tmu6_resources,
+        .num_resources  = ARRAY_SIZE(tmu6_resources),
+};
+
+static struct sh_timer_config tmu7_platform_data = {
+        .name = "TMU7",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu7_resources[] = {
+        [0] = {
+                .name   = "TMU7",
+                .start  = 0xffd82014,
+                .end    = 0xffd8201f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 23,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu7_device = {
+        .name           = "sh_tmu",
+        .id             = 7,
+        .dev = {
+                .platform_data  = &tmu7_platform_data,
+        },
+        .resource       = tmu7_resources,
+        .num_resources  = ARRAY_SIZE(tmu7_resources),
+};
+
+static struct sh_timer_config tmu8_platform_data = {
+        .name = "TMU8",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu8_resources[] = {
+        [0] = {
+                .name   = "TMU8",
+                .start  = 0xffd82020,
+                .end    = 0xffd8202b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 24,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu8_device = {
+        .name           = "sh_tmu",
+        .id             = 8,
+        .dev = {
+                .platform_data  = &tmu8_platform_data,
+        },
+        .resource       = tmu8_resources,
+        .num_resources  = ARRAY_SIZE(tmu8_resources),
+};
+
 static struct platform_device *sh7770_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
+        &tmu6_device,
+        &tmu7_device,
+        &tmu8_device,
         &sci_device,
 };
 
@@ -87,6 +370,269 @@ static int __init sh7770_devices_setup(void)
 }
 __initcall(sh7770_devices_setup);
 
+static struct platform_device *sh7770_early_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
+        &tmu6_device,
+        &tmu7_device,
+        &tmu8_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7770_early_devices,
+                                   ARRAY_SIZE(sh7770_early_devices));
+}
+
+enum {
+        UNUSED = 0,
+
+        /* interrupt sources */
+        IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
+        IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
+        IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
+        IRL_HHLL, IRL_HHLH, IRL_HHHL,
+
+        IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
+
+        GPIO,
+        TMU0, TMU1, TMU2, TMU2_TICPI,
+        TMU3, TMU4, TMU5, TMU5_TICPI,
+        TMU6, TMU7, TMU8,
+        HAC, IPI, SPDIF, HUDI, I2C,
+        DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
+        I2S0, I2S1, I2S2, I2S3,
+        SRC_RX, SRC_TX, SRC_SPDIF,
+        DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D,
+        GFX3D_MBX, GFX3D_DMAC,
+        EXBUS_ATA,
+        SPI0, SPI1,
+        SCIF089, SCIF1234, SCIF567,
+        ADC,
+        BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
+        BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
+        BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31,
+
+        /* interrupt groups */
+        TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC,
+};
+
+static struct intc_vect vectors[] __initdata = {
+        INTC_VECT(GPIO, 0x3e0),
+        INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
+        INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
+        INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0),
+        INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0),
+        INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520),
+        INTC_VECT(TMU8, 0x540),
+        INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),
+        INTC_VECT(SPDIF, 0x5e0),
+        INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620),
+        INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
+        INTC_VECT(DMAC0_DMINT2, 0x680),
+        INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0),
+        INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700),
+        INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740),
+        INTC_VECT(SRC_SPDIF, 0x760),
+        INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0),
+        INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0),
+        INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860),
+        INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0),
+        INTC_VECT(GFX2D, 0x8c0),
+        INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920),
+        INTC_VECT(EXBUS_ATA, 0x940),
+        INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
+        INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0),
+        INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00),
+        INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40),
+        INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80),
+        INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0),
+        INTC_VECT(ADC, 0xb20),
+        INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0),
+        INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00),
+        INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40),
+        INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80),
+        INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0),
+        INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00),
+        INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40),
+        INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80),
+        INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0),
+        INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00),
+        INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40),
+        INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80),
+        INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0),
+        INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00),
+        INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40),
+        INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80),
+};
+
+static struct intc_group groups[] __initdata = {
+        INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
+                   TMU5_TICPI, TMU6, TMU7, TMU8),
+        INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2),
+        INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3),
+        INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF),
+        INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC),
+        INTC_GROUP(SPI, SPI0, SPI1),
+        INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567),
+        INTC_GROUP(BBDMAC,
+                   BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
+                   BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
+                   BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31),
+};
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+        { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
+          { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,
+            GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S,
+            DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+        { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },
+        { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
+        { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } },
+        { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } },
+        { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } },
+        { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
+        { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } },
+        { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } },
+        { 0xffe00020, 0, 32, 8, /* INT2PRI8 */
+          { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } },
+        { 0xffe00024, 0, 32, 8, /* INT2PRI9 */
+          { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } },
+        { 0xffe00028, 0, 32, 8, /* INT2PRI10 */
+          { BBDMAC_29, BBDMAC_30, BBDMAC_31 } },
+        { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
+          { TMU1, TMU2, TMU2_TICPI, TMU3 } },
+        { 0xffe00030, 0, 32, 8, /* INT2PRI12 */
+          { TMU4, TMU5, TMU5_TICPI, TMU6 } },
+        { 0xffe00034, 0, 32, 8, /* INT2PRI13 */
+          { TMU7, TMU8 } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups,
+                         mask_registers, prio_registers, NULL);
+
+/* Support for external interrupt pins in IRQ mode */
+static struct intc_vect irq_vectors[] __initdata = {
+        INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
+        INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
+        INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
+};
+
+static struct intc_mask_reg irq_mask_registers[] __initdata = {
+        { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } },
+};
+
+static struct intc_prio_reg irq_prio_registers[] __initdata = {
+        { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
+                                               IRQ4, IRQ5, } },
+};
+
+static struct intc_sense_reg irq_sense_registers[] __initdata = {
+        { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
+                                            IRQ4, IRQ5, } },
+};
+
+static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors,
+                         NULL, irq_mask_registers, irq_prio_registers,
+                         irq_sense_registers);
+
+/* External interrupt pins in IRL mode */
+static struct intc_vect irl_vectors[] __initdata = {
+        INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
+        INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
+        INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
+        INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
+        INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
+        INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
+        INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
+        INTC_VECT(IRL_HHHL, 0x3c0),
+};
+
+static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
+        { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
+          { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
+            IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
+            IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
+            IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
+};
+
+static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
+        { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
+          { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+            IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
+            IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
+            IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
+            IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
+};
+
+static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
+                         NULL, irl7654_mask_registers, NULL, NULL);
+
+static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
+                         NULL, irl3210_mask_registers, NULL, NULL);
+
+#define INTC_ICR0       0xffd00000
+#define INTC_INTMSK0    0xffd00044
+#define INTC_INTMSK1    0xffd00048
+#define INTC_INTMSK2    0xffd40080
+#define INTC_INTMSKCLR1 0xffd00068
+#define INTC_INTMSKCLR2 0xffd40084
+
 void __init plat_irq_setup(void)
 {
+        /* disable IRQ7-0 */
+        ctrl_outl(0xff000000, INTC_INTMSK0);
+
+        /* disable IRL3-0 + IRL7-4 */
+        ctrl_outl(0xc0000000, INTC_INTMSK1);
+        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+
+        /* select IRL mode for IRL3-0 + IRL7-4 */
+        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+
+        /* disable holding function, ie enable "SH-4 Mode" */
+        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+
+        register_intc_controller(&intc_desc);
+}
+
+void __init plat_irq_setup_pins(int mode)
+{
+        switch (mode) {
+        case IRQ_MODE_IRQ:
+                /* select IRQ mode for IRL3-0 + IRL7-4 */
+                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
+                register_intc_controller(&intc_irq_desc);
+                break;
+        case IRQ_MODE_IRL7654:
+                /* enable IRL7-4 but don't provide any masking */
+                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                break;
+        case IRQ_MODE_IRL3210:
+                /* enable IRL0-3 but don't provide any masking */
+                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                break;
+        case IRQ_MODE_IRL7654_MASK:
+                /* enable IRL7-4 and mask using cpu intc controller */
+                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                register_intc_controller(&intc_irl7654_desc);
+                break;
+        case IRQ_MODE_IRL3210_MASK:
+                /* enable IRL0-3 and mask using cpu intc controller */
+                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                register_intc_controller(&intc_irl3210_desc);
+                break;
+        default:
+                BUG();
+        }
 }
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 6f7227cd65bf..715e05b431e5 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -12,6 +12,189 @@
 #include <linux/serial.h>
 #include <linux/io.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
+
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffd80008,
+                .end    = 0xffd80013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 28,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffd80014,
+                .end    = 0xffd8001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 29,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffd80020,
+                .end    = 0xffd8002f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 30,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
+static struct sh_timer_config tmu3_platform_data = {
+        .name = "TMU3",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu3_resources[] = {
+        [0] = {
+                .name   = "TMU3",
+                .start  = 0xffdc0008,
+                .end    = 0xffdc0013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 96,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu3_device = {
+        .name           = "sh_tmu",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &tmu3_platform_data,
+        },
+        .resource       = tmu3_resources,
+        .num_resources  = ARRAY_SIZE(tmu3_resources),
+};
+
+static struct sh_timer_config tmu4_platform_data = {
+        .name = "TMU4",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu4_resources[] = {
+        [0] = {
+                .name   = "TMU4",
+                .start  = 0xffdc0014,
+                .end    = 0xffdc001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 97,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu4_device = {
+        .name           = "sh_tmu",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &tmu4_platform_data,
+        },
+        .resource       = tmu4_resources,
+        .num_resources  = ARRAY_SIZE(tmu4_resources),
+};
+
+static struct sh_timer_config tmu5_platform_data = {
+        .name = "TMU5",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu5_resources[] = {
+        [0] = {
+                .name   = "TMU5",
+                .start  = 0xffdc0020,
+                .end    = 0xffdc002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 98,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu5_device = {
+        .name           = "sh_tmu",
+        .id             = 5,
+        .dev = {
+                .platform_data  = &tmu5_platform_data,
+        },
+        .resource       = tmu5_resources,
+        .num_resources  = ARRAY_SIZE(tmu5_resources),
+};
 
 static struct resource rtc_resources[] = {
         [0] = {
@@ -58,6 +241,12 @@ static struct platform_device sci_device = {
 };
 
 static struct platform_device *sh7780_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
         &rtc_device,
         &sci_device,
 };
@@ -69,6 +258,21 @@ static int __init sh7780_devices_setup(void)
 }
 __initcall(sh7780_devices_setup);
 
+static struct platform_device *sh7780_early_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7780_early_devices,
+                                   ARRAY_SIZE(sh7780_early_devices));
+}
+
 enum {
         UNUSED = 0,
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index d80802a49dbd..af561402570b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -13,39 +13,228 @@
 #include <linux/serial_sci.h>
 #include <linux/io.h>
 #include <linux/mm.h>
+#include <linux/sh_timer.h>
 #include <asm/mmzone.h>
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "tmu012_fck",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffd80008,
+                .end    = 0xffd80013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 28,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "tmu012_fck",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffd80014,
+                .end    = 0xffd8001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 29,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "tmu012_fck",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffd80020,
+                .end    = 0xffd8002f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 30,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
+static struct sh_timer_config tmu3_platform_data = {
+        .name = "TMU3",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "tmu345_fck",
+};
+
+static struct resource tmu3_resources[] = {
+        [0] = {
+                .name   = "TMU3",
+                .start  = 0xffdc0008,
+                .end    = 0xffdc0013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 96,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu3_device = {
+        .name           = "sh_tmu",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &tmu3_platform_data,
+        },
+        .resource       = tmu3_resources,
+        .num_resources  = ARRAY_SIZE(tmu3_resources),
+};
+
+static struct sh_timer_config tmu4_platform_data = {
+        .name = "TMU4",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "tmu345_fck",
+};
+
+static struct resource tmu4_resources[] = {
+        [0] = {
+                .name   = "TMU4",
+                .start  = 0xffdc0014,
+                .end    = 0xffdc001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 97,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu4_device = {
+        .name           = "sh_tmu",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &tmu4_platform_data,
+        },
+        .resource       = tmu4_resources,
+        .num_resources  = ARRAY_SIZE(tmu4_resources),
+};
+
+static struct sh_timer_config tmu5_platform_data = {
+        .name = "TMU5",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "tmu345_fck",
+};
+
+static struct resource tmu5_resources[] = {
+        [0] = {
+                .name   = "TMU5",
+                .start  = 0xffdc0020,
+                .end    = 0xffdc002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 98,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu5_device = {
+        .name           = "sh_tmu",
+        .id             = 5,
+        .dev = {
+                .platform_data  = &tmu5_platform_data,
+        },
+        .resource       = tmu5_resources,
+        .num_resources  = ARRAY_SIZE(tmu5_resources),
+};
+
 static struct plat_sci_port sci_platform_data[] = {
         {
                 .mapbase        = 0xffea0000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 40, 40, 40, 40 },
+                .clk            = "scif_fck",
         }, {
                 .mapbase        = 0xffeb0000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 44, 44, 44, 44 },
+                .clk            = "scif_fck",
         }, {
                 .mapbase        = 0xffec0000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 60, 60, 60, 60 },
+                .clk            = "scif_fck",
         }, {
                 .mapbase        = 0xffed0000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 61, 61, 61, 61 },
+                .clk            = "scif_fck",
         }, {
                 .mapbase        = 0xffee0000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 62, 62, 62, 62 },
+                .clk            = "scif_fck",
         }, {
                 .mapbase        = 0xffef0000,
                 .flags          = UPF_BOOT_AUTOCONF,
                 .type           = PORT_SCIF,
                 .irqs           = { 63, 63, 63, 63 },
+                .clk            = "scif_fck",
         }, {
                 .flags = 0,
         }
@@ -60,6 +249,12 @@ static struct platform_device sci_device = {
 };
 
 static struct platform_device *sh7785_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
         &sci_device,
 };
 
@@ -70,6 +265,21 @@ static int __init sh7785_devices_setup(void)
 }
 __initcall(sh7785_devices_setup);
 
+static struct platform_device *sh7785_early_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7785_early_devices,
+                                   ARRAY_SIZE(sh7785_early_devices));
+}
+
 enum {
         UNUSED = 0,
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 90e8cfff55fd..93e0d2c017e8 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2009  Renesas Solutions Corp.
  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ * Paul Mundt <paul.mundt@renesas.com>
  *
  * Based on SH7785 Setup
  *
@@ -19,6 +20,7 @@
 #include <linux/io.h>
 #include <linux/mm.h>
 #include <linux/dma-mapping.h>
+#include <linux/sh_timer.h>
 #include <asm/mmzone.h>
 
 static struct plat_sci_port sci_platform_data[] = {
@@ -69,6 +71,368 @@ static struct platform_device sci_device = {
         },
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffd80008,
+                .end    = 0xffd80013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffd80014,
+                .end    = 0xffd8001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffd80020,
+                .end    = 0xffd8002f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
+static struct sh_timer_config tmu3_platform_data = {
+        .name = "TMU3",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu3_resources[] = {
+        [0] = {
+                .name   = "TMU3",
+                .start  = 0xffda0008,
+                .end    = 0xffda0013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 20,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu3_device = {
+        .name           = "sh_tmu",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &tmu3_platform_data,
+        },
+        .resource       = tmu3_resources,
+        .num_resources  = ARRAY_SIZE(tmu3_resources),
+};
+
+static struct sh_timer_config tmu4_platform_data = {
+        .name = "TMU4",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu4_resources[] = {
+        [0] = {
+                .name   = "TMU4",
+                .start  = 0xffda0014,
+                .end    = 0xffda001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 21,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu4_device = {
+        .name           = "sh_tmu",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &tmu4_platform_data,
+        },
+        .resource       = tmu4_resources,
+        .num_resources  = ARRAY_SIZE(tmu4_resources),
+};
+
+static struct sh_timer_config tmu5_platform_data = {
+        .name = "TMU5",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu5_resources[] = {
+        [0] = {
+                .name   = "TMU5",
+                .start  = 0xffda0020,
+                .end    = 0xffda002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 22,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu5_device = {
+        .name           = "sh_tmu",
+        .id             = 5,
+        .dev = {
+                .platform_data  = &tmu5_platform_data,
+        },
+        .resource       = tmu5_resources,
+        .num_resources  = ARRAY_SIZE(tmu5_resources),
+};
+
+static struct sh_timer_config tmu6_platform_data = {
+        .name = "TMU6",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu6_resources[] = {
+        [0] = {
+                .name   = "TMU6",
+                .start  = 0xffdc0008,
+                .end    = 0xffdc0013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 45,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu6_device = {
+        .name           = "sh_tmu",
+        .id             = 6,
+        .dev = {
+                .platform_data  = &tmu6_platform_data,
+        },
+        .resource       = tmu6_resources,
+        .num_resources  = ARRAY_SIZE(tmu6_resources),
+};
+
+static struct sh_timer_config tmu7_platform_data = {
+        .name = "TMU7",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu7_resources[] = {
+        [0] = {
+                .name   = "TMU7",
+                .start  = 0xffdc0014,
+                .end    = 0xffdc001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 45,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu7_device = {
+        .name           = "sh_tmu",
+        .id             = 7,
+        .dev = {
+                .platform_data  = &tmu7_platform_data,
+        },
+        .resource       = tmu7_resources,
+        .num_resources  = ARRAY_SIZE(tmu7_resources),
+};
+
+static struct sh_timer_config tmu8_platform_data = {
+        .name = "TMU8",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu8_resources[] = {
+        [0] = {
+                .name   = "TMU8",
+                .start  = 0xffdc0020,
+                .end    = 0xffdc002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 45,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu8_device = {
+        .name           = "sh_tmu",
+        .id             = 8,
+        .dev = {
+                .platform_data  = &tmu8_platform_data,
+        },
+        .resource       = tmu8_resources,
+        .num_resources  = ARRAY_SIZE(tmu8_resources),
+};
+
+static struct sh_timer_config tmu9_platform_data = {
+        .name = "TMU9",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu9_resources[] = {
+        [0] = {
+                .name   = "TMU9",
+                .start  = 0xffde0008,
+                .end    = 0xffde0013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 46,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu9_device = {
+        .name           = "sh_tmu",
+        .id             = 9,
+        .dev = {
+                .platform_data  = &tmu9_platform_data,
+        },
+        .resource       = tmu9_resources,
+        .num_resources  = ARRAY_SIZE(tmu9_resources),
+};
+
+static struct sh_timer_config tmu10_platform_data = {
+        .name = "TMU10",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu10_resources[] = {
+        [0] = {
+                .name   = "TMU10",
+                .start  = 0xffde0014,
+                .end    = 0xffde001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 46,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu10_device = {
+        .name           = "sh_tmu",
+        .id             = 10,
+        .dev = {
+                .platform_data  = &tmu10_platform_data,
+        },
+        .resource       = tmu10_resources,
+        .num_resources  = ARRAY_SIZE(tmu10_resources),
+};
+
+static struct sh_timer_config tmu11_platform_data = {
+        .name = "TMU11",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu11_resources[] = {
+        [0] = {
+                .name   = "TMU11",
+                .start  = 0xffde0020,
+                .end    = 0xffde002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 46,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu11_device = {
+        .name           = "sh_tmu",
+        .id             = 11,
+        .dev = {
+                .platform_data  = &tmu11_platform_data,
+        },
+        .resource       = tmu11_resources,
+        .num_resources  = ARRAY_SIZE(tmu11_resources),
+};
+
 static struct resource usb_ohci_resources[] = {
         [0] = {
                 .start  = 0xffe70400,
@@ -94,6 +458,21 @@ static struct platform_device usb_ohci_device = {
         .resource       = usb_ohci_resources,
 };
 
+static struct platform_device *sh7786_early_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
+        &tmu6_device,
+        &tmu7_device,
+        &tmu8_device,
+        &tmu9_device,
+        &tmu10_device,
+        &tmu11_device,
+};
+
 static struct platform_device *sh7786_devices[] __initdata = {
         &sci_device,
         &usb_ohci_device,
@@ -156,12 +535,26 @@ static void __init sh7786_usb_setup(void)
 
 static int __init sh7786_devices_setup(void)
 {
+        int ret;
+
         sh7786_usb_setup();
+
+        ret = platform_add_devices(sh7786_early_devices,
+                                   ARRAY_SIZE(sh7786_early_devices));
+        if (unlikely(ret != 0))
+                return ret;
+
         return platform_add_devices(sh7786_devices,
                                     ARRAY_SIZE(sh7786_devices));
 }
 device_initcall(sh7786_devices_setup);
 
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7786_early_devices,
+                                   ARRAY_SIZE(sh7786_early_devices));
+}
+
 enum {
         UNUSED = 0,
 
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index bd35f32534b9..53c65fd9ccef 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -1,7 +1,7 @@
 /*
- * SH-X3 Setup
+ * SH-X3 Prototype Setup
  *
- *  Copyright (C) 2007  Paul Mundt
+ *  Copyright (C) 2007 - 2009  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -12,6 +12,7 @@
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
 #include <linux/io.h>
+#include <linux/sh_timer.h>
 #include <asm/mmzone.h>
 
 static struct plat_sci_port sci_platform_data[] = {
@@ -48,17 +49,221 @@ static struct platform_device sci_device = {
         },
 };
 
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = 0xffc10008,
+                .end    = 0xffc10013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 16,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = 0xffc10014,
+                .end    = 0xffc1001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 17,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = 0xffc10020,
+                .end    = 0xffc1002f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
+static struct sh_timer_config tmu3_platform_data = {
+        .name = "TMU3",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu3_resources[] = {
+        [0] = {
+                .name   = "TMU3",
+                .start  = 0xffc20008,
+                .end    = 0xffc20013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 19,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu3_device = {
+        .name           = "sh_tmu",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &tmu3_platform_data,
+        },
+        .resource       = tmu3_resources,
+        .num_resources  = ARRAY_SIZE(tmu3_resources),
+};
+
+static struct sh_timer_config tmu4_platform_data = {
+        .name = "TMU4",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu4_resources[] = {
+        [0] = {
+                .name   = "TMU4",
+                .start  = 0xffc20014,
+                .end    = 0xffc2001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 20,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu4_device = {
+        .name           = "sh_tmu",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &tmu4_platform_data,
+        },
+        .resource       = tmu4_resources,
+        .num_resources  = ARRAY_SIZE(tmu4_resources),
+};
+
+static struct sh_timer_config tmu5_platform_data = {
+        .name = "TMU5",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu5_resources[] = {
+        [0] = {
+                .name   = "TMU5",
+                .start  = 0xffc20020,
+                .end    = 0xffc2002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 21,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu5_device = {
+        .name           = "sh_tmu",
+        .id             = 5,
+        .dev = {
+                .platform_data  = &tmu5_platform_data,
+        },
+        .resource       = tmu5_resources,
+        .num_resources  = ARRAY_SIZE(tmu5_resources),
+};
+
+static struct platform_device *shx3_early_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+        &tmu3_device,
+        &tmu4_device,
+        &tmu5_device,
+};
+
 static struct platform_device *shx3_devices[] __initdata = {
         &sci_device,
 };
 
 static int __init shx3_devices_setup(void)
 {
+        int ret;
+
+        ret = platform_add_devices(shx3_early_devices,
+                                   ARRAY_SIZE(shx3_early_devices));
+        if (unlikely(ret != 0))
+                return ret;
+
         return platform_add_devices(shx3_devices,
                                     ARRAY_SIZE(shx3_devices));
 }
 __initcall(shx3_devices_setup);
 
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(shx3_early_devices,
+                                   ARRAY_SIZE(shx3_early_devices));
+}
+
 enum {
         UNUSED = 0,
 
diff --git a/arch/sh/kernel/cpu/sh5/Makefile b/arch/sh/kernel/cpu/sh5/Makefile
index ce4602ea23a8..a184a31e686e 100644
--- a/arch/sh/kernel/cpu/sh5/Makefile
+++ b/arch/sh/kernel/cpu/sh5/Makefile
@@ -6,6 +6,9 @@ obj-y := entry.o probe.o switchto.o
 obj-$(CONFIG_SH_FPU)            += fpu.o
 obj-$(CONFIG_KALLSYMS)          += unwind.o
 
+# CPU subtype setup
+obj-$(CONFIG_CPU_SH5)           += setup-sh5.o
+
 # Primary on-chip clocks (common)
 clock-$(CONFIG_CPU_SH5)         := clock-sh5.o
 
diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c
index 52c49248833a..7f864ebc51d3 100644
--- a/arch/sh/kernel/cpu/sh5/clock-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c
@@ -32,30 +32,30 @@ static struct clk_ops sh5_master_clk_ops = {
         .init           = master_clk_init,
 };
 
-static void module_clk_recalc(struct clk *clk)
+static unsigned long module_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007;
-        clk->rate = clk->parent->rate / ifc_table[idx];
+        return clk->parent->rate / ifc_table[idx];
 }
 
 static struct clk_ops sh5_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
+static unsigned long bus_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007;
-        clk->rate = clk->parent->rate / ifc_table[idx];
+        return clk->parent->rate / ifc_table[idx];
 }
 
 static struct clk_ops sh5_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long cpu_clk_recalc(struct clk *clk)
 {
         int idx = (ctrl_inw(cprc_base) & 0x0007);
-        clk->rate = clk->parent->rate / ifc_table[idx];
+        return clk->parent->rate / ifc_table[idx];
 }
 
 static struct clk_ops sh5_cpu_clk_ops = {
@@ -71,7 +71,7 @@ static struct clk_ops *sh5_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
-        cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC");
+        cprc_base = (unsigned long)ioremap_nocache(CPRC_BASE, 1024);
         BUG_ON(!cprc_base);
 
         if (idx < ARRAY_SIZE(sh5_clk_ops))
diff --git a/arch/sh/kernel/cpu/sh5/entry.S b/arch/sh/kernel/cpu/sh5/entry.S
index 7e49cb812f8b..b0aacf675258 100644
--- a/arch/sh/kernel/cpu/sh5/entry.S
+++ b/arch/sh/kernel/cpu/sh5/entry.S
@@ -812,27 +812,6 @@ no_underflow:
         ! exceptions
         add     SP, ZERO, r14
 
-#ifdef CONFIG_POOR_MANS_STRACE
-        /* We've pushed all the registers now, so only r2-r4 hold anything
-         * useful. Move them into callee save registers */
-        or      r2, ZERO, r28
-        or      r3, ZERO, r29
-        or      r4, ZERO, r30
-
-        /* Preserve r2 as the event code */
-        movi    evt_debug, r3
-        ori     r3, 1, r3
-        ptabs   r3, tr0
-
-        or      SP, ZERO, r6
-        getcon  TRA, r5
-        blink   tr0, LINK
-
-        or      r28, ZERO, r2
-        or      r29, ZERO, r3
-        or      r30, ZERO, r4
-#endif
-
         /* For syscall and debug race condition, get TRA now */
         getcon  TRA, r5
 
@@ -887,11 +866,6 @@ no_underflow:
  */
         .global ret_from_irq
 ret_from_irq:
-#ifdef CONFIG_POOR_MANS_STRACE
-        pta     evt_debug_ret_from_irq, tr0
-        ori     SP, 0, r2
-        blink   tr0, LINK
-#endif
         ld.q    SP, FRAME_S(FSSR), r6
         shlri   r6, 30, r6
         andi    r6, 1, r6
@@ -905,12 +879,6 @@ ret_from_irq:
 ret_from_exception:
         preempt_stop()
 
-#ifdef CONFIG_POOR_MANS_STRACE
-        pta     evt_debug_ret_from_exc, tr0
-        ori     SP, 0, r2
-        blink   tr0, LINK
-#endif
-
         ld.q    SP, FRAME_S(FSSR), r6
         shlri   r6, 30, r6
         andi    r6, 1, r6
@@ -1236,18 +1204,6 @@ syscall_bad:
         .global syscall_ret
 syscall_ret:
         st.q    SP, FRAME_R(9), r2      /* Expecting SP back to BASIC frame */
-
-#ifdef CONFIG_POOR_MANS_STRACE
-        /* nothing useful in registers at this point */
-
-        movi    evt_debug2, r5
-        ori     r5, 1, r5
-        ptabs   r5, tr0
-        ld.q    SP, FRAME_R(9), r2
-        or      SP, ZERO, r3
-        blink   tr0, LINK
-#endif
-
         ld.q    SP, FRAME_S(FSPC), r2
         addi    r2, 4, r2               /* Move PC, being pre-execution event */
         st.q    SP, FRAME_S(FSPC), r2
@@ -1268,25 +1224,12 @@ ret_from_fork:
         ptabs   r5, tr0
         blink   tr0, LINK
 
-#ifdef CONFIG_POOR_MANS_STRACE
-        /* nothing useful in registers at this point */
-
-        movi    evt_debug2, r5
-        ori     r5, 1, r5
-        ptabs   r5, tr0
-        ld.q    SP, FRAME_R(9), r2
-        or      SP, ZERO, r3
-        blink   tr0, LINK
-#endif
-
         ld.q    SP, FRAME_S(FSPC), r2
         addi    r2, 4, r2               /* Move PC, being pre-execution event */
         st.q    SP, FRAME_S(FSPC), r2
         pta     ret_from_syscall, tr0
         blink   tr0, ZERO
 
-
-
 syscall_allowed:
         /* Use LINK to deflect the exit point, default is syscall_ret */
         pta     syscall_ret, tr0
@@ -1410,8 +1353,8 @@ peek_real_address_q:
            r2(out) : result quadword
 
            This is provided as a cheapskate way of manipulating device
-           registers for debugging (to avoid the need to onchip_remap the debug
-           module, and to avoid the need to onchip_remap the watchpoint
+           registers for debugging (to avoid the need to ioremap the debug
+           module, and to avoid the need to ioremap the watchpoint
            controller in a way that identity maps sufficient bits to avoid the
            SH5-101 cut2 silicon defect).
 
@@ -1459,8 +1402,8 @@ poke_real_address_q:
            r3 : quadword value to write.
 
            This is provided as a cheapskate way of manipulating device
-           registers for debugging (to avoid the need to onchip_remap the debug
-           module, and to avoid the need to onchip_remap the watchpoint
+           registers for debugging (to avoid the need to ioremap the debug
+           module, and to avoid the need to ioremap the watchpoint
            controller in a way that identity maps sufficient bits to avoid the
            SH5-101 cut2 silicon defect).
 
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
new file mode 100644
index 000000000000..f5ff1ac57fc2
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -0,0 +1,195 @@
+/*
+ * SH5-101/SH5-103 CPU Setup
+ *
+ *  Copyright (C) 2009  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/serial_sci.h>
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/sh_timer.h>
+#include <asm/addrspace.h>
+
+static struct plat_sci_port sci_platform_data[] = {
+        {
+                .mapbase        = PHYS_PERIPHERAL_BLOCK + 0x01030000,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
+                .type           = PORT_SCIF,
+                .irqs           = { 39, 40, 42, 0 },
+        }, {
+                .flags = 0,
+        }
+};
+
+static struct platform_device sci_device = {
+        .name           = "sh-sci",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = sci_platform_data,
+        },
+};
+
+static struct resource rtc_resources[] = {
+        [0] = {
+                .start  = PHYS_PERIPHERAL_BLOCK + 0x01040000,
+                .end    = PHYS_PERIPHERAL_BLOCK + 0x01040000 + 0x58 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        [1] = {
+                /* Period IRQ */
+                .start  = IRQ_PRI,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* Carry IRQ */
+                .start  = IRQ_CUI,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                /* Alarm IRQ */
+                .start  = IRQ_ATI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device rtc_device = {
+        .name           = "sh-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(rtc_resources),
+        .resource       = rtc_resources,
+};
+
+#define TMU_BLOCK_OFF   0x01020000
+#define TMU_BASE        PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF
+#define TMU0_BASE       (TMU_BASE + 0x8 + (0xc * 0x0))
+#define TMU1_BASE       (TMU_BASE + 0x8 + (0xc * 0x1))
+#define TMU2_BASE       (TMU_BASE + 0x8 + (0xc * 0x2))
+
+static struct sh_timer_config tmu0_platform_data = {
+        .name = "TMU0",
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clk = "peripheral_clk",
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .name   = "TMU0",
+                .start  = TMU0_BASE,
+                .end    = TMU0_BASE + 0xc - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_TUNI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .name = "TMU1",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clk = "peripheral_clk",
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .name   = "TMU1",
+                .start  = TMU1_BASE,
+                .end    = TMU1_BASE + 0xc - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_TUNI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct sh_timer_config tmu2_platform_data = {
+        .name = "TMU2",
+        .channel_offset = 0x1c,
+        .timer_bit = 2,
+        .clk = "peripheral_clk",
+};
+
+static struct resource tmu2_resources[] = {
+        [0] = {
+                .name   = "TMU2",
+                .start  = TMU2_BASE,
+                .end    = TMU2_BASE + 0xc - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_TUNI2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu2_device = {
+        .name           = "sh_tmu",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &tmu2_platform_data,
+        },
+        .resource       = tmu2_resources,
+        .num_resources  = ARRAY_SIZE(tmu2_resources),
+};
+
+static struct platform_device *sh5_early_devices[] __initdata = {
+        &tmu0_device,
+        &tmu1_device,
+        &tmu2_device,
+};
+
+static struct platform_device *sh5_devices[] __initdata = {
+        &sci_device,
+        &rtc_device,
+};
+
+static int __init sh5_devices_setup(void)
+{
+        int ret;
+
+        ret = platform_add_devices(sh5_early_devices,
+                                   ARRAY_SIZE(sh5_early_devices));
+        if (unlikely(ret != 0))
+                return ret;
+
+        return platform_add_devices(sh5_devices,
+                                    ARRAY_SIZE(sh5_devices));
+}
+__initcall(sh5_devices_setup);
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh5_early_devices,
+                                   ARRAY_SIZE(sh5_early_devices));
+}
diff --git a/arch/sh/kernel/io.c b/arch/sh/kernel/io.c
index 29cf4588fc05..4f85fffaa557 100644
--- a/arch/sh/kernel/io.c
+++ b/arch/sh/kernel/io.c
@@ -12,6 +12,7 @@
  * for more details.
  */
 #include <linux/module.h>
+#include <linux/pci.h>
 #include <asm/machvec.h>
 #include <asm/io.h>
 
diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c
index c22853b059ef..77dfecb64373 100644
--- a/arch/sh/kernel/io_trapped.c
+++ b/arch/sh/kernel/io_trapped.c
@@ -267,7 +267,7 @@ static struct mem_access trapped_io_access = {
 int handle_trapped_io(struct pt_regs *regs, unsigned long address)
 {
         mm_segment_t oldfs;
-        opcode_t instruction;
+        insn_size_t instruction;
         int tmp;
 
         if (!lookup_tiop(address))
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index 3f1372eb0091..3d09062f4682 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -31,39 +31,64 @@ void ack_bad_irq(unsigned int irq)
 }
 
 #if defined(CONFIG_PROC_FS)
+/*
+ * /proc/interrupts printing:
+ */
+static int show_other_interrupts(struct seq_file *p, int prec)
+{
+        seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
+        return 0;
+}
+
 int show_interrupts(struct seq_file *p, void *v)
 {
-        int i = *(loff_t *) v, j;
-        struct irqaction * action;
-        unsigned long flags;
+        unsigned long flags, any_count = 0;
+        int i = *(loff_t *)v, j, prec;
+        struct irqaction *action;
+        struct irq_desc *desc;
+
+        if (i > nr_irqs)
+                return 0;
+
+        for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
+                j *= 10;
+
+        if (i == nr_irqs)
+                return show_other_interrupts(p, prec);
 
         if (i == 0) {
-                seq_puts(p, "           ");
+                seq_printf(p, "%*s", prec + 8, "");
                 for_each_online_cpu(j)
-                        seq_printf(p, "CPU%d       ",j);
+                        seq_printf(p, "CPU%-8d", j);
                 seq_putc(p, '\n');
         }
 
-        if (i < sh_mv.mv_nr_irqs) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
-                action = irq_desc[i].action;
-                if (!action)
-                        goto unlock;
-                seq_printf(p, "%3d: ",i);
-                for_each_online_cpu(j)
-                        seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
-                seq_printf(p, " %14s", irq_desc[i].chip->name);
-                seq_printf(p, "-%-8s", irq_desc[i].name);
-                seq_printf(p, "  %s", action->name);
+        desc = irq_to_desc(i);
+        if (!desc)
+                return 0;
+
+        spin_lock_irqsave(&desc->lock, flags);
+        for_each_online_cpu(j)
+                any_count |= kstat_irqs_cpu(i, j);
+        action = desc->action;
+        if (!action && !any_count)
+                goto out;
+
+        seq_printf(p, "%*d: ", prec, i);
+        for_each_online_cpu(j)
+                seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
+        seq_printf(p, " %14s", desc->chip->name);
+        seq_printf(p, "-%-8s", desc->name);
 
-                for (action=action->next; action; action = action->next)
+        if (action) {
+                seq_printf(p, "  %s", action->name);
+                while ((action = action->next) != NULL)
                         seq_printf(p, ", %s", action->name);
-                seq_putc(p, '\n');
-unlock:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-        } else if (i == sh_mv.mv_nr_irqs)
-                seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count));
+        }
 
+        seq_putc(p, '\n');
+out:
+        spin_unlock_irqrestore(&desc->lock, flags);
         return 0;
 }
 #endif
@@ -254,3 +279,11 @@ void __init init_IRQ(void)
 
         irq_ctx_init(smp_processor_id());
 }
+
+#ifdef CONFIG_SPARSE_IRQ
+int __init arch_probe_nr_irqs(void)
+{
+        nr_irqs = sh_mv.mv_nr_irqs;
+        return 0;
+}
+#endif
diff --git a/arch/sh/kernel/kgdb.c b/arch/sh/kernel/kgdb.c
index 7c747e7d71b8..305aad742aec 100644
--- a/arch/sh/kernel/kgdb.c
+++ b/arch/sh/kernel/kgdb.c
@@ -47,7 +47,7 @@ char in_nmi = 0;	/* Set during NMI to prevent re-entry */
 /* Calculate the new address for after a step */
 static short *get_step_address(struct pt_regs *linux_regs)
 {
-        opcode_t op = __raw_readw(linux_regs->pc);
+        insn_size_t op = __raw_readw(linux_regs->pc);
         long addr;
 
         /* BT */
@@ -134,7 +134,7 @@ static short *get_step_address(struct pt_regs *linux_regs)
  */
 
 static unsigned long stepped_address;
-static opcode_t stepped_opcode;
+static insn_size_t stepped_opcode;
 
 static void do_single_step(struct pt_regs *linux_regs)
 {
diff --git a/arch/sh/kernel/timers/timer-broadcast.c b/arch/sh/kernel/localtimer.c
index 96e8eaea1e62..96e8eaea1e62 100644
--- a/arch/sh/kernel/timers/timer-broadcast.c
+++ b/arch/sh/kernel/localtimer.c
diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
index c1ea41e5812a..548f6607fd0f 100644
--- a/arch/sh/kernel/machvec.c
+++ b/arch/sh/kernel/machvec.c
@@ -129,6 +129,7 @@ void __init sh_mv_setup(void)
         mv_set(ioport_map);
         mv_set(ioport_unmap);
         mv_set(irq_demux);
+        mv_set(mode_pins);
 
         if (!sh_mv.mv_nr_irqs)
                 sh_mv.mv_nr_irqs = NR_IRQS;
diff --git a/arch/sh/kernel/module.c b/arch/sh/kernel/module.c
index c43081039dd5..c19b0f7d2cc1 100644
--- a/arch/sh/kernel/module.c
+++ b/arch/sh/kernel/module.c
@@ -90,7 +90,7 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
                  * SHmedia, the LSB of the symbol needs to be asserted
                  * for the CPU to be in SHmedia mode when it starts executing
                  * the branch target. */
-                relocation |= (sym->st_other & 4);
+                relocation |= !!(sym->st_other & 4);
 #endif
 
                 switch (ELF32_R_TYPE(rel[i].r_info)) {
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 6d94725d22f2..9289ede29c7b 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -251,7 +251,8 @@ static void ubc_set_tracing(int asid, unsigned long pc)
 
         if (current_cpu_data.type == CPU_SH7729 ||
             current_cpu_data.type == CPU_SH7710 ||
-            current_cpu_data.type == CPU_SH7712) {
+            current_cpu_data.type == CPU_SH7712 ||
+            current_cpu_data.type == CPU_SH7203){
                 ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA);
                 ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR);
         } else {
@@ -407,6 +408,7 @@ asmlinkage void break_point_trap(void)
 #else
         ctrl_outw(0, UBC_BBRA);
         ctrl_outw(0, UBC_BBRB);
+        ctrl_outl(0, UBC_BRCR);
 #endif
         current->thread.ubc_pc = 0;
         ubc_usercnt -= 1;
diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c
index f7b22dd83b0c..3392e835a374 100644
--- a/arch/sh/kernel/ptrace_32.c
+++ b/arch/sh/kernel/ptrace_32.c
@@ -334,6 +334,14 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                                         [(addr - (long)&dummy->fpu) >> 2];
                 } else if (addr == (long) &dummy->u_fpvalid)
                         tmp = !!tsk_used_math(child);
+                else if (addr == PT_TEXT_ADDR)
+                        tmp = child->mm->start_code;
+                else if (addr == PT_DATA_ADDR)
+                        tmp = child->mm->start_data;
+                else if (addr == PT_TEXT_END_ADDR)
+                        tmp = child->mm->end_code;
+                else if (addr == PT_TEXT_LEN)
+                        tmp = child->mm->end_code - child->mm->start_code;
                 else
                         tmp = 0;
                 ret = put_user(tmp, datap);
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 04a6004fccc4..dd38338553ef 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -29,6 +29,7 @@
 #include <linux/mmzone.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/platform_device.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/page.h>
@@ -155,7 +156,7 @@ static void __init reserve_crashkernel(void)
                         &crash_size, &crash_base);
         if (ret == 0 && crash_size) {
                 if (crash_base <= 0) {
-                        vp = alloc_bootmem_nopanic(crash_size); 
+                        vp = alloc_bootmem_nopanic(crash_size);
                         if (!vp) {
                                 printk(KERN_INFO "crashkernel allocation "
                                        "failed\n");
@@ -184,7 +185,6 @@ static inline void __init reserve_crashkernel(void)
 {}
 #endif
 
-#ifndef CONFIG_GENERIC_CALIBRATE_DELAY
 void __cpuinit calibrate_delay(void)
 {
         struct clk *clk = clk_get(NULL, "cpu_clk");
@@ -200,7 +200,6 @@ void __cpuinit calibrate_delay(void)
                          (loops_per_jiffy/(5000/HZ)) % 100,
                          loops_per_jiffy);
 }
-#endif
 
 void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
                                                 unsigned long end_pfn)
@@ -328,6 +327,10 @@ static int __init parse_elfcorehdr(char *arg)
 early_param("elfcorehdr", parse_elfcorehdr);
 #endif
 
+void __init __attribute__ ((weak)) plat_early_device_setup(void)
+{
+}
+
 void __init setup_arch(char **cmdline_p)
 {
         enable_mmu();
@@ -381,6 +384,8 @@ void __init setup_arch(char **cmdline_p)
 
         parse_early_param();
 
+        plat_early_device_setup();
+
         sh_mv_setup();
 
         /*
@@ -415,6 +420,18 @@ void __init setup_arch(char **cmdline_p)
 #endif
 }
 
+/* processor boot mode configuration */
+int generic_mode_pins(void)
+{
+        pr_warning("generic_mode_pins(): missing mode pin configuration\n");
+        return 0;
+}
+
+int test_mode_pin(int pin)
+{
+        return sh_mv.mv_mode_pins() & pin;
+}
+
 static const char *cpu_name[] = {
         [CPU_SH7201]    = "SH7201",
         [CPU_SH7203]    = "SH7203",     [CPU_SH7263]    = "SH7263",
@@ -435,7 +452,8 @@ static const char *cpu_name[] = {
         [CPU_SH7722]    = "SH7722",     [CPU_SHX3]      = "SH-X3",
         [CPU_SH5_101]   = "SH5-101",    [CPU_SH5_103]   = "SH5-103",
         [CPU_MXG]       = "MX-G",       [CPU_SH7723]    = "SH7723",
-        [CPU_SH7366]    = "SH7366",     [CPU_SH_NONE]   = "Unknown"
+        [CPU_SH7366]    = "SH7366",     [CPU_SH7724]    = "SH7724",
+        [CPU_SH_NONE]   = "Unknown"
 };
 
 const char *get_cpu_subtype(struct sh_cpuinfo *c)
diff --git a/arch/sh/kernel/sh_ksyms_32.c b/arch/sh/kernel/sh_ksyms_32.c
index 528de2955c81..fcc5de31f83b 100644
--- a/arch/sh/kernel/sh_ksyms_32.c
+++ b/arch/sh/kernel/sh_ksyms_32.c
@@ -19,14 +19,10 @@
 #include <asm/ftrace.h>
 
 extern int dump_fpu(struct pt_regs *, elf_fpregset_t *);
-extern struct hw_interrupt_type no_irq_type;
 
 /* platform dependent support */
 EXPORT_SYMBOL(dump_fpu);
 EXPORT_SYMBOL(kernel_thread);
-EXPORT_SYMBOL(irq_desc);
-EXPORT_SYMBOL(no_irq_type);
-
 EXPORT_SYMBOL(strlen);
 
 /* PCI exports */
@@ -41,11 +37,6 @@ EXPORT_SYMBOL(memcpy);
 EXPORT_SYMBOL(memset);
 EXPORT_SYMBOL(memmove);
 EXPORT_SYMBOL(__copy_user);
-
-#ifdef CONFIG_MMU
-EXPORT_SYMBOL(get_vm_area);
-#endif
-
 EXPORT_SYMBOL(__udelay);
 EXPORT_SYMBOL(__ndelay);
 EXPORT_SYMBOL(__const_udelay);
diff --git a/arch/sh/kernel/sh_ksyms_64.c b/arch/sh/kernel/sh_ksyms_64.c
index 0d74d6b8774e..8f54ef0cfbca 100644
--- a/arch/sh/kernel/sh_ksyms_64.c
+++ b/arch/sh/kernel/sh_ksyms_64.c
@@ -76,5 +76,7 @@ EXPORT_SYMBOL(strcpy);
 #define DECLARE_EXPORT(name) extern void name(void);EXPORT_SYMBOL(name)
 
 DECLARE_EXPORT(__sdivsi3);
+DECLARE_EXPORT(__sdivsi3_1);
+DECLARE_EXPORT(__sdivsi3_2);
 DECLARE_EXPORT(__udivsi3);
 DECLARE_EXPORT(__div_table);
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index 05202edd8e21..a9fff9f731ec 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -350,4 +350,5 @@ ENTRY(sys_call_table)
         .long sys_pipe2
         .long sys_inotify_init1
         .long sys_preadv
-        .long sys_writev
+        .long sys_pwritev
+        .long sys_rt_tgsigqueueinfo     /* 335 */
diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S
index a083609f9284..75c1889af1ed 100644
--- a/arch/sh/kernel/syscalls_64.S
+++ b/arch/sh/kernel/syscalls_64.S
@@ -389,3 +389,4 @@ sys_call_table:
         .long sys_inotify_init1         /* 360 */
         .long sys_preadv
         .long sys_pwritev
+        .long sys_rt_tgsigqueueinfo
diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c
new file mode 100644
index 000000000000..2edde32c764b
--- /dev/null
+++ b/arch/sh/kernel/time.c
@@ -0,0 +1,125 @@
+/*
+ *  arch/sh/kernel/time.c
+ *
+ *  Copyright (C) 1999  Tetsuya Okada & Niibe Yutaka
+ *  Copyright (C) 2000  Philipp Rumpf <prumpf@tux.org>
+ *  Copyright (C) 2002 - 2009  Paul Mundt
+ *  Copyright (C) 2002  M. R. Brown  <mrbrown@linux-sh.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/profile.h>
+#include <linux/timex.h>
+#include <linux/sched.h>
+#include <linux/clockchips.h>
+#include <linux/platform_device.h>
+#include <linux/smp.h>
+#include <linux/rtc.h>
+#include <asm/clock.h>
+#include <asm/rtc.h>
+
+/* Dummy RTC ops */
+static void null_rtc_get_time(struct timespec *tv)
+{
+        tv->tv_sec = mktime(2000, 1, 1, 0, 0, 0);
+        tv->tv_nsec = 0;
+}
+
+static int null_rtc_set_time(const time_t secs)
+{
+        return 0;
+}
+
+void (*rtc_sh_get_time)(struct timespec *) = null_rtc_get_time;
+int (*rtc_sh_set_time)(const time_t) = null_rtc_set_time;
+
+#ifdef CONFIG_GENERIC_CMOS_UPDATE
+unsigned long read_persistent_clock(void)
+{
+        struct timespec tv;
+        rtc_sh_get_time(&tv);
+        return tv.tv_sec;
+}
+
+int update_persistent_clock(struct timespec now)
+{
+        return rtc_sh_set_time(now.tv_sec);
+}
+#endif
+
+unsigned int get_rtc_time(struct rtc_time *tm)
+{
+        if (rtc_sh_get_time != null_rtc_get_time) {
+                struct timespec tv;
+
+                rtc_sh_get_time(&tv);
+                rtc_time_to_tm(tv.tv_sec, tm);
+        }
+
+        return RTC_24H;
+}
+EXPORT_SYMBOL(get_rtc_time);
+
+int set_rtc_time(struct rtc_time *tm)
+{
+        unsigned long secs;
+
+        rtc_tm_to_time(tm, &secs);
+        return rtc_sh_set_time(secs);
+}
+EXPORT_SYMBOL(set_rtc_time);
+
+static int __init rtc_generic_init(void)
+{
+        struct platform_device *pdev;
+
+        if (rtc_sh_get_time == null_rtc_get_time)
+                return -ENODEV;
+
+        pdev = platform_device_register_simple("rtc-generic", -1, NULL, 0);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+
+        return 0;
+}
+module_init(rtc_generic_init);
+
+void (*board_time_init)(void);
+
+unsigned long long sched_clock(void)
+{
+        return (jiffies_64 - INITIAL_JIFFIES) * (NSEC_PER_SEC / HZ);
+}
+
+static void __init sh_late_time_init(void)
+{
+        /*
+         * Make sure all compiled-in early timers register themselves.
+         * Run probe() for one "earlytimer" device.
+         */
+        early_platform_driver_register_all("earlytimer");
+        early_platform_driver_probe("earlytimer", 1, 0);
+}
+
+void __init time_init(void)
+{
+        if (board_time_init)
+                board_time_init();
+
+        clk_init();
+
+        rtc_sh_get_time(&xtime);
+        set_normalized_timespec(&wall_to_monotonic,
+                                -xtime.tv_sec, -xtime.tv_nsec);
+
+#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
+        local_timer_setup(smp_processor_id());
+#endif
+
+        late_time_init = sh_late_time_init;
+}
diff --git a/arch/sh/kernel/time_32.c b/arch/sh/kernel/time_32.c
deleted file mode 100644
index 1700d2465f6c..000000000000
--- a/arch/sh/kernel/time_32.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- *  arch/sh/kernel/time_32.c
- *
- *  Copyright (C) 1999  Tetsuya Okada & Niibe Yutaka
- *  Copyright (C) 2000  Philipp Rumpf <prumpf@tux.org>
- *  Copyright (C) 2002 - 2008  Paul Mundt
- *  Copyright (C) 2002  M. R. Brown  <mrbrown@linux-sh.org>
- *
- *  Some code taken from i386 version.
- *    Copyright (C) 1991, 1992, 1995  Linus Torvalds
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/profile.h>
-#include <linux/timex.h>
-#include <linux/sched.h>
-#include <linux/clockchips.h>
-#include <linux/mc146818rtc.h>  /* for rtc_lock */
-#include <linux/smp.h>
-#include <asm/clock.h>
-#include <asm/rtc.h>
-#include <asm/timer.h>
-#include <asm/kgdb.h>
-
-struct sys_timer *sys_timer;
-
-/* Move this somewhere more sensible.. */
-DEFINE_SPINLOCK(rtc_lock);
-EXPORT_SYMBOL(rtc_lock);
-
-/* Dummy RTC ops */
-static void null_rtc_get_time(struct timespec *tv)
-{
-        tv->tv_sec = mktime(2000, 1, 1, 0, 0, 0);
-        tv->tv_nsec = 0;
-}
-
-static int null_rtc_set_time(const time_t secs)
-{
-        return 0;
-}
-
-void (*rtc_sh_get_time)(struct timespec *) = null_rtc_get_time;
-int (*rtc_sh_set_time)(const time_t) = null_rtc_set_time;
-
-#ifndef CONFIG_GENERIC_TIME
-void do_gettimeofday(struct timeval *tv)
-{
-        unsigned long flags;
-        unsigned long seq;
-        unsigned long usec, sec;
-
-        do {
-                /*
-                 * Turn off IRQs when grabbing xtime_lock, so that
-                 * the sys_timer get_offset code doesn't have to handle it.
-                 */
-                seq = read_seqbegin_irqsave(&xtime_lock, flags);
-                usec = get_timer_offset();
-                sec = xtime.tv_sec;
-                usec += xtime.tv_nsec / NSEC_PER_USEC;
-        } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
-
-        while (usec >= 1000000) {
-                usec -= 1000000;
-                sec++;
-        }
-
-        tv->tv_sec = sec;
-        tv->tv_usec = usec;
-}
-EXPORT_SYMBOL(do_gettimeofday);
-
-int do_settimeofday(struct timespec *tv)
-{
-        time_t wtm_sec, sec = tv->tv_sec;
-        long wtm_nsec, nsec = tv->tv_nsec;
-
-        if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
-                return -EINVAL;
-
-        write_seqlock_irq(&xtime_lock);
-        /*
-         * This is revolting. We need to set "xtime" correctly. However, the
-         * value in this location is the value at the most recent update of
-         * wall time.  Discover what correction gettimeofday() would have
-         * made, and then undo it!
-         */
-        nsec -= get_timer_offset() * NSEC_PER_USEC;
-
-        wtm_sec  = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
-        wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
-
-        set_normalized_timespec(&xtime, sec, nsec);
-        set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
-
-        ntp_clear();
-        write_sequnlock_irq(&xtime_lock);
-        clock_was_set();
-
-        return 0;
-}
-EXPORT_SYMBOL(do_settimeofday);
-#endif /* !CONFIG_GENERIC_TIME */
-
-/* last time the RTC clock got updated */
-static long last_rtc_update;
-
-/*
- * handle_timer_tick() needs to keep up the real-time clock,
- * as well as call the "do_timer()" routine every clocktick
- */
-void handle_timer_tick(void)
-{
-        if (current->pid)
-                profile_tick(CPU_PROFILING);
-
-        /*
-         * Here we are in the timer irq handler. We just have irqs locally
-         * disabled but we don't know if the timer_bh is running on the other
-         * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
-         * the irq version of write_lock because as just said we have irq
-         * locally disabled. -arca
-         */
-        write_seqlock(&xtime_lock);
-        do_timer(1);
-
-        /*
-         * If we have an externally synchronized Linux clock, then update
-         * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
-         * called as close as possible to 500 ms before the new second starts.
-         */
-        if (ntp_synced() &&
-            xtime.tv_sec > last_rtc_update + 660 &&
-            (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
-            (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
-                if (rtc_sh_set_time(xtime.tv_sec) == 0)
-                        last_rtc_update = xtime.tv_sec;
-                else
-                        /* do it again in 60s */
-                        last_rtc_update = xtime.tv_sec - 600;
-        }
-        write_sequnlock(&xtime_lock);
-
-#ifndef CONFIG_SMP
-        update_process_times(user_mode(get_irq_regs()));
-#endif
-}
-
-#ifdef CONFIG_PM
-int timer_suspend(struct sys_device *dev, pm_message_t state)
-{
-        struct sys_timer *sys_timer = container_of(dev, struct sys_timer, dev);
-
-        sys_timer->ops->stop();
-
-        return 0;
-}
-
-int timer_resume(struct sys_device *dev)
-{
-        struct sys_timer *sys_timer = container_of(dev, struct sys_timer, dev);
-
-        sys_timer->ops->start();
-
-        return 0;
-}
-#else
-#define timer_suspend NULL
-#define timer_resume NULL
-#endif
-
-static struct sysdev_class timer_sysclass = {
-        .name    = "timer",
-        .suspend = timer_suspend,
-        .resume  = timer_resume,
-};
-
-static int __init timer_init_sysfs(void)
-{
-        int ret;
-
-        if (!sys_timer)
-                return 0;
-
-        ret = sysdev_class_register(&timer_sysclass);
-        if (ret != 0)
-                return ret;
-
-        sys_timer->dev.cls = &timer_sysclass;
-        return sysdev_register(&sys_timer->dev);
-}
-device_initcall(timer_init_sysfs);
-
-void (*board_time_init)(void);
-
-struct clocksource clocksource_sh = {
-        .name           = "SuperH",
-};
-
-#ifdef CONFIG_GENERIC_TIME
-unsigned long long sched_clock(void)
-{
-        unsigned long long cycles;
-
-        /* jiffies based sched_clock if no clocksource is installed */
-        if (!clocksource_sh.rating)
-                return (unsigned long long)jiffies * (NSEC_PER_SEC / HZ);
-
-        cycles = clocksource_sh.read(&clocksource_sh);
-        return cyc2ns(&clocksource_sh, cycles);
-}
-#endif
-
-void __init time_init(void)
-{
-        if (board_time_init)
-                board_time_init();
-
-        clk_init();
-
-        rtc_sh_get_time(&xtime);
-        set_normalized_timespec(&wall_to_monotonic,
-                                -xtime.tv_sec, -xtime.tv_nsec);
-
-#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
-        local_timer_setup(smp_processor_id());
-#endif
-
-        /*
-         * Find the timer to use as the system timer, it will be
-         * initialized for us.
-         */
-        sys_timer = get_sys_timer();
-        if (unlikely(!sys_timer))
-                panic("System timer missing.\n");
-
-        printk(KERN_INFO "Using %s for system timer\n", sys_timer->name);
-}
diff --git a/arch/sh/kernel/time_64.c b/arch/sh/kernel/time_64.c
deleted file mode 100644
index 988c77c37231..000000000000
--- a/arch/sh/kernel/time_64.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * arch/sh/kernel/time_64.c
- *
- * Copyright (C) 2000, 2001  Paolo Alberelli
- * Copyright (C) 2003 - 2007  Paul Mundt
- * Copyright (C) 2003  Richard Curnow
- *
- *    Original TMU/RTC code taken from sh version.
- *    Copyright (C) 1999  Tetsuya Okada & Niibe Yutaka
- *      Some code taken from i386 version.
- *      Copyright (C) 1991, 1992, 1995  Linus Torvalds
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/errno.h>
-#include <linux/rwsem.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/profile.h>
-#include <linux/smp.h>
-#include <linux/module.h>
-#include <linux/bcd.h>
-#include <linux/timex.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <cpu/registers.h>       /* required by inline __asm__ stmt. */
-#include <cpu/irq.h>
-#include <asm/addrspace.h>
-#include <asm/processor.h>
-#include <asm/uaccess.h>
-#include <asm/delay.h>
-#include <asm/clock.h>
-
-#define TMU_TOCR_INIT   0x00
-#define TMU0_TCR_INIT   0x0020
-#define TMU_TSTR_INIT   1
-#define TMU_TSTR_OFF    0
-
-/* Real Time Clock */
-#define RTC_BLOCK_OFF   0x01040000
-#define RTC_BASE        PHYS_PERIPHERAL_BLOCK + RTC_BLOCK_OFF
-#define RTC_RCR1_CIE    0x10    /* Carry Interrupt Enable */
-#define RTC_RCR1        (rtc_base + 0x38)
-
-/* Time Management Unit */
-#define TMU_BLOCK_OFF   0x01020000
-#define TMU_BASE        PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF
-#define TMU0_BASE       tmu_base + 0x8 + (0xc * 0x0)
-#define TMU1_BASE       tmu_base + 0x8 + (0xc * 0x1)
-#define TMU2_BASE       tmu_base + 0x8 + (0xc * 0x2)
-
-#define TMU_TOCR        tmu_base+0x0    /* Byte access */
-#define TMU_TSTR        tmu_base+0x4    /* Byte access */
-
-#define TMU0_TCOR       TMU0_BASE+0x0   /* Long access */
-#define TMU0_TCNT       TMU0_BASE+0x4   /* Long access */
-#define TMU0_TCR        TMU0_BASE+0x8   /* Word access */
-
-#define TICK_SIZE (tick_nsec / 1000)
-
-static unsigned long tmu_base, rtc_base;
-unsigned long cprc_base;
-
-/* Variables to allow interpolation of time of day to resolution better than a
- * jiffy. */
-
-/* This is effectively protected by xtime_lock */
-static unsigned long ctc_last_interrupt;
-static unsigned long long usecs_per_jiffy = 1000000/HZ; /* Approximation */
-
-#define CTC_JIFFY_SCALE_SHIFT 40
-
-/* 2**CTC_JIFFY_SCALE_SHIFT / ctc_ticks_per_jiffy */
-static unsigned long long scaled_recip_ctc_ticks_per_jiffy;
-
-/* Estimate number of microseconds that have elapsed since the last timer tick,
-   by scaling the delta that has occurred in the CTC register.
-
-   WARNING WARNING WARNING : This algorithm relies on the CTC decrementing at
-   the CPU clock rate.  If the CPU sleeps, the CTC stops counting.  Bear this
-   in mind if enabling SLEEP_WORKS in process.c.  In that case, this algorithm
-   probably needs to use TMU.TCNT0 instead.  This will work even if the CPU is
-   sleeping, though will be coarser.
-
-   FIXME : What if usecs_per_tick is moving around too much, e.g. if an adjtime
-   is running or if the freq or tick arguments of adjtimex are modified after
-   we have calibrated the scaling factor?  This will result in either a jump at
-   the end of a tick period, or a wrap backwards at the start of the next one,
-   if the application is reading the time of day often enough.  I think we
-   ought to do better than this.  For this reason, usecs_per_jiffy is left
-   separated out in the calculation below.  This allows some future hook into
-   the adjtime-related stuff in kernel/timer.c to remove this hazard.
-
-*/
-
-static unsigned long usecs_since_tick(void)
-{
-        unsigned long long current_ctc;
-        long ctc_ticks_since_interrupt;
-        unsigned long long ull_ctc_ticks_since_interrupt;
-        unsigned long result;
-
-        unsigned long long mul1_out;
-        unsigned long long mul1_out_high;
-        unsigned long long mul2_out_low, mul2_out_high;
-
-        /* Read CTC register */
-        asm ("getcon cr62, %0" : "=r" (current_ctc));
-        /* Note, the CTC counts down on each CPU clock, not up.
-           Note(2), use long type to get correct wraparound arithmetic when
-           the counter crosses zero. */
-        ctc_ticks_since_interrupt = (long) ctc_last_interrupt - (long) current_ctc;
-        ull_ctc_ticks_since_interrupt = (unsigned long long) ctc_ticks_since_interrupt;
-
-        /* Inline assembly to do 32x32x32->64 multiplier */
-        asm volatile ("mulu.l %1, %2, %0" :
-             "=r" (mul1_out) :
-             "r" (ull_ctc_ticks_since_interrupt), "r" (usecs_per_jiffy));
-
-        mul1_out_high = mul1_out >> 32;
-
-        asm volatile ("mulu.l %1, %2, %0" :
-             "=r" (mul2_out_low) :
-             "r" (mul1_out), "r" (scaled_recip_ctc_ticks_per_jiffy));
-
-#if 1
-        asm volatile ("mulu.l %1, %2, %0" :
-             "=r" (mul2_out_high) :
-             "r" (mul1_out_high), "r" (scaled_recip_ctc_ticks_per_jiffy));
-#endif
-
-        result = (unsigned long) (((mul2_out_high << 32) + mul2_out_low) >> CTC_JIFFY_SCALE_SHIFT);
-
-        return result;
-}
-
-void do_gettimeofday(struct timeval *tv)
-{
-        unsigned long flags;
-        unsigned long seq;
-        unsigned long usec, sec;
-
-        do {
-                seq = read_seqbegin_irqsave(&xtime_lock, flags);
-                usec = usecs_since_tick();
-                sec = xtime.tv_sec;
-                usec += xtime.tv_nsec / 1000;
-        } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
-
-        while (usec >= 1000000) {
-                usec -= 1000000;
-                sec++;
-        }
-
-        tv->tv_sec = sec;
-        tv->tv_usec = usec;
-}
-EXPORT_SYMBOL(do_gettimeofday);
-
-int do_settimeofday(struct timespec *tv)
-{
-        time_t wtm_sec, sec = tv->tv_sec;
-        long wtm_nsec, nsec = tv->tv_nsec;
-
-        if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
-                return -EINVAL;
-
-        write_seqlock_irq(&xtime_lock);
-        /*
-         * This is revolting. We need to set "xtime" correctly. However, the
-         * value in this location is the value at the most recent update of
-         * wall time.  Discover what correction gettimeofday() would have
-         * made, and then undo it!
-         */
-        nsec -= 1000 * usecs_since_tick();
-
-        wtm_sec  = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
-        wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
-
-        set_normalized_timespec(&xtime, sec, nsec);
-        set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
-
-        ntp_clear();
-        write_sequnlock_irq(&xtime_lock);
-        clock_was_set();
-
-        return 0;
-}
-EXPORT_SYMBOL(do_settimeofday);
-
-/* Dummy RTC ops */
-static void null_rtc_get_time(struct timespec *tv)
-{
-        tv->tv_sec = mktime(2000, 1, 1, 0, 0, 0);
-        tv->tv_nsec = 0;
-}
-
-static int null_rtc_set_time(const time_t secs)
-{
-        return 0;
-}
-
-void (*rtc_sh_get_time)(struct timespec *) = null_rtc_get_time;
-int (*rtc_sh_set_time)(const time_t) = null_rtc_set_time;
-
-/* last time the RTC clock got updated */
-static long last_rtc_update;
-
-/*
- * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "do_timer()" routine every clocktick
- */
-static inline void do_timer_interrupt(void)
-{
-        unsigned long long current_ctc;
-
-        if (current->pid)
-                profile_tick(CPU_PROFILING);
-
-        /*
-         * Here we are in the timer irq handler. We just have irqs locally
-         * disabled but we don't know if the timer_bh is running on the other
-         * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
-         * the irq version of write_lock because as just said we have irq
-         * locally disabled. -arca
-         */
-        write_seqlock(&xtime_lock);
-        asm ("getcon cr62, %0" : "=r" (current_ctc));
-        ctc_last_interrupt = (unsigned long) current_ctc;
-
-        do_timer(1);
-
-        /*
-         * If we have an externally synchronized Linux clock, then update
-         * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
-         * called as close as possible to 500 ms before the new second starts.
-         */
-        if (ntp_synced() &&
-            xtime.tv_sec > last_rtc_update + 660 &&
-            (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
-            (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
-                if (rtc_sh_set_time(xtime.tv_sec) == 0)
-                        last_rtc_update = xtime.tv_sec;
-                else
-                        /* do it again in 60 s */
-                        last_rtc_update = xtime.tv_sec - 600;
-        }
-        write_sequnlock(&xtime_lock);
-
-#ifndef CONFIG_SMP
-        update_process_times(user_mode(get_irq_regs()));
-#endif
-}
-
-/*
- * This is the same as the above, except we _also_ save the current
- * Time Stamp Counter value at the time of the timer interrupt, so that
- * we later on can estimate the time of day more exactly.
- */
-static irqreturn_t timer_interrupt(int irq, void *dev_id)
-{
-        unsigned long timer_status;
-
-        /* Clear UNF bit */
-        timer_status = ctrl_inw(TMU0_TCR);
-        timer_status &= ~0x100;
-        ctrl_outw(timer_status, TMU0_TCR);
-
-        do_timer_interrupt();
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction irq0  = {
-        .handler = timer_interrupt,
-        .flags = IRQF_DISABLED,
-        .name = "timer",
-};
-
-void __init time_init(void)
-{
-        unsigned long interval;
-        struct clk *clk;
-
-        tmu_base = onchip_remap(TMU_BASE, 1024, "TMU");
-        if (!tmu_base) {
-                panic("Unable to remap TMU\n");
-        }
-
-        rtc_base = onchip_remap(RTC_BASE, 1024, "RTC");
-        if (!rtc_base) {
-                panic("Unable to remap RTC\n");
-        }
-
-        clk = clk_get(NULL, "cpu_clk");
-        scaled_recip_ctc_ticks_per_jiffy = ((1ULL << CTC_JIFFY_SCALE_SHIFT) /
-                        (unsigned long long)(clk_get_rate(clk) / HZ));
-
-        rtc_sh_get_time(&xtime);
-
-        setup_irq(TIMER_IRQ, &irq0);
-
-        clk = clk_get(NULL, "module_clk");
-        interval = (clk_get_rate(clk)/(HZ*4));
-
-        printk("Interval = %ld\n", interval);
-
-        /* Start TMU0 */
-        ctrl_outb(TMU_TSTR_OFF, TMU_TSTR);
-        ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
-        ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
-        ctrl_outl(interval, TMU0_TCOR);
-        ctrl_outl(interval, TMU0_TCNT);
-        ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
-}
-
-static struct resource rtc_resources[] = {
-        [0] = {
-                /* RTC base, filled in by rtc_init */
-                .flags  = IORESOURCE_IO,
-        },
-        [1] = {
-                /* Period IRQ */
-                .start  = IRQ_PRI,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                /* Carry IRQ */
-                .start  = IRQ_CUI,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                /* Alarm IRQ */
-                .start  = IRQ_ATI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device rtc_device = {
-        .name           = "sh-rtc",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(rtc_resources),
-        .resource       = rtc_resources,
-};
-
-static int __init rtc_init(void)
-{
-        rtc_resources[0].start  = rtc_base;
-        rtc_resources[0].end    = rtc_resources[0].start + 0x58 - 1;
-
-        return platform_device_register(&rtc_device);
-}
-device_initcall(rtc_init);
diff --git a/arch/sh/kernel/timers/Makefile b/arch/sh/kernel/timers/Makefile
deleted file mode 100644
index 0b7f8577193f..000000000000
--- a/arch/sh/kernel/timers/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Makefile for the various Linux/SuperH timers
-#
-
-obj-y   := timer.o
-
-obj-$(CONFIG_SH_TMU)            += timer-tmu.o
-obj-$(CONFIG_SH_MTU2)           += timer-mtu2.o
-obj-$(CONFIG_SH_CMT)            += timer-cmt.o
-
-obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)     += timer-broadcast.o
diff --git a/arch/sh/kernel/timers/timer-cmt.c b/arch/sh/kernel/timers/timer-cmt.c
deleted file mode 100644
index 9aa348658ae3..000000000000
--- a/arch/sh/kernel/timers/timer-cmt.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * arch/sh/kernel/timers/timer-cmt.c - CMT Timer Support
- *
- *  Copyright (C) 2005  Yoshinori Sato
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/seqlock.h>
-#include <asm/timer.h>
-#include <asm/rtc.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/clock.h>
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7619)
-#define CMT_CMSTR       0xf84a0070
-#define CMT_CMCSR_0     0xf84a0072
-#define CMT_CMCNT_0     0xf84a0074
-#define CMT_CMCOR_0     0xf84a0076
-#define CMT_CMCSR_1     0xf84a0078
-#define CMT_CMCNT_1     0xf84a007a
-#define CMT_CMCOR_1     0xf84a007c
-
-#define STBCR3          0xf80a0000
-#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR3) & ~0x10, STBCR3); } while(0)
-#define CMT_CMCSR_INIT  0x0040
-#define CMT_CMCSR_CALIB 0x0000
-#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7206) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7263)
-#define CMT_CMSTR       0xfffec000
-#define CMT_CMCSR_0     0xfffec002
-#define CMT_CMCNT_0     0xfffec004
-#define CMT_CMCOR_0     0xfffec006
-
-#define STBCR4          0xfffe040c
-#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR4) & ~0x04, STBCR4); } while(0)
-#define CMT_CMCSR_INIT  0x0040
-#define CMT_CMCSR_CALIB 0x0000
-#else
-#error "Unknown CPU SUBTYPE"
-#endif
-
-static unsigned long cmt_timer_get_offset(void)
-{
-        int count;
-        static unsigned short count_p = 0xffff;    /* for the first call after boot */
-        static unsigned long jiffies_p = 0;
-
-        /*
-         * cache volatile jiffies temporarily; we have IRQs turned off.
-         */
-        unsigned long jiffies_t;
-
-        /* timer count may underflow right here */
-        count =  ctrl_inw(CMT_CMCOR_0);
-        count -= ctrl_inw(CMT_CMCNT_0);
-
-        jiffies_t = jiffies;
-
-        /*
-         * avoiding timer inconsistencies (they are rare, but they happen)...
-         * there is one kind of problem that must be avoided here:
-         *  1. the timer counter underflows
-         */
-
-        if (jiffies_t == jiffies_p) {
-                if (count > count_p) {
-                        /* the nutcase */
-                        if (ctrl_inw(CMT_CMCSR_0) & 0x80) { /* Check CMF bit */
-                                count -= LATCH;
-                        } else {
-                                printk("%s (): hardware timer problem?\n",
-                                       __func__);
-                        }
-                }
-        } else
-                jiffies_p = jiffies_t;
-
-        count_p = count;
-
-        count = ((LATCH-1) - count) * TICK_SIZE;
-        count = (count + LATCH/2) / LATCH;
-
-        return count;
-}
-
-static irqreturn_t cmt_timer_interrupt(int irq, void *dev_id)
-{
-        unsigned long timer_status;
-
-        /* Clear CMF bit */
-        timer_status = ctrl_inw(CMT_CMCSR_0);
-        timer_status &= ~0x80;
-        ctrl_outw(timer_status, CMT_CMCSR_0);
-
-        handle_timer_tick();
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction cmt_irq = {
-        .name           = "timer",
-        .handler        = cmt_timer_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-};
-
-static void cmt_clk_init(struct clk *clk)
-{
-        u8 divisor = CMT_CMCSR_INIT & 0x3;
-        ctrl_inw(CMT_CMCSR_0);
-        ctrl_outw(CMT_CMCSR_INIT, CMT_CMCSR_0);
-        clk->parent = clk_get(NULL, "module_clk");
-        clk->rate = clk->parent->rate / (8 << (divisor << 1));
-}
-
-static void cmt_clk_recalc(struct clk *clk)
-{
-        u8 divisor = ctrl_inw(CMT_CMCSR_0) & 0x3;
-        clk->rate = clk->parent->rate / (8 << (divisor << 1));
-}
-
-static struct clk_ops cmt_clk_ops = {
-        .init           = cmt_clk_init,
-        .recalc         = cmt_clk_recalc,
-};
-
-static struct clk cmt0_clk = {
-        .name           = "cmt0_clk",
-        .ops            = &cmt_clk_ops,
-};
-
-static int cmt_timer_start(void)
-{
-        ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR);
-        return 0;
-}
-
-static int cmt_timer_stop(void)
-{
-        ctrl_outw(ctrl_inw(CMT_CMSTR) & ~0x01, CMT_CMSTR);
-        return 0;
-}
-
-static int cmt_timer_init(void)
-{
-        unsigned long interval;
-
-        cmt_clock_enable();
-
-        setup_irq(CONFIG_SH_TIMER_IRQ, &cmt_irq);
-
-        cmt0_clk.parent = clk_get(NULL, "module_clk");
-
-        cmt_timer_stop();
-
-        interval = cmt0_clk.parent->rate / 8 / HZ;
-        printk(KERN_INFO "Interval = %ld\n", interval);
-
-        ctrl_outw(interval, CMT_CMCOR_0);
-
-        clk_register(&cmt0_clk);
-        clk_enable(&cmt0_clk);
-
-        cmt_timer_start();
-
-        return 0;
-}
-
-static struct sys_timer_ops cmt_timer_ops = {
-        .init           = cmt_timer_init,
-        .start          = cmt_timer_start,
-        .stop           = cmt_timer_stop,
-#ifndef CONFIG_GENERIC_TIME
-        .get_offset     = cmt_timer_get_offset,
-#endif
-};
-
-struct sys_timer cmt_timer = {
-        .name   = "cmt",
-        .ops    = &cmt_timer_ops,
-};
diff --git a/arch/sh/kernel/timers/timer-mtu2.c b/arch/sh/kernel/timers/timer-mtu2.c
deleted file mode 100644
index 9b0ef0126479..000000000000
--- a/arch/sh/kernel/timers/timer-mtu2.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * arch/sh/kernel/timers/timer-mtu2.c - MTU2 Timer Support
- *
- *  Copyright (C) 2005  Paul Mundt
- *
- * Based off of arch/sh/kernel/timers/timer-tmu.c
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/seqlock.h>
-#include <asm/timer.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/clock.h>
-
-/*
- * We use channel 1 for our lowly system timer. Channel 2 would be the other
- * likely candidate, but we leave it alone as it has higher divisors that
- * would be of more use to other more interesting applications.
- *
- * TODO: Presently we only implement a 16-bit single-channel system timer.
- * However, we can implement channel cascade if we go the overflow route and
- * get away with using 2 MTU2 channels as a 32-bit timer.
- */
-#define MTU2_TSTR       0xfffe4280
-#define MTU2_TCR_1      0xfffe4380
-#define MTU2_TMDR_1     0xfffe4381
-#define MTU2_TIOR_1     0xfffe4382
-#define MTU2_TIER_1     0xfffe4384
-#define MTU2_TSR_1      0xfffe4385
-#define MTU2_TCNT_1     0xfffe4386      /* 16-bit counter */
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7201) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7203)
-#define MTU2_TGRA_1     0xfffe4388
-#else
-#define MTU2_TGRA_1     0xfffe438a
-#endif
-
-#define STBCR3          0xfffe0408
-
-#define MTU2_TSTR_CST1  (1 << 1)        /* Counter Start 1 */
-
-#define MTU2_TSR_TGFA   (1 << 0)        /* GRA compare match */
-
-#define MTU2_TIER_TGIEA (1 << 0)        /* GRA compare match  interrupt enable */
-
-#define MTU2_TCR_INIT   0x22
-
-#define MTU2_TCR_CALIB  0x00
-
-static unsigned long mtu2_timer_get_offset(void)
-{
-        int count;
-        static int count_p = 0x7fff;    /* for the first call after boot */
-        static unsigned long jiffies_p = 0;
-
-        /*
-         * cache volatile jiffies temporarily; we have IRQs turned off.
-         */
-        unsigned long jiffies_t;
-
-        /* timer count may underflow right here */
-        count = ctrl_inw(MTU2_TCNT_1);  /* read the latched count */
-
-        jiffies_t = jiffies;
-
-        /*
-         * avoiding timer inconsistencies (they are rare, but they happen)...
-         * there is one kind of problem that must be avoided here:
-         *  1. the timer counter underflows
-         */
-
-        if (jiffies_t == jiffies_p) {
-                if (count > count_p) {
-                        if (ctrl_inb(MTU2_TSR_1) & MTU2_TSR_TGFA) {
-                                count -= LATCH;
-                        } else {
-                                printk("%s (): hardware timer problem?\n",
-                                       __func__);
-                        }
-                }
-        } else
-                jiffies_p = jiffies_t;
-
-        count_p = count;
-
-        count = ((LATCH-1) - count) * TICK_SIZE;
-        count = (count + LATCH/2) / LATCH;
-
-        return count;
-}
-
-static irqreturn_t mtu2_timer_interrupt(int irq, void *dev_id)
-{
-        unsigned long timer_status;
-
-        /* Clear TGFA bit */
-        timer_status = ctrl_inb(MTU2_TSR_1);
-        timer_status &= ~MTU2_TSR_TGFA;
-        ctrl_outb(timer_status, MTU2_TSR_1);
-
-        /* Do timer tick */
-        handle_timer_tick();
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction mtu2_irq = {
-        .name           = "timer",
-        .handler        = mtu2_timer_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-};
-
-static unsigned int divisors[] = { 1, 4, 16, 64, 1, 1, 256 };
-
-static void mtu2_clk_init(struct clk *clk)
-{
-        u8 idx = MTU2_TCR_INIT & 0x7;
-
-        clk->rate = clk->parent->rate / divisors[idx];
-        /* Start TCNT counting */
-        ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
-
-}
-
-static void mtu2_clk_recalc(struct clk *clk)
-{
-        u8 idx = ctrl_inb(MTU2_TCR_1) & 0x7;
-        clk->rate = clk->parent->rate / divisors[idx];
-}
-
-static struct clk_ops mtu2_clk_ops = {
-        .init           = mtu2_clk_init,
-        .recalc         = mtu2_clk_recalc,
-};
-
-static struct clk mtu2_clk1 = {
-        .name           = "mtu2_clk1",
-        .ops            = &mtu2_clk_ops,
-};
-
-static int mtu2_timer_start(void)
-{
-        ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
-        return 0;
-}
-
-static int mtu2_timer_stop(void)
-{
-        ctrl_outb(ctrl_inb(MTU2_TSTR) & ~MTU2_TSTR_CST1, MTU2_TSTR);
-        return 0;
-}
-
-static int mtu2_timer_init(void)
-{
-        unsigned long interval;
-
-        setup_irq(CONFIG_SH_TIMER_IRQ, &mtu2_irq);
-
-        mtu2_clk1.parent = clk_get(NULL, "module_clk");
-
-        ctrl_outb(ctrl_inb(STBCR3) & (~0x20), STBCR3);
-
-        /* Normal operation */
-        ctrl_outb(0, MTU2_TMDR_1);
-        ctrl_outb(MTU2_TCR_INIT, MTU2_TCR_1);
-        ctrl_outb(0x01, MTU2_TIOR_1);
-
-        /* Enable underflow interrupt */
-        ctrl_outb(ctrl_inb(MTU2_TIER_1) | MTU2_TIER_TGIEA, MTU2_TIER_1);
-
-        interval = CONFIG_SH_PCLK_FREQ / 16 / HZ;
-        printk(KERN_INFO "Interval = %ld\n", interval);
-
-        ctrl_outw(interval, MTU2_TGRA_1);
-        ctrl_outw(0, MTU2_TCNT_1);
-
-        clk_register(&mtu2_clk1);
-        clk_enable(&mtu2_clk1);
-
-        return 0;
-}
-
-struct sys_timer_ops mtu2_timer_ops = {
-        .init           = mtu2_timer_init,
-        .start          = mtu2_timer_start,
-        .stop           = mtu2_timer_stop,
-#ifndef CONFIG_GENERIC_TIME
-        .get_offset     = mtu2_timer_get_offset,
-#endif
-};
-
-struct sys_timer mtu2_timer = {
-        .name   = "mtu2",
-        .ops    = &mtu2_timer_ops,
-};
diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c
deleted file mode 100644
index fe8d8930ccb6..000000000000
--- a/arch/sh/kernel/timers/timer-tmu.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
- *
- *  Copyright (C) 2005 - 2007  Paul Mundt
- *
- * TMU handling code hacked out of arch/sh/kernel/time.c
- *
- *  Copyright (C) 1999  Tetsuya Okada & Niibe Yutaka
- *  Copyright (C) 2000  Philipp Rumpf <prumpf@tux.org>
- *  Copyright (C) 2002, 2003, 2004  Paul Mundt
- *  Copyright (C) 2002  M. R. Brown  <mrbrown@linux-sh.org>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/seqlock.h>
-#include <linux/clockchips.h>
-#include <asm/timer.h>
-#include <asm/rtc.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/clock.h>
-
-#define TMU_TOCR_INIT   0x00
-#define TMU_TCR_INIT    0x0020
-
-#define TMU0            (0)
-#define TMU1            (1)
-
-static inline void _tmu_start(int tmu_num)
-{
-        ctrl_outb(ctrl_inb(TMU_012_TSTR) | (0x1<<tmu_num), TMU_012_TSTR);
-}
-
-static inline void _tmu_set_irq(int tmu_num, int enabled)
-{
-        register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
-        ctrl_outw( (enabled ? ctrl_inw(tmu_tcr) | (1<<5) : ctrl_inw(tmu_tcr) & ~(1<<5)), tmu_tcr);
-}
-
-static inline void _tmu_stop(int tmu_num)
-{
-        ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~(0x1<<tmu_num), TMU_012_TSTR);
-}
-
-static inline void _tmu_clear_status(int tmu_num)
-{
-        register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
-        /* Clear UNF bit */
-        ctrl_outw(ctrl_inw(tmu_tcr) & ~0x100, tmu_tcr);
-}
-
-static inline unsigned long _tmu_read(int tmu_num)
-{
-        return ctrl_inl(TMU0_TCNT+0xC*tmu_num);
-}
-
-static int tmu_timer_start(void)
-{
-        _tmu_start(TMU0);
-        _tmu_start(TMU1);
-        _tmu_set_irq(TMU0,1);
-        return 0;
-}
-
-static int tmu_timer_stop(void)
-{
-        _tmu_stop(TMU0);
-        _tmu_stop(TMU1);
-        _tmu_clear_status(TMU0);
-        return 0;
-}
-
-/*
- * also when the module_clk is scaled the TMU1
- * will show the same frequency
- */
-static int tmus_are_scaled;
-
-static cycle_t tmu_timer_read(struct clocksource *cs)
-{
-        return ((cycle_t)(~_tmu_read(TMU1)))<<tmus_are_scaled;
-}
-
-
-static unsigned long tmu_latest_interval[3];
-static void tmu_timer_set_interval(int tmu_num, unsigned long interval, unsigned int reload)
-{
-        unsigned long tmu_tcnt = TMU0_TCNT + tmu_num*0xC;
-        unsigned long tmu_tcor = TMU0_TCOR + tmu_num*0xC;
-
-        _tmu_stop(tmu_num);
-
-        ctrl_outl(interval, tmu_tcnt);
-        tmu_latest_interval[tmu_num] = interval;
-
-        /*
-         * TCNT reloads from TCOR on underflow, clear it if we don't
-         * intend to auto-reload
-         */
-        ctrl_outl( reload ? interval : 0 , tmu_tcor);
-
-        _tmu_start(tmu_num);
-}
-
-static int tmu_set_next_event(unsigned long cycles,
-                              struct clock_event_device *evt)
-{
-        tmu_timer_set_interval(TMU0,cycles, evt->mode == CLOCK_EVT_MODE_PERIODIC);
-        _tmu_set_irq(TMU0,1);
-        return 0;
-}
-
-static void tmu_set_mode(enum clock_event_mode mode,
-                         struct clock_event_device *evt)
-{
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                ctrl_outl(tmu_latest_interval[TMU0], TMU0_TCOR);
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                ctrl_outl(0, TMU0_TCOR);
-                break;
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-}
-
-static struct clock_event_device tmu0_clockevent = {
-        .name           = "tmu0",
-        .shift          = 32,
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .set_mode       = tmu_set_mode,
-        .set_next_event = tmu_set_next_event,
-};
-
-static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
-{
-        struct clock_event_device *evt = &tmu0_clockevent;
-        _tmu_clear_status(TMU0);
-        _tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT);
-
-        switch (tmu0_clockevent.mode) {
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_PERIODIC:
-                evt->event_handler(evt);
-                break;
-        default:
-                break;
-        }
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction tmu0_irq = {
-        .name           = "periodic/oneshot timer",
-        .handler        = tmu_timer_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-};
-
-static void __init tmu_clk_init(struct clk *clk)
-{
-        u8 divisor  = TMU_TCR_INIT & 0x7;
-        int tmu_num = clk->name[3]-'0';
-        ctrl_outw(TMU_TCR_INIT, TMU0_TCR+(tmu_num*0xC));
-        clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
-}
-
-static void tmu_clk_recalc(struct clk *clk)
-{
-        int tmu_num = clk->name[3]-'0';
-        unsigned long prev_rate = clk_get_rate(clk);
-        unsigned long flags;
-        u8 divisor = ctrl_inw(TMU0_TCR+tmu_num*0xC) & 0x7;
-        clk->rate  = clk_get_rate(clk->parent) / (4 << (divisor << 1));
-
-        if(prev_rate==clk_get_rate(clk))
-                return;
-
-        if(tmu_num)
-                return; /* No more work on TMU1 */
-
-        local_irq_save(flags);
-        tmus_are_scaled = (prev_rate > clk->rate);
-
-        _tmu_stop(TMU0);
-
-        tmu0_clockevent.mult = div_sc(clk->rate, NSEC_PER_SEC,
-                                tmu0_clockevent.shift);
-        tmu0_clockevent.max_delta_ns =
-                        clockevent_delta2ns(-1, &tmu0_clockevent);
-        tmu0_clockevent.min_delta_ns =
-                        clockevent_delta2ns(1, &tmu0_clockevent);
-
-        if (tmus_are_scaled)
-                tmu_latest_interval[TMU0] >>= 1;
-        else
-                tmu_latest_interval[TMU0] <<= 1;
-
-        tmu_timer_set_interval(TMU0,
-                tmu_latest_interval[TMU0],
-                tmu0_clockevent.mode == CLOCK_EVT_MODE_PERIODIC);
-
-        _tmu_start(TMU0);
-
-        local_irq_restore(flags);
-}
-
-static struct clk_ops tmu_clk_ops = {
-        .init           = tmu_clk_init,
-        .recalc         = tmu_clk_recalc,
-};
-
-static struct clk tmu0_clk = {
-        .name           = "tmu0_clk",
-        .ops            = &tmu_clk_ops,
-};
-
-static struct clk tmu1_clk = {
-        .name           = "tmu1_clk",
-        .ops            = &tmu_clk_ops,
-};
-
-static int tmu_timer_init(void)
-{
-        unsigned long interval;
-        unsigned long frequency;
-
-        setup_irq(CONFIG_SH_TIMER_IRQ, &tmu0_irq);
-
-        tmu0_clk.parent = clk_get(NULL, "module_clk");
-        tmu1_clk.parent = clk_get(NULL, "module_clk");
-
-        tmu_timer_stop();
-
-#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
-    !defined(CONFIG_CPU_SUBTYPE_SH7721) && \
-    !defined(CONFIG_CPU_SUBTYPE_SH7760) && \
-    !defined(CONFIG_CPU_SUBTYPE_SH7785) && \
-    !defined(CONFIG_CPU_SUBTYPE_SH7786) && \
-    !defined(CONFIG_CPU_SUBTYPE_SHX3)
-        ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
-#endif
-
-        clk_register(&tmu0_clk);
-        clk_register(&tmu1_clk);
-        clk_enable(&tmu0_clk);
-        clk_enable(&tmu1_clk);
-
-        frequency = clk_get_rate(&tmu0_clk);
-        interval = (frequency + HZ / 2) / HZ;
-
-        tmu_timer_set_interval(TMU0,interval, 1);
-        tmu_timer_set_interval(TMU1,~0,1);
-
-        _tmu_start(TMU1);
-
-        clocksource_sh.rating = 200;
-        clocksource_sh.mask = CLOCKSOURCE_MASK(32);
-        clocksource_sh.read = tmu_timer_read;
-        clocksource_sh.shift = 10;
-        clocksource_sh.mult = clocksource_hz2mult(clk_get_rate(&tmu1_clk),
-                                                  clocksource_sh.shift);
-        clocksource_sh.flags = CLOCK_SOURCE_IS_CONTINUOUS;
-        clocksource_register(&clocksource_sh);
-
-        tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
-                                      tmu0_clockevent.shift);
-        tmu0_clockevent.max_delta_ns =
-                        clockevent_delta2ns(-1, &tmu0_clockevent);
-        tmu0_clockevent.min_delta_ns =
-                        clockevent_delta2ns(1, &tmu0_clockevent);
-
-        tmu0_clockevent.cpumask = cpumask_of(0);
-        tmu0_clockevent.rating = 100;
-
-        clockevents_register_device(&tmu0_clockevent);
-
-        return 0;
-}
-
-static struct sys_timer_ops tmu_timer_ops = {
-        .init           = tmu_timer_init,
-        .start          = tmu_timer_start,
-        .stop           = tmu_timer_stop,
-};
-
-struct sys_timer tmu_timer = {
-        .name   = "tmu",
-        .ops    = &tmu_timer_ops,
-};
diff --git a/arch/sh/kernel/timers/timer.c b/arch/sh/kernel/timers/timer.c
deleted file mode 100644
index 4e7e747d1b69..000000000000
--- a/arch/sh/kernel/timers/timer.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * arch/sh/kernel/timers/timer.c - Common timer code
- *
- *  Copyright (C) 2005  Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/timer.h>
-#include <linux/string.h>
-#include <asm/timer.h>
-
-static struct sys_timer *sys_timers[] = {
-#ifdef CONFIG_SH_TMU
-        &tmu_timer,
-#endif
-#ifdef CONFIG_SH_MTU2
-        &mtu2_timer,
-#endif
-#ifdef CONFIG_SH_CMT
-        &cmt_timer,
-#endif
-        NULL,
-};
-
-static char timer_override[10];
-static int __init timer_setup(char *str)
-{
-        if (str)
-                strlcpy(timer_override, str, sizeof(timer_override));
-        return 1;
-}
-__setup("timer=", timer_setup);
-
-struct sys_timer *get_sys_timer(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(sys_timers); i++) {
-                struct sys_timer *t = sys_timers[i];
-
-                if (unlikely(!t))
-                        break;
-                if (unlikely(timer_override[0]))
-                        if ((strcmp(timer_override, t->name) != 0))
-                                continue;
-                if (likely(t->ops->init() == 0))
-                        return t;
-        }
-
-        return NULL;
-}
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index 438f1ebcc453..46348ed07cc3 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -22,11 +22,11 @@ static void handle_BUG(struct pt_regs *regs)
 
 int is_valid_bugaddr(unsigned long addr)
 {
-        unsigned short opcode;
+        insn_size_t opcode;
 
         if (addr < PAGE_OFFSET)
                 return 0;
-        if (probe_kernel_address((u16 *)addr, opcode))
+        if (probe_kernel_address((insn_size_t *)addr, opcode))
                 return 0;
 
         return opcode == TRAPA_BUG_OPCODE;
@@ -66,7 +66,7 @@ BUILD_TRAP_HANDLER(bug)
 
 #ifdef CONFIG_BUG
         if (__kernel_text_address(instruction_pointer(regs))) {
-                opcode_t insn = *(opcode_t *)instruction_pointer(regs);
+                insn_size_t insn = *(insn_size_t *)instruction_pointer(regs);
                 if (insn == TRAPA_BUG_OPCODE)
                         handle_BUG(regs);
         }
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index 30ca9c51e52d..2b772776fcda 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -34,6 +34,7 @@
 # define TRAP_ILLEGAL_SLOT_INST 6
 # define TRAP_ADDRESS_ERROR     9
 # ifdef CONFIG_CPU_SH2A
+#  define TRAP_UBC              12
 #  define TRAP_FPU_ERROR        13
 #  define TRAP_DIVZERO_ERROR    17
 #  define TRAP_DIVOVF_ERROR     18
@@ -176,7 +177,7 @@ static struct mem_access user_mem_access = {
  *   (if that instruction is in a branch delay slot)
  * - return 0 if emulation okay, -EFAULT on existential error
  */
-static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
+static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
                                 struct mem_access *ma)
 {
         int ret, index, count;
@@ -321,10 +322,10 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
  * - fetches the instruction from PC+2
  */
 static inline int handle_delayslot(struct pt_regs *regs,
-                                   opcode_t old_instruction,
+                                   insn_size_t old_instruction,
                                    struct mem_access *ma)
 {
-        opcode_t instruction;
+        insn_size_t instruction;
         void __user *addr = (void __user *)(regs->pc +
                 instruction_size(old_instruction));
 
@@ -364,7 +365,7 @@ static inline int handle_delayslot(struct pt_regs *regs,
 
 static int handle_unaligned_notify_count = 10;
 
-int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
+int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
                             struct mem_access *ma)
 {
         u_int rm;
@@ -522,7 +523,7 @@ asmlinkage void do_address_error(struct pt_regs *regs,
         unsigned long error_code = 0;
         mm_segment_t oldfs;
         siginfo_t info;
-        opcode_t instruction;
+        insn_size_t instruction;
         int tmp;
 
         /* Intentional ifdef */
@@ -849,6 +850,10 @@ void __init trap_init(void)
 #endif
 #endif
 
+#ifdef TRAP_UBC
+        set_exception_table_vec(TRAP_UBC, break_point_trap);
+#endif
+
         /* Setup VBR for boot cpu */
         per_cpu_trap_init();
 }
diff --git a/arch/sh/kernel/traps_64.c b/arch/sh/kernel/traps_64.c
index a85831cbf18b..267e5ebbb475 100644
--- a/arch/sh/kernel/traps_64.c
+++ b/arch/sh/kernel/traps_64.c
@@ -370,7 +370,6 @@ static int generate_and_check_address(struct pt_regs *regs,
                 return -1;
         }
 
-#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
         /* Check accessible.  For misaligned access in the kernel, assume the
            address is always accessible (and if not, just fault when the
            load/store gets done.) */
@@ -380,18 +379,13 @@ static int generate_and_check_address(struct pt_regs *regs,
                 }
                 /* Do access_ok check later - it depends on whether it's a load or a store. */
         }
-#endif
 
         *address = addr;
         return 0;
 }
 
-/* Default value as for sh */
-#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
 static int user_mode_unaligned_fixup_count = 10;
 static int user_mode_unaligned_fixup_enable = 1;
-#endif
-
 static int kernel_mode_unaligned_fixup_count = 32;
 
 static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
@@ -440,7 +434,6 @@ static int misaligned_load(struct pt_regs *regs,
         }
 
         destreg = (opcode >> 4) & 0x3f;
-#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
         if (user_mode(regs)) {
                 __u64 buffer;
 
@@ -470,9 +463,7 @@ static int misaligned_load(struct pt_regs *regs,
                                 width_shift, (unsigned long) regs->pc);
                         break;
                 }
-        } else
-#endif
-        {
+        } else {
                 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
                 __u64 lo, hi;
 
@@ -519,7 +510,6 @@ static int misaligned_store(struct pt_regs *regs,
         }
 
         srcreg = (opcode >> 4) & 0x3f;
-#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
         if (user_mode(regs)) {
                 __u64 buffer;
 
@@ -546,9 +536,7 @@ static int misaligned_store(struct pt_regs *regs,
                 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
                         return -1; /* fault */
                 }
-        } else
-#endif
-        {
+        } else {
                 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
                 __u64 val = regs->regs[srcreg];
 
@@ -576,7 +564,6 @@ static int misaligned_store(struct pt_regs *regs,
 
 }
 
-#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
 /* Never need to fix up misaligned FPU accesses within the kernel since that's a real
    error. */
 static int misaligned_fpu_load(struct pt_regs *regs,
@@ -727,7 +714,6 @@ static int misaligned_fpu_store(struct pt_regs *regs,
                 return -1;
         }
 }
-#endif
 
 static int misaligned_fixup(struct pt_regs *regs)
 {
@@ -735,12 +721,8 @@ static int misaligned_fixup(struct pt_regs *regs)
         int error;
         int major, minor;
 
-#if !defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
-        /* Never fixup user mode misaligned accesses without this option enabled. */
-        return -1;
-#else
-        if (!user_mode_unaligned_fixup_enable) return -1;
-#endif
+        if (!user_mode_unaligned_fixup_enable)
+                return -1;
 
         error = read_opcode(regs->pc, &opcode, user_mode(regs));
         if (error < 0) {
@@ -749,15 +731,12 @@ static int misaligned_fixup(struct pt_regs *regs)
         major = (opcode >> 26) & 0x3f;
         minor = (opcode >> 16) & 0xf;
 
-#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
         if (user_mode(regs) && (user_mode_unaligned_fixup_count > 0)) {
                 --user_mode_unaligned_fixup_count;
                 /* Only do 'count' worth of these reports, to remove a potential DoS against syslog */
                 printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
                        current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
-        } else
-#endif
-        if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
+        } else if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
                 --kernel_mode_unaligned_fixup_count;
                 if (in_interrupt()) {
                         printk("Fixing up unaligned kernelspace access in interrupt pc=0x%08x ins=0x%08lx\n",
@@ -830,7 +809,6 @@ static int misaligned_fixup(struct pt_regs *regs)
                         }
                         break;
 
-#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
                 case (0x94>>2): /* FLD.S */
                         error = misaligned_fpu_load(regs, opcode, 1, 2, 0);
                         break;
@@ -881,7 +859,6 @@ static int misaligned_fixup(struct pt_regs *regs)
                                 break;
                         }
                         break;
-#endif
 
                 default:
                         /* Fault */
@@ -907,7 +884,6 @@ static ctl_table unaligned_table[] = {
                 .mode           = 0644,
                 .proc_handler   = &proc_dointvec
         },
-#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
         {
                 .ctl_name       = CTL_UNNUMBERED,
                 .procname       = "user_reports",
@@ -923,7 +899,6 @@ static ctl_table unaligned_table[] = {
                 .maxlen         = sizeof(int),
                 .mode           = 0644,
                 .proc_handler   = &proc_dointvec},
-#endif
         {}
 };
 
diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S
index d7d4991f32af..f53c76acaede 100644
--- a/arch/sh/kernel/vmlinux.lds.S
+++ b/arch/sh/kernel/vmlinux.lds.S
@@ -1,5 +1,178 @@
-#ifdef CONFIG_SUPERH32
-# include "vmlinux_32.lds.S"
+/*
+ * ld script to make SuperH Linux kernel
+ * Written by Niibe Yutaka and Paul Mundt
+ */
+#ifdef CONFIG_SUPERH64
+#define LOAD_OFFSET     CONFIG_PAGE_OFFSET
+OUTPUT_ARCH(sh:sh5)
 #else
-# include "vmlinux_64.lds.S"
+#define LOAD_OFFSET     0
+OUTPUT_ARCH(sh)
 #endif
+
+#include <asm/thread_info.h>
+#include <asm/cache.h>
+#include <asm-generic/vmlinux.lds.h>
+
+ENTRY(_start)
+SECTIONS
+{
+#ifdef CONFIG_PMB_FIXED
+        . = CONFIG_PAGE_OFFSET + (CONFIG_MEMORY_START & 0x1fffffff) +
+            CONFIG_ZERO_PAGE_OFFSET;
+#elif defined(CONFIG_32BIT)
+        . = CONFIG_PAGE_OFFSET + CONFIG_ZERO_PAGE_OFFSET;
+#else
+        . = CONFIG_PAGE_OFFSET + CONFIG_MEMORY_START + CONFIG_ZERO_PAGE_OFFSET;
+#endif
+
+        _text = .;              /* Text and read-only data */
+
+        .empty_zero_page : AT(ADDR(.empty_zero_page) - LOAD_OFFSET) {
+                *(.empty_zero_page)
+        } = 0
+
+        .text : AT(ADDR(.text) - LOAD_OFFSET) {
+                HEAD_TEXT
+                TEXT_TEXT
+
+#ifdef CONFIG_SUPERH64
+                *(.text64)
+                *(.text..SHmedia32)
+#endif
+
+                SCHED_TEXT
+                LOCK_TEXT
+                KPROBES_TEXT
+                IRQENTRY_TEXT
+                *(.fixup)
+                *(.gnu.warning)
+                _etext = .;             /* End of text section */
+        } = 0x0009
+
+        . = ALIGN(16);          /* Exception table */
+        __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
+                __start___ex_table = .;
+                *(__ex_table)
+                __stop___ex_table = .;
+        }
+
+        NOTES
+        RO_DATA(PAGE_SIZE)
+
+        /*
+         * Code which must be executed uncached and the associated data
+         */
+        . = ALIGN(PAGE_SIZE);
+        .uncached : AT(ADDR(.uncached) - LOAD_OFFSET) {
+                __uncached_start = .;
+                *(.uncached.text)
+                *(.uncached.data)
+                __uncached_end = .;
+        }
+
+        . = ALIGN(THREAD_SIZE);
+        .data : AT(ADDR(.data) - LOAD_OFFSET) {         /* Data */
+                *(.data.init_task)
+
+                . = ALIGN(L1_CACHE_BYTES);
+                *(.data.cacheline_aligned)
+
+                . = ALIGN(L1_CACHE_BYTES);
+                *(.data.read_mostly)
+
+                . = ALIGN(PAGE_SIZE);
+                *(.data.page_aligned)
+
+                __nosave_begin = .;
+                *(.data.nosave)
+                . = ALIGN(PAGE_SIZE);
+                __nosave_end = .;
+
+                DATA_DATA
+                CONSTRUCTORS
+        }
+
+        _edata = .;                     /* End of data section */
+
+        . = ALIGN(PAGE_SIZE);           /* Init code and data */
+        .init.text : AT(ADDR(.init.text) - LOAD_OFFSET) {
+                __init_begin = .;
+                _sinittext = .;
+                INIT_TEXT
+                _einittext = .;
+        }
+
+        .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) { INIT_DATA }
+
+        . = ALIGN(16);
+        .init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) {
+                __setup_start = .;
+                *(.init.setup)
+                __setup_end = .;
+        }
+
+        .initcall.init : AT(ADDR(.initcall.init) - LOAD_OFFSET) {
+                __initcall_start = .;
+                INITCALLS
+                __initcall_end = .;
+        }
+
+        .con_initcall.init : AT(ADDR(.con_initcall.init) - LOAD_OFFSET) {
+                __con_initcall_start = .;
+                *(.con_initcall.init)
+                __con_initcall_end = .;
+        }
+
+        SECURITY_INIT
+
+#ifdef CONFIG_BLK_DEV_INITRD
+        . = ALIGN(PAGE_SIZE);
+        .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
+                __initramfs_start = .;
+                *(.init.ramfs)
+                __initramfs_end = .;
+        }
+#endif
+
+        . = ALIGN(4);
+        .machvec.init : AT(ADDR(.machvec.init) - LOAD_OFFSET) {
+                __machvec_start = .;
+                *(.machvec.init)
+                __machvec_end = .;
+        }
+
+        PERCPU(PAGE_SIZE)
+
+        /*
+         * .exit.text is discarded at runtime, not link time, to deal with
+         * references from __bug_table
+         */
+        .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) { EXIT_TEXT }
+        .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) { EXIT_DATA }
+
+        . = ALIGN(PAGE_SIZE);
+        .bss : AT(ADDR(.bss) - LOAD_OFFSET) {
+                __init_end = .;
+                __bss_start = .;                /* BSS */
+                *(.bss.page_aligned)
+                *(.bss)
+                *(COMMON)
+                . = ALIGN(4);
+                _ebss = .;                      /* uClinux MTD sucks */
+                _end = . ;
+        }
+
+        /*
+         * When something in the kernel is NOT compiled as a module, the
+         * module cleanup code and data are put into these segments. Both
+         * can then be thrown away, as cleanup code is never called unless
+         * it's a module.
+         */
+        /DISCARD/ : {
+                *(.exitcall.exit)
+        }
+
+        STABS_DEBUG
+        DWARF_DEBUG
+}
diff --git a/arch/sh/kernel/vmlinux_32.lds.S b/arch/sh/kernel/vmlinux_32.lds.S
deleted file mode 100644
index dd9b2ee1312d..000000000000
--- a/arch/sh/kernel/vmlinux_32.lds.S
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * ld script to make SuperH Linux kernel
- * Written by Niibe Yutaka
- */
-#include <asm/thread_info.h>
-#include <asm/cache.h>
-#include <asm-generic/vmlinux.lds.h>
-
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-#else
-OUTPUT_FORMAT("elf32-shbig-linux", "elf32-shbig-linux", "elf32-shbig-linux")
-#endif
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-SECTIONS
-{
-#ifdef CONFIG_PMB_FIXED
-        . = CONFIG_PAGE_OFFSET + (CONFIG_MEMORY_START & 0x1fffffff) +
-            CONFIG_ZERO_PAGE_OFFSET;
-#elif defined(CONFIG_32BIT)
-        . = CONFIG_PAGE_OFFSET + CONFIG_ZERO_PAGE_OFFSET;
-#else
-        . = CONFIG_PAGE_OFFSET + CONFIG_MEMORY_START + CONFIG_ZERO_PAGE_OFFSET;
-#endif
-
-        _text = .;                      /* Text and read-only data */
-
-        .empty_zero_page : {
-                *(.empty_zero_page)
-        } = 0
-
-        .text : {
-                HEAD_TEXT
-                TEXT_TEXT
-                SCHED_TEXT
-                LOCK_TEXT
-                KPROBES_TEXT
-                *(.fixup)
-                *(.gnu.warning)
-        } = 0x0009
-
-        . = ALIGN(16);          /* Exception table */
-        __start___ex_table = .;
-        __ex_table : { *(__ex_table) }
-        __stop___ex_table = .;
-
-        _etext = .;                     /* End of text section */
-
-        NOTES
-        RO_DATA(PAGE_SIZE)
-
-        /*
-         * Code which must be executed uncached and the associated data
-         */
-        . = ALIGN(PAGE_SIZE);
-        __uncached_start = .;
-        .uncached.text : { *(.uncached.text) }
-        .uncached.data : { *(.uncached.data) }
-        __uncached_end = .;
-
-        . = ALIGN(THREAD_SIZE);
-        .data : {                       /* Data */
-                *(.data.init_task)
-
-                . = ALIGN(L1_CACHE_BYTES);
-                *(.data.cacheline_aligned)
-
-                . = ALIGN(L1_CACHE_BYTES);
-                *(.data.read_mostly)
-
-                . = ALIGN(PAGE_SIZE);
-                *(.data.page_aligned)
-
-                __nosave_begin = .;
-                *(.data.nosave)
-                . = ALIGN(PAGE_SIZE);
-                __nosave_end = .;
-
-                DATA_DATA
-                CONSTRUCTORS
-        }
-
-        _edata = .;                     /* End of data section */
-
-        . = ALIGN(PAGE_SIZE);           /* Init code and data */
-        __init_begin = .;
-        _sinittext = .;
-        .init.text : { INIT_TEXT }
-        _einittext = .;
-        .init.data : { INIT_DATA }
-
-        . = ALIGN(16);
-        __setup_start = .;
-        .init.setup : { *(.init.setup) }
-        __setup_end = .;
-
-        __initcall_start = .;
-        .initcall.init : {
-                INITCALLS
-        }
-        __initcall_end = .;
-        __con_initcall_start = .;
-        .con_initcall.init : { *(.con_initcall.init) }
-        __con_initcall_end = .;
-
-        SECURITY_INIT
-
-#ifdef CONFIG_BLK_DEV_INITRD
-        . = ALIGN(PAGE_SIZE);
-        __initramfs_start = .;
-        .init.ramfs : { *(.init.ramfs) }
-        __initramfs_end = .;
-#endif
-
-        . = ALIGN(4);
-        __machvec_start = .;
-        .machvec.init : { *(.machvec.init) }
-        __machvec_end = .;
-
-        PERCPU(PAGE_SIZE)
-
-        /*
-         * .exit.text is discarded at runtime, not link time, to deal with
-         * references from __bug_table
-         */
-        .exit.text : { EXIT_TEXT }
-        .exit.data : { EXIT_DATA }
-
-        . = ALIGN(PAGE_SIZE);
-        .bss : {
-                __init_end = .;
-                __bss_start = .;                /* BSS */
-                *(.bss.page_aligned)
-                *(.bss)
-                *(COMMON)
-                . = ALIGN(4);
-                _ebss = .;                      /* uClinux MTD sucks */
-                _end = . ;
-        }
-
-        /*
-         * When something in the kernel is NOT compiled as a module, the
-         * module cleanup code and data are put into these segments. Both
-         * can then be thrown away, as cleanup code is never called unless
-         * it's a module.
-         */
-        /DISCARD/ : {
-                *(.exitcall.exit)
-        }
-
-        STABS_DEBUG
-        DWARF_DEBUG
-}
diff --git a/arch/sh/kernel/vmlinux_64.lds.S b/arch/sh/kernel/vmlinux_64.lds.S
deleted file mode 100644
index 69664460c688..000000000000
--- a/arch/sh/kernel/vmlinux_64.lds.S
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * ld script to make SH64 Linux kernel
- *
- * Copyright (C) 2000, 2001  Paolo Alberelli
- *
- * benedict.gaster@superh.com:   2nd May 2002
- *    Add definition of empty_zero_page to be the first page of kernel image.
- *
- * benedict.gaster@superh.com:   3rd May 2002
- *    Added support for ramdisk, removing statically linked romfs at the
- *    same time.
- *
- * lethal@linux-sh.org:          9th May 2003
- *    Kill off GLOBAL_NAME() usage and other CDC-isms.
- *
- * lethal@linux-sh.org:         19th May 2003
- *    Remove support for ancient toolchains.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <asm/page.h>
-#include <asm/cache.h>
-#include <asm/thread_info.h>
-
-#define LOAD_OFFSET     CONFIG_PAGE_OFFSET
-#include <asm-generic/vmlinux.lds.h>
-
-OUTPUT_ARCH(sh:sh5)
-
-#define C_PHYS(x) AT (ADDR(x) - LOAD_OFFSET)
-
-ENTRY(__start)
-SECTIONS
-{
-        . = CONFIG_PAGE_OFFSET + CONFIG_MEMORY_START + PAGE_SIZE;
-        _text = .;                      /* Text and read-only data */
-
-        .empty_zero_page : C_PHYS(.empty_zero_page) {
-                *(.empty_zero_page)
-        } = 0
-
-        .text : C_PHYS(.text) {
-                HEAD_TEXT
-                TEXT_TEXT
-                *(.text64)
-                *(.text..SHmedia32)
-                SCHED_TEXT
-                LOCK_TEXT
-                KPROBES_TEXT
-                *(.fixup)
-                *(.gnu.warning)
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-        } = 0x6ff0fff0
-#else
-        } = 0xf0fff06f
-#endif
-
-        /* We likely want __ex_table to be Cache Line aligned */
-        . = ALIGN(L1_CACHE_BYTES);              /* Exception table */
-        __start___ex_table = .;
-        __ex_table : C_PHYS(__ex_table) { *(__ex_table) }
-        __stop___ex_table = .;
-
-        _etext = .;                     /* End of text section */
-
-        NOTES 
-        RO_DATA(PAGE_SIZE)
-
-        . = ALIGN(THREAD_SIZE);
-        .data : C_PHYS(.data) {                 /* Data */
-                *(.data.init_task)
-
-                . = ALIGN(L1_CACHE_BYTES);
-                *(.data.cacheline_aligned)
-
-                . = ALIGN(L1_CACHE_BYTES);
-                *(.data.read_mostly)
-
-                . = ALIGN(PAGE_SIZE);
-                *(.data.page_aligned)
-
-                __nosave_begin = .;
-                *(.data.nosave)
-                . = ALIGN(PAGE_SIZE);
-                __nosave_end = .;
-
-                DATA_DATA
-                CONSTRUCTORS
-        }
-
-        _edata = .;                     /* End of data section */
-
-        . = ALIGN(PAGE_SIZE);           /* Init code and data */
-        __init_begin = .;
-        _sinittext = .;
-        .init.text : C_PHYS(.init.text) { INIT_TEXT }
-        _einittext = .;
-        .init.data : C_PHYS(.init.data) { INIT_DATA }
-        . = ALIGN(L1_CACHE_BYTES);      /* Better if Cache Line aligned */
-        __setup_start = .;
-        .init.setup : C_PHYS(.init.setup) { *(.init.setup) }
-        __setup_end = .;
-        __initcall_start = .;
-        .initcall.init : C_PHYS(.initcall.init) {
-                INITCALLS
-        }
-        __initcall_end = .;
-        __con_initcall_start = .;
-        .con_initcall.init : C_PHYS(.con_initcall.init) {
-                *(.con_initcall.init)
-        }
-        __con_initcall_end = .;
-
-        SECURITY_INIT
-
-#ifdef CONFIG_BLK_DEV_INITRD
-        . = ALIGN(PAGE_SIZE);
-        __initramfs_start = .;
-        .init.ramfs : C_PHYS(.init.ramfs) { *(.init.ramfs) }
-        __initramfs_end = .;
-#endif
-
-        . = ALIGN(8);
-        __machvec_start = .;
-        .machvec.init : C_PHYS(.machvec.init) { *(.machvec.init) }
-        __machvec_end = .;
-
-        PERCPU(PAGE_SIZE)
-
-        /*
-         * .exit.text is discarded at runtime, not link time, to deal with
-         * references from __bug_table
-         */
-        .exit.text : C_PHYS(.exit.text) { EXIT_TEXT }
-        .exit.data : C_PHYS(.exit.data) { EXIT_DATA }
-
-        . = ALIGN(PAGE_SIZE);
-        .bss : C_PHYS(.bss) {
-                __init_end = .;
-                __bss_start = .;                /* BSS */
-                *(.bss.page_aligned)
-                *(.bss)
-                *(COMMON)
-                . = ALIGN(4);
-                _ebss = .;                      /* uClinux MTD sucks */
-                _end = . ;
-        }
-
-        /*
-         * When something in the kernel is NOT compiled as a module, the
-         * module cleanup code and data are put into these segments. Both
-         * can then be thrown away, as cleanup code is never called unless
-         * it's a module.
-         */
-        /DISCARD/ : {
-                *(.exitcall.exit)
-        }
-
-        STABS_DEBUG
-        DWARF_DEBUG
-}