sh: Preparation for uncached jumps through PMB.

Presently most of the 29-bit physical parts do P1/P2 segmentation
with a 1:1 cached/uncached mapping, jumping between the two to
control the caching behaviour. This provides the basic infrastructure
to maintain this behaviour on 32-bit physical parts that don't map
P1/P2 at all, using a shiny new linker section and corresponding
fixmap entry.

Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

3 files changed, 15 insertions, 6 deletions

diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index fd1688e6c61c..0f0c76a842e4 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -64,11 +64,11 @@ static void __init speculative_execution_init(void)
  * Generic first-level cache init
  */
 #ifdef CONFIG_SUPERH32
-static void __init cache_init(void)
+static void __uses_jump_to_uncached cache_init(void)
 {
         unsigned long ccr, flags;
 
-        jump_to_P2();
+        jump_to_uncached();
         ccr = ctrl_inl(CCR);
 
         /*
@@ -145,7 +145,7 @@ static void __init cache_init(void)
 #endif
 
         ctrl_outl(flags, CCR);
-        back_to_P1();
+        back_to_cached();
 }
 #else
 #define cache_init()    do { } while (0)
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index bf579e061e09..22070e43e34d 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -16,11 +16,11 @@
 #include <asm/cache.h>
 #include <asm/io.h>
 
-int __init detect_cpu_and_cache_system(void)
+int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
 {
         unsigned long addr0, addr1, data0, data1, data2, data3;
 
-        jump_to_P2();
+        jump_to_uncached();
         /*
          * Check if the entry shadows or not.
          * When shadowed, it's 128-entry system.
@@ -48,7 +48,7 @@ int __init detect_cpu_and_cache_system(void)
         ctrl_outl(data0&~SH_CACHE_VALID, addr0);
         ctrl_outl(data2&~SH_CACHE_VALID, addr1);
 
-        back_to_P1();
+        back_to_cached();
 
         boot_cpu_data.dcache.ways               = 4;
         boot_cpu_data.dcache.entry_shift        = 4;
diff --git a/arch/sh/kernel/vmlinux_32.lds.S b/arch/sh/kernel/vmlinux_32.lds.S
index 0956fb3681a3..50c69c18dced 100644
--- a/arch/sh/kernel/vmlinux_32.lds.S
+++ b/arch/sh/kernel/vmlinux_32.lds.S
@@ -43,6 +43,15 @@ SECTIONS
         NOTES
         RO_DATA(PAGE_SIZE)
 
+        /*
+         * Code which must be executed uncached and the associated data
+         */
+        . = ALIGN(PAGE_SIZE);
+        __uncached_start = .;
+        .uncached.text : { *(.uncached.text) }
+        .uncached.data : { *(.uncached.data) }
+        __uncached_end = .;
+
         . = ALIGN(THREAD_SIZE);
         .data : {                       /* Data */
                 *(.data.init_task)