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authorLinus Torvalds <torvalds@linux-foundation.org>2009-09-18 12:43:09 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-09-18 12:43:09 -0400
commit515b696b282f856c3ad1679ccd658120faa387d0 (patch)
treed9d7c1185c396617f128ca23463062308d11393b /arch/sh/kernel
parentfa877c71e2136bd682b45022c96d5e073ced9f58 (diff)
parent064a16dc41be879d12bd5de5d2f9d38d890e0ee7 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (262 commits) sh: mach-ecovec24: Add user debug switch support sh: Kill off unused se_skipped in alignment trap notification code. sh: Wire up HAVE_SYSCALL_TRACEPOINTS. video: sh_mobile_lcdcfb: use both register sets for display panning video: sh_mobile_lcdcfb: implement display panning sh: Fix up sh7705 flush_dcache_page() build. sh: kfr2r09: document the PLL/FLL <-> RF relationship. sh: mach-ecovec24: need asm/clock.h. sh: mach-ecovec24: deassert usb irq on boot. sh: Add KEYSC support for EcoVec24 sh: add kycr2_delay for sh_keysc sh: cpufreq: Include CPU id in info messages. sh: multi-evt support for SH-X3 proto CPU. sh: clkfwk: remove bogus set_bus_parent() from SH7709. sh: Fix the indication point of the liquid crystal of AP-325RXA(AP3300) sh: Add EcoVec24 romImage defconfig sh: USB disable process is needed if romImage boot for EcoVec24 sh: EcoVec24: add HIZA setting for LED sh: EcoVec24: write MAC address in boot sh: Add romImage support for EcoVec24 ...
Diffstat (limited to 'arch/sh/kernel')
-rw-r--r--arch/sh/kernel/Makefile44
-rw-r--r--arch/sh/kernel/Makefile_3237
-rw-r--r--arch/sh/kernel/Makefile_6419
-rw-r--r--arch/sh/kernel/asm-offsets.c1
-rw-r--r--arch/sh/kernel/cpu/Makefile2
-rw-r--r--arch/sh/kernel/cpu/hwblk.c155
-rw-r--r--arch/sh/kernel/cpu/init.c36
-rw-r--r--arch/sh/kernel/cpu/irq/ipr.c1
-rw-r--r--arch/sh/kernel/cpu/sh2/entry.S3
-rw-r--r--arch/sh/kernel/cpu/sh2/probe.c1
-rw-r--r--arch/sh/kernel/cpu/sh2a/entry.S3
-rw-r--r--arch/sh/kernel/cpu/sh2a/probe.c2
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7709.c11
-rw-r--r--arch/sh/kernel/cpu/sh3/entry.S102
-rw-r--r--arch/sh/kernel/cpu/sh3/ex.S4
-rw-r--r--arch/sh/kernel/cpu/sh3/probe.c2
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c21
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile9
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c63
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c113
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c124
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c130
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c106
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c117
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c121
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c2019
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c39
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c42
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c43
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c513
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c55
-rw-r--r--arch/sh/kernel/cpu/sh4a/smp-shx3.c2
-rw-r--r--arch/sh/kernel/cpu/sh5/probe.c2
-rw-r--r--arch/sh/kernel/cpu/shmobile/Makefile2
-rw-r--r--arch/sh/kernel/cpu/shmobile/cpuidle.c113
-rw-r--r--arch/sh/kernel/cpu/shmobile/pm.c42
-rw-r--r--arch/sh/kernel/cpu/shmobile/pm_runtime.c303
-rw-r--r--arch/sh/kernel/cpu/shmobile/sleep.S155
-rw-r--r--arch/sh/kernel/cpufreq.c10
-rw-r--r--arch/sh/kernel/dumpstack.c123
-rw-r--r--arch/sh/kernel/dwarf.c972
-rw-r--r--arch/sh/kernel/early_printk.c5
-rw-r--r--arch/sh/kernel/entry-common.S103
-rw-r--r--arch/sh/kernel/ftrace.c188
-rw-r--r--arch/sh/kernel/io.c97
-rw-r--r--arch/sh/kernel/io_generic.c50
-rw-r--r--arch/sh/kernel/io_trapped.c10
-rw-r--r--arch/sh/kernel/irq.c19
-rw-r--r--arch/sh/kernel/kgdb.c4
-rw-r--r--arch/sh/kernel/localtimer.c9
-rw-r--r--arch/sh/kernel/nmi_debug.c77
-rw-r--r--arch/sh/kernel/process_32.c25
-rw-r--r--arch/sh/kernel/process_64.c24
-rw-r--r--arch/sh/kernel/ptrace_32.c9
-rw-r--r--arch/sh/kernel/ptrace_64.c9
-rw-r--r--arch/sh/kernel/setup.c80
-rw-r--r--arch/sh/kernel/sh_ksyms_32.c10
-rw-r--r--arch/sh/kernel/sh_ksyms_64.c9
-rw-r--r--arch/sh/kernel/signal_32.c12
-rw-r--r--arch/sh/kernel/signal_64.c38
-rw-r--r--arch/sh/kernel/stacktrace.c98
-rw-r--r--arch/sh/kernel/sys_sh.c43
-rw-r--r--arch/sh/kernel/syscalls_32.S2
-rw-r--r--arch/sh/kernel/syscalls_64.S2
-rw-r--r--arch/sh/kernel/time.c31
-rw-r--r--arch/sh/kernel/traps.c45
-rw-r--r--arch/sh/kernel/traps_32.c218
-rw-r--r--arch/sh/kernel/unwinder.c164
-rw-r--r--arch/sh/kernel/vmlinux.lds.S94
70 files changed, 6332 insertions, 807 deletions
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index 349d833deab5..a2d0a40f3848 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -1,5 +1,41 @@
1ifeq ($(CONFIG_SUPERH32),y) 1#
2include ${srctree}/arch/sh/kernel/Makefile_32 2# Makefile for the Linux/SuperH kernel.
3else 3#
4include ${srctree}/arch/sh/kernel/Makefile_64 4
5extra-y := head_$(BITS).o init_task.o vmlinux.lds
6
7ifdef CONFIG_FUNCTION_TRACER
8# Do not profile debug and lowlevel utilities
9CFLAGS_REMOVE_ftrace.o = -pg
5endif 10endif
11
12obj-y := debugtraps.o dumpstack.o idle.o io.o io_generic.o irq.o \
13 machvec.o nmi_debug.o process_$(BITS).o ptrace_$(BITS).o \
14 setup.o signal_$(BITS).o sys_sh.o sys_sh$(BITS).o \
15 syscalls_$(BITS).o time.o topology.o traps.o \
16 traps_$(BITS).o unwinder.o
17
18obj-y += cpu/
19obj-$(CONFIG_VSYSCALL) += vsyscall/
20obj-$(CONFIG_SMP) += smp.o
21obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o
22obj-$(CONFIG_KGDB) += kgdb.o
23obj-$(CONFIG_SH_CPU_FREQ) += cpufreq.o
24obj-$(CONFIG_MODULES) += sh_ksyms_$(BITS).o module.o
25obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
26obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
27obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
28obj-$(CONFIG_STACKTRACE) += stacktrace.o
29obj-$(CONFIG_IO_TRAPPED) += io_trapped.o
30obj-$(CONFIG_KPROBES) += kprobes.o
31obj-$(CONFIG_GENERIC_GPIO) += gpio.o
32obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
33obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o
34obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
35obj-$(CONFIG_DUMP_CODE) += disassemble.o
36obj-$(CONFIG_HIBERNATION) += swsusp.o
37obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o
38
39obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o
40
41EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/Makefile_32 b/arch/sh/kernel/Makefile_32
deleted file mode 100644
index 9411e3e31e68..000000000000
--- a/arch/sh/kernel/Makefile_32
+++ /dev/null
@@ -1,37 +0,0 @@
1#
2# Makefile for the Linux/SuperH kernel.
3#
4
5extra-y := head_32.o init_task.o vmlinux.lds
6
7ifdef CONFIG_FUNCTION_TRACER
8# Do not profile debug and lowlevel utilities
9CFLAGS_REMOVE_ftrace.o = -pg
10endif
11
12obj-y := debugtraps.o idle.o io.o io_generic.o irq.o \
13 machvec.o process_32.o ptrace_32.o setup.o signal_32.o \
14 sys_sh.o sys_sh32.o syscalls_32.o time.o topology.o \
15 traps.o traps_32.o
16
17obj-y += cpu/
18obj-$(CONFIG_VSYSCALL) += vsyscall/
19obj-$(CONFIG_SMP) += smp.o
20obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o
21obj-$(CONFIG_KGDB) += kgdb.o
22obj-$(CONFIG_SH_CPU_FREQ) += cpufreq.o
23obj-$(CONFIG_MODULES) += sh_ksyms_32.o module.o
24obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
25obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
26obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
27obj-$(CONFIG_STACKTRACE) += stacktrace.o
28obj-$(CONFIG_IO_TRAPPED) += io_trapped.o
29obj-$(CONFIG_KPROBES) += kprobes.o
30obj-$(CONFIG_GENERIC_GPIO) += gpio.o
31obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
32obj-$(CONFIG_DUMP_CODE) += disassemble.o
33obj-$(CONFIG_HIBERNATION) += swsusp.o
34
35obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o
36
37EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/Makefile_64 b/arch/sh/kernel/Makefile_64
deleted file mode 100644
index 67b9f6c6326b..000000000000
--- a/arch/sh/kernel/Makefile_64
+++ /dev/null
@@ -1,19 +0,0 @@
1extra-y := head_64.o init_task.o vmlinux.lds
2
3obj-y := debugtraps.o idle.o io.o io_generic.o irq.o machvec.o process_64.o \
4 ptrace_64.o setup.o signal_64.o sys_sh.o sys_sh64.o \
5 syscalls_64.o time.o topology.o traps.o traps_64.o
6
7obj-y += cpu/
8obj-$(CONFIG_SMP) += smp.o
9obj-$(CONFIG_SH_CPU_FREQ) += cpufreq.o
10obj-$(CONFIG_MODULES) += sh_ksyms_64.o module.o
11obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
12obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
13obj-$(CONFIG_STACKTRACE) += stacktrace.o
14obj-$(CONFIG_IO_TRAPPED) += io_trapped.o
15obj-$(CONFIG_GENERIC_GPIO) += gpio.o
16
17obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o
18
19EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/asm-offsets.c b/arch/sh/kernel/asm-offsets.c
index 99aceb28ee24..d218e808294e 100644
--- a/arch/sh/kernel/asm-offsets.c
+++ b/arch/sh/kernel/asm-offsets.c
@@ -26,6 +26,7 @@ int main(void)
26 DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); 26 DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
27 DEFINE(TI_PRE_COUNT, offsetof(struct thread_info, preempt_count)); 27 DEFINE(TI_PRE_COUNT, offsetof(struct thread_info, preempt_count));
28 DEFINE(TI_RESTART_BLOCK,offsetof(struct thread_info, restart_block)); 28 DEFINE(TI_RESTART_BLOCK,offsetof(struct thread_info, restart_block));
29 DEFINE(TI_SIZE, sizeof(struct thread_info));
29 30
30#ifdef CONFIG_HIBERNATION 31#ifdef CONFIG_HIBERNATION
31 DEFINE(PBE_ADDRESS, offsetof(struct pbe, address)); 32 DEFINE(PBE_ADDRESS, offsetof(struct pbe, address));
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index eecad7cbd61e..3d6b9312dc47 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -19,4 +19,4 @@ obj-$(CONFIG_UBC_WAKEUP) += ubc.o
19obj-$(CONFIG_SH_ADC) += adc.o 19obj-$(CONFIG_SH_ADC) += adc.o
20obj-$(CONFIG_SH_CLK_CPG) += clock-cpg.o 20obj-$(CONFIG_SH_CLK_CPG) += clock-cpg.o
21 21
22obj-y += irq/ init.o clock.o 22obj-y += irq/ init.o clock.o hwblk.o
diff --git a/arch/sh/kernel/cpu/hwblk.c b/arch/sh/kernel/cpu/hwblk.c
new file mode 100644
index 000000000000..c0ad7d46e784
--- /dev/null
+++ b/arch/sh/kernel/cpu/hwblk.c
@@ -0,0 +1,155 @@
1#include <linux/clk.h>
2#include <linux/compiler.h>
3#include <linux/slab.h>
4#include <linux/io.h>
5#include <linux/spinlock.h>
6#include <asm/suspend.h>
7#include <asm/hwblk.h>
8#include <asm/clock.h>
9
10static DEFINE_SPINLOCK(hwblk_lock);
11
12static void hwblk_area_mod_cnt(struct hwblk_info *info,
13 int area, int counter, int value, int goal)
14{
15 struct hwblk_area *hap = info->areas + area;
16
17 hap->cnt[counter] += value;
18
19 if (hap->cnt[counter] != goal)
20 return;
21
22 if (hap->flags & HWBLK_AREA_FLAG_PARENT)
23 hwblk_area_mod_cnt(info, hap->parent, counter, value, goal);
24}
25
26
27static int __hwblk_mod_cnt(struct hwblk_info *info, int hwblk,
28 int counter, int value, int goal)
29{
30 struct hwblk *hp = info->hwblks + hwblk;
31
32 hp->cnt[counter] += value;
33 if (hp->cnt[counter] == goal)
34 hwblk_area_mod_cnt(info, hp->area, counter, value, goal);
35
36 return hp->cnt[counter];
37}
38
39static void hwblk_mod_cnt(struct hwblk_info *info, int hwblk,
40 int counter, int value, int goal)
41{
42 unsigned long flags;
43
44 spin_lock_irqsave(&hwblk_lock, flags);
45 __hwblk_mod_cnt(info, hwblk, counter, value, goal);
46 spin_unlock_irqrestore(&hwblk_lock, flags);
47}
48
49void hwblk_cnt_inc(struct hwblk_info *info, int hwblk, int counter)
50{
51 hwblk_mod_cnt(info, hwblk, counter, 1, 1);
52}
53
54void hwblk_cnt_dec(struct hwblk_info *info, int hwblk, int counter)
55{
56 hwblk_mod_cnt(info, hwblk, counter, -1, 0);
57}
58
59void hwblk_enable(struct hwblk_info *info, int hwblk)
60{
61 struct hwblk *hp = info->hwblks + hwblk;
62 unsigned long tmp;
63 unsigned long flags;
64 int ret;
65
66 spin_lock_irqsave(&hwblk_lock, flags);
67
68 ret = __hwblk_mod_cnt(info, hwblk, HWBLK_CNT_USAGE, 1, 1);
69 if (ret == 1) {
70 tmp = __raw_readl(hp->mstp);
71 tmp &= ~(1 << hp->bit);
72 __raw_writel(tmp, hp->mstp);
73 }
74
75 spin_unlock_irqrestore(&hwblk_lock, flags);
76}
77
78void hwblk_disable(struct hwblk_info *info, int hwblk)
79{
80 struct hwblk *hp = info->hwblks + hwblk;
81 unsigned long tmp;
82 unsigned long flags;
83 int ret;
84
85 spin_lock_irqsave(&hwblk_lock, flags);
86
87 ret = __hwblk_mod_cnt(info, hwblk, HWBLK_CNT_USAGE, -1, 0);
88 if (ret == 0) {
89 tmp = __raw_readl(hp->mstp);
90 tmp |= 1 << hp->bit;
91 __raw_writel(tmp, hp->mstp);
92 }
93
94 spin_unlock_irqrestore(&hwblk_lock, flags);
95}
96
97struct hwblk_info *hwblk_info;
98
99int __init hwblk_register(struct hwblk_info *info)
100{
101 hwblk_info = info;
102 return 0;
103}
104
105int __init __weak arch_hwblk_init(void)
106{
107 return 0;
108}
109
110int __weak arch_hwblk_sleep_mode(void)
111{
112 return SUSP_SH_SLEEP;
113}
114
115int __init hwblk_init(void)
116{
117 return arch_hwblk_init();
118}
119
120/* allow clocks to enable and disable hardware blocks */
121static int sh_hwblk_clk_enable(struct clk *clk)
122{
123 if (!hwblk_info)
124 return -ENOENT;
125
126 hwblk_enable(hwblk_info, clk->arch_flags);
127 return 0;
128}
129
130static void sh_hwblk_clk_disable(struct clk *clk)
131{
132 if (hwblk_info)
133 hwblk_disable(hwblk_info, clk->arch_flags);
134}
135
136static struct clk_ops sh_hwblk_clk_ops = {
137 .enable = sh_hwblk_clk_enable,
138 .disable = sh_hwblk_clk_disable,
139 .recalc = followparent_recalc,
140};
141
142int __init sh_hwblk_clk_register(struct clk *clks, int nr)
143{
144 struct clk *clkp;
145 int ret = 0;
146 int k;
147
148 for (k = 0; !ret && (k < nr); k++) {
149 clkp = clks + k;
150 clkp->ops = &sh_hwblk_clk_ops;
151 ret |= clk_register(clkp);
152 }
153
154 return ret;
155}
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index ad85421099cd..e932ebef4738 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * CPU init code 4 * CPU init code
5 * 5 *
6 * Copyright (C) 2002 - 2007 Paul Mundt 6 * Copyright (C) 2002 - 2009 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow 7 * Copyright (C) 2003 Richard Curnow
8 * 8 *
9 * This file is subject to the terms and conditions of the GNU General Public 9 * This file is subject to the terms and conditions of the GNU General Public
@@ -62,6 +62,37 @@ static void __init speculative_execution_init(void)
62#define speculative_execution_init() do { } while (0) 62#define speculative_execution_init() do { } while (0)
63#endif 63#endif
64 64
65#ifdef CONFIG_CPU_SH4A
66#define EXPMASK 0xff2f0004
67#define EXPMASK_RTEDS (1 << 0)
68#define EXPMASK_BRDSSLP (1 << 1)
69#define EXPMASK_MMCAW (1 << 4)
70
71static void __init expmask_init(void)
72{
73 unsigned long expmask = __raw_readl(EXPMASK);
74
75 /*
76 * Future proofing.
77 *
78 * Disable support for slottable sleep instruction
79 * and non-nop instructions in the rte delay slot.
80 */
81 expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP);
82
83 /*
84 * Enable associative writes to the memory-mapped cache array
85 * until the cache flush ops have been rewritten.
86 */
87 expmask |= EXPMASK_MMCAW;
88
89 __raw_writel(expmask, EXPMASK);
90 ctrl_barrier();
91}
92#else
93#define expmask_init() do { } while (0)
94#endif
95
65/* 2nd-level cache init */ 96/* 2nd-level cache init */
66void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void) 97void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void)
67{ 98{
@@ -268,11 +299,9 @@ asmlinkage void __init sh_cpu_init(void)
268 cache_init(); 299 cache_init();
269 300
270 if (raw_smp_processor_id() == 0) { 301 if (raw_smp_processor_id() == 0) {
271#ifdef CONFIG_MMU
272 shm_align_mask = max_t(unsigned long, 302 shm_align_mask = max_t(unsigned long,
273 current_cpu_data.dcache.way_size - 1, 303 current_cpu_data.dcache.way_size - 1,
274 PAGE_SIZE - 1); 304 PAGE_SIZE - 1);
275#endif
276 305
277 /* Boot CPU sets the cache shape */ 306 /* Boot CPU sets the cache shape */
278 detect_cache_shape(); 307 detect_cache_shape();
@@ -321,4 +350,5 @@ asmlinkage void __init sh_cpu_init(void)
321#endif 350#endif
322 351
323 speculative_execution_init(); 352 speculative_execution_init();
353 expmask_init();
324} 354}
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 808d99a48efb..c1508a90fc6a 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -35,6 +35,7 @@ static void disable_ipr_irq(unsigned int irq)
35 unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; 35 unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
36 /* Set the priority in IPR to 0 */ 36 /* Set the priority in IPR to 0 */
37 __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr); 37 __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr);
38 (void)__raw_readw(addr); /* Read back to flush write posting */
38} 39}
39 40
40static void enable_ipr_irq(unsigned int irq) 41static void enable_ipr_irq(unsigned int irq)
diff --git a/arch/sh/kernel/cpu/sh2/entry.S b/arch/sh/kernel/cpu/sh2/entry.S
index becc54c45692..c8a4331d9b8d 100644
--- a/arch/sh/kernel/cpu/sh2/entry.S
+++ b/arch/sh/kernel/cpu/sh2/entry.S
@@ -227,8 +227,9 @@ ENTRY(sh_bios_handler)
227 mov.l @r15+, r14 227 mov.l @r15+, r14
228 add #8,r15 228 add #8,r15
229 lds.l @r15+, pr 229 lds.l @r15+, pr
230 mov.l @r15+,r15
230 rte 231 rte
231 mov.l @r15+,r15 232 nop
232 .align 2 233 .align 2
2331: .long gdb_vbr_vector 2341: .long gdb_vbr_vector
234#endif /* CONFIG_SH_STANDARD_BIOS */ 235#endif /* CONFIG_SH_STANDARD_BIOS */
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index 5916d9096b99..1db6d8883888 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -29,6 +29,7 @@ int __init detect_cpu_and_cache_system(void)
29 */ 29 */
30 boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED; 30 boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
31 boot_cpu_data.icache = boot_cpu_data.dcache; 31 boot_cpu_data.icache = boot_cpu_data.dcache;
32 boot_cpu_data.family = CPU_FAMILY_SH2;
32 33
33 return 0; 34 return 0;
34} 35}
diff --git a/arch/sh/kernel/cpu/sh2a/entry.S b/arch/sh/kernel/cpu/sh2a/entry.S
index ab3903eeda5c..222742ddc0d6 100644
--- a/arch/sh/kernel/cpu/sh2a/entry.S
+++ b/arch/sh/kernel/cpu/sh2a/entry.S
@@ -176,8 +176,9 @@ ENTRY(sh_bios_handler)
176 movml.l @r15+,r14 176 movml.l @r15+,r14
177 add #8,r15 177 add #8,r15
178 lds.l @r15+, pr 178 lds.l @r15+, pr
179 mov.l @r15+,r15
179 rte 180 rte
180 mov.l @r15+,r15 181 nop
181 .align 2 182 .align 2
1821: .long gdb_vbr_vector 1831: .long gdb_vbr_vector
183#endif /* CONFIG_SH_STANDARD_BIOS */ 184#endif /* CONFIG_SH_STANDARD_BIOS */
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index e098e2f6aa08..6825d6507164 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -15,6 +15,8 @@
15 15
16int __init detect_cpu_and_cache_system(void) 16int __init detect_cpu_and_cache_system(void)
17{ 17{
18 boot_cpu_data.family = CPU_FAMILY_SH2A;
19
18 /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */ 20 /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */
19 boot_cpu_data.flags |= CPU_HAS_OP32; 21 boot_cpu_data.flags |= CPU_HAS_OP32;
20 22
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7709.c b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
index fa30b6017730..e8749505bd2a 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
@@ -22,13 +22,6 @@ static int stc_multipliers[] = { 1, 2, 4, 8, 3, 6, 1, 1 };
22static int ifc_divisors[] = { 1, 2, 4, 1, 3, 1, 1, 1 }; 22static int ifc_divisors[] = { 1, 2, 4, 1, 3, 1, 1, 1 };
23static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 }; 23static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
24 24
25static void set_bus_parent(struct clk *clk)
26{
27 struct clk *bus_clk = clk_get(NULL, "bus_clk");
28 clk->parent = bus_clk;
29 clk_put(bus_clk);
30}
31
32static void master_clk_init(struct clk *clk) 25static void master_clk_init(struct clk *clk)
33{ 26{
34 int frqcr = ctrl_inw(FRQCR); 27 int frqcr = ctrl_inw(FRQCR);
@@ -50,9 +43,6 @@ static unsigned long module_clk_recalc(struct clk *clk)
50} 43}
51 44
52static struct clk_ops sh7709_module_clk_ops = { 45static struct clk_ops sh7709_module_clk_ops = {
53#ifdef CLOCK_MODE_0_1_2_7
54 .init = set_bus_parent,
55#endif
56 .recalc = module_clk_recalc, 46 .recalc = module_clk_recalc,
57}; 47};
58 48
@@ -78,7 +68,6 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
78} 68}
79 69
80static struct clk_ops sh7709_cpu_clk_ops = { 70static struct clk_ops sh7709_cpu_clk_ops = {
81 .init = set_bus_parent,
82 .recalc = cpu_clk_recalc, 71 .recalc = cpu_clk_recalc,
83}; 72};
84 73
diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
index 3cb531f233f2..0151933e5253 100644
--- a/arch/sh/kernel/cpu/sh3/entry.S
+++ b/arch/sh/kernel/cpu/sh3/entry.S
@@ -53,10 +53,6 @@
53 * syscall # 53 * syscall #
54 * 54 *
55 */ 55 */
56#if defined(CONFIG_KGDB)
57NMI_VEC = 0x1c0 ! Must catch early for debounce
58#endif
59
60/* Offsets to the stack */ 56/* Offsets to the stack */
61OFF_R0 = 0 /* Return value. New ABI also arg4 */ 57OFF_R0 = 0 /* Return value. New ABI also arg4 */
62OFF_R1 = 4 /* New ABI: arg5 */ 58OFF_R1 = 4 /* New ABI: arg5 */
@@ -71,7 +67,6 @@ OFF_PC = (16*4)
71OFF_SR = (16*4+8) 67OFF_SR = (16*4+8)
72OFF_TRA = (16*4+6*4) 68OFF_TRA = (16*4+6*4)
73 69
74
75#define k0 r0 70#define k0 r0
76#define k1 r1 71#define k1 r1
77#define k2 r2 72#define k2 r2
@@ -113,34 +108,34 @@ OFF_TRA = (16*4+6*4)
113#if defined(CONFIG_MMU) 108#if defined(CONFIG_MMU)
114 .align 2 109 .align 2
115ENTRY(tlb_miss_load) 110ENTRY(tlb_miss_load)
116 bra call_dpf 111 bra call_handle_tlbmiss
117 mov #0, r5 112 mov #0, r5
118 113
119 .align 2 114 .align 2
120ENTRY(tlb_miss_store) 115ENTRY(tlb_miss_store)
121 bra call_dpf 116 bra call_handle_tlbmiss
122 mov #1, r5 117 mov #1, r5
123 118
124 .align 2 119 .align 2
125ENTRY(initial_page_write) 120ENTRY(initial_page_write)
126 bra call_dpf 121 bra call_handle_tlbmiss
127 mov #1, r5 122 mov #2, r5
128 123
129 .align 2 124 .align 2
130ENTRY(tlb_protection_violation_load) 125ENTRY(tlb_protection_violation_load)
131 bra call_dpf 126 bra call_do_page_fault
132 mov #0, r5 127 mov #0, r5
133 128
134 .align 2 129 .align 2
135ENTRY(tlb_protection_violation_store) 130ENTRY(tlb_protection_violation_store)
136 bra call_dpf 131 bra call_do_page_fault
137 mov #1, r5 132 mov #1, r5
138 133
139call_dpf: 134call_handle_tlbmiss:
135 setup_frame_reg
140 mov.l 1f, r0 136 mov.l 1f, r0
141 mov r5, r8 137 mov r5, r8
142 mov.l @r0, r6 138 mov.l @r0, r6
143 mov r6, r9
144 mov.l 2f, r0 139 mov.l 2f, r0
145 sts pr, r10 140 sts pr, r10
146 jsr @r0 141 jsr @r0
@@ -151,16 +146,25 @@ call_dpf:
151 lds r10, pr 146 lds r10, pr
152 rts 147 rts
153 nop 148 nop
1540: mov.l 3f, r0 1490:
155 mov r9, r6
156 mov r8, r5 150 mov r8, r5
151call_do_page_fault:
152 mov.l 1f, r0
153 mov.l @r0, r6
154
155 sti
156
157 mov.l 3f, r0
158 mov.l 4f, r1
159 mov r15, r4
157 jmp @r0 160 jmp @r0
158 mov r15, r4 161 lds r1, pr
159 162
160 .align 2 163 .align 2
1611: .long MMU_TEA 1641: .long MMU_TEA
1622: .long __do_page_fault 1652: .long handle_tlbmiss
1633: .long do_page_fault 1663: .long do_page_fault
1674: .long ret_from_exception
164 168
165 .align 2 169 .align 2
166ENTRY(address_error_load) 170ENTRY(address_error_load)
@@ -256,7 +260,7 @@ restore_all:
256 ! 260 !
257 ! Calculate new SR value 261 ! Calculate new SR value
258 mov k3, k2 ! original SR value 262 mov k3, k2 ! original SR value
259 mov #0xf0, k1 263 mov #0xfffffff0, k1
260 extu.b k1, k1 264 extu.b k1, k1
261 not k1, k1 265 not k1, k1
262 and k1, k2 ! Mask original SR value 266 and k1, k2 ! Mask original SR value
@@ -272,21 +276,12 @@ restore_all:
2726: or k0, k2 ! Set the IMASK-bits 2766: or k0, k2 ! Set the IMASK-bits
273 ldc k2, ssr 277 ldc k2, ssr
274 ! 278 !
275#if defined(CONFIG_KGDB)
276 ! Clear in_nmi
277 mov.l 6f, k0
278 mov #0, k1
279 mov.b k1, @k0
280#endif
281 mov k4, r15 279 mov k4, r15
282 rte 280 rte
283 nop 281 nop
284 282
285 .align 2 283 .align 2
2865: .long 0x00001000 ! DSP 2845: .long 0x00001000 ! DSP
287#ifdef CONFIG_KGDB
2886: .long in_nmi
289#endif
2907: .long 0x30000000 2857: .long 0x30000000
291 286
292! common exception handler 287! common exception handler
@@ -478,23 +473,6 @@ ENTRY(save_low_regs)
478! 473!
479 .balign 512,0,512 474 .balign 512,0,512
480ENTRY(handle_interrupt) 475ENTRY(handle_interrupt)
481#if defined(CONFIG_KGDB)
482 mov.l 2f, k2
483 ! Debounce (filter nested NMI)
484 mov.l @k2, k0
485 mov.l 9f, k1
486 cmp/eq k1, k0
487 bf 11f
488 mov.l 10f, k1
489 tas.b @k1
490 bt 11f
491 rte
492 nop
493 .align 2
4949: .long NMI_VEC
49510: .long in_nmi
49611:
497#endif /* defined(CONFIG_KGDB) */
498 sts pr, k3 ! save original pr value in k3 476 sts pr, k3 ! save original pr value in k3
499 mova exception_data, k0 477 mova exception_data, k0
500 478
@@ -507,13 +485,49 @@ ENTRY(handle_interrupt)
507 bsr save_regs ! needs original pr value in k3 485 bsr save_regs ! needs original pr value in k3
508 mov #-1, k2 ! default vector kept in k2 486 mov #-1, k2 ! default vector kept in k2
509 487
488 setup_frame_reg
489
490 stc sr, r0 ! get status register
491 shlr2 r0
492 and #0x3c, r0
493 cmp/eq #0x3c, r0
494 bf 9f
495 TRACE_IRQS_OFF
4969:
497
510 ! Setup return address and jump to do_IRQ 498 ! Setup return address and jump to do_IRQ
511 mov.l 4f, r9 ! fetch return address 499 mov.l 4f, r9 ! fetch return address
512 lds r9, pr ! put return address in pr 500 lds r9, pr ! put return address in pr
513 mov.l 2f, r4 501 mov.l 2f, r4
514 mov.l 3f, r9 502 mov.l 3f, r9
515 mov.l @r4, r4 ! pass INTEVT vector as arg0 503 mov.l @r4, r4 ! pass INTEVT vector as arg0
504
505 shlr2 r4
506 shlr r4
507 mov r4, r0 ! save vector->jmp table offset for later
508
509 shlr2 r4 ! vector to IRQ# conversion
510 add #-0x10, r4
511
512 cmp/pz r4 ! is it a valid IRQ?
513 bt 10f
514
515 /*
516 * We got here as a result of taking the INTEVT path for something
517 * that isn't a valid hard IRQ, therefore we bypass the do_IRQ()
518 * path and special case the event dispatch instead. This is the
519 * expected path for the NMI (and any other brilliantly implemented
520 * exception), which effectively wants regular exception dispatch
521 * but is unfortunately reported through INTEVT rather than
522 * EXPEVT. Grr.
523 */
524 mov.l 6f, r9
525 mov.l @(r0, r9), r9
516 jmp @r9 526 jmp @r9
527 mov r15, r8 ! trap handlers take saved regs in r8
528
52910:
530 jmp @r9 ! Off to do_IRQ() we go.
517 mov r15, r5 ! pass saved registers as arg1 531 mov r15, r5 ! pass saved registers as arg1
518 532
519ENTRY(exception_none) 533ENTRY(exception_none)
diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S
index e5a0de39a2db..46610c35c232 100644
--- a/arch/sh/kernel/cpu/sh3/ex.S
+++ b/arch/sh/kernel/cpu/sh3/ex.S
@@ -48,9 +48,7 @@ ENTRY(exception_handling_table)
48 .long system_call ! Unconditional Trap /* 160 */ 48 .long system_call ! Unconditional Trap /* 160 */
49 .long exception_error ! reserved_instruction (filled by trap_init) /* 180 */ 49 .long exception_error ! reserved_instruction (filled by trap_init) /* 180 */
50 .long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/ 50 .long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/
51ENTRY(nmi_slot) 51 .long nmi_trap_handler /* 1C0 */ ! Allow trap to debugger
52 .long kgdb_handle_exception /* 1C0 */ ! Allow trap to debugger
53ENTRY(user_break_point_trap)
54 .long break_point_trap /* 1E0 */ 52 .long break_point_trap /* 1E0 */
55 53
56 /* 54 /*
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index 10f2a760c5ee..f9c7df64eb01 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -107,5 +107,7 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
107 boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED; 107 boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
108 boot_cpu_data.icache = boot_cpu_data.dcache; 108 boot_cpu_data.icache = boot_cpu_data.dcache;
109 109
110 boot_cpu_data.family = CPU_FAMILY_SH3;
111
110 return 0; 112 return 0;
111} 113}
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 6c78d0a9c857..d36f0c45f55f 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -57,8 +57,12 @@ int __init detect_cpu_and_cache_system(void)
57 * Setup some generic flags we can probe on SH-4A parts 57 * Setup some generic flags we can probe on SH-4A parts
58 */ 58 */
59 if (((pvr >> 16) & 0xff) == 0x10) { 59 if (((pvr >> 16) & 0xff) == 0x10) {
60 if ((cvr & 0x10000000) == 0) 60 boot_cpu_data.family = CPU_FAMILY_SH4A;
61
62 if ((cvr & 0x10000000) == 0) {
61 boot_cpu_data.flags |= CPU_HAS_DSP; 63 boot_cpu_data.flags |= CPU_HAS_DSP;
64 boot_cpu_data.family = CPU_FAMILY_SH4AL_DSP;
65 }
62 66
63 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER; 67 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER;
64 boot_cpu_data.cut_major = pvr & 0x7f; 68 boot_cpu_data.cut_major = pvr & 0x7f;
@@ -68,6 +72,7 @@ int __init detect_cpu_and_cache_system(void)
68 } else { 72 } else {
69 /* And some SH-4 defaults.. */ 73 /* And some SH-4 defaults.. */
70 boot_cpu_data.flags |= CPU_HAS_PTEA; 74 boot_cpu_data.flags |= CPU_HAS_PTEA;
75 boot_cpu_data.family = CPU_FAMILY_SH4;
71 } 76 }
72 77
73 /* FPU detection works for everyone */ 78 /* FPU detection works for everyone */
@@ -139,8 +144,15 @@ int __init detect_cpu_and_cache_system(void)
139 } 144 }
140 break; 145 break;
141 case 0x300b: 146 case 0x300b:
142 boot_cpu_data.type = CPU_SH7724; 147 switch (prr) {
143 boot_cpu_data.flags |= CPU_HAS_L2_CACHE; 148 case 0x20:
149 boot_cpu_data.type = CPU_SH7724;
150 boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
151 break;
152 case 0x50:
153 boot_cpu_data.type = CPU_SH7757;
154 break;
155 }
144 break; 156 break;
145 case 0x4000: /* 1st cut */ 157 case 0x4000: /* 1st cut */
146 case 0x4001: /* 2nd cut */ 158 case 0x4001: /* 2nd cut */
@@ -173,9 +185,6 @@ int __init detect_cpu_and_cache_system(void)
173 boot_cpu_data.dcache.ways = 2; 185 boot_cpu_data.dcache.ways = 2;
174 186
175 break; 187 break;
176 default:
177 boot_cpu_data.type = CPU_SH_NONE;
178 break;
179 } 188 }
180 189
181 /* 190 /*
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index ebdd391d5f42..490d5dc9e372 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -3,6 +3,7 @@
3# 3#
4 4
5# CPU subtype setup 5# CPU subtype setup
6obj-$(CONFIG_CPU_SUBTYPE_SH7757) += setup-sh7757.o
6obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o 7obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
7obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o 8obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
8obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
@@ -19,15 +20,16 @@ obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
19smp-$(CONFIG_CPU_SHX3) := smp-shx3.o 20smp-$(CONFIG_CPU_SHX3) := smp-shx3.o
20 21
21# Primary on-chip clocks (common) 22# Primary on-chip clocks (common)
23clock-$(CONFIG_CPU_SUBTYPE_SH7757) := clock-sh7757.o
22clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o 24clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o
23clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o 25clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
24clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o 26clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
25clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o 27clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
26clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
27clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o 29clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
28clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o hwblk-sh7722.o
29clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o hwblk-sh7723.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o 32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o hwblk-sh7724.o
31clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o 33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o
32clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
33 35
@@ -35,6 +37,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
35pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o 37pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
36pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o 38pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
37pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o 39pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o
40pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o
38pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 41pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
39pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o 42pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
40 43
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 40f859354f79..ea38b554dc05 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -22,6 +22,8 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <asm/clock.h> 24#include <asm/clock.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7722.h>
25 27
26/* SH7722 registers */ 28/* SH7722 registers */
27#define FRQCR 0xa4150000 29#define FRQCR 0xa4150000
@@ -30,9 +32,6 @@
30#define SCLKBCR 0xa415000c 32#define SCLKBCR 0xa415000c
31#define IRDACLKCR 0xa4150018 33#define IRDACLKCR 0xa4150018
32#define PLLCR 0xa4150024 34#define PLLCR 0xa4150024
33#define MSTPCR0 0xa4150030
34#define MSTPCR1 0xa4150034
35#define MSTPCR2 0xa4150038
36#define DLLFRQ 0xa4150050 35#define DLLFRQ 0xa4150050
37 36
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 37/* Fixed 32 KHz root clock for RTC and Power Management purposes */
@@ -140,35 +139,37 @@ struct clk div6_clks[] = {
140 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 139 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
141}; 140};
142 141
143#define MSTP(_str, _parent, _reg, _bit, _flags) \ 142#define R_CLK &r_clk
144 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 143#define P_CLK &div4_clks[DIV4_P]
144#define B_CLK &div4_clks[DIV4_B]
145#define U_CLK &div4_clks[DIV4_U]
145 146
146static struct clk mstp_clks[] = { 147static struct clk mstp_clks[] = {
147 MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 148 SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT),
148 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 149 SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT),
149 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 150 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU, 0),
150 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), 151 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
151 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 152 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
152 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 153 SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
153 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), 154 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
154 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), 155 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
155 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), 156 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
156 157
157 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 158 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
158 MSTP("rtc0", &r_clk, MSTPCR1, 8, 0), 159 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
159 160
160 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 161 SH_HWBLK_CLK("sdhi0", -1, P_CLK, HWBLK_SDHI, 0),
161 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0), 162 SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
162 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 163 SH_HWBLK_CLK("usbf0", -1, P_CLK, HWBLK_USBF, 0),
163 MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 9, 0), 164 SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
164 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0), 165 SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
165 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 166 SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
166 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), 167 SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0),
167 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 168 SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
168 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 169 SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
169 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 170 SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU, 0),
170 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 171 SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
171 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), 172 SH_HWBLK_CLK("lcdc0", -1, P_CLK, HWBLK_LCDC, 0),
172}; 173};
173 174
174int __init arch_clk_init(void) 175int __init arch_clk_init(void)
@@ -191,7 +192,7 @@ int __init arch_clk_init(void)
191 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 192 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
192 193
193 if (!ret) 194 if (!ret)
194 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 195 ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks));
195 196
196 return ret; 197 return ret;
197} 198}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index e67c2678b8ae..20a31c2255a8 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -22,6 +22,8 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <asm/clock.h> 24#include <asm/clock.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7723.h>
25 27
26/* SH7723 registers */ 28/* SH7723 registers */
27#define FRQCR 0xa4150000 29#define FRQCR 0xa4150000
@@ -30,9 +32,6 @@
30#define SCLKBCR 0xa415000c 32#define SCLKBCR 0xa415000c
31#define IRDACLKCR 0xa4150018 33#define IRDACLKCR 0xa4150018
32#define PLLCR 0xa4150024 34#define PLLCR 0xa4150024
33#define MSTPCR0 0xa4150030
34#define MSTPCR1 0xa4150034
35#define MSTPCR2 0xa4150038
36#define DLLFRQ 0xa4150050 35#define DLLFRQ 0xa4150050
37 36
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 37/* Fixed 32 KHz root clock for RTC and Power Management purposes */
@@ -140,60 +139,64 @@ struct clk div6_clks[] = {
140 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 139 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
141}; 140};
142 141
143#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \ 142#define R_CLK (&r_clk)
144 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT) 143#define P_CLK (&div4_clks[DIV4_P])
144#define B_CLK (&div4_clks[DIV4_B])
145#define U_CLK (&div4_clks[DIV4_U])
146#define I_CLK (&div4_clks[DIV4_I])
147#define SH_CLK (&div4_clks[DIV4_SH])
145 148
146static struct clk mstp_clks[] = { 149static struct clk mstp_clks[] = {
147 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ 150 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
148 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0), 151 SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT),
149 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0), 152 SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT),
150 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0), 153 SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT),
151 MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 28, 1, 1, 0), 154 SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT),
152 MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0), 155 SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT),
153 MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0), 156 SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT),
154 MSTP("intc0", &div4_clks[DIV4_I], MSTPCR0, 22, 1, 1, 0), 157 SH_HWBLK_CLK("intc0", -1, I_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT),
155 MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1), 158 SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0),
156 MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0), 159 SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
157 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0), 160 SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
158 MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0), 161 SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
159 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0), 162 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0),
160 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0), 163 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
161 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0), 164 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
162 MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1), 165 SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
163 MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 11, 0, 1, 0), 166 SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0),
164 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0), 167 SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
165 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0), 168 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
166 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0), 169 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
167 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0), 170 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
168 MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0), 171 SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0),
169 MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0), 172 SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0),
170 MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0), 173 SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0),
171 MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0), 174 SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
172 MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0), 175 SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
173 MSTP("meram0", &div4_clks[DIV4_SH], MSTPCR0, 0, 1, 1, 0), 176 SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0),
174 177
175 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0), 178 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
176 MSTP("rtc0", &r_clk, MSTPCR1, 8, 0, 0, 0), 179 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
177 180
178 MSTP("atapi0", &div4_clks[DIV4_SH], MSTPCR2, 28, 0, 1, 0), 181 SH_HWBLK_CLK("atapi0", -1, SH_CLK, HWBLK_ATAPI, 0),
179 MSTP("adc0", &div4_clks[DIV4_P], MSTPCR2, 27, 0, 1, 0), 182 SH_HWBLK_CLK("adc0", -1, P_CLK, HWBLK_ADC, 0),
180 MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0), 183 SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0),
181 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0), 184 SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0),
182 MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0), 185 SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0),
183 MSTP("icb0", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1), 186 SH_HWBLK_CLK("icb0", -1, B_CLK, HWBLK_ICB, CLK_ENABLE_ON_INIT),
184 MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0), 187 SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0),
185 MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0), 188 SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0),
186 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0, 0, 0), 189 SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
187 MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 11, 0, 1, 0), 190 SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB, 0),
188 MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 10, 0, 1, 1), 191 SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
189 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0, 1, 0), 192 SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
190 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1), 193 SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU2H1, 0),
191 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1), 194 SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
192 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1), 195 SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
193 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1), 196 SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
194 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1), 197 SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU2H0, 0),
195 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1), 198 SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
196 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1), 199 SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
197}; 200};
198 201
199int __init arch_clk_init(void) 202int __init arch_clk_init(void)
@@ -216,7 +219,7 @@ int __init arch_clk_init(void)
216 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 219 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
217 220
218 if (!ret) 221 if (!ret)
219 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 222 ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks));
220 223
221 return ret; 224 return ret;
222} 225}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 5d5c9b952883..dfe9192be63e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -22,6 +22,8 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <asm/clock.h> 24#include <asm/clock.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7724.h>
25 27
26/* SH7724 registers */ 28/* SH7724 registers */
27#define FRQCRA 0xa4150000 29#define FRQCRA 0xa4150000
@@ -31,9 +33,6 @@
31#define FCLKBCR 0xa415000c 33#define FCLKBCR 0xa415000c
32#define IRDACLKCR 0xa4150018 34#define IRDACLKCR 0xa4150018
33#define PLLCR 0xa4150024 35#define PLLCR 0xa4150024
34#define MSTPCR0 0xa4150030
35#define MSTPCR1 0xa4150034
36#define MSTPCR2 0xa4150038
37#define SPUCLKCR 0xa415003c 36#define SPUCLKCR 0xa415003c
38#define FLLFRQ 0xa4150050 37#define FLLFRQ 0xa4150050
39#define LSTATS 0xa4150060 38#define LSTATS 0xa4150060
@@ -128,7 +127,7 @@ struct clk *main_clks[] = {
128 &div3_clk, 127 &div3_clk,
129}; 128};
130 129
131static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; 130static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
132 131
133static struct clk_div_mult_table div4_table = { 132static struct clk_div_mult_table div4_table = {
134 .divisors = divisors, 133 .divisors = divisors,
@@ -156,64 +155,67 @@ struct clk div6_clks[] = {
156 SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0), 155 SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0),
157}; 156};
158 157
159#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \ 158#define R_CLK (&r_clk)
160 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT) 159#define P_CLK (&div4_clks[DIV4_P])
160#define B_CLK (&div4_clks[DIV4_B])
161#define I_CLK (&div4_clks[DIV4_I])
162#define SH_CLK (&div4_clks[DIV4_SH])
161 163
162static struct clk mstp_clks[] = { 164static struct clk mstp_clks[] = {
163 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0), 165 SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT),
164 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0), 166 SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT),
165 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0), 167 SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT),
166 MSTP("rs0", &div4_clks[DIV4_B], MSTPCR0, 28, 1, 1, 0), 168 SH_HWBLK_CLK("rs0", -1, B_CLK, HWBLK_RSMEM, CLK_ENABLE_ON_INIT),
167 MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0), 169 SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT),
168 MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 26, 1, 1, 0), 170 SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT),
169 MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0), 171 SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT),
170 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 1, 1, 0), 172 SH_HWBLK_CLK("intc0", -1, P_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT),
171 MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1), 173 SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0),
172 MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0), 174 SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
173 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0), 175 SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
174 MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0), 176 SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
175 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0), 177 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0),
176 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0), 178 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
177 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0), 179 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
178 MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1), 180 SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
179 MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0), 181 SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0),
180 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0), 182 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
181 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0), 183 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
182 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0), 184 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
183 MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0), 185 SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0),
184 MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0), 186 SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0),
185 MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0), 187 SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0),
186 MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0), 188 SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
187 MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0), 189 SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
188 190
189 MSTP("keysc0", &r_clk, MSTPCR1, 12, 0, 0, 0), 191 SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
190 MSTP("rtc0", &r_clk, MSTPCR1, 11, 0, 0, 0), 192 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
191 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0), 193 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC0, 0),
192 MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0, 1, 0), 194 SH_HWBLK_CLK("i2c1", -1, P_CLK, HWBLK_IIC1, 0),
193 195
194 MSTP("mmc0", &div4_clks[DIV4_B], MSTPCR2, 29, 0, 1, 0), 196 SH_HWBLK_CLK("mmc0", -1, B_CLK, HWBLK_MMC, 0),
195 MSTP("eth0", &div4_clks[DIV4_B], MSTPCR2, 28, 0, 1, 0), 197 SH_HWBLK_CLK("eth0", -1, B_CLK, HWBLK_ETHER, 0),
196 MSTP("atapi0", &div4_clks[DIV4_B], MSTPCR2, 26, 0, 1, 0), 198 SH_HWBLK_CLK("atapi0", -1, B_CLK, HWBLK_ATAPI, 0),
197 MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0), 199 SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0),
198 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0), 200 SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0),
199 MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0), 201 SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0),
200 MSTP("usb1", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1), 202 SH_HWBLK_CLK("usb1", -1, B_CLK, HWBLK_USB1, 0),
201 MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 20, 0, 1, 1), 203 SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB0, 0),
202 MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 19, 0, 1, 1), 204 SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
203 MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0), 205 SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0),
204 MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0), 206 SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0),
205 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 15, 1, 1, 1), 207 SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU1, 0),
206 MSTP("ceu1", &div4_clks[DIV4_B], MSTPCR2, 13, 0, 1, 1), 208 SH_HWBLK_CLK("ceu1", -1, B_CLK, HWBLK_CEU1, 0),
207 MSTP("beu1", &div4_clks[DIV4_B], MSTPCR2, 12, 0, 1, 1), 209 SH_HWBLK_CLK("beu1", -1, B_CLK, HWBLK_BEU1, 0),
208 MSTP("2ddmac0", &div4_clks[DIV4_SH], MSTPCR2, 10, 0, 1, 1), 210 SH_HWBLK_CLK("2ddmac0", -1, SH_CLK, HWBLK_2DDMAC, 0),
209 MSTP("spu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0, 1, 0), 211 SH_HWBLK_CLK("spu0", -1, B_CLK, HWBLK_SPU, 0),
210 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1), 212 SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0),
211 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1), 213 SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
212 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1), 214 SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU0, 0),
213 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1), 215 SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU0, 0),
214 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1), 216 SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU0, 0),
215 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1), 217 SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
216 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1), 218 SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
217}; 219};
218 220
219int __init arch_clk_init(void) 221int __init arch_clk_init(void)
@@ -236,7 +238,7 @@ int __init arch_clk_init(void)
236 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 238 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
237 239
238 if (!ret) 240 if (!ret)
239 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 241 ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks));
240 242
241 return ret; 243 return ret;
242} 244}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
new file mode 100644
index 000000000000..ddc235ca9664
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -0,0 +1,130 @@
1/*
2 * arch/sh/kernel/cpu/sh4/clock-sh7757.c
3 *
4 * SH7757 support for the clock framework
5 *
6 * Copyright (C) 2009 Renesas Solutions Corp.
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <asm/clock.h>
16#include <asm/freq.h>
17
18static int ifc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
19 16, 1, 1, 32, 1, 1, 1, 1 };
20static int sfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
21 16, 1, 1, 32, 1, 1, 1, 1 };
22static int bfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
23 16, 1, 1, 32, 1, 1, 1, 1 };
24static int p1fc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
25 16, 1, 1, 32, 1, 1, 1, 1 };
26
27static void master_clk_init(struct clk *clk)
28{
29 clk->rate = CONFIG_SH_PCLK_FREQ * 16;
30}
31
32static struct clk_ops sh7757_master_clk_ops = {
33 .init = master_clk_init,
34};
35
36static void module_clk_recalc(struct clk *clk)
37{
38 int idx = ctrl_inl(FRQCR) & 0x0000000f;
39 clk->rate = clk->parent->rate / p1fc_divisors[idx];
40}
41
42static struct clk_ops sh7757_module_clk_ops = {
43 .recalc = module_clk_recalc,
44};
45
46static void bus_clk_recalc(struct clk *clk)
47{
48 int idx = (ctrl_inl(FRQCR) >> 8) & 0x0000000f;
49 clk->rate = clk->parent->rate / bfc_divisors[idx];
50}
51
52static struct clk_ops sh7757_bus_clk_ops = {
53 .recalc = bus_clk_recalc,
54};
55
56static void cpu_clk_recalc(struct clk *clk)
57{
58 int idx = (ctrl_inl(FRQCR) >> 20) & 0x0000000f;
59 clk->rate = clk->parent->rate / ifc_divisors[idx];
60}
61
62static struct clk_ops sh7757_cpu_clk_ops = {
63 .recalc = cpu_clk_recalc,
64};
65
66static struct clk_ops *sh7757_clk_ops[] = {
67 &sh7757_master_clk_ops,
68 &sh7757_module_clk_ops,
69 &sh7757_bus_clk_ops,
70 &sh7757_cpu_clk_ops,
71};
72
73void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
74{
75 if (idx < ARRAY_SIZE(sh7757_clk_ops))
76 *ops = sh7757_clk_ops[idx];
77}
78
79static void shyway_clk_recalc(struct clk *clk)
80{
81 int idx = (ctrl_inl(FRQCR) >> 12) & 0x0000000f;
82 clk->rate = clk->parent->rate / sfc_divisors[idx];
83}
84
85static struct clk_ops sh7757_shyway_clk_ops = {
86 .recalc = shyway_clk_recalc,
87};
88
89static struct clk sh7757_shyway_clk = {
90 .name = "shyway_clk",
91 .flags = CLK_ENABLE_ON_INIT,
92 .ops = &sh7757_shyway_clk_ops,
93};
94
95/*
96 * Additional sh7757-specific on-chip clocks that aren't already part of the
97 * clock framework
98 */
99static struct clk *sh7757_onchip_clocks[] = {
100 &sh7757_shyway_clk,
101};
102
103static int __init sh7757_clk_init(void)
104{
105 struct clk *clk = clk_get(NULL, "master_clk");
106 int i;
107
108 for (i = 0; i < ARRAY_SIZE(sh7757_onchip_clocks); i++) {
109 struct clk *clkp = sh7757_onchip_clocks[i];
110
111 clkp->parent = clk;
112 clk_register(clkp);
113 clk_enable(clkp);
114 }
115
116 /*
117 * Now that we have the rest of the clocks registered, we need to
118 * force the parent clock to propagate so that these clocks will
119 * automatically figure out their rate. We cheat by handing the
120 * parent clock its current rate and forcing child propagation.
121 */
122 clk_set_rate(clk, clk_get_rate(clk));
123
124 clk_put(clk);
125
126 return 0;
127}
128
129arch_initcall(sh7757_clk_init);
130
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
new file mode 100644
index 000000000000..a288b5d92341
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
@@ -0,0 +1,106 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
3 *
4 * SH7722 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7722.h>
27
28/* SH7722 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7722 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7722_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7722_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_URAM] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_XYMEM] = HWBLK(MSTPCR0, 26, CORE_AREA),
48 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
49 [HWBLK_DMAC] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
50 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
51 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
52 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
53 [HWBLK_TMU] = HWBLK(MSTPCR0, 15, CORE_AREA),
54 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
55 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
56 [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
57 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 7, CORE_AREA),
58 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 6, CORE_AREA),
59 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 5, CORE_AREA),
60 [HWBLK_SIO] = HWBLK(MSTPCR0, 3, CORE_AREA),
61 [HWBLK_SIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
62 [HWBLK_SIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
63
64 [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
65 [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
66
67 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
68 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
69 [HWBLK_SDHI] = HWBLK(MSTPCR2, 18, CORE_AREA),
70 [HWBLK_SIM] = HWBLK(MSTPCR2, 16, CORE_AREA),
71 [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
72 [HWBLK_TSIF] = HWBLK(MSTPCR2, 13, SUB_AREA),
73 [HWBLK_USBF] = HWBLK(MSTPCR2, 11, CORE_AREA),
74 [HWBLK_2DG] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
75 [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
76 [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
77 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
78 [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
79 [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
80 [HWBLK_VEU] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
81 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
82 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
83};
84
85static struct hwblk_info sh7722_hwblk_info = {
86 .areas = sh7722_hwblk_area,
87 .nr_areas = ARRAY_SIZE(sh7722_hwblk_area),
88 .hwblks = sh7722_hwblk,
89 .nr_hwblks = ARRAY_SIZE(sh7722_hwblk),
90};
91
92int arch_hwblk_sleep_mode(void)
93{
94 if (!sh7722_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
95 return SUSP_SH_STANDBY | SUSP_SH_SF;
96
97 if (!sh7722_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
98 return SUSP_SH_SLEEP | SUSP_SH_SF;
99
100 return SUSP_SH_SLEEP;
101}
102
103int __init arch_hwblk_init(void)
104{
105 return hwblk_register(&sh7722_hwblk_info);
106}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
new file mode 100644
index 000000000000..a7f4684d2032
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
@@ -0,0 +1,117 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
3 *
4 * SH7723 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7723.h>
27
28/* SH7723 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7723 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7723_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7723_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_L2C] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
49 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
50 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
51 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
52 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
53 [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
54 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
55 [HWBLK_SUBC] = HWBLK(MSTPCR0, 16, CORE_AREA),
56 [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59 [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60 [HWBLK_TMU1] = HWBLK(MSTPCR0, 11, CORE_AREA),
61 [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
62 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
63 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
64 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
65 [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
66 [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
67 [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
68 [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
69 [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
70 [HWBLK_MERAM] = HWBLK(MSTPCR0, 0, CORE_AREA),
71
72 [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
74
75 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
76 [HWBLK_ADC] = HWBLK(MSTPCR2, 27, CORE_AREA),
77 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
78 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
79 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
80 [HWBLK_ICB] = HWBLK(MSTPCR2, 21, CORE_AREA_BM),
81 [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
82 [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
83 [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
84 [HWBLK_USB] = HWBLK(MSTPCR2, 11, CORE_AREA),
85 [HWBLK_2DG] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
86 [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
87 [HWBLK_VEU2H1] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
88 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
89 [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
90 [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
91 [HWBLK_VEU2H0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
92 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
93 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
94};
95
96static struct hwblk_info sh7723_hwblk_info = {
97 .areas = sh7723_hwblk_area,
98 .nr_areas = ARRAY_SIZE(sh7723_hwblk_area),
99 .hwblks = sh7723_hwblk,
100 .nr_hwblks = ARRAY_SIZE(sh7723_hwblk),
101};
102
103int arch_hwblk_sleep_mode(void)
104{
105 if (!sh7723_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
106 return SUSP_SH_STANDBY | SUSP_SH_SF;
107
108 if (!sh7723_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
109 return SUSP_SH_SLEEP | SUSP_SH_SF;
110
111 return SUSP_SH_SLEEP;
112}
113
114int __init arch_hwblk_init(void)
115{
116 return hwblk_register(&sh7723_hwblk_info);
117}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
new file mode 100644
index 000000000000..1613ad6013c3
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
@@ -0,0 +1,121 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
3 *
4 * SH7724 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7724.h>
27
28/* SH7724 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7724 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7724_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7724_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_RSMEM] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48 [HWBLK_L2C] = HWBLK(MSTPCR0, 26, CORE_AREA),
49 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
50 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
51 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
52 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
53 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
54 [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
55 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
56 [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59 [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60 [HWBLK_TMU1] = HWBLK(MSTPCR0, 10, CORE_AREA),
61 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
62 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
63 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
64 [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
65 [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
66 [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
67 [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
68 [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
69
70 [HWBLK_KEYSC] = HWBLK(MSTPCR1, 12, SUB_AREA),
71 [HWBLK_RTC] = HWBLK(MSTPCR1, 11, SUB_AREA),
72 [HWBLK_IIC0] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_IIC1] = HWBLK(MSTPCR1, 8, CORE_AREA),
74
75 [HWBLK_MMC] = HWBLK(MSTPCR2, 29, CORE_AREA),
76 [HWBLK_ETHER] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
77 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 26, CORE_AREA_BM),
78 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
79 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
80 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
81 [HWBLK_USB1] = HWBLK(MSTPCR2, 21, CORE_AREA),
82 [HWBLK_USB0] = HWBLK(MSTPCR2, 20, CORE_AREA),
83 [HWBLK_2DG] = HWBLK(MSTPCR2, 19, CORE_AREA_BM),
84 [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
85 [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
86 [HWBLK_VEU1] = HWBLK(MSTPCR2, 15, CORE_AREA_BM),
87 [HWBLK_CEU1] = HWBLK(MSTPCR2, 13, CORE_AREA_BM),
88 [HWBLK_BEU1] = HWBLK(MSTPCR2, 12, CORE_AREA_BM),
89 [HWBLK_2DDMAC] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
90 [HWBLK_SPU] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
91 [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
92 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
93 [HWBLK_BEU0] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
94 [HWBLK_CEU0] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
95 [HWBLK_VEU0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
96 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
97 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
98};
99
100static struct hwblk_info sh7724_hwblk_info = {
101 .areas = sh7724_hwblk_area,
102 .nr_areas = ARRAY_SIZE(sh7724_hwblk_area),
103 .hwblks = sh7724_hwblk,
104 .nr_hwblks = ARRAY_SIZE(sh7724_hwblk),
105};
106
107int arch_hwblk_sleep_mode(void)
108{
109 if (!sh7724_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
110 return SUSP_SH_STANDBY | SUSP_SH_SF;
111
112 if (!sh7724_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
113 return SUSP_SH_SLEEP | SUSP_SH_SF;
114
115 return SUSP_SH_SLEEP;
116}
117
118int __init arch_hwblk_init(void)
119{
120 return hwblk_register(&sh7724_hwblk_info);
121}
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
new file mode 100644
index 000000000000..ed23b155c097
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
@@ -0,0 +1,2019 @@
1/*
2 * SH7757 (A0 step) Pinmux
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 *
8 * Based on SH7757 Pinmux
9 * Copyright (C) 2008 Magnus Damm
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <cpu/sh7757.h>
20
21enum {
22 PINMUX_RESERVED = 0,
23
24 PINMUX_DATA_BEGIN,
25 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
26 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
27 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
28 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
29 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
30 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
31 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
32 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
33 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
34 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
35 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
36 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
37 PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
38 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
39 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
40 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
41 PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
42 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA,
43 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
44 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
45 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
46 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
47 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
48 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
49 PTM6_DATA, PTM5_DATA, PTM4_DATA,
50 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
51 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
52 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
53 PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
54 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA,
55 PTP6_DATA, PTP5_DATA, PTP4_DATA,
56 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA,
57 PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
58 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
59 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
60 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
61 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
62 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
63 PTT5_DATA, PTT4_DATA,
64 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
65 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
66 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
67 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
68 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
69 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
70 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
71 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
72 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
73 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
74 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
75 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
76 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
77 PINMUX_DATA_END,
78
79 PINMUX_INPUT_BEGIN,
80 PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
81 PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
82 PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
83 PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
84 PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
85 PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
86 PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
87 PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
88 PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN,
89 PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
90 PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
91 PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
92 PTG7_IN, PTG6_IN, PTG5_IN, PTG4_IN,
93 PTG3_IN, PTG2_IN, PTG1_IN, PTG0_IN,
94 PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
95 PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
96 PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN,
97 PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN,
98 PTJ7_IN, PTJ6_IN, PTJ5_IN, PTJ4_IN,
99 PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
100 PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
101 PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
102 PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
103 PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
104 PTM6_IN, PTM5_IN, PTM4_IN,
105 PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
106 PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
107 PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
108 PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN,
109 PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN,
110 PTP6_IN, PTP5_IN, PTP4_IN,
111 PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN,
112 PTQ6_IN, PTQ5_IN, PTQ4_IN,
113 PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
114 PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
115 PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
116 PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN,
117 PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
118 PTT5_IN, PTT4_IN,
119 PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
120 PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
121 PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
122 PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
123 PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
124 PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
125 PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
126 PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
127 PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
128 PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
129 PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
130 PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
131 PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
132 PINMUX_INPUT_END,
133
134 PINMUX_INPUT_PULLUP_BEGIN,
135 PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
136 PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
137 PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
138 PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU,
139 PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU,
140 PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU,
141 PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
142 PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
143 PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
144 PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
145 PINMUX_INPUT_PULLUP_END,
146
147 PINMUX_OUTPUT_BEGIN,
148 PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
149 PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
150 PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
151 PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
152 PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
153 PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
154 PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
155 PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
156 PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT,
157 PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
158 PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
159 PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
160 PTG7_OUT, PTG6_OUT, PTG5_OUT, PTG4_OUT,
161 PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
162 PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
163 PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
164 PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT,
165 PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT,
166 PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ4_OUT,
167 PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
168 PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
169 PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
170 PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
171 PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
172 PTM6_OUT, PTM5_OUT, PTM4_OUT,
173 PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
174 PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
175 PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
176 PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT,
177 PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT,
178 PTP6_OUT, PTP5_OUT, PTP4_OUT,
179 PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT,
180 PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
181 PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
182 PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
183 PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT,
184 PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT,
185 PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
186 PTT5_OUT, PTT4_OUT,
187 PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
188 PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
189 PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
190 PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
191 PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
192 PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
193 PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
194 PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
195 PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
196 PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
197 PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
198 PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
199 PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
200 PINMUX_OUTPUT_END,
201
202 PINMUX_FUNCTION_BEGIN,
203 PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
204 PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
205 PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
206 PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
207 PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
208 PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
209 PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
210 PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
211 PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN,
212 PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
213 PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
214 PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
215 PTG7_FN, PTG6_FN, PTG5_FN, PTG4_FN,
216 PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
217 PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
218 PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
219 PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN,
220 PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN,
221 PTJ7_FN, PTJ6_FN, PTJ5_FN, PTJ4_FN,
222 PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
223 PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
224 PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
225 PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN,
226 PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
227 PTM6_FN, PTM5_FN, PTM4_FN,
228 PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
229 PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN,
230 PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
231 PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN,
232 PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN,
233 PTP6_FN, PTP5_FN, PTP4_FN,
234 PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN,
235 PTQ6_FN, PTQ5_FN, PTQ4_FN,
236 PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
237 PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
238 PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
239 PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN,
240 PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
241 PTT5_FN, PTT4_FN,
242 PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
243 PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
244 PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
245 PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
246 PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
247 PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
248 PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
249 PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
250 PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
251 PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
252 PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
253 PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
254 PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
255
256 PS0_15_FN1, PS0_15_FN3,
257 PS0_14_FN1, PS0_14_FN3,
258 PS0_13_FN1, PS0_13_FN3,
259 PS0_12_FN1, PS0_12_FN3,
260 PS0_7_FN1, PS0_7_FN2,
261 PS0_6_FN1, PS0_6_FN2,
262 PS0_5_FN1, PS0_5_FN2,
263 PS0_4_FN1, PS0_4_FN2,
264 PS0_3_FN1, PS0_3_FN2,
265 PS0_2_FN1, PS0_2_FN2,
266 PS0_1_FN1, PS0_1_FN2,
267
268 PS1_7_FN1, PS1_7_FN3,
269 PS1_6_FN1, PS1_6_FN3,
270
271 PS2_13_FN1, PS2_13_FN3,
272 PS2_12_FN1, PS2_12_FN3,
273 PS2_1_FN1, PS2_1_FN2,
274 PS2_0_FN1, PS2_0_FN2,
275
276 PS4_15_FN1, PS4_15_FN2,
277 PS4_14_FN1, PS4_14_FN2,
278 PS4_13_FN1, PS4_13_FN2,
279 PS4_12_FN1, PS4_12_FN2,
280 PS4_11_FN1, PS4_11_FN2,
281 PS4_10_FN1, PS4_10_FN2,
282 PS4_9_FN1, PS4_9_FN2,
283 PS4_3_FN1, PS4_3_FN2,
284 PS4_2_FN1, PS4_2_FN2,
285 PS4_1_FN1, PS4_1_FN2,
286 PS4_0_FN1, PS4_0_FN2,
287
288 PS5_9_FN1, PS5_9_FN2,
289 PS5_8_FN1, PS5_8_FN2,
290 PS5_7_FN1, PS5_7_FN2,
291 PS5_6_FN1, PS5_6_FN2,
292 PS5_5_FN1, PS5_5_FN2,
293 PS5_4_FN1, PS5_4_FN2,
294
295 /* AN15 to 8 : EVENT15 to 8 */
296 PS6_7_FN_AN, PS6_7_FN_EV,
297 PS6_6_FN_AN, PS6_6_FN_EV,
298 PS6_5_FN_AN, PS6_5_FN_EV,
299 PS6_4_FN_AN, PS6_4_FN_EV,
300 PS6_3_FN_AN, PS6_3_FN_EV,
301 PS6_2_FN_AN, PS6_2_FN_EV,
302 PS6_1_FN_AN, PS6_1_FN_EV,
303 PS6_0_FN_AN, PS6_0_FN_EV,
304
305 PINMUX_FUNCTION_END,
306
307 PINMUX_MARK_BEGIN,
308 /* PTA (mobule: LBSC, CPG, LPC) */
309 BS_MARK, RDWR_MARK, WE1_MARK, RDY_MARK,
310 MD10_MARK, MD9_MARK, MD8_MARK,
311 LGPIO7_MARK, LGPIO6_MARK, LGPIO5_MARK, LGPIO4_MARK,
312 LGPIO3_MARK, LGPIO2_MARK, LGPIO1_MARK, LGPIO0_MARK,
313
314 /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
315 D15_MARK, D14_MARK, D13_MARK, D12_MARK,
316 D11_MARK, D10_MARK, D9_MARK, D8_MARK,
317 ET0_MDC_MARK, ET0_MDIO_MARK, ET1_MDC_MARK, ET1_MDIO_MARK,
318 SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK,
319 WPSZ1_MARK, WPSZ0_MARK, FWID_MARK, FLSHSZ_MARK,
320 LPC_SPIEN_MARK, BASEL_MARK,
321
322 /* PTC (mobule: SD) */
323 SD_WP_MARK, SD_CD_MARK, SD_CLK_MARK, SD_CMD_MARK,
324 SD_D3_MARK, SD_D2_MARK, SD_D1_MARK, SD_D0_MARK,
325
326 /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
327 IRQ7_MARK, IRQ6_MARK, IRQ5_MARK, IRQ4_MARK,
328 IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
329 MD6_MARK, MD5_MARK, MD3_MARK, MD2_MARK,
330 MD1_MARK, MD0_MARK, ADTRG1_MARK, ADTRG0_MARK,
331
332 /* PTE (mobule: EtherC) */
333 ET0_CRS_DV_MARK, ET0_TXD1_MARK,
334 ET0_TXD0_MARK, ET0_TX_EN_MARK,
335 ET0_REF_CLK_MARK, ET0_RXD1_MARK,
336 ET0_RXD0_MARK, ET0_RX_ER_MARK,
337
338 /* PTF (mobule: EtherC) */
339 ET1_CRS_DV_MARK, ET1_TXD1_MARK,
340 ET1_TXD0_MARK, ET1_TX_EN_MARK,
341 ET1_REF_CLK_MARK, ET1_RXD1_MARK,
342 ET1_RXD0_MARK, ET1_RX_ER_MARK,
343
344 /* PTG (mobule: SYSTEM, PWMX, LPC) */
345 STATUS0_MARK, STATUS1_MARK,
346 PWX0_MARK, PWX1_MARK, PWX2_MARK, PWX3_MARK,
347 SERIRQ_MARK, CLKRUN_MARK, LPCPD_MARK, LDRQ_MARK,
348
349 /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
350 TCLK_MARK, RXD4_MARK, TXD4_MARK,
351 SP1_MOSI_MARK, SP1_MISO_MARK, SP1_SCK_MARK, SP1_SCK_FB_MARK,
352 SP1_SS0_MARK, SP1_SS1_MARK, SP0_SS1_MARK,
353
354 /* PTI (mobule: INTC) */
355 IRQ15_MARK, IRQ14_MARK, IRQ13_MARK, IRQ12_MARK,
356 IRQ11_MARK, IRQ10_MARK, IRQ9_MARK, IRQ8_MARK,
357
358 /* PTJ (mobule: SCIF234, SERMUX) */
359 RXD3_MARK, TXD3_MARK, RXD2_MARK, TXD2_MARK,
360 COM1_TXD_MARK, COM1_RXD_MARK, COM1_RTS_MARK, COM1_CTS_MARK,
361
362 /* PTK (mobule: SERMUX) */
363 COM2_TXD_MARK, COM2_RXD_MARK, COM2_RTS_MARK, COM2_CTS_MARK,
364 COM2_DTR_MARK, COM2_DSR_MARK, COM2_DCD_MARK, COM2_RI_MARK,
365
366 /* PTL (mobule: SERMUX) */
367 RAC_TXD_MARK, RAC_RXD_MARK, RAC_RTS_MARK, RAC_CTS_MARK,
368 RAC_DTR_MARK, RAC_DSR_MARK, RAC_DCD_MARK, RAC_RI_MARK,
369
370 /* PTM (mobule: IIC, LPC) */
371 SDA6_MARK, SCL6_MARK, SDA7_MARK, SCL7_MARK,
372 WP_MARK, FMS0_MARK, FMS1_MARK,
373
374 /* PTN (mobule: SCIF234, EVC) */
375 SCK2_MARK, RTS4_MARK, RTS3_MARK, RTS2_MARK,
376 CTS4_MARK, CTS3_MARK, CTS2_MARK,
377 EVENT7_MARK, EVENT6_MARK, EVENT5_MARK, EVENT4_MARK,
378 EVENT3_MARK, EVENT2_MARK, EVENT1_MARK, EVENT0_MARK,
379
380 /* PTO (mobule: SGPIO) */
381 SGPIO0_CLK_MARK, SGPIO0_LOAD_MARK,
382 SGPIO0_DI_MARK, SGPIO0_DO_MARK,
383 SGPIO1_CLK_MARK, SGPIO1_LOAD_MARK,
384 SGPIO1_DI_MARK, SGPIO1_DO_MARK,
385
386 /* PTP (mobule: JMC, SCIF234) */
387 JMCTCK_MARK, JMCTMS_MARK, JMCTDO_MARK, JMCTDI_MARK,
388 JMCRST_MARK, SCK4_MARK, SCK3_MARK,
389
390 /* PTQ (mobule: LPC) */
391 LAD3_MARK, LAD2_MARK, LAD1_MARK, LAD0_MARK,
392 LFRAME_MARK, LRESET_MARK, LCLK_MARK,
393
394 /* PTR (mobule: GRA, IIC) */
395 DDC3_MARK, DDC2_MARK,
396 SDA8_MARK, SCL8_MARK, SDA2_MARK, SCL2_MARK,
397 SDA1_MARK, SCL1_MARK, SDA0_MARK, SCL0_MARK,
398
399 /* PTS (mobule: GRA, IIC) */
400 DDC1_MARK, DDC0_MARK,
401 SDA9_MARK, SCL9_MARK, SDA5_MARK, SCL5_MARK,
402 SDA4_MARK, SCL4_MARK, SDA3_MARK, SCL3_MARK,
403
404 /* PTT (mobule: SYSTEM, PWMX) */
405 AUDSYNC_MARK, AUDCK_MARK,
406 AUDATA3_MARK, AUDATA2_MARK,
407 AUDATA1_MARK, AUDATA0_MARK,
408 PWX7_MARK, PWX6_MARK, PWX5_MARK, PWX4_MARK,
409
410 /* PTU (mobule: LBSC, DMAC) */
411 CS6_MARK, CS5_MARK, CS4_MARK, CS0_MARK,
412 RD_MARK, WE0_MARK, A25_MARK, A24_MARK,
413 DREQ0_MARK, DACK0_MARK,
414
415 /* PTV (mobule: LBSC, DMAC) */
416 A23_MARK, A22_MARK, A21_MARK, A20_MARK,
417 A19_MARK, A18_MARK, A17_MARK, A16_MARK,
418 TEND0_MARK, DREQ1_MARK, DACK1_MARK, TEND1_MARK,
419
420 /* PTW (mobule: LBSC) */
421 A15_MARK, A14_MARK, A13_MARK, A12_MARK,
422 A11_MARK, A10_MARK, A9_MARK, A8_MARK,
423
424 /* PTX (mobule: LBSC) */
425 A7_MARK, A6_MARK, A5_MARK, A4_MARK,
426 A3_MARK, A2_MARK, A1_MARK, A0_MARK,
427
428 /* PTY (mobule: LBSC) */
429 D7_MARK, D6_MARK, D5_MARK, D4_MARK,
430 D3_MARK, D2_MARK, D1_MARK, D0_MARK,
431 PINMUX_MARK_END,
432};
433
434static pinmux_enum_t pinmux_data[] = {
435 /* PTA GPIO */
436 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
437 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
438 PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
439 PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT),
440 PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT),
441 PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT),
442 PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT),
443 PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT),
444
445 /* PTB GPIO */
446 PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
447 PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
448 PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
449 PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
450 PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
451 PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
452 PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
453 PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
454
455 /* PTC GPIO */
456 PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT),
457 PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT),
458 PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT),
459 PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
460 PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
461 PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
462 PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT),
463 PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
464
465 /* PTD GPIO */
466 PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT),
467 PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT),
468 PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT),
469 PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT),
470 PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT),
471 PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT),
472 PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT),
473 PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
474
475 /* PTE GPIO */
476 PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT),
477 PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
478 PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
479 PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT),
480 PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT),
481 PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT),
482
483 /* PTF GPIO */
484 PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT),
485 PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT),
486 PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT),
487 PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT),
488 PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT),
489 PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT),
490 PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT),
491 PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT),
492
493 /* PTG GPIO */
494 PINMUX_DATA(PTG7_DATA, PTG7_IN, PTG7_OUT),
495 PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT),
496 PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT),
497 PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT),
498 PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT),
499 PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT),
500 PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT),
501 PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT),
502
503 /* PTH GPIO */
504 PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT),
505 PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT),
506 PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT),
507 PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT),
508 PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT),
509 PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT),
510 PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT),
511 PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT),
512
513 /* PTI GPIO */
514 PINMUX_DATA(PTI7_DATA, PTI7_IN, PTI7_OUT),
515 PINMUX_DATA(PTI6_DATA, PTI6_IN, PTI6_OUT),
516 PINMUX_DATA(PTI5_DATA, PTI5_IN, PTI5_OUT),
517 PINMUX_DATA(PTI4_DATA, PTI4_IN, PTI4_OUT),
518 PINMUX_DATA(PTI3_DATA, PTI3_IN, PTI3_OUT),
519 PINMUX_DATA(PTI2_DATA, PTI2_IN, PTI2_OUT),
520 PINMUX_DATA(PTI1_DATA, PTI1_IN, PTI1_OUT),
521 PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT),
522
523 /* PTJ GPIO */
524 PINMUX_DATA(PTJ7_DATA, PTJ7_IN, PTJ7_OUT),
525 PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT),
526 PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT),
527 PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT),
528 PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT),
529 PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT),
530 PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT),
531 PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT),
532
533 /* PTK GPIO */
534 PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT),
535 PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT),
536 PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT),
537 PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT),
538 PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT),
539 PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT),
540 PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT),
541 PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
542
543 /* PTL GPIO */
544 PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT),
545 PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
546 PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
547 PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
548 PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT),
549 PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT),
550 PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT),
551 PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT),
552
553 /* PTM GPIO */
554 PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT),
555 PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT),
556 PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT),
557 PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT),
558 PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT),
559 PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT),
560 PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
561
562 /* PTN GPIO */
563 PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT),
564 PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT),
565 PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT),
566 PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT),
567 PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT),
568 PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT),
569 PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT),
570 PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT),
571
572 /* PTO GPIO */
573 PINMUX_DATA(PTO7_DATA, PTO7_IN, PTO7_OUT),
574 PINMUX_DATA(PTO6_DATA, PTO6_IN, PTO6_OUT),
575 PINMUX_DATA(PTO5_DATA, PTO5_IN, PTO5_OUT),
576 PINMUX_DATA(PTO4_DATA, PTO4_IN, PTO4_OUT),
577 PINMUX_DATA(PTO3_DATA, PTO3_IN, PTO3_OUT),
578 PINMUX_DATA(PTO2_DATA, PTO2_IN, PTO2_OUT),
579 PINMUX_DATA(PTO1_DATA, PTO1_IN, PTO1_OUT),
580 PINMUX_DATA(PTO0_DATA, PTO0_IN, PTO0_OUT),
581
582 /* PTQ GPIO */
583 PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT),
584 PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT),
585 PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT),
586 PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT),
587 PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT),
588 PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT),
589 PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT),
590
591 /* PTR GPIO */
592 PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT),
593 PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT),
594 PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT),
595 PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT),
596 PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT),
597 PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT),
598 PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT),
599 PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT),
600
601 /* PTS GPIO */
602 PINMUX_DATA(PTS7_DATA, PTS7_IN, PTS7_OUT),
603 PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT),
604 PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT),
605 PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT),
606 PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT),
607 PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT),
608 PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT),
609 PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
610
611 /* PTT GPIO */
612 PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT),
613 PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
614 PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
615 PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT),
616 PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT),
617 PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT),
618
619 /* PTU GPIO */
620 PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT),
621 PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT),
622 PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT),
623 PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT),
624 PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT),
625 PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT),
626 PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT),
627 PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT),
628
629 /* PTV GPIO */
630 PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT),
631 PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT),
632 PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT),
633 PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT),
634 PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT),
635 PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT),
636 PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT),
637 PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT),
638
639 /* PTW GPIO */
640 PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT),
641 PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT),
642 PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT),
643 PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT),
644 PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT),
645 PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT),
646 PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT),
647 PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT),
648
649 /* PTX GPIO */
650 PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT),
651 PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT),
652 PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT),
653 PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT),
654 PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT),
655 PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT),
656 PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT),
657 PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT),
658
659 /* PTY GPIO */
660 PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT),
661 PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT),
662 PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT),
663 PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT),
664 PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT),
665 PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT),
666 PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT),
667 PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT),
668
669 /* PTZ GPIO */
670 PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT),
671 PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT),
672 PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT),
673 PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT),
674 PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT),
675 PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT),
676 PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT),
677 PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT),
678
679 /* PTA FN */
680 PINMUX_DATA(BS_MARK, PS0_15_FN1, PTA7_FN),
681 PINMUX_DATA(LGPIO7_MARK, PS0_15_FN3, PTA7_FN),
682 PINMUX_DATA(RDWR_MARK, PS0_14_FN1, PTA6_FN),
683 PINMUX_DATA(LGPIO6_MARK, PS0_14_FN3, PTA6_FN),
684 PINMUX_DATA(WE1_MARK, PS0_13_FN1, PTA5_FN),
685 PINMUX_DATA(LGPIO5_MARK, PS0_13_FN3, PTA5_FN),
686 PINMUX_DATA(RDY_MARK, PS0_12_FN1, PTA4_FN),
687 PINMUX_DATA(LGPIO4_MARK, PS0_12_FN3, PTA4_FN),
688 PINMUX_DATA(LGPIO3_MARK, PTA3_FN),
689 PINMUX_DATA(LGPIO2_MARK, PTA2_FN),
690 PINMUX_DATA(LGPIO1_MARK, PTA1_FN),
691 PINMUX_DATA(LGPIO0_MARK, PTA0_FN),
692
693 /* PTB FN */
694 PINMUX_DATA(D15_MARK, PS0_7_FN1, PTB7_FN),
695 PINMUX_DATA(ET0_MDC_MARK, PS0_7_FN2, PTB7_FN),
696 PINMUX_DATA(D14_MARK, PS0_6_FN1, PTB6_FN),
697 PINMUX_DATA(ET0_MDIO_MARK, PS0_6_FN2, PTB6_FN),
698 PINMUX_DATA(D13_MARK, PS0_5_FN1, PTB5_FN),
699 PINMUX_DATA(ET1_MDC_MARK, PS0_5_FN2, PTB5_FN),
700 PINMUX_DATA(D12_MARK, PS0_4_FN1, PTB4_FN),
701 PINMUX_DATA(ET1_MDIO_MARK, PS0_4_FN2, PTB4_FN),
702 PINMUX_DATA(D11_MARK, PS0_3_FN1, PTB3_FN),
703 PINMUX_DATA(SIM_D_MARK, PS0_3_FN2, PTB3_FN),
704 PINMUX_DATA(D10_MARK, PS0_2_FN1, PTB2_FN),
705 PINMUX_DATA(SIM_CLK_MARK, PS0_2_FN2, PTB2_FN),
706 PINMUX_DATA(D9_MARK, PS0_1_FN1, PTB1_FN),
707 PINMUX_DATA(SIM_RST_MARK, PS0_1_FN2, PTB1_FN),
708 PINMUX_DATA(D8_MARK, PTB0_FN),
709
710 /* PTC FN */
711 PINMUX_DATA(SD_WP_MARK, PTC7_FN),
712 PINMUX_DATA(SD_CD_MARK, PTC6_FN),
713 PINMUX_DATA(SD_CLK_MARK, PTC5_FN),
714 PINMUX_DATA(SD_CMD_MARK, PTC4_FN),
715 PINMUX_DATA(SD_D3_MARK, PTC3_FN),
716 PINMUX_DATA(SD_D2_MARK, PTC2_FN),
717 PINMUX_DATA(SD_D1_MARK, PTC1_FN),
718 PINMUX_DATA(SD_D0_MARK, PTC0_FN),
719
720 /* PTD FN */
721 PINMUX_DATA(IRQ7_MARK, PS1_7_FN1, PTD7_FN),
722 PINMUX_DATA(ADTRG1_MARK, PS1_7_FN3, PTD7_FN),
723 PINMUX_DATA(IRQ6_MARK, PS1_6_FN1, PTD6_FN),
724 PINMUX_DATA(ADTRG0_MARK, PS1_6_FN3, PTD6_FN),
725 PINMUX_DATA(IRQ5_MARK, PTD5_FN),
726 PINMUX_DATA(IRQ4_MARK, PTD4_FN),
727 PINMUX_DATA(IRQ3_MARK, PTD3_FN),
728 PINMUX_DATA(IRQ2_MARK, PTD2_FN),
729 PINMUX_DATA(IRQ1_MARK, PTD1_FN),
730 PINMUX_DATA(IRQ0_MARK, PTD0_FN),
731
732 /* PTE FN */
733 PINMUX_DATA(ET0_CRS_DV_MARK, PTE7_FN),
734 PINMUX_DATA(ET0_TXD1_MARK, PTE6_FN),
735 PINMUX_DATA(ET0_TXD0_MARK, PTE5_FN),
736 PINMUX_DATA(ET0_TX_EN_MARK, PTE4_FN),
737 PINMUX_DATA(ET0_REF_CLK_MARK, PTE3_FN),
738 PINMUX_DATA(ET0_RXD1_MARK, PTE2_FN),
739 PINMUX_DATA(ET0_RXD0_MARK, PTE1_FN),
740 PINMUX_DATA(ET0_RX_ER_MARK, PTE0_FN),
741
742 /* PTF FN */
743 PINMUX_DATA(ET1_CRS_DV_MARK, PTF7_FN),
744 PINMUX_DATA(ET1_TXD1_MARK, PTF6_FN),
745 PINMUX_DATA(ET1_TXD0_MARK, PTF5_FN),
746 PINMUX_DATA(ET1_TX_EN_MARK, PTF4_FN),
747 PINMUX_DATA(ET1_REF_CLK_MARK, PTF3_FN),
748 PINMUX_DATA(ET1_RXD1_MARK, PTF2_FN),
749 PINMUX_DATA(ET1_RXD0_MARK, PTF1_FN),
750 PINMUX_DATA(ET1_RX_ER_MARK, PTF0_FN),
751
752 /* PTG FN */
753 PINMUX_DATA(PWX0_MARK, PTG7_FN),
754 PINMUX_DATA(PWX1_MARK, PTG6_FN),
755 PINMUX_DATA(STATUS0_MARK, PS2_13_FN1, PTG5_FN),
756 PINMUX_DATA(PWX2_MARK, PS2_13_FN3, PTG5_FN),
757 PINMUX_DATA(STATUS1_MARK, PS2_12_FN1, PTG4_FN),
758 PINMUX_DATA(PWX3_MARK, PS2_12_FN3, PTG4_FN),
759 PINMUX_DATA(SERIRQ_MARK, PTG3_FN),
760 PINMUX_DATA(CLKRUN_MARK, PTG2_FN),
761 PINMUX_DATA(LPCPD_MARK, PTG1_FN),
762 PINMUX_DATA(LDRQ_MARK, PTG0_FN),
763
764 /* PTH FN */
765 PINMUX_DATA(SP1_MOSI_MARK, PTH7_FN),
766 PINMUX_DATA(SP1_MISO_MARK, PTH6_FN),
767 PINMUX_DATA(SP1_SCK_MARK, PTH5_FN),
768 PINMUX_DATA(SP1_SCK_FB_MARK, PTH4_FN),
769 PINMUX_DATA(SP1_SS0_MARK, PTH3_FN),
770 PINMUX_DATA(TCLK_MARK, PTH2_FN),
771 PINMUX_DATA(RXD4_MARK, PS2_1_FN1, PTH1_FN),
772 PINMUX_DATA(SP1_SS1_MARK, PS2_1_FN2, PTH1_FN),
773 PINMUX_DATA(TXD4_MARK, PS2_0_FN1, PTH0_FN),
774 PINMUX_DATA(SP0_SS1_MARK, PS2_0_FN2, PTH0_FN),
775
776 /* PTI FN */
777 PINMUX_DATA(IRQ15_MARK, PTI7_FN),
778 PINMUX_DATA(IRQ14_MARK, PTI6_FN),
779 PINMUX_DATA(IRQ13_MARK, PTI5_FN),
780 PINMUX_DATA(IRQ12_MARK, PTI4_FN),
781 PINMUX_DATA(IRQ11_MARK, PTI3_FN),
782 PINMUX_DATA(IRQ10_MARK, PTI2_FN),
783 PINMUX_DATA(IRQ9_MARK, PTI1_FN),
784 PINMUX_DATA(IRQ8_MARK, PTI0_FN),
785
786 /* PTJ FN */
787 PINMUX_DATA(RXD3_MARK, PTJ7_FN),
788 PINMUX_DATA(TXD3_MARK, PTJ6_FN),
789 PINMUX_DATA(RXD2_MARK, PTJ5_FN),
790 PINMUX_DATA(TXD2_MARK, PTJ4_FN),
791 PINMUX_DATA(COM1_TXD_MARK, PTJ3_FN),
792 PINMUX_DATA(COM1_RXD_MARK, PTJ2_FN),
793 PINMUX_DATA(COM1_RTS_MARK, PTJ1_FN),
794 PINMUX_DATA(COM1_CTS_MARK, PTJ0_FN),
795
796 /* PTK FN */
797 PINMUX_DATA(COM2_TXD_MARK, PTK7_FN),
798 PINMUX_DATA(COM2_RXD_MARK, PTK6_FN),
799 PINMUX_DATA(COM2_RTS_MARK, PTK5_FN),
800 PINMUX_DATA(COM2_CTS_MARK, PTK4_FN),
801 PINMUX_DATA(COM2_DTR_MARK, PTK3_FN),
802 PINMUX_DATA(COM2_DSR_MARK, PTK2_FN),
803 PINMUX_DATA(COM2_DCD_MARK, PTK1_FN),
804 PINMUX_DATA(COM2_RI_MARK, PTK0_FN),
805
806 /* PTL FN */
807 PINMUX_DATA(RAC_TXD_MARK, PTL7_FN),
808 PINMUX_DATA(RAC_RXD_MARK, PTL6_FN),
809 PINMUX_DATA(RAC_RTS_MARK, PTL5_FN),
810 PINMUX_DATA(RAC_CTS_MARK, PTL4_FN),
811 PINMUX_DATA(RAC_DTR_MARK, PTL3_FN),
812 PINMUX_DATA(RAC_DSR_MARK, PTL2_FN),
813 PINMUX_DATA(RAC_DCD_MARK, PTL1_FN),
814 PINMUX_DATA(RAC_RI_MARK, PTL0_FN),
815
816 /* PTM FN */
817 PINMUX_DATA(WP_MARK, PTM6_FN),
818 PINMUX_DATA(FMS0_MARK, PTM5_FN),
819 PINMUX_DATA(FMS1_MARK, PTM4_FN),
820 PINMUX_DATA(SDA6_MARK, PTM3_FN),
821 PINMUX_DATA(SCL6_MARK, PTM2_FN),
822 PINMUX_DATA(SDA7_MARK, PTM1_FN),
823 PINMUX_DATA(SCL7_MARK, PTM0_FN),
824
825 /* PTN FN */
826 PINMUX_DATA(SCK2_MARK, PS4_15_FN1, PTN7_FN),
827 PINMUX_DATA(EVENT7_MARK, PS4_15_FN2, PTN7_FN),
828 PINMUX_DATA(RTS4_MARK, PS4_14_FN1, PTN6_FN),
829 PINMUX_DATA(EVENT6_MARK, PS4_14_FN2, PTN6_FN),
830 PINMUX_DATA(RTS3_MARK, PS4_13_FN1, PTN5_FN),
831 PINMUX_DATA(EVENT5_MARK, PS4_13_FN2, PTN5_FN),
832 PINMUX_DATA(RTS2_MARK, PS4_12_FN1, PTN4_FN),
833 PINMUX_DATA(EVENT4_MARK, PS4_12_FN2, PTN4_FN),
834 PINMUX_DATA(CTS4_MARK, PS4_11_FN1, PTN3_FN),
835 PINMUX_DATA(EVENT3_MARK, PS4_11_FN2, PTN3_FN),
836 PINMUX_DATA(CTS3_MARK, PS4_10_FN1, PTN2_FN),
837 PINMUX_DATA(EVENT2_MARK, PS4_10_FN2, PTN2_FN),
838 PINMUX_DATA(CTS2_MARK, PS4_9_FN1, PTN1_FN),
839 PINMUX_DATA(EVENT1_MARK, PS4_9_FN2, PTN1_FN),
840 PINMUX_DATA(EVENT0_MARK, PTN0_FN),
841
842 /* PTO FN */
843 PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN),
844 PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN),
845 PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN),
846 PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN),
847 PINMUX_DATA(SGPIO1_CLK_MARK, PTO3_FN),
848 PINMUX_DATA(SGPIO1_LOAD_MARK, PTO2_FN),
849 PINMUX_DATA(SGPIO1_DI_MARK, PTO1_FN),
850 PINMUX_DATA(SGPIO1_DO_MARK, PTO0_FN),
851
852 /* PTP FN */
853 PINMUX_DATA(JMCTCK_MARK, PTP6_FN),
854 PINMUX_DATA(JMCTMS_MARK, PTP5_FN),
855 PINMUX_DATA(JMCTDO_MARK, PTP4_FN),
856 PINMUX_DATA(JMCTDI_MARK, PTP3_FN),
857 PINMUX_DATA(JMCRST_MARK, PTP2_FN),
858 PINMUX_DATA(SCK4_MARK, PTP1_FN),
859 PINMUX_DATA(SCK3_MARK, PTP0_FN),
860
861 /* PTQ FN */
862 PINMUX_DATA(LAD3_MARK, PTQ6_FN),
863 PINMUX_DATA(LAD2_MARK, PTQ5_FN),
864 PINMUX_DATA(LAD1_MARK, PTQ4_FN),
865 PINMUX_DATA(LAD0_MARK, PTQ3_FN),
866 PINMUX_DATA(LFRAME_MARK, PTQ2_FN),
867 PINMUX_DATA(SCK4_MARK, PTQ1_FN),
868 PINMUX_DATA(SCK3_MARK, PTQ0_FN),
869
870 /* PTR FN */
871 PINMUX_DATA(SDA8_MARK, PTR7_FN), /* DDC3? */
872 PINMUX_DATA(SCL8_MARK, PTR6_FN), /* DDC2? */
873 PINMUX_DATA(SDA2_MARK, PTR5_FN),
874 PINMUX_DATA(SCL2_MARK, PTR4_FN),
875 PINMUX_DATA(SDA1_MARK, PTR3_FN),
876 PINMUX_DATA(SCL1_MARK, PTR2_FN),
877 PINMUX_DATA(SDA0_MARK, PTR1_FN),
878 PINMUX_DATA(SCL0_MARK, PTR0_FN),
879
880 /* PTS FN */
881 PINMUX_DATA(SDA9_MARK, PTS7_FN), /* DDC1? */
882 PINMUX_DATA(SCL9_MARK, PTS6_FN), /* DDC0? */
883 PINMUX_DATA(SDA5_MARK, PTS5_FN),
884 PINMUX_DATA(SCL5_MARK, PTS4_FN),
885 PINMUX_DATA(SDA4_MARK, PTS3_FN),
886 PINMUX_DATA(SCL4_MARK, PTS2_FN),
887 PINMUX_DATA(SDA3_MARK, PTS1_FN),
888 PINMUX_DATA(SCL3_MARK, PTS0_FN),
889
890 /* PTT FN */
891 PINMUX_DATA(AUDSYNC_MARK, PTS5_FN),
892 PINMUX_DATA(AUDCK_MARK, PTS4_FN),
893 PINMUX_DATA(AUDATA3_MARK, PS4_3_FN1, PTS3_FN),
894 PINMUX_DATA(PWX7_MARK, PS4_3_FN2, PTS3_FN),
895 PINMUX_DATA(AUDATA2_MARK, PS4_2_FN1, PTS2_FN),
896 PINMUX_DATA(PWX6_MARK, PS4_2_FN2, PTS2_FN),
897 PINMUX_DATA(AUDATA1_MARK, PS4_1_FN1, PTS1_FN),
898 PINMUX_DATA(PWX5_MARK, PS4_1_FN2, PTS1_FN),
899 PINMUX_DATA(AUDATA0_MARK, PS4_0_FN1, PTS0_FN),
900 PINMUX_DATA(PWX4_MARK, PS4_0_FN2, PTS0_FN),
901
902 /* PTU FN */
903 PINMUX_DATA(CS6_MARK, PTU7_FN),
904 PINMUX_DATA(CS5_MARK, PTU6_FN),
905 PINMUX_DATA(CS4_MARK, PTU5_FN),
906 PINMUX_DATA(CS0_MARK, PTU4_FN),
907 PINMUX_DATA(RD_MARK, PTU3_FN),
908 PINMUX_DATA(WE0_MARK, PTU2_FN),
909 PINMUX_DATA(A25_MARK, PS5_9_FN1, PTU1_FN),
910 PINMUX_DATA(DREQ0_MARK, PS5_9_FN2, PTU1_FN),
911 PINMUX_DATA(A24_MARK, PS5_8_FN1, PTU0_FN),
912 PINMUX_DATA(DACK0_MARK, PS5_8_FN2, PTU0_FN),
913
914 /* PTV FN */
915 PINMUX_DATA(A23_MARK, PS5_7_FN1, PTV7_FN),
916 PINMUX_DATA(TEND0_MARK, PS5_7_FN2, PTV7_FN),
917 PINMUX_DATA(A22_MARK, PS5_6_FN1, PTV6_FN),
918 PINMUX_DATA(DREQ1_MARK, PS5_6_FN2, PTV6_FN),
919 PINMUX_DATA(A21_MARK, PS5_5_FN1, PTV5_FN),
920 PINMUX_DATA(DACK1_MARK, PS5_5_FN2, PTV5_FN),
921 PINMUX_DATA(A20_MARK, PS5_4_FN1, PTV4_FN),
922 PINMUX_DATA(TEND1_MARK, PS5_4_FN2, PTV4_FN),
923 PINMUX_DATA(A19_MARK, PTV3_FN),
924 PINMUX_DATA(A18_MARK, PTV2_FN),
925 PINMUX_DATA(A17_MARK, PTV1_FN),
926 PINMUX_DATA(A16_MARK, PTV0_FN),
927
928 /* PTW FN */
929 PINMUX_DATA(A15_MARK, PTW7_FN),
930 PINMUX_DATA(A14_MARK, PTW6_FN),
931 PINMUX_DATA(A13_MARK, PTW5_FN),
932 PINMUX_DATA(A12_MARK, PTW4_FN),
933 PINMUX_DATA(A11_MARK, PTW3_FN),
934 PINMUX_DATA(A10_MARK, PTW2_FN),
935 PINMUX_DATA(A9_MARK, PTW1_FN),
936 PINMUX_DATA(A8_MARK, PTW0_FN),
937
938 /* PTX FN */
939 PINMUX_DATA(A7_MARK, PTX7_FN),
940 PINMUX_DATA(A6_MARK, PTX6_FN),
941 PINMUX_DATA(A5_MARK, PTX5_FN),
942 PINMUX_DATA(A4_MARK, PTX4_FN),
943 PINMUX_DATA(A3_MARK, PTX3_FN),
944 PINMUX_DATA(A2_MARK, PTX2_FN),
945 PINMUX_DATA(A1_MARK, PTX1_FN),
946 PINMUX_DATA(A0_MARK, PTX0_FN),
947
948 /* PTY FN */
949 PINMUX_DATA(D7_MARK, PTY7_FN),
950 PINMUX_DATA(D6_MARK, PTY6_FN),
951 PINMUX_DATA(D5_MARK, PTY5_FN),
952 PINMUX_DATA(D4_MARK, PTY4_FN),
953 PINMUX_DATA(D3_MARK, PTY3_FN),
954 PINMUX_DATA(D2_MARK, PTY2_FN),
955 PINMUX_DATA(D1_MARK, PTY1_FN),
956 PINMUX_DATA(D0_MARK, PTY0_FN),
957};
958
959static struct pinmux_gpio pinmux_gpios[] = {
960 /* PTA */
961 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
962 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
963 PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
964 PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
965 PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
966 PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
967 PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
968 PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
969
970 /* PTB */
971 PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
972 PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
973 PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
974 PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
975 PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
976 PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
977 PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
978 PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
979
980 /* PTC */
981 PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
982 PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
983 PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
984 PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
985 PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
986 PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
987 PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
988 PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
989
990 /* PTD */
991 PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
992 PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
993 PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
994 PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
995 PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
996 PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
997 PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
998 PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
999
1000 /* PTE */
1001 PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
1002 PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
1003 PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
1004 PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
1005 PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
1006 PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
1007 PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
1008 PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
1009
1010 /* PTF */
1011 PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
1012 PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
1013 PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
1014 PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
1015 PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
1016 PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
1017 PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
1018 PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
1019
1020 /* PTG */
1021 PINMUX_GPIO(GPIO_PTG7, PTG7_DATA),
1022 PINMUX_GPIO(GPIO_PTG6, PTG6_DATA),
1023 PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
1024 PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
1025 PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
1026 PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
1027 PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
1028 PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
1029
1030 /* PTH */
1031 PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
1032 PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
1033 PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
1034 PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
1035 PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
1036 PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
1037 PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
1038 PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
1039
1040 /* PTI */
1041 PINMUX_GPIO(GPIO_PTI7, PTI7_DATA),
1042 PINMUX_GPIO(GPIO_PTI6, PTI6_DATA),
1043 PINMUX_GPIO(GPIO_PTI5, PTI5_DATA),
1044 PINMUX_GPIO(GPIO_PTI4, PTI4_DATA),
1045 PINMUX_GPIO(GPIO_PTI3, PTI3_DATA),
1046 PINMUX_GPIO(GPIO_PTI2, PTI2_DATA),
1047 PINMUX_GPIO(GPIO_PTI1, PTI1_DATA),
1048 PINMUX_GPIO(GPIO_PTI0, PTI0_DATA),
1049
1050 /* PTJ */
1051 PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
1052 PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
1053 PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
1054 PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA),
1055 PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
1056 PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
1057 PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
1058 PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
1059
1060 /* PTK */
1061 PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
1062 PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
1063 PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
1064 PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
1065 PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
1066 PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
1067 PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
1068 PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
1069
1070 /* PTL */
1071 PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
1072 PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
1073 PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
1074 PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
1075 PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
1076 PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
1077 PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
1078 PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
1079
1080 /* PTM */
1081 PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
1082 PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
1083 PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
1084 PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
1085 PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
1086 PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
1087 PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
1088
1089 /* PTN */
1090 PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
1091 PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
1092 PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
1093 PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
1094 PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
1095 PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
1096 PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
1097 PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
1098
1099 /* PTO */
1100 PINMUX_GPIO(GPIO_PTO7, PTO7_DATA),
1101 PINMUX_GPIO(GPIO_PTO6, PTO6_DATA),
1102 PINMUX_GPIO(GPIO_PTO5, PTO5_DATA),
1103 PINMUX_GPIO(GPIO_PTO4, PTO4_DATA),
1104 PINMUX_GPIO(GPIO_PTO3, PTO3_DATA),
1105 PINMUX_GPIO(GPIO_PTO2, PTO2_DATA),
1106 PINMUX_GPIO(GPIO_PTO1, PTO1_DATA),
1107 PINMUX_GPIO(GPIO_PTO0, PTO0_DATA),
1108
1109 /* PTP */
1110 PINMUX_GPIO(GPIO_PTP6, PTP6_DATA),
1111 PINMUX_GPIO(GPIO_PTP5, PTP5_DATA),
1112 PINMUX_GPIO(GPIO_PTP4, PTP4_DATA),
1113 PINMUX_GPIO(GPIO_PTP3, PTP3_DATA),
1114 PINMUX_GPIO(GPIO_PTP2, PTP2_DATA),
1115 PINMUX_GPIO(GPIO_PTP1, PTP1_DATA),
1116 PINMUX_GPIO(GPIO_PTP0, PTP0_DATA),
1117
1118 /* PTQ */
1119 PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
1120 PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
1121 PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
1122 PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
1123 PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
1124 PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
1125 PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
1126
1127 /* PTR */
1128 PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
1129 PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
1130 PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
1131 PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
1132 PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
1133 PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
1134 PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
1135 PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
1136
1137 /* PTS */
1138 PINMUX_GPIO(GPIO_PTS7, PTS7_DATA),
1139 PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
1140 PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
1141 PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
1142 PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
1143 PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
1144 PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
1145 PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
1146
1147 /* PTT */
1148 PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
1149 PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
1150 PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
1151 PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
1152 PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
1153 PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
1154
1155 /* PTU */
1156 PINMUX_GPIO(GPIO_PTU7, PTU7_DATA),
1157 PINMUX_GPIO(GPIO_PTU6, PTU6_DATA),
1158 PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
1159 PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
1160 PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
1161 PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
1162 PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
1163 PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
1164
1165 /* PTV */
1166 PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
1167 PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
1168 PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
1169 PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
1170 PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
1171 PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
1172 PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
1173 PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
1174
1175 /* PTW */
1176 PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
1177 PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
1178 PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
1179 PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
1180 PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
1181 PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
1182 PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
1183 PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
1184
1185 /* PTX */
1186 PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
1187 PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
1188 PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
1189 PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
1190 PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
1191 PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
1192 PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
1193 PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
1194
1195 /* PTY */
1196 PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
1197 PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
1198 PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
1199 PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
1200 PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
1201 PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
1202 PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
1203 PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
1204
1205 /* PTZ */
1206 PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
1207 PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
1208 PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
1209 PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
1210 PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
1211 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
1212 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1213 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1214
1215 /* PTA (mobule: LBSC, CPG, LPC) */
1216 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
1217 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
1218 PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK),
1219 PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK),
1220 PINMUX_GPIO(GPIO_FN_MD10, MD10_MARK),
1221 PINMUX_GPIO(GPIO_FN_MD9, MD9_MARK),
1222 PINMUX_GPIO(GPIO_FN_MD8, MD8_MARK),
1223 PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK),
1224 PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK),
1225 PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK),
1226 PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK),
1227 PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK),
1228 PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK),
1229 PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK),
1230 PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK),
1231
1232 /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
1233 PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
1234 PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
1235 PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
1236 PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
1237 PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
1238 PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
1239 PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
1240 PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
1241 PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK),
1242 PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK),
1243 PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK),
1244 PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK),
1245 PINMUX_GPIO(GPIO_FN_WPSZ1, WPSZ1_MARK),
1246 PINMUX_GPIO(GPIO_FN_WPSZ0, WPSZ0_MARK),
1247 PINMUX_GPIO(GPIO_FN_FWID, FWID_MARK),
1248 PINMUX_GPIO(GPIO_FN_FLSHSZ, FLSHSZ_MARK),
1249 PINMUX_GPIO(GPIO_FN_LPC_SPIEN, LPC_SPIEN_MARK),
1250 PINMUX_GPIO(GPIO_FN_BASEL, BASEL_MARK),
1251
1252 /* PTC (mobule: SD) */
1253 PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK),
1254 PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK),
1255 PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK),
1256 PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK),
1257 PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK),
1258 PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK),
1259 PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK),
1260 PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK),
1261
1262 /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
1263 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
1264 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
1265 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
1266 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
1267 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
1268 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
1269 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
1270 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
1271 PINMUX_GPIO(GPIO_FN_MD6, MD6_MARK),
1272 PINMUX_GPIO(GPIO_FN_MD5, MD5_MARK),
1273 PINMUX_GPIO(GPIO_FN_MD3, MD3_MARK),
1274 PINMUX_GPIO(GPIO_FN_MD2, MD2_MARK),
1275 PINMUX_GPIO(GPIO_FN_MD1, MD1_MARK),
1276 PINMUX_GPIO(GPIO_FN_MD0, MD0_MARK),
1277 PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK),
1278 PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK),
1279
1280 /* PTE (mobule: EtherC) */
1281 PINMUX_GPIO(GPIO_FN_ET0_CRS_DV, ET0_CRS_DV_MARK),
1282 PINMUX_GPIO(GPIO_FN_ET0_TXD1, ET0_TXD1_MARK),
1283 PINMUX_GPIO(GPIO_FN_ET0_TXD0, ET0_TXD0_MARK),
1284 PINMUX_GPIO(GPIO_FN_ET0_TX_EN, ET0_TX_EN_MARK),
1285 PINMUX_GPIO(GPIO_FN_ET0_REF_CLK, ET0_REF_CLK_MARK),
1286 PINMUX_GPIO(GPIO_FN_ET0_RXD1, ET0_RXD1_MARK),
1287 PINMUX_GPIO(GPIO_FN_ET0_RXD0, ET0_RXD0_MARK),
1288 PINMUX_GPIO(GPIO_FN_ET0_RX_ER, ET0_RX_ER_MARK),
1289
1290 /* PTF (mobule: EtherC) */
1291 PINMUX_GPIO(GPIO_FN_ET1_CRS_DV, ET1_CRS_DV_MARK),
1292 PINMUX_GPIO(GPIO_FN_ET1_TXD1, ET1_TXD1_MARK),
1293 PINMUX_GPIO(GPIO_FN_ET1_TXD0, ET1_TXD0_MARK),
1294 PINMUX_GPIO(GPIO_FN_ET1_TX_EN, ET1_TX_EN_MARK),
1295 PINMUX_GPIO(GPIO_FN_ET1_REF_CLK, ET1_REF_CLK_MARK),
1296 PINMUX_GPIO(GPIO_FN_ET1_RXD1, ET1_RXD1_MARK),
1297 PINMUX_GPIO(GPIO_FN_ET1_RXD0, ET1_RXD0_MARK),
1298 PINMUX_GPIO(GPIO_FN_ET1_RX_ER, ET1_RX_ER_MARK),
1299
1300 /* PTG (mobule: SYSTEM, PWMX, LPC) */
1301 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
1302 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
1303 PINMUX_GPIO(GPIO_FN_PWX0, PWX0_MARK),
1304 PINMUX_GPIO(GPIO_FN_PWX1, PWX1_MARK),
1305 PINMUX_GPIO(GPIO_FN_PWX2, PWX2_MARK),
1306 PINMUX_GPIO(GPIO_FN_PWX3, PWX3_MARK),
1307 PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK),
1308 PINMUX_GPIO(GPIO_FN_CLKRUN, CLKRUN_MARK),
1309 PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK),
1310 PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK),
1311
1312 /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
1313 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
1314 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
1315 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
1316 PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK),
1317 PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK),
1318 PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK),
1319 PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK),
1320 PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK),
1321 PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK),
1322 PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK),
1323
1324 /* PTI (mobule: INTC) */
1325 PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK),
1326 PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK),
1327 PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK),
1328 PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK),
1329 PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK),
1330 PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK),
1331 PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK),
1332 PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK),
1333
1334 /* PTJ (mobule: SCIF234, SERMUX) */
1335 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
1336 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
1337 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
1338 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
1339 PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK),
1340 PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK),
1341 PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK),
1342 PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK),
1343
1344 /* PTK (mobule: SERMUX) */
1345 PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK),
1346 PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK),
1347 PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK),
1348 PINMUX_GPIO(GPIO_FN_COM2_CTS, COM2_CTS_MARK),
1349 PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK),
1350 PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK),
1351 PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK),
1352 PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK),
1353
1354 /* PTL (mobule: SERMUX) */
1355 PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK),
1356 PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK),
1357 PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK),
1358 PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK),
1359 PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK),
1360 PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK),
1361 PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK),
1362 PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK),
1363
1364 /* PTM (mobule: IIC, LPC) */
1365 PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK),
1366 PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK),
1367 PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK),
1368 PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK),
1369 PINMUX_GPIO(GPIO_FN_WP, WP_MARK),
1370 PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK),
1371 PINMUX_GPIO(GPIO_FN_FMS1, FMS1_MARK),
1372
1373 /* PTN (mobule: SCIF234, EVC) */
1374 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
1375 PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK),
1376 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
1377 PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK),
1378 PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK),
1379 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
1380 PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK),
1381 PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK),
1382 PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK),
1383 PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK),
1384 PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK),
1385 PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK),
1386 PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK),
1387 PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK),
1388 PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK),
1389
1390 /* PTO (mobule: SGPIO) */
1391 PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK),
1392 PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK),
1393 PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK),
1394 PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK),
1395 PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK),
1396 PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK),
1397 PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK),
1398 PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK),
1399
1400 /* PTP (mobule: JMC, SCIF234) */
1401 PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK),
1402 PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK),
1403 PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK),
1404 PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK),
1405 PINMUX_GPIO(GPIO_FN_JMCRST, JMCRST_MARK),
1406 PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
1407 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
1408
1409 /* PTQ (mobule: LPC) */
1410 PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK),
1411 PINMUX_GPIO(GPIO_FN_LAD2, LAD2_MARK),
1412 PINMUX_GPIO(GPIO_FN_LAD1, LAD1_MARK),
1413 PINMUX_GPIO(GPIO_FN_LAD0, LAD0_MARK),
1414 PINMUX_GPIO(GPIO_FN_LFRAME, LFRAME_MARK),
1415 PINMUX_GPIO(GPIO_FN_LRESET, LRESET_MARK),
1416 PINMUX_GPIO(GPIO_FN_LCLK, LCLK_MARK),
1417
1418 /* PTR (mobule: GRA, IIC) */
1419 PINMUX_GPIO(GPIO_FN_DDC3, DDC3_MARK),
1420 PINMUX_GPIO(GPIO_FN_DDC2, DDC2_MARK),
1421 PINMUX_GPIO(GPIO_FN_SDA8, SDA8_MARK),
1422 PINMUX_GPIO(GPIO_FN_SCL8, SCL8_MARK),
1423 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
1424 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
1425 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
1426 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
1427 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
1428 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
1429
1430 /* PTS (mobule: GRA, IIC) */
1431 PINMUX_GPIO(GPIO_FN_DDC1, DDC1_MARK),
1432 PINMUX_GPIO(GPIO_FN_DDC0, DDC0_MARK),
1433 PINMUX_GPIO(GPIO_FN_SDA9, SDA9_MARK),
1434 PINMUX_GPIO(GPIO_FN_SCL9, SCL9_MARK),
1435 PINMUX_GPIO(GPIO_FN_SDA5, SDA5_MARK),
1436 PINMUX_GPIO(GPIO_FN_SCL5, SCL5_MARK),
1437 PINMUX_GPIO(GPIO_FN_SDA4, SDA4_MARK),
1438 PINMUX_GPIO(GPIO_FN_SCL4, SCL4_MARK),
1439 PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
1440 PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
1441
1442 /* PTT (mobule: SYSTEM, PWMX) */
1443 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
1444 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
1445 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
1446 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
1447 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
1448 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
1449 PINMUX_GPIO(GPIO_FN_PWX7, PWX7_MARK),
1450 PINMUX_GPIO(GPIO_FN_PWX6, PWX6_MARK),
1451 PINMUX_GPIO(GPIO_FN_PWX5, PWX5_MARK),
1452 PINMUX_GPIO(GPIO_FN_PWX4, PWX4_MARK),
1453
1454 /* PTU (mobule: LBSC, DMAC) */
1455 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
1456 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
1457 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
1458 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
1459 PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
1460 PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK),
1461 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1462 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1463 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
1464 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
1465
1466 /* PTV (mobule: LBSC, DMAC) */
1467 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
1468 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
1469 PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
1470 PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
1471 PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
1472 PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
1473 PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
1474 PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
1475 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
1476 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
1477 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
1478 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
1479
1480 /* PTW (mobule: LBSC) */
1481 PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
1482 PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
1483 PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
1484 PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
1485 PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
1486 PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
1487 PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
1488 PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
1489 PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
1490
1491 /* PTX (mobule: LBSC) */
1492 PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
1493 PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
1494 PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
1495 PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
1496 PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
1497 PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
1498 PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
1499 PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
1500
1501 /* PTY (mobule: LBSC) */
1502 PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
1503 PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
1504 PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
1505 PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
1506 PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
1507 PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
1508 PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
1509 PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
1510 };
1511
1512static struct pinmux_cfg_reg pinmux_config_regs[] = {
1513 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
1514 PTA7_FN, PTA7_OUT, PTA7_IN, 0,
1515 PTA6_FN, PTA6_OUT, PTA6_IN, 0,
1516 PTA5_FN, PTA5_OUT, PTA5_IN, 0,
1517 PTA4_FN, PTA4_OUT, PTA4_IN, 0,
1518 PTA3_FN, PTA3_OUT, PTA3_IN, 0,
1519 PTA2_FN, PTA2_OUT, PTA2_IN, 0,
1520 PTA1_FN, PTA1_OUT, PTA1_IN, 0,
1521 PTA0_FN, PTA0_OUT, PTA0_IN, 0 }
1522 },
1523 { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) {
1524 PTB7_FN, PTB7_OUT, PTB7_IN, 0,
1525 PTB6_FN, PTB6_OUT, PTB6_IN, 0,
1526 PTB5_FN, PTB5_OUT, PTB5_IN, 0,
1527 PTB4_FN, PTB4_OUT, PTB4_IN, 0,
1528 PTB3_FN, PTB3_OUT, PTB3_IN, 0,
1529 PTB2_FN, PTB2_OUT, PTB2_IN, 0,
1530 PTB1_FN, PTB1_OUT, PTB1_IN, 0,
1531 PTB0_FN, PTB0_OUT, PTB0_IN, 0 }
1532 },
1533 { PINMUX_CFG_REG("PCCR", 0xffec0004, 16, 2) {
1534 PTC7_FN, PTC7_OUT, PTC7_IN, 0,
1535 PTC6_FN, PTC6_OUT, PTC6_IN, 0,
1536 PTC5_FN, PTC5_OUT, PTC5_IN, 0,
1537 PTC4_FN, PTC4_OUT, PTC4_IN, 0,
1538 PTC3_FN, PTC3_OUT, PTC3_IN, 0,
1539 PTC2_FN, PTC2_OUT, PTC2_IN, 0,
1540 PTC1_FN, PTC1_OUT, PTC1_IN, 0,
1541 PTC0_FN, PTC0_OUT, PTC0_IN, 0 }
1542 },
1543 { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) {
1544 PTD7_FN, PTD7_OUT, PTD7_IN, 0,
1545 PTD6_FN, PTD6_OUT, PTD6_IN, 0,
1546 PTD5_FN, PTD5_OUT, PTD5_IN, 0,
1547 PTD4_FN, PTD4_OUT, PTD4_IN, 0,
1548 PTD3_FN, PTD3_OUT, PTD3_IN, 0,
1549 PTD2_FN, PTD2_OUT, PTD2_IN, 0,
1550 PTD1_FN, PTD1_OUT, PTD1_IN, 0,
1551 PTD0_FN, PTD0_OUT, PTD0_IN, 0 }
1552 },
1553 { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) {
1554 PTE7_FN, PTE7_OUT, PTE7_IN, 0,
1555 PTE6_FN, PTE6_OUT, PTE6_IN, 0,
1556 PTE5_FN, PTE5_OUT, PTE5_IN, 0,
1557 PTE4_FN, PTE4_OUT, PTE4_IN, 0,
1558 PTE3_FN, PTE3_OUT, PTE3_IN, 0,
1559 PTE2_FN, PTE2_OUT, PTE2_IN, 0,
1560 PTE1_FN, PTE1_OUT, PTE1_IN, 0,
1561 PTE0_FN, PTE0_OUT, PTE0_IN, 0 }
1562 },
1563 { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) {
1564 PTF7_FN, PTF7_OUT, PTF7_IN, 0,
1565 PTF6_FN, PTF6_OUT, PTF6_IN, 0,
1566 PTF5_FN, PTF5_OUT, PTF5_IN, 0,
1567 PTF4_FN, PTF4_OUT, PTF4_IN, 0,
1568 PTF3_FN, PTF3_OUT, PTF3_IN, 0,
1569 PTF2_FN, PTF2_OUT, PTF2_IN, 0,
1570 PTF1_FN, PTF1_OUT, PTF1_IN, 0,
1571 PTF0_FN, PTF0_OUT, PTF0_IN, 0 }
1572 },
1573 { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) {
1574 PTG7_FN, PTG7_OUT, PTG7_IN, 0,
1575 PTG6_FN, PTG6_OUT, PTG6_IN, 0,
1576 PTG5_FN, PTG5_OUT, PTG5_IN, 0,
1577 PTG4_FN, PTG4_OUT, PTG4_IN, 0,
1578 PTG3_FN, PTG3_OUT, PTG3_IN, 0,
1579 PTG2_FN, PTG2_OUT, PTG2_IN, 0,
1580 PTG1_FN, PTG1_OUT, PTG1_IN, 0,
1581 PTG0_FN, PTG0_OUT, PTG0_IN, 0 }
1582 },
1583 { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) {
1584 PTH7_FN, PTH7_OUT, PTH7_IN, 0,
1585 PTH6_FN, PTH6_OUT, PTH6_IN, 0,
1586 PTH5_FN, PTH5_OUT, PTH5_IN, 0,
1587 PTH4_FN, PTH4_OUT, PTH4_IN, 0,
1588 PTH3_FN, PTH3_OUT, PTH3_IN, 0,
1589 PTH2_FN, PTH2_OUT, PTH2_IN, 0,
1590 PTH1_FN, PTH1_OUT, PTH1_IN, 0,
1591 PTH0_FN, PTH0_OUT, PTH0_IN, 0 }
1592 },
1593 { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) {
1594 PTI7_FN, PTI7_OUT, PTI7_IN, 0,
1595 PTI6_FN, PTI6_OUT, PTI6_IN, 0,
1596 PTI5_FN, PTI5_OUT, PTI5_IN, 0,
1597 PTI4_FN, PTI4_OUT, PTI4_IN, 0,
1598 PTI3_FN, PTI3_OUT, PTI3_IN, 0,
1599 PTI2_FN, PTI2_OUT, PTI2_IN, 0,
1600 PTI1_FN, PTI1_OUT, PTI1_IN, 0,
1601 PTI0_FN, PTI0_OUT, PTI0_IN, 0 }
1602 },
1603 { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) {
1604 PTJ7_FN, PTJ7_OUT, PTJ7_IN, 0,
1605 PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0,
1606 PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0,
1607 PTJ4_FN, PTJ4_OUT, PTJ4_IN, 0,
1608 PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0,
1609 PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0,
1610 PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0,
1611 PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 }
1612 },
1613 { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) {
1614 PTK7_FN, PTK7_OUT, PTK7_IN, 0,
1615 PTK6_FN, PTK6_OUT, PTK6_IN, 0,
1616 PTK5_FN, PTK5_OUT, PTK5_IN, 0,
1617 PTK4_FN, PTK4_OUT, PTK4_IN, 0,
1618 PTK3_FN, PTK3_OUT, PTK3_IN, 0,
1619 PTK2_FN, PTK2_OUT, PTK2_IN, 0,
1620 PTK1_FN, PTK1_OUT, PTK1_IN, 0,
1621 PTK0_FN, PTK0_OUT, PTK0_IN, 0 }
1622 },
1623 { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) {
1624 PTL7_FN, PTL7_OUT, PTL7_IN, 0,
1625 PTL6_FN, PTL6_OUT, PTL6_IN, 0,
1626 PTL5_FN, PTL5_OUT, PTL5_IN, 0,
1627 PTL4_FN, PTL4_OUT, PTL4_IN, 0,
1628 PTL3_FN, PTL3_OUT, PTL3_IN, 0,
1629 PTL2_FN, PTL2_OUT, PTL2_IN, 0,
1630 PTL1_FN, PTL1_OUT, PTL1_IN, 0,
1631 PTL0_FN, PTL0_OUT, PTL0_IN, 0 }
1632 },
1633 { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) {
1634 0, 0, 0, 0, /* reserved: always set 1 */
1635 PTM6_FN, PTM6_OUT, PTM6_IN, 0,
1636 PTM5_FN, PTM5_OUT, PTM5_IN, 0,
1637 PTM4_FN, PTM4_OUT, PTM4_IN, 0,
1638 PTM3_FN, PTM3_OUT, PTM3_IN, 0,
1639 PTM2_FN, PTM2_OUT, PTM2_IN, 0,
1640 PTM1_FN, PTM1_OUT, PTM1_IN, 0,
1641 PTM0_FN, PTM0_OUT, PTM0_IN, 0 }
1642 },
1643 { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) {
1644 PTN7_FN, PTN7_OUT, PTN7_IN, 0,
1645 PTN6_FN, PTN6_OUT, PTN6_IN, 0,
1646 PTN5_FN, PTN5_OUT, PTN5_IN, 0,
1647 PTN4_FN, PTN4_OUT, PTN4_IN, 0,
1648 PTN3_FN, PTN3_OUT, PTN3_IN, 0,
1649 PTN2_FN, PTN2_OUT, PTN2_IN, 0,
1650 PTN1_FN, PTN1_OUT, PTN1_IN, 0,
1651 PTN0_FN, PTN0_OUT, PTN0_IN, 0 }
1652 },
1653 { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) {
1654 PTO7_FN, PTO7_OUT, PTO7_IN, 0,
1655 PTO6_FN, PTO6_OUT, PTO6_IN, 0,
1656 PTO5_FN, PTO5_OUT, PTO5_IN, 0,
1657 PTO4_FN, PTO4_OUT, PTO4_IN, 0,
1658 PTO3_FN, PTO3_OUT, PTO3_IN, 0,
1659 PTO2_FN, PTO2_OUT, PTO2_IN, 0,
1660 PTO1_FN, PTO1_OUT, PTO1_IN, 0,
1661 PTO0_FN, PTO0_OUT, PTO0_IN, 0 }
1662 },
1663 { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) {
1664 0, 0, 0, 0, /* reserved: always set 1 */
1665 PTP6_FN, PTP6_OUT, PTP6_IN, 0,
1666 PTP5_FN, PTP5_OUT, PTP5_IN, 0,
1667 PTP4_FN, PTP4_OUT, PTP4_IN, 0,
1668 PTP3_FN, PTP3_OUT, PTP3_IN, 0,
1669 PTP2_FN, PTP2_OUT, PTP2_IN, 0,
1670 PTP1_FN, PTP1_OUT, PTP1_IN, 0,
1671 PTP0_FN, PTP0_OUT, PTP0_IN, 0 }
1672 },
1673 { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) {
1674 0, 0, 0, 0, /* reserved: always set 1 */
1675 PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0,
1676 PTQ5_FN, PTQ5_OUT, PTQ5_IN, 0,
1677 PTQ4_FN, PTQ4_OUT, PTQ4_IN, 0,
1678 PTQ3_FN, PTQ3_OUT, PTQ3_IN, 0,
1679 PTQ2_FN, PTQ2_OUT, PTQ2_IN, 0,
1680 PTQ1_FN, PTQ1_OUT, PTQ1_IN, 0,
1681 PTQ0_FN, PTQ0_OUT, PTQ0_IN, 0 }
1682 },
1683 { PINMUX_CFG_REG("PRCR", 0xffec0022, 16, 2) {
1684 PTR7_FN, PTR7_OUT, PTR7_IN, 0,
1685 PTR6_FN, PTR6_OUT, PTR6_IN, 0,
1686 PTR5_FN, PTR5_OUT, PTR5_IN, 0,
1687 PTR4_FN, PTR4_OUT, PTR4_IN, 0,
1688 PTR3_FN, PTR3_OUT, PTR3_IN, 0,
1689 PTR2_FN, PTR2_OUT, PTR2_IN, 0,
1690 PTR1_FN, PTR1_OUT, PTR1_IN, 0,
1691 PTR0_FN, PTR0_OUT, PTR0_IN, 0 }
1692 },
1693 { PINMUX_CFG_REG("PSCR", 0xffec0024, 16, 2) {
1694 PTS7_FN, PTS7_OUT, PTS7_IN, 0,
1695 PTS6_FN, PTS6_OUT, PTS6_IN, 0,
1696 PTS5_FN, PTS5_OUT, PTS5_IN, 0,
1697 PTS4_FN, PTS4_OUT, PTS4_IN, 0,
1698 PTS3_FN, PTS3_OUT, PTS3_IN, 0,
1699 PTS2_FN, PTS2_OUT, PTS2_IN, 0,
1700 PTS1_FN, PTS1_OUT, PTS1_IN, 0,
1701 PTS0_FN, PTS0_OUT, PTS0_IN, 0 }
1702 },
1703 { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) {
1704 0, 0, 0, 0, /* reserved: always set 1 */
1705 0, 0, 0, 0, /* reserved: always set 1 */
1706 PTT5_FN, PTT5_OUT, PTT5_IN, 0,
1707 PTT4_FN, PTT4_OUT, PTT4_IN, 0,
1708 PTT3_FN, PTT3_OUT, PTT3_IN, 0,
1709 PTT2_FN, PTT2_OUT, PTT2_IN, 0,
1710 PTT1_FN, PTT1_OUT, PTT1_IN, 0,
1711 PTT0_FN, PTT0_OUT, PTT0_IN, 0 }
1712 },
1713 { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) {
1714 PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU,
1715 PTU6_FN, PTU6_OUT, PTU6_IN, PTU6_IN_PU,
1716 PTU5_FN, PTU5_OUT, PTU5_IN, PTU5_IN_PU,
1717 PTU4_FN, PTU4_OUT, PTU4_IN, PTU4_IN_PU,
1718 PTU3_FN, PTU3_OUT, PTU3_IN, PTU3_IN_PU,
1719 PTU2_FN, PTU2_OUT, PTU2_IN, PTU2_IN_PU,
1720 PTU1_FN, PTU1_OUT, PTU1_IN, PTU1_IN_PU,
1721 PTU0_FN, PTU0_OUT, PTU0_IN, PTU0_IN_PU }
1722 },
1723 { PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2) {
1724 PTV7_FN, PTV7_OUT, PTV7_IN, PTV7_IN_PU,
1725 PTV6_FN, PTV6_OUT, PTV6_IN, PTV6_IN_PU,
1726 PTV5_FN, PTV5_OUT, PTV5_IN, PTV5_IN_PU,
1727 PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU,
1728 PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU,
1729 PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU,
1730 PTV1_FN, PTV1_OUT, PTV1_IN, PTV1_IN_PU,
1731 PTV0_FN, PTV0_OUT, PTV0_IN, PTV0_IN_PU }
1732 },
1733 { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) {
1734 PTW7_FN, PTW7_OUT, PTW7_IN, PTW7_IN_PU,
1735 PTW6_FN, PTW6_OUT, PTW6_IN, PTW6_IN_PU,
1736 PTW5_FN, PTW5_OUT, PTW5_IN, PTW5_IN_PU,
1737 PTW4_FN, PTW4_OUT, PTW4_IN, PTW4_IN_PU,
1738 PTW3_FN, PTW3_OUT, PTW3_IN, PTW3_IN_PU,
1739 PTW2_FN, PTW2_OUT, PTW2_IN, PTW2_IN_PU,
1740 PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU,
1741 PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU }
1742 },
1743 { PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2) {
1744 PTX7_FN, PTX7_OUT, PTX7_IN, PTX7_IN_PU,
1745 PTX6_FN, PTX6_OUT, PTX6_IN, PTX6_IN_PU,
1746 PTX5_FN, PTX5_OUT, PTX5_IN, PTX5_IN_PU,
1747 PTX4_FN, PTX4_OUT, PTX4_IN, PTX4_IN_PU,
1748 PTX3_FN, PTX3_OUT, PTX3_IN, PTX3_IN_PU,
1749 PTX2_FN, PTX2_OUT, PTX2_IN, PTX2_IN_PU,
1750 PTX1_FN, PTX1_OUT, PTX1_IN, PTX1_IN_PU,
1751 PTX0_FN, PTX0_OUT, PTX0_IN, PTX0_IN_PU }
1752 },
1753 { PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2) {
1754 PTY7_FN, PTY7_OUT, PTY7_IN, PTY7_IN_PU,
1755 PTY6_FN, PTY6_OUT, PTY6_IN, PTY6_IN_PU,
1756 PTY5_FN, PTY5_OUT, PTY5_IN, PTY5_IN_PU,
1757 PTY4_FN, PTY4_OUT, PTY4_IN, PTY4_IN_PU,
1758 PTY3_FN, PTY3_OUT, PTY3_IN, PTY3_IN_PU,
1759 PTY2_FN, PTY2_OUT, PTY2_IN, PTY2_IN_PU,
1760 PTY1_FN, PTY1_OUT, PTY1_IN, PTY1_IN_PU,
1761 PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU }
1762 },
1763 { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) {
1764 0, PTZ7_OUT, PTZ7_IN, 0,
1765 0, PTZ6_OUT, PTZ6_IN, 0,
1766 0, PTZ5_OUT, PTZ5_IN, 0,
1767 0, PTZ4_OUT, PTZ4_IN, 0,
1768 0, PTZ3_OUT, PTZ3_IN, 0,
1769 0, PTZ2_OUT, PTZ2_IN, 0,
1770 0, PTZ1_OUT, PTZ1_IN, 0,
1771 0, PTZ0_OUT, PTZ0_IN, 0 }
1772 },
1773
1774 { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) {
1775 PS0_15_FN3, PS0_15_FN1,
1776 PS0_14_FN3, PS0_14_FN1,
1777 PS0_13_FN3, PS0_13_FN1,
1778 PS0_12_FN3, PS0_12_FN1,
1779 0, 0,
1780 0, 0,
1781 0, 0,
1782 0, 0,
1783 PS0_7_FN2, PS0_7_FN1,
1784 PS0_6_FN2, PS0_6_FN1,
1785 PS0_5_FN2, PS0_5_FN1,
1786 PS0_4_FN2, PS0_4_FN1,
1787 PS0_3_FN2, PS0_3_FN1,
1788 PS0_2_FN2, PS0_2_FN1,
1789 PS0_1_FN2, PS0_1_FN1,
1790 0, 0, }
1791 },
1792 { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) {
1793 0, 0,
1794 0, 0,
1795 0, 0,
1796 0, 0,
1797 0, 0,
1798 0, 0,
1799 0, 0,
1800 0, 0,
1801 PS1_7_FN1, PS1_7_FN3,
1802 PS1_6_FN1, PS1_6_FN3,
1803 0, 0,
1804 0, 0,
1805 0, 0,
1806 0, 0,
1807 0, 0,
1808 0, 0, }
1809 },
1810 { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) {
1811 0, 0,
1812 0, 0,
1813 PS2_13_FN3, PS2_13_FN1,
1814 PS2_12_FN3, PS2_12_FN1,
1815 0, 0,
1816 0, 0,
1817 0, 0,
1818 0, 0,
1819 0, 0,
1820 0, 0,
1821 0, 0,
1822 0, 0,
1823 0, 0,
1824 0, 0,
1825 PS2_1_FN1, PS2_1_FN2,
1826 PS2_0_FN1, PS2_0_FN2, }
1827 },
1828 { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) {
1829 PS4_15_FN2, PS4_15_FN1,
1830 PS4_14_FN2, PS4_14_FN1,
1831 PS4_13_FN2, PS4_13_FN1,
1832 PS4_12_FN2, PS4_12_FN1,
1833 PS4_11_FN2, PS4_11_FN1,
1834 PS4_10_FN2, PS4_10_FN1,
1835 PS4_9_FN2, PS4_9_FN1,
1836 0, 0,
1837 0, 0,
1838 0, 0,
1839 0, 0,
1840 0, 0,
1841 PS4_3_FN2, PS4_3_FN1,
1842 PS4_2_FN2, PS4_2_FN1,
1843 PS4_1_FN2, PS4_1_FN1,
1844 PS4_0_FN2, PS4_0_FN1, }
1845 },
1846 { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) {
1847 0, 0,
1848 0, 0,
1849 0, 0,
1850 0, 0,
1851 0, 0,
1852 0, 0,
1853 PS5_9_FN1, PS5_9_FN2,
1854 PS5_8_FN1, PS5_8_FN2,
1855 PS5_7_FN1, PS5_7_FN2,
1856 PS5_6_FN1, PS5_6_FN2,
1857 PS5_5_FN1, PS5_5_FN2,
1858 0, 0,
1859 0, 0,
1860 0, 0,
1861 0, 0,
1862 0, 0, }
1863 },
1864 { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) {
1865 0, 0,
1866 0, 0,
1867 0, 0,
1868 0, 0,
1869 0, 0,
1870 0, 0,
1871 0, 0,
1872 0, 0,
1873 PS6_7_FN_AN, PS6_7_FN_EV,
1874 PS6_6_FN_AN, PS6_6_FN_EV,
1875 PS6_5_FN_AN, PS6_5_FN_EV,
1876 PS6_4_FN_AN, PS6_4_FN_EV,
1877 PS6_3_FN_AN, PS6_3_FN_EV,
1878 PS6_2_FN_AN, PS6_2_FN_EV,
1879 PS6_1_FN_AN, PS6_1_FN_EV,
1880 PS6_0_FN_AN, PS6_0_FN_EV, }
1881 },
1882 {}
1883};
1884
1885static struct pinmux_data_reg pinmux_data_regs[] = {
1886 { PINMUX_DATA_REG("PADR", 0xffec0034, 8) {
1887 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1888 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
1889 },
1890 { PINMUX_DATA_REG("PBDR", 0xffec0036, 8) {
1891 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
1892 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
1893 },
1894 { PINMUX_DATA_REG("PCDR", 0xffec0038, 8) {
1895 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
1896 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
1897 },
1898 { PINMUX_DATA_REG("PDDR", 0xffec003a, 8) {
1899 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
1900 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
1901 },
1902 { PINMUX_DATA_REG("PEDR", 0xffec003c, 8) {
1903 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
1904 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
1905 },
1906 { PINMUX_DATA_REG("PFDR", 0xffec003e, 8) {
1907 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
1908 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
1909 },
1910 { PINMUX_DATA_REG("PGDR", 0xffec0040, 8) {
1911 PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
1912 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
1913 },
1914 { PINMUX_DATA_REG("PHDR", 0xffec0042, 8) {
1915 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
1916 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
1917 },
1918 { PINMUX_DATA_REG("PIDR", 0xffec0044, 8) {
1919 PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
1920 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA }
1921 },
1922 { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) {
1923 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
1924 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
1925 },
1926 { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) {
1927 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
1928 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
1929 },
1930 { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) {
1931 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
1932 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
1933 },
1934 { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) {
1935 0, PTM6_DATA, PTM5_DATA, PTM4_DATA,
1936 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
1937 },
1938 { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) {
1939 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
1940 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
1941 },
1942 { PINMUX_DATA_REG("PODR", 0xffec0050, 8) {
1943 PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
1944 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA }
1945 },
1946 { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) {
1947 0, PTP6_DATA, PTP5_DATA, PTP4_DATA,
1948 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
1949 },
1950 { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) {
1951 0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
1952 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
1953 },
1954 { PINMUX_DATA_REG("PRDR", 0xffec0056, 8) {
1955 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
1956 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
1957 },
1958 { PINMUX_DATA_REG("PSDR", 0xffec0058, 8) {
1959 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
1960 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
1961 },
1962 { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) {
1963 0, 0, PTT5_DATA, PTT4_DATA,
1964 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
1965 },
1966 { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) {
1967 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
1968 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
1969 },
1970 { PINMUX_DATA_REG("PVDR", 0xffec005e, 8) {
1971 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
1972 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
1973 },
1974 { PINMUX_DATA_REG("PWDR", 0xffec0060, 8) {
1975 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
1976 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
1977 },
1978 { PINMUX_DATA_REG("PXDR", 0xffec0062, 8) {
1979 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
1980 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
1981 },
1982 { PINMUX_DATA_REG("PYDR", 0xffec0064, 8) {
1983 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
1984 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
1985 },
1986 { PINMUX_DATA_REG("PZDR", 0xffec0066, 8) {
1987 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
1988 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
1989 },
1990 { },
1991};
1992
1993static struct pinmux_info sh7757_pinmux_info = {
1994 .name = "sh7757_pfc",
1995 .reserved_id = PINMUX_RESERVED,
1996 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1997 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1998 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1999 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2000 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2001 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2002
2003 .first_gpio = GPIO_PTA7,
2004 .last_gpio = GPIO_FN_D0,
2005
2006 .gpios = pinmux_gpios,
2007 .cfg_regs = pinmux_config_regs,
2008 .data_regs = pinmux_data_regs,
2009
2010 .gpio_data = pinmux_data,
2011 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2012};
2013
2014static int __init plat_pinmux_setup(void)
2015{
2016 return register_pinmux(&sh7757_pinmux_info);
2017}
2018
2019arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 1a956b1beccc..4a9010bf4fd3 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -40,7 +40,7 @@ static struct platform_device iic_device = {
40}; 40};
41 41
42static struct r8a66597_platdata r8a66597_data = { 42static struct r8a66597_platdata r8a66597_data = {
43 /* This set zero to all members */ 43 .on_chip = 1,
44}; 44};
45 45
46static struct resource usb_host_resources[] = { 46static struct resource usb_host_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index cda76ebf87c3..35097753456c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -13,9 +13,11 @@
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/uio_driver.h> 15#include <linux/uio_driver.h>
16#include <linux/usb/m66592.h>
16#include <linux/sh_timer.h> 17#include <linux/sh_timer.h>
17#include <asm/clock.h> 18#include <asm/clock.h>
18#include <asm/mmzone.h> 19#include <asm/mmzone.h>
20#include <cpu/sh7722.h>
19 21
20static struct resource rtc_resources[] = { 22static struct resource rtc_resources[] = {
21 [0] = { 23 [0] = {
@@ -45,11 +47,18 @@ static struct platform_device rtc_device = {
45 .id = -1, 47 .id = -1,
46 .num_resources = ARRAY_SIZE(rtc_resources), 48 .num_resources = ARRAY_SIZE(rtc_resources),
47 .resource = rtc_resources, 49 .resource = rtc_resources,
50 .archdata = {
51 .hwblk_id = HWBLK_RTC,
52 },
53};
54
55static struct m66592_platdata usbf_platdata = {
56 .on_chip = 1,
48}; 57};
49 58
50static struct resource usbf_resources[] = { 59static struct resource usbf_resources[] = {
51 [0] = { 60 [0] = {
52 .name = "m66592_udc", 61 .name = "USBF",
53 .start = 0x04480000, 62 .start = 0x04480000,
54 .end = 0x044800FF, 63 .end = 0x044800FF,
55 .flags = IORESOURCE_MEM, 64 .flags = IORESOURCE_MEM,
@@ -67,9 +76,13 @@ static struct platform_device usbf_device = {
67 .dev = { 76 .dev = {
68 .dma_mask = NULL, 77 .dma_mask = NULL,
69 .coherent_dma_mask = 0xffffffff, 78 .coherent_dma_mask = 0xffffffff,
79 .platform_data = &usbf_platdata,
70 }, 80 },
71 .num_resources = ARRAY_SIZE(usbf_resources), 81 .num_resources = ARRAY_SIZE(usbf_resources),
72 .resource = usbf_resources, 82 .resource = usbf_resources,
83 .archdata = {
84 .hwblk_id = HWBLK_USBF,
85 },
73}; 86};
74 87
75static struct resource iic_resources[] = { 88static struct resource iic_resources[] = {
@@ -91,6 +104,9 @@ static struct platform_device iic_device = {
91 .id = 0, /* "i2c0" clock */ 104 .id = 0, /* "i2c0" clock */
92 .num_resources = ARRAY_SIZE(iic_resources), 105 .num_resources = ARRAY_SIZE(iic_resources),
93 .resource = iic_resources, 106 .resource = iic_resources,
107 .archdata = {
108 .hwblk_id = HWBLK_IIC,
109 },
94}; 110};
95 111
96static struct uio_info vpu_platform_data = { 112static struct uio_info vpu_platform_data = {
@@ -119,6 +135,9 @@ static struct platform_device vpu_device = {
119 }, 135 },
120 .resource = vpu_resources, 136 .resource = vpu_resources,
121 .num_resources = ARRAY_SIZE(vpu_resources), 137 .num_resources = ARRAY_SIZE(vpu_resources),
138 .archdata = {
139 .hwblk_id = HWBLK_VPU,
140 },
122}; 141};
123 142
124static struct uio_info veu_platform_data = { 143static struct uio_info veu_platform_data = {
@@ -147,6 +166,9 @@ static struct platform_device veu_device = {
147 }, 166 },
148 .resource = veu_resources, 167 .resource = veu_resources,
149 .num_resources = ARRAY_SIZE(veu_resources), 168 .num_resources = ARRAY_SIZE(veu_resources),
169 .archdata = {
170 .hwblk_id = HWBLK_VEU,
171 },
150}; 172};
151 173
152static struct uio_info jpu_platform_data = { 174static struct uio_info jpu_platform_data = {
@@ -175,6 +197,9 @@ static struct platform_device jpu_device = {
175 }, 197 },
176 .resource = jpu_resources, 198 .resource = jpu_resources,
177 .num_resources = ARRAY_SIZE(jpu_resources), 199 .num_resources = ARRAY_SIZE(jpu_resources),
200 .archdata = {
201 .hwblk_id = HWBLK_JPU,
202 },
178}; 203};
179 204
180static struct sh_timer_config cmt_platform_data = { 205static struct sh_timer_config cmt_platform_data = {
@@ -207,6 +232,9 @@ static struct platform_device cmt_device = {
207 }, 232 },
208 .resource = cmt_resources, 233 .resource = cmt_resources,
209 .num_resources = ARRAY_SIZE(cmt_resources), 234 .num_resources = ARRAY_SIZE(cmt_resources),
235 .archdata = {
236 .hwblk_id = HWBLK_CMT,
237 },
210}; 238};
211 239
212static struct sh_timer_config tmu0_platform_data = { 240static struct sh_timer_config tmu0_platform_data = {
@@ -238,6 +266,9 @@ static struct platform_device tmu0_device = {
238 }, 266 },
239 .resource = tmu0_resources, 267 .resource = tmu0_resources,
240 .num_resources = ARRAY_SIZE(tmu0_resources), 268 .num_resources = ARRAY_SIZE(tmu0_resources),
269 .archdata = {
270 .hwblk_id = HWBLK_TMU,
271 },
241}; 272};
242 273
243static struct sh_timer_config tmu1_platform_data = { 274static struct sh_timer_config tmu1_platform_data = {
@@ -269,6 +300,9 @@ static struct platform_device tmu1_device = {
269 }, 300 },
270 .resource = tmu1_resources, 301 .resource = tmu1_resources,
271 .num_resources = ARRAY_SIZE(tmu1_resources), 302 .num_resources = ARRAY_SIZE(tmu1_resources),
303 .archdata = {
304 .hwblk_id = HWBLK_TMU,
305 },
272}; 306};
273 307
274static struct sh_timer_config tmu2_platform_data = { 308static struct sh_timer_config tmu2_platform_data = {
@@ -299,6 +333,9 @@ static struct platform_device tmu2_device = {
299 }, 333 },
300 .resource = tmu2_resources, 334 .resource = tmu2_resources,
301 .num_resources = ARRAY_SIZE(tmu2_resources), 335 .num_resources = ARRAY_SIZE(tmu2_resources),
336 .archdata = {
337 .hwblk_id = HWBLK_TMU,
338 },
302}; 339};
303 340
304static struct plat_sci_port sci_platform_data[] = { 341static struct plat_sci_port sci_platform_data[] = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index b45dace9539f..4caa5a7ca86e 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -18,6 +18,7 @@
18#include <linux/io.h> 18#include <linux/io.h>
19#include <asm/clock.h> 19#include <asm/clock.h>
20#include <asm/mmzone.h> 20#include <asm/mmzone.h>
21#include <cpu/sh7723.h>
21 22
22static struct uio_info vpu_platform_data = { 23static struct uio_info vpu_platform_data = {
23 .name = "VPU5", 24 .name = "VPU5",
@@ -45,6 +46,9 @@ static struct platform_device vpu_device = {
45 }, 46 },
46 .resource = vpu_resources, 47 .resource = vpu_resources,
47 .num_resources = ARRAY_SIZE(vpu_resources), 48 .num_resources = ARRAY_SIZE(vpu_resources),
49 .archdata = {
50 .hwblk_id = HWBLK_VPU,
51 },
48}; 52};
49 53
50static struct uio_info veu0_platform_data = { 54static struct uio_info veu0_platform_data = {
@@ -73,6 +77,9 @@ static struct platform_device veu0_device = {
73 }, 77 },
74 .resource = veu0_resources, 78 .resource = veu0_resources,
75 .num_resources = ARRAY_SIZE(veu0_resources), 79 .num_resources = ARRAY_SIZE(veu0_resources),
80 .archdata = {
81 .hwblk_id = HWBLK_VEU2H0,
82 },
76}; 83};
77 84
78static struct uio_info veu1_platform_data = { 85static struct uio_info veu1_platform_data = {
@@ -101,6 +108,9 @@ static struct platform_device veu1_device = {
101 }, 108 },
102 .resource = veu1_resources, 109 .resource = veu1_resources,
103 .num_resources = ARRAY_SIZE(veu1_resources), 110 .num_resources = ARRAY_SIZE(veu1_resources),
111 .archdata = {
112 .hwblk_id = HWBLK_VEU2H1,
113 },
104}; 114};
105 115
106static struct sh_timer_config cmt_platform_data = { 116static struct sh_timer_config cmt_platform_data = {
@@ -133,6 +143,9 @@ static struct platform_device cmt_device = {
133 }, 143 },
134 .resource = cmt_resources, 144 .resource = cmt_resources,
135 .num_resources = ARRAY_SIZE(cmt_resources), 145 .num_resources = ARRAY_SIZE(cmt_resources),
146 .archdata = {
147 .hwblk_id = HWBLK_CMT,
148 },
136}; 149};
137 150
138static struct sh_timer_config tmu0_platform_data = { 151static struct sh_timer_config tmu0_platform_data = {
@@ -164,6 +177,9 @@ static struct platform_device tmu0_device = {
164 }, 177 },
165 .resource = tmu0_resources, 178 .resource = tmu0_resources,
166 .num_resources = ARRAY_SIZE(tmu0_resources), 179 .num_resources = ARRAY_SIZE(tmu0_resources),
180 .archdata = {
181 .hwblk_id = HWBLK_TMU0,
182 },
167}; 183};
168 184
169static struct sh_timer_config tmu1_platform_data = { 185static struct sh_timer_config tmu1_platform_data = {
@@ -195,6 +211,9 @@ static struct platform_device tmu1_device = {
195 }, 211 },
196 .resource = tmu1_resources, 212 .resource = tmu1_resources,
197 .num_resources = ARRAY_SIZE(tmu1_resources), 213 .num_resources = ARRAY_SIZE(tmu1_resources),
214 .archdata = {
215 .hwblk_id = HWBLK_TMU0,
216 },
198}; 217};
199 218
200static struct sh_timer_config tmu2_platform_data = { 219static struct sh_timer_config tmu2_platform_data = {
@@ -225,6 +244,9 @@ static struct platform_device tmu2_device = {
225 }, 244 },
226 .resource = tmu2_resources, 245 .resource = tmu2_resources,
227 .num_resources = ARRAY_SIZE(tmu2_resources), 246 .num_resources = ARRAY_SIZE(tmu2_resources),
247 .archdata = {
248 .hwblk_id = HWBLK_TMU0,
249 },
228}; 250};
229 251
230static struct sh_timer_config tmu3_platform_data = { 252static struct sh_timer_config tmu3_platform_data = {
@@ -255,6 +277,9 @@ static struct platform_device tmu3_device = {
255 }, 277 },
256 .resource = tmu3_resources, 278 .resource = tmu3_resources,
257 .num_resources = ARRAY_SIZE(tmu3_resources), 279 .num_resources = ARRAY_SIZE(tmu3_resources),
280 .archdata = {
281 .hwblk_id = HWBLK_TMU1,
282 },
258}; 283};
259 284
260static struct sh_timer_config tmu4_platform_data = { 285static struct sh_timer_config tmu4_platform_data = {
@@ -285,6 +310,9 @@ static struct platform_device tmu4_device = {
285 }, 310 },
286 .resource = tmu4_resources, 311 .resource = tmu4_resources,
287 .num_resources = ARRAY_SIZE(tmu4_resources), 312 .num_resources = ARRAY_SIZE(tmu4_resources),
313 .archdata = {
314 .hwblk_id = HWBLK_TMU1,
315 },
288}; 316};
289 317
290static struct sh_timer_config tmu5_platform_data = { 318static struct sh_timer_config tmu5_platform_data = {
@@ -315,6 +343,9 @@ static struct platform_device tmu5_device = {
315 }, 343 },
316 .resource = tmu5_resources, 344 .resource = tmu5_resources,
317 .num_resources = ARRAY_SIZE(tmu5_resources), 345 .num_resources = ARRAY_SIZE(tmu5_resources),
346 .archdata = {
347 .hwblk_id = HWBLK_TMU1,
348 },
318}; 349};
319 350
320static struct plat_sci_port sci_platform_data[] = { 351static struct plat_sci_port sci_platform_data[] = {
@@ -395,10 +426,13 @@ static struct platform_device rtc_device = {
395 .id = -1, 426 .id = -1,
396 .num_resources = ARRAY_SIZE(rtc_resources), 427 .num_resources = ARRAY_SIZE(rtc_resources),
397 .resource = rtc_resources, 428 .resource = rtc_resources,
429 .archdata = {
430 .hwblk_id = HWBLK_RTC,
431 },
398}; 432};
399 433
400static struct r8a66597_platdata r8a66597_data = { 434static struct r8a66597_platdata r8a66597_data = {
401 /* This set zero to all members */ 435 .on_chip = 1,
402}; 436};
403 437
404static struct resource sh7723_usb_host_resources[] = { 438static struct resource sh7723_usb_host_resources[] = {
@@ -424,6 +458,9 @@ static struct platform_device sh7723_usb_host_device = {
424 }, 458 },
425 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), 459 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources),
426 .resource = sh7723_usb_host_resources, 460 .resource = sh7723_usb_host_resources,
461 .archdata = {
462 .hwblk_id = HWBLK_USB,
463 },
427}; 464};
428 465
429static struct resource iic_resources[] = { 466static struct resource iic_resources[] = {
@@ -445,6 +482,9 @@ static struct platform_device iic_device = {
445 .id = 0, /* "i2c0" clock */ 482 .id = 0, /* "i2c0" clock */
446 .num_resources = ARRAY_SIZE(iic_resources), 483 .num_resources = ARRAY_SIZE(iic_resources),
447 .resource = iic_resources, 484 .resource = iic_resources,
485 .archdata = {
486 .hwblk_id = HWBLK_IIC,
487 },
448}; 488};
449 489
450static struct platform_device *sh7723_devices[] __initdata = { 490static struct platform_device *sh7723_devices[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index a04edaab9a29..f3851fd757ec 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <asm/clock.h> 23#include <asm/clock.h>
24#include <asm/mmzone.h> 24#include <asm/mmzone.h>
25#include <cpu/sh7724.h>
25 26
26/* Serial */ 27/* Serial */
27static struct plat_sci_port sci_platform_data[] = { 28static struct plat_sci_port sci_platform_data[] = {
@@ -103,6 +104,9 @@ static struct platform_device rtc_device = {
103 .id = -1, 104 .id = -1,
104 .num_resources = ARRAY_SIZE(rtc_resources), 105 .num_resources = ARRAY_SIZE(rtc_resources),
105 .resource = rtc_resources, 106 .resource = rtc_resources,
107 .archdata = {
108 .hwblk_id = HWBLK_RTC,
109 },
106}; 110};
107 111
108/* I2C0 */ 112/* I2C0 */
@@ -125,6 +129,9 @@ static struct platform_device iic0_device = {
125 .id = 0, /* "i2c0" clock */ 129 .id = 0, /* "i2c0" clock */
126 .num_resources = ARRAY_SIZE(iic0_resources), 130 .num_resources = ARRAY_SIZE(iic0_resources),
127 .resource = iic0_resources, 131 .resource = iic0_resources,
132 .archdata = {
133 .hwblk_id = HWBLK_IIC0,
134 },
128}; 135};
129 136
130/* I2C1 */ 137/* I2C1 */
@@ -147,6 +154,9 @@ static struct platform_device iic1_device = {
147 .id = 1, /* "i2c1" clock */ 154 .id = 1, /* "i2c1" clock */
148 .num_resources = ARRAY_SIZE(iic1_resources), 155 .num_resources = ARRAY_SIZE(iic1_resources),
149 .resource = iic1_resources, 156 .resource = iic1_resources,
157 .archdata = {
158 .hwblk_id = HWBLK_IIC1,
159 },
150}; 160};
151 161
152/* VPU */ 162/* VPU */
@@ -176,6 +186,9 @@ static struct platform_device vpu_device = {
176 }, 186 },
177 .resource = vpu_resources, 187 .resource = vpu_resources,
178 .num_resources = ARRAY_SIZE(vpu_resources), 188 .num_resources = ARRAY_SIZE(vpu_resources),
189 .archdata = {
190 .hwblk_id = HWBLK_VPU,
191 },
179}; 192};
180 193
181/* VEU0 */ 194/* VEU0 */
@@ -205,6 +218,9 @@ static struct platform_device veu0_device = {
205 }, 218 },
206 .resource = veu0_resources, 219 .resource = veu0_resources,
207 .num_resources = ARRAY_SIZE(veu0_resources), 220 .num_resources = ARRAY_SIZE(veu0_resources),
221 .archdata = {
222 .hwblk_id = HWBLK_VEU0,
223 },
208}; 224};
209 225
210/* VEU1 */ 226/* VEU1 */
@@ -234,6 +250,9 @@ static struct platform_device veu1_device = {
234 }, 250 },
235 .resource = veu1_resources, 251 .resource = veu1_resources,
236 .num_resources = ARRAY_SIZE(veu1_resources), 252 .num_resources = ARRAY_SIZE(veu1_resources),
253 .archdata = {
254 .hwblk_id = HWBLK_VEU1,
255 },
237}; 256};
238 257
239static struct sh_timer_config cmt_platform_data = { 258static struct sh_timer_config cmt_platform_data = {
@@ -266,6 +285,9 @@ static struct platform_device cmt_device = {
266 }, 285 },
267 .resource = cmt_resources, 286 .resource = cmt_resources,
268 .num_resources = ARRAY_SIZE(cmt_resources), 287 .num_resources = ARRAY_SIZE(cmt_resources),
288 .archdata = {
289 .hwblk_id = HWBLK_CMT,
290 },
269}; 291};
270 292
271static struct sh_timer_config tmu0_platform_data = { 293static struct sh_timer_config tmu0_platform_data = {
@@ -297,6 +319,9 @@ static struct platform_device tmu0_device = {
297 }, 319 },
298 .resource = tmu0_resources, 320 .resource = tmu0_resources,
299 .num_resources = ARRAY_SIZE(tmu0_resources), 321 .num_resources = ARRAY_SIZE(tmu0_resources),
322 .archdata = {
323 .hwblk_id = HWBLK_TMU0,
324 },
300}; 325};
301 326
302static struct sh_timer_config tmu1_platform_data = { 327static struct sh_timer_config tmu1_platform_data = {
@@ -328,6 +353,9 @@ static struct platform_device tmu1_device = {
328 }, 353 },
329 .resource = tmu1_resources, 354 .resource = tmu1_resources,
330 .num_resources = ARRAY_SIZE(tmu1_resources), 355 .num_resources = ARRAY_SIZE(tmu1_resources),
356 .archdata = {
357 .hwblk_id = HWBLK_TMU0,
358 },
331}; 359};
332 360
333static struct sh_timer_config tmu2_platform_data = { 361static struct sh_timer_config tmu2_platform_data = {
@@ -358,6 +386,9 @@ static struct platform_device tmu2_device = {
358 }, 386 },
359 .resource = tmu2_resources, 387 .resource = tmu2_resources,
360 .num_resources = ARRAY_SIZE(tmu2_resources), 388 .num_resources = ARRAY_SIZE(tmu2_resources),
389 .archdata = {
390 .hwblk_id = HWBLK_TMU0,
391 },
361}; 392};
362 393
363 394
@@ -389,6 +420,9 @@ static struct platform_device tmu3_device = {
389 }, 420 },
390 .resource = tmu3_resources, 421 .resource = tmu3_resources,
391 .num_resources = ARRAY_SIZE(tmu3_resources), 422 .num_resources = ARRAY_SIZE(tmu3_resources),
423 .archdata = {
424 .hwblk_id = HWBLK_TMU1,
425 },
392}; 426};
393 427
394static struct sh_timer_config tmu4_platform_data = { 428static struct sh_timer_config tmu4_platform_data = {
@@ -419,6 +453,9 @@ static struct platform_device tmu4_device = {
419 }, 453 },
420 .resource = tmu4_resources, 454 .resource = tmu4_resources,
421 .num_resources = ARRAY_SIZE(tmu4_resources), 455 .num_resources = ARRAY_SIZE(tmu4_resources),
456 .archdata = {
457 .hwblk_id = HWBLK_TMU1,
458 },
422}; 459};
423 460
424static struct sh_timer_config tmu5_platform_data = { 461static struct sh_timer_config tmu5_platform_data = {
@@ -449,6 +486,9 @@ static struct platform_device tmu5_device = {
449 }, 486 },
450 .resource = tmu5_resources, 487 .resource = tmu5_resources,
451 .num_resources = ARRAY_SIZE(tmu5_resources), 488 .num_resources = ARRAY_SIZE(tmu5_resources),
489 .archdata = {
490 .hwblk_id = HWBLK_TMU1,
491 },
452}; 492};
453 493
454/* JPU */ 494/* JPU */
@@ -478,6 +518,9 @@ static struct platform_device jpu_device = {
478 }, 518 },
479 .resource = jpu_resources, 519 .resource = jpu_resources,
480 .num_resources = ARRAY_SIZE(jpu_resources), 520 .num_resources = ARRAY_SIZE(jpu_resources),
521 .archdata = {
522 .hwblk_id = HWBLK_JPU,
523 },
481}; 524};
482 525
483static struct platform_device *sh7724_devices[] __initdata = { 526static struct platform_device *sh7724_devices[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
new file mode 100644
index 000000000000..c470e15f2e03
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -0,0 +1,513 @@
1/*
2 * SH7757 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/platform_device.h>
13#include <linux/init.h>
14#include <linux/serial.h>
15#include <linux/serial_sci.h>
16#include <linux/io.h>
17#include <linux/mm.h>
18#include <linux/sh_timer.h>
19
20static struct sh_timer_config tmu0_platform_data = {
21 .name = "TMU0",
22 .channel_offset = 0x04,
23 .timer_bit = 0,
24 .clk = "peripheral_clk",
25 .clockevent_rating = 200,
26};
27
28static struct resource tmu0_resources[] = {
29 [0] = {
30 .name = "TMU0",
31 .start = 0xfe430008,
32 .end = 0xfe430013,
33 .flags = IORESOURCE_MEM,
34 },
35 [1] = {
36 .start = 28,
37 .flags = IORESOURCE_IRQ,
38 },
39};
40
41static struct platform_device tmu0_device = {
42 .name = "sh_tmu",
43 .id = 0,
44 .dev = {
45 .platform_data = &tmu0_platform_data,
46 },
47 .resource = tmu0_resources,
48 .num_resources = ARRAY_SIZE(tmu0_resources),
49};
50
51static struct sh_timer_config tmu1_platform_data = {
52 .name = "TMU1",
53 .channel_offset = 0x10,
54 .timer_bit = 1,
55 .clk = "peripheral_clk",
56 .clocksource_rating = 200,
57};
58
59static struct resource tmu1_resources[] = {
60 [0] = {
61 .name = "TMU1",
62 .start = 0xfe430014,
63 .end = 0xfe43001f,
64 .flags = IORESOURCE_MEM,
65 },
66 [1] = {
67 .start = 29,
68 .flags = IORESOURCE_IRQ,
69 },
70};
71
72static struct platform_device tmu1_device = {
73 .name = "sh_tmu",
74 .id = 1,
75 .dev = {
76 .platform_data = &tmu1_platform_data,
77 },
78 .resource = tmu1_resources,
79 .num_resources = ARRAY_SIZE(tmu1_resources),
80};
81
82static struct plat_sci_port sci_platform_data[] = {
83 {
84 .mapbase = 0xfe4b0000, /* SCIF2 */
85 .flags = UPF_BOOT_AUTOCONF,
86 .type = PORT_SCIF,
87 .irqs = { 40, 40, 40, 40 },
88 }, {
89 .mapbase = 0xfe4c0000, /* SCIF3 */
90 .flags = UPF_BOOT_AUTOCONF,
91 .type = PORT_SCIF,
92 .irqs = { 76, 76, 76, 76 },
93 }, {
94 .mapbase = 0xfe4d0000, /* SCIF4 */
95 .flags = UPF_BOOT_AUTOCONF,
96 .type = PORT_SCIF,
97 .irqs = { 104, 104, 104, 104 },
98 }, {
99 .flags = 0,
100 }
101};
102
103static struct platform_device sci_device = {
104 .name = "sh-sci",
105 .id = -1,
106 .dev = {
107 .platform_data = sci_platform_data,
108 },
109};
110
111static struct platform_device *sh7757_devices[] __initdata = {
112 &tmu0_device,
113 &tmu1_device,
114 &sci_device,
115};
116
117static int __init sh7757_devices_setup(void)
118{
119 return platform_add_devices(sh7757_devices,
120 ARRAY_SIZE(sh7757_devices));
121}
122arch_initcall(sh7757_devices_setup);
123
124enum {
125 UNUSED = 0,
126
127 /* interrupt sources */
128
129 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
130 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
131 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
132 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
133
134 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
135 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
136 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
137 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
138 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
139
140 SDHI,
141 DVC,
142 IRQ8, IRQ9, IRQ10,
143 WDT0,
144 TMU0, TMU1, TMU2, TMU2_TICPI,
145 HUDI,
146
147 ARC4,
148 DMAC0,
149 IRQ11,
150 SCIF2,
151 DMAC1_6,
152 USB0,
153 IRQ12,
154 JMC,
155 SPI1,
156 IRQ13, IRQ14,
157 USB1,
158 TMR01, TMR23, TMR45,
159 WDT1,
160 FRT,
161 LPC,
162 SCIF0, SCIF1, SCIF3,
163 PECI0I, PECI1I, PECI2I,
164 IRQ15,
165 ETHERC,
166 SPI0,
167 ADC1,
168 DMAC1_8,
169 SIM,
170 TMU3, TMU4, TMU5,
171 ADC0,
172 SCIF4,
173 IIC0_0, IIC0_1, IIC0_2, IIC0_3,
174 IIC1_0, IIC1_1, IIC1_2, IIC1_3,
175 IIC2_0, IIC2_1, IIC2_2, IIC2_3,
176 IIC3_0, IIC3_1, IIC3_2, IIC3_3,
177 IIC4_0, IIC4_1, IIC4_2, IIC4_3,
178 IIC5_0, IIC5_1, IIC5_2, IIC5_3,
179 IIC6_0, IIC6_1, IIC6_2, IIC6_3,
180 IIC7_0, IIC7_1, IIC7_2, IIC7_3,
181 IIC8_0, IIC8_1, IIC8_2, IIC8_3,
182 IIC9_0, IIC9_1, IIC9_2, IIC9_3,
183 PCIINTA,
184 PCIE,
185 SGPIO,
186
187 /* interrupt groups */
188
189 TMU012, TMU345,
190};
191
192static struct intc_vect vectors[] __initdata = {
193 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
194 INTC_VECT(SDHI, 0x4c0),
195 INTC_VECT(DVC, 0x4e0),
196 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
197 INTC_VECT(IRQ10, 0x540),
198 INTC_VECT(WDT0, 0x560),
199 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
200 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
201 INTC_VECT(HUDI, 0x600),
202 INTC_VECT(ARC4, 0x620),
203 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
204 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
205 INTC_VECT(DMAC0, 0x6c0),
206 INTC_VECT(IRQ11, 0x6e0),
207 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
208 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
209 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
210 INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0),
211 INTC_VECT(USB0, 0x840),
212 INTC_VECT(IRQ12, 0x880),
213 INTC_VECT(JMC, 0x8a0),
214 INTC_VECT(SPI1, 0x8c0),
215 INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
216 INTC_VECT(USB1, 0x920),
217 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
218 INTC_VECT(TMR45, 0xa40),
219 INTC_VECT(WDT1, 0xa60),
220 INTC_VECT(FRT, 0xa80),
221 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
222 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
223 INTC_VECT(LPC, 0xb20),
224 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
225 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
226 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
227 INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20),
228 INTC_VECT(PECI2I, 0xc40),
229 INTC_VECT(IRQ15, 0xc60),
230 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
231 INTC_VECT(SPI0, 0xcc0),
232 INTC_VECT(ADC1, 0xce0),
233 INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20),
234 INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60),
235 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
236 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
237 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
238 INTC_VECT(TMU5, 0xe40),
239 INTC_VECT(ADC0, 0xe60),
240 INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
241 INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
242 INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
243 INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
244 INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
245 INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
246 INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
247 INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
248 INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
249 INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
250 INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
251 INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
252 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
253 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
254 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
255 INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980),
256 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
257 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
258 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
259 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
260 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
261 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
262 INTC_VECT(PCIINTA, 0x1ce0),
263 INTC_VECT(PCIE, 0x1e00),
264 INTC_VECT(SGPIO, 0x1f80),
265 INTC_VECT(SGPIO, 0x1fa0),
266};
267
268static struct intc_group groups[] __initdata = {
269 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
270 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
271};
272
273static struct intc_mask_reg mask_registers[] __initdata = {
274 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
275 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
276
277 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
278 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
279 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
280 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
281 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
282 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
283 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
284 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
285 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
286
287 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
288 { 0, 0, 0, 0, 0, 0, 0, 0,
289 0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45,
290 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0,
291 HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012
292 } },
293
294 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
295 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
296 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
297 ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I,
298 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
299 } },
300
301 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
302 { IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0,
303 0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
304 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
305 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2
306 } },
307
308 { 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */
309 { 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0,
310 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
311 PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3,
312 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
313 } },
314};
315
316#define INTPRI 0xffd00010
317#define INT2PRI0 0xffd40000
318#define INT2PRI1 0xffd40004
319#define INT2PRI2 0xffd40008
320#define INT2PRI3 0xffd4000c
321#define INT2PRI4 0xffd40010
322#define INT2PRI5 0xffd40014
323#define INT2PRI6 0xffd40018
324#define INT2PRI7 0xffd4001c
325#define INT2PRI8 0xffd400a0
326#define INT2PRI9 0xffd400a4
327#define INT2PRI10 0xffd400a8
328#define INT2PRI11 0xffd400ac
329#define INT2PRI12 0xffd400b0
330#define INT2PRI13 0xffd400b4
331#define INT2PRI14 0xffd400b8
332#define INT2PRI15 0xffd400bc
333#define INT2PRI16 0xffd10000
334#define INT2PRI17 0xffd10004
335#define INT2PRI18 0xffd10008
336#define INT2PRI19 0xffd1000c
337#define INT2PRI20 0xffd10010
338#define INT2PRI21 0xffd10014
339#define INT2PRI22 0xffd10018
340#define INT2PRI23 0xffd1001c
341#define INT2PRI24 0xffd100a0
342#define INT2PRI25 0xffd100a4
343#define INT2PRI26 0xffd100a8
344#define INT2PRI27 0xffd100ac
345#define INT2PRI28 0xffd100b0
346#define INT2PRI29 0xffd100b4
347#define INT2PRI30 0xffd100b8
348#define INT2PRI31 0xffd100bc
349
350static struct intc_prio_reg prio_registers[] __initdata = {
351 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
352 IRQ4, IRQ5, IRQ6, IRQ7 } },
353
354 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
355 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
356 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } },
357 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } },
358 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
359 { INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } },
360 { INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } },
361 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
362 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
363 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
364 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } },
365 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } },
366 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
367 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
368
369 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
370 { INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } },
371 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
372 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
373 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
374 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
375 { INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } },
376 { INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } },
377 { INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } },
378 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
379 { INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } },
380 { INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } },
381 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } },
382 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
383 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } },
384 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
385};
386
387static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
388 mask_registers, prio_registers, NULL);
389
390/* Support for external interrupt pins in IRQ mode */
391static struct intc_vect vectors_irq0123[] __initdata = {
392 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
393 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
394};
395
396static struct intc_vect vectors_irq4567[] __initdata = {
397 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
398 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
399};
400
401static struct intc_sense_reg sense_registers[] __initdata = {
402 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
403 IRQ4, IRQ5, IRQ6, IRQ7 } },
404};
405
406static struct intc_mask_reg ack_registers[] __initdata = {
407 { 0xffd00024, 0, 32, /* INTREQ */
408 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
409};
410
411static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
412 vectors_irq0123, NULL, mask_registers,
413 prio_registers, sense_registers, ack_registers);
414
415static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
416 vectors_irq4567, NULL, mask_registers,
417 prio_registers, sense_registers, ack_registers);
418
419/* External interrupt pins in IRL mode */
420static struct intc_vect vectors_irl0123[] __initdata = {
421 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
422 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
423 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
424 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
425 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
426 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
427 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
428 INTC_VECT(IRL0_HHHL, 0x3c0),
429};
430
431static struct intc_vect vectors_irl4567[] __initdata = {
432 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
433 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
434 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
435 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
436 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
437 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
438 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
439 INTC_VECT(IRL4_HHHL, 0xcc0),
440};
441
442static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
443 NULL, mask_registers, NULL, NULL);
444
445static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
446 NULL, mask_registers, NULL, NULL);
447
448#define INTC_ICR0 0xffd00000
449#define INTC_INTMSK0 0xffd00044
450#define INTC_INTMSK1 0xffd00048
451#define INTC_INTMSK2 0xffd40080
452#define INTC_INTMSKCLR1 0xffd00068
453#define INTC_INTMSKCLR2 0xffd40084
454
455void __init plat_irq_setup(void)
456{
457 /* disable IRQ3-0 + IRQ7-4 */
458 ctrl_outl(0xff000000, INTC_INTMSK0);
459
460 /* disable IRL3-0 + IRL7-4 */
461 ctrl_outl(0xc0000000, INTC_INTMSK1);
462 ctrl_outl(0xfffefffe, INTC_INTMSK2);
463
464 /* select IRL mode for IRL3-0 + IRL7-4 */
465 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
466
467 /* disable holding function, ie enable "SH-4 Mode" */
468 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
469
470 register_intc_controller(&intc_desc);
471}
472
473void __init plat_irq_setup_pins(int mode)
474{
475 switch (mode) {
476 case IRQ_MODE_IRQ7654:
477 /* select IRQ mode for IRL7-4 */
478 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
479 register_intc_controller(&intc_desc_irq4567);
480 break;
481 case IRQ_MODE_IRQ3210:
482 /* select IRQ mode for IRL3-0 */
483 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
484 register_intc_controller(&intc_desc_irq0123);
485 break;
486 case IRQ_MODE_IRL7654:
487 /* enable IRL7-4 but don't provide any masking */
488 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
489 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
490 break;
491 case IRQ_MODE_IRL3210:
492 /* enable IRL0-3 but don't provide any masking */
493 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
494 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
495 break;
496 case IRQ_MODE_IRL7654_MASK:
497 /* enable IRL7-4 and mask using cpu intc controller */
498 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
499 register_intc_controller(&intc_desc_irl4567);
500 break;
501 case IRQ_MODE_IRL3210_MASK:
502 /* enable IRL0-3 and mask using cpu intc controller */
503 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
504 register_intc_controller(&intc_desc_irl0123);
505 break;
506 default:
507 BUG();
508 }
509}
510
511void __init plat_mem_setup(void)
512{
513}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 07f078961c71..e848443deeb9 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -268,11 +268,7 @@ enum {
268 UNUSED = 0, 268 UNUSED = 0,
269 269
270 /* interrupt sources */ 270 /* interrupt sources */
271 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, 271 IRL, IRQ0, IRQ1, IRQ2, IRQ3,
272 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
273 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
274 IRL_HHLL, IRL_HHLH, IRL_HHHL,
275 IRQ0, IRQ1, IRQ2, IRQ3,
276 HUDII, 272 HUDII,
277 TMU0, TMU1, TMU2, TMU3, TMU4, TMU5, 273 TMU0, TMU1, TMU2, TMU3, TMU4, TMU5,
278 PCII0, PCII1, PCII2, PCII3, PCII4, 274 PCII0, PCII1, PCII2, PCII3, PCII4,
@@ -287,10 +283,7 @@ enum {
287 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9, 283 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
288 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE, 284 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
289 IIC, VIN0, VIN1, VCORE0, ATAPI, 285 IIC, VIN0, VIN1, VCORE0, ATAPI,
290 DTU0_TEND, DTU0_AE, DTU0_TMISS, 286 DTU0, DTU1, DTU2, DTU3,
291 DTU1_TEND, DTU1_AE, DTU1_TMISS,
292 DTU2_TEND, DTU2_AE, DTU2_TMISS,
293 DTU3_TEND, DTU3_AE, DTU3_TMISS,
294 FE0, FE1, 287 FE0, FE1,
295 GPIO0, GPIO1, GPIO2, GPIO3, 288 GPIO0, GPIO1, GPIO2, GPIO3,
296 PAM, IRM, 289 PAM, IRM,
@@ -298,8 +291,8 @@ enum {
298 INTICI4, INTICI5, INTICI6, INTICI7, 291 INTICI4, INTICI5, INTICI6, INTICI7,
299 292
300 /* interrupt groups */ 293 /* interrupt groups */
301 IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3, 294 PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
302 DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3, 295 DMAC0, DMAC1,
303}; 296};
304 297
305static struct intc_vect vectors[] __initdata = { 298static struct intc_vect vectors[] __initdata = {
@@ -332,14 +325,14 @@ static struct intc_vect vectors[] __initdata = {
332 INTC_VECT(IIC, 0xae0), 325 INTC_VECT(IIC, 0xae0),
333 INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20), 326 INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
334 INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60), 327 INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
335 INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20), 328 INTC_VECT(DTU0, 0xc00), INTC_VECT(DTU0, 0xc20),
336 INTC_VECT(DTU0_TMISS, 0xc40), 329 INTC_VECT(DTU0, 0xc40),
337 INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80), 330 INTC_VECT(DTU1, 0xc60), INTC_VECT(DTU1, 0xc80),
338 INTC_VECT(DTU1_TMISS, 0xca0), 331 INTC_VECT(DTU1, 0xca0),
339 INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0), 332 INTC_VECT(DTU2, 0xcc0), INTC_VECT(DTU2, 0xce0),
340 INTC_VECT(DTU2_TMISS, 0xd00), 333 INTC_VECT(DTU2, 0xd00),
341 INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40), 334 INTC_VECT(DTU3, 0xd20), INTC_VECT(DTU3, 0xd40),
342 INTC_VECT(DTU3_TMISS, 0xd60), 335 INTC_VECT(DTU3, 0xd60),
343 INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20), 336 INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
344 INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60), 337 INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
345 INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0), 338 INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
@@ -351,10 +344,6 @@ static struct intc_vect vectors[] __initdata = {
351}; 344};
352 345
353static struct intc_group groups[] __initdata = { 346static struct intc_group groups[] __initdata = {
354 INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
355 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
356 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
357 IRL_HHLL, IRL_HHLH, IRL_HHHL),
358 INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9), 347 INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
359 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), 348 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
360 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), 349 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
@@ -364,10 +353,6 @@ static struct intc_group groups[] __initdata = {
364 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE), 353 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
365 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, 354 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
366 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11), 355 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
367 INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS),
368 INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS),
369 INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS),
370 INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
371}; 356};
372 357
373static struct intc_mask_reg mask_registers[] __initdata = { 358static struct intc_mask_reg mask_registers[] __initdata = {
@@ -434,14 +419,14 @@ static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
434 419
435/* External interrupt pins in IRL mode */ 420/* External interrupt pins in IRL mode */
436static struct intc_vect vectors_irl[] __initdata = { 421static struct intc_vect vectors_irl[] __initdata = {
437 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), 422 INTC_VECT(IRL, 0x200), INTC_VECT(IRL, 0x220),
438 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), 423 INTC_VECT(IRL, 0x240), INTC_VECT(IRL, 0x260),
439 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), 424 INTC_VECT(IRL, 0x280), INTC_VECT(IRL, 0x2a0),
440 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), 425 INTC_VECT(IRL, 0x2c0), INTC_VECT(IRL, 0x2e0),
441 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), 426 INTC_VECT(IRL, 0x300), INTC_VECT(IRL, 0x320),
442 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), 427 INTC_VECT(IRL, 0x340), INTC_VECT(IRL, 0x360),
443 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), 428 INTC_VECT(IRL, 0x380), INTC_VECT(IRL, 0x3a0),
444 INTC_VECT(IRL_HHHL, 0x3c0), 429 INTC_VECT(IRL, 0x3c0),
445}; 430};
446 431
447static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups, 432static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
index 2b6b0d50c576..185ec3976a25 100644
--- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
@@ -57,6 +57,8 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
57{ 57{
58 int i; 58 int i;
59 59
60 local_timer_setup(0);
61
60 BUILD_BUG_ON(SMP_MSG_NR >= 8); 62 BUILD_BUG_ON(SMP_MSG_NR >= 8);
61 63
62 for (i = 0; i < SMP_MSG_NR; i++) 64 for (i = 0; i < SMP_MSG_NR; i++)
diff --git a/arch/sh/kernel/cpu/sh5/probe.c b/arch/sh/kernel/cpu/sh5/probe.c
index 92ad844b5c12..521d05b3f7ba 100644
--- a/arch/sh/kernel/cpu/sh5/probe.c
+++ b/arch/sh/kernel/cpu/sh5/probe.c
@@ -34,6 +34,8 @@ int __init detect_cpu_and_cache_system(void)
34 /* CPU.VCR aliased at CIR address on SH5-101 */ 34 /* CPU.VCR aliased at CIR address on SH5-101 */
35 boot_cpu_data.type = CPU_SH5_101; 35 boot_cpu_data.type = CPU_SH5_101;
36 36
37 boot_cpu_data.family = CPU_FAMILY_SH5;
38
37 /* 39 /*
38 * First, setup some sane values for the I-cache. 40 * First, setup some sane values for the I-cache.
39 */ 41 */
diff --git a/arch/sh/kernel/cpu/shmobile/Makefile b/arch/sh/kernel/cpu/shmobile/Makefile
index 08bfa7c7db29..a39f88ea1a85 100644
--- a/arch/sh/kernel/cpu/shmobile/Makefile
+++ b/arch/sh/kernel/cpu/shmobile/Makefile
@@ -4,3 +4,5 @@
4 4
5# Power Management & Sleep mode 5# Power Management & Sleep mode
6obj-$(CONFIG_PM) += pm.o sleep.o 6obj-$(CONFIG_PM) += pm.o sleep.o
7obj-$(CONFIG_CPU_IDLE) += cpuidle.o
8obj-$(CONFIG_PM_RUNTIME) += pm_runtime.o
diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
new file mode 100644
index 000000000000..1c504bd972c3
--- /dev/null
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -0,0 +1,113 @@
1/*
2 * arch/sh/kernel/cpu/shmobile/cpuidle.c
3 *
4 * Cpuidle support code for SuperH Mobile
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/suspend.h>
16#include <linux/cpuidle.h>
17#include <asm/suspend.h>
18#include <asm/uaccess.h>
19#include <asm/hwblk.h>
20
21static unsigned long cpuidle_mode[] = {
22 SUSP_SH_SLEEP, /* regular sleep mode */
23 SUSP_SH_SLEEP | SUSP_SH_SF, /* sleep mode + self refresh */
24 SUSP_SH_STANDBY | SUSP_SH_SF, /* software standby mode + self refresh */
25};
26
27static int cpuidle_sleep_enter(struct cpuidle_device *dev,
28 struct cpuidle_state *state)
29{
30 unsigned long allowed_mode = arch_hwblk_sleep_mode();
31 ktime_t before, after;
32 int requested_state = state - &dev->states[0];
33 int allowed_state;
34 int k;
35
36 /* convert allowed mode to allowed state */
37 for (k = ARRAY_SIZE(cpuidle_mode) - 1; k > 0; k--)
38 if (cpuidle_mode[k] == allowed_mode)
39 break;
40
41 allowed_state = k;
42
43 /* take the following into account for sleep mode selection:
44 * - allowed_state: best mode allowed by hardware (clock deps)
45 * - requested_state: best mode allowed by software (latencies)
46 */
47 k = min_t(int, allowed_state, requested_state);
48
49 dev->last_state = &dev->states[k];
50 before = ktime_get();
51 sh_mobile_call_standby(cpuidle_mode[k]);
52 after = ktime_get();
53 return ktime_to_ns(ktime_sub(after, before)) >> 10;
54}
55
56static struct cpuidle_device cpuidle_dev;
57static struct cpuidle_driver cpuidle_driver = {
58 .name = "sh_idle",
59 .owner = THIS_MODULE,
60};
61
62void sh_mobile_setup_cpuidle(void)
63{
64 struct cpuidle_device *dev = &cpuidle_dev;
65 struct cpuidle_state *state;
66 int i;
67
68 cpuidle_register_driver(&cpuidle_driver);
69
70 for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
71 dev->states[i].name[0] = '\0';
72 dev->states[i].desc[0] = '\0';
73 }
74
75 i = CPUIDLE_DRIVER_STATE_START;
76
77 state = &dev->states[i++];
78 snprintf(state->name, CPUIDLE_NAME_LEN, "C0");
79 strncpy(state->desc, "SuperH Sleep Mode", CPUIDLE_DESC_LEN);
80 state->exit_latency = 1;
81 state->target_residency = 1 * 2;
82 state->power_usage = 3;
83 state->flags = 0;
84 state->flags |= CPUIDLE_FLAG_SHALLOW;
85 state->flags |= CPUIDLE_FLAG_TIME_VALID;
86 state->enter = cpuidle_sleep_enter;
87
88 dev->safe_state = state;
89
90 state = &dev->states[i++];
91 snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
92 strncpy(state->desc, "SuperH Sleep Mode [SF]", CPUIDLE_DESC_LEN);
93 state->exit_latency = 100;
94 state->target_residency = 1 * 2;
95 state->power_usage = 1;
96 state->flags = 0;
97 state->flags |= CPUIDLE_FLAG_TIME_VALID;
98 state->enter = cpuidle_sleep_enter;
99
100 state = &dev->states[i++];
101 snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
102 strncpy(state->desc, "SuperH Mobile Standby Mode [SF]", CPUIDLE_DESC_LEN);
103 state->exit_latency = 2300;
104 state->target_residency = 1 * 2;
105 state->power_usage = 1;
106 state->flags = 0;
107 state->flags |= CPUIDLE_FLAG_TIME_VALID;
108 state->enter = cpuidle_sleep_enter;
109
110 dev->state_count = i;
111
112 cpuidle_register_device(dev);
113}
diff --git a/arch/sh/kernel/cpu/shmobile/pm.c b/arch/sh/kernel/cpu/shmobile/pm.c
index 8c067adf6830..ee3c2aaf66fb 100644
--- a/arch/sh/kernel/cpu/shmobile/pm.c
+++ b/arch/sh/kernel/cpu/shmobile/pm.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/sh/kernel/cpu/sh4a/pm-sh_mobile.c 2 * arch/sh/kernel/cpu/shmobile/pm.c
3 * 3 *
4 * Power management support code for SuperH Mobile 4 * Power management support code for SuperH Mobile
5 * 5 *
@@ -32,40 +32,20 @@
32 * 32 *
33 * R-standby mode is unsupported, but will be added in the future 33 * R-standby mode is unsupported, but will be added in the future
34 * U-standby mode is low priority since it needs bootloader hacks 34 * U-standby mode is low priority since it needs bootloader hacks
35 *
36 * All modes should be tied in with cpuidle. But before that can
37 * happen we need to keep track of enabled hardware blocks so we
38 * can avoid entering sleep modes that stop clocks to hardware
39 * blocks that are in use even though the cpu core is idle.
40 */ 35 */
41 36
37#define ILRAM_BASE 0xe5200000
38
42extern const unsigned char sh_mobile_standby[]; 39extern const unsigned char sh_mobile_standby[];
43extern const unsigned int sh_mobile_standby_size; 40extern const unsigned int sh_mobile_standby_size;
44 41
45static void sh_mobile_call_standby(unsigned long mode) 42void sh_mobile_call_standby(unsigned long mode)
46{ 43{
47 extern void *vbr_base; 44 void *onchip_mem = (void *)ILRAM_BASE;
48 void *onchip_mem = (void *)0xe5200000; /* ILRAM */ 45 void (*standby_onchip_mem)(unsigned long, unsigned long) = onchip_mem;
49 void (*standby_onchip_mem)(unsigned long) = onchip_mem;
50
51 /* Note: Wake up from sleep may generate exceptions!
52 * Setup VBR to point to on-chip ram if self-refresh is
53 * going to be used.
54 */
55 if (mode & SUSP_SH_SF)
56 asm volatile("ldc %0, vbr" : : "r" (onchip_mem) : "memory");
57
58 /* Copy the assembly snippet to the otherwise ununsed ILRAM */
59 memcpy(onchip_mem, sh_mobile_standby, sh_mobile_standby_size);
60 wmb();
61 ctrl_barrier();
62 46
63 /* Let assembly snippet in on-chip memory handle the rest */ 47 /* Let assembly snippet in on-chip memory handle the rest */
64 standby_onchip_mem(mode); 48 standby_onchip_mem(mode, ILRAM_BASE);
65
66 /* Put VBR back in System RAM again */
67 if (mode & SUSP_SH_SF)
68 asm volatile("ldc %0, vbr" : : "r" (&vbr_base) : "memory");
69} 49}
70 50
71static int sh_pm_enter(suspend_state_t state) 51static int sh_pm_enter(suspend_state_t state)
@@ -85,7 +65,15 @@ static struct platform_suspend_ops sh_pm_ops = {
85 65
86static int __init sh_pm_init(void) 66static int __init sh_pm_init(void)
87{ 67{
68 void *onchip_mem = (void *)ILRAM_BASE;
69
70 /* Copy the assembly snippet to the otherwise ununsed ILRAM */
71 memcpy(onchip_mem, sh_mobile_standby, sh_mobile_standby_size);
72 wmb();
73 ctrl_barrier();
74
88 suspend_set_ops(&sh_pm_ops); 75 suspend_set_ops(&sh_pm_ops);
76 sh_mobile_setup_cpuidle();
89 return 0; 77 return 0;
90} 78}
91 79
diff --git a/arch/sh/kernel/cpu/shmobile/pm_runtime.c b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
new file mode 100644
index 000000000000..7c615b17e209
--- /dev/null
+++ b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
@@ -0,0 +1,303 @@
1/*
2 * arch/sh/kernel/cpu/shmobile/pm_runtime.c
3 *
4 * Runtime PM support code for SuperH Mobile
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/pm_runtime.h>
16#include <linux/platform_device.h>
17#include <linux/mutex.h>
18#include <asm/hwblk.h>
19
20static DEFINE_SPINLOCK(hwblk_lock);
21static LIST_HEAD(hwblk_idle_list);
22static struct work_struct hwblk_work;
23
24extern struct hwblk_info *hwblk_info;
25
26static void platform_pm_runtime_not_idle(struct platform_device *pdev)
27{
28 unsigned long flags;
29
30 /* remove device from idle list */
31 spin_lock_irqsave(&hwblk_lock, flags);
32 if (test_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags)) {
33 list_del(&pdev->archdata.entry);
34 __clear_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags);
35 }
36 spin_unlock_irqrestore(&hwblk_lock, flags);
37}
38
39static int __platform_pm_runtime_resume(struct platform_device *pdev)
40{
41 struct device *d = &pdev->dev;
42 struct pdev_archdata *ad = &pdev->archdata;
43 int hwblk = ad->hwblk_id;
44 int ret = -ENOSYS;
45
46 dev_dbg(d, "__platform_pm_runtime_resume() [%d]\n", hwblk);
47
48 if (d->driver && d->driver->pm && d->driver->pm->runtime_resume) {
49 hwblk_enable(hwblk_info, hwblk);
50 ret = 0;
51
52 if (test_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags)) {
53 ret = d->driver->pm->runtime_resume(d);
54 if (!ret)
55 clear_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
56 else
57 hwblk_disable(hwblk_info, hwblk);
58 }
59 }
60
61 dev_dbg(d, "__platform_pm_runtime_resume() [%d] - returns %d\n",
62 hwblk, ret);
63
64 return ret;
65}
66
67static int __platform_pm_runtime_suspend(struct platform_device *pdev)
68{
69 struct device *d = &pdev->dev;
70 struct pdev_archdata *ad = &pdev->archdata;
71 int hwblk = ad->hwblk_id;
72 int ret = -ENOSYS;
73
74 dev_dbg(d, "__platform_pm_runtime_suspend() [%d]\n", hwblk);
75
76 if (d->driver && d->driver->pm && d->driver->pm->runtime_suspend) {
77 BUG_ON(!test_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags));
78
79 hwblk_enable(hwblk_info, hwblk);
80 ret = d->driver->pm->runtime_suspend(d);
81 hwblk_disable(hwblk_info, hwblk);
82
83 if (!ret) {
84 set_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
85 platform_pm_runtime_not_idle(pdev);
86 hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE);
87 }
88 }
89
90 dev_dbg(d, "__platform_pm_runtime_suspend() [%d] - returns %d\n",
91 hwblk, ret);
92
93 return ret;
94}
95
96static void platform_pm_runtime_work(struct work_struct *work)
97{
98 struct platform_device *pdev;
99 unsigned long flags;
100 int ret;
101
102 /* go through the idle list and suspend one device at a time */
103 do {
104 spin_lock_irqsave(&hwblk_lock, flags);
105 if (list_empty(&hwblk_idle_list))
106 pdev = NULL;
107 else
108 pdev = list_first_entry(&hwblk_idle_list,
109 struct platform_device,
110 archdata.entry);
111 spin_unlock_irqrestore(&hwblk_lock, flags);
112
113 if (pdev) {
114 mutex_lock(&pdev->archdata.mutex);
115 ret = __platform_pm_runtime_suspend(pdev);
116
117 /* at this point the platform device may be:
118 * suspended: ret = 0, FLAG_SUSP set, clock stopped
119 * failed: ret < 0, FLAG_IDLE set, clock stopped
120 */
121 mutex_unlock(&pdev->archdata.mutex);
122 } else {
123 ret = -ENODEV;
124 }
125 } while (!ret);
126}
127
128/* this function gets called from cpuidle context when all devices in the
129 * main power domain are unused but some are counted as idle, ie the hwblk
130 * counter values are (HWBLK_CNT_USAGE == 0) && (HWBLK_CNT_IDLE != 0)
131 */
132void platform_pm_runtime_suspend_idle(void)
133{
134 queue_work(pm_wq, &hwblk_work);
135}
136
137int platform_pm_runtime_suspend(struct device *dev)
138{
139 struct platform_device *pdev = to_platform_device(dev);
140 struct pdev_archdata *ad = &pdev->archdata;
141 unsigned long flags;
142 int hwblk = ad->hwblk_id;
143 int ret = 0;
144
145 dev_dbg(dev, "platform_pm_runtime_suspend() [%d]\n", hwblk);
146
147 /* ignore off-chip platform devices */
148 if (!hwblk)
149 goto out;
150
151 /* interrupt context not allowed */
152 might_sleep();
153
154 /* catch misconfigured drivers not starting with resume */
155 if (test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags)) {
156 ret = -EINVAL;
157 goto out;
158 }
159
160 /* serialize */
161 mutex_lock(&ad->mutex);
162
163 /* disable clock */
164 hwblk_disable(hwblk_info, hwblk);
165
166 /* put device on idle list */
167 spin_lock_irqsave(&hwblk_lock, flags);
168 list_add_tail(&pdev->archdata.entry, &hwblk_idle_list);
169 __set_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags);
170 spin_unlock_irqrestore(&hwblk_lock, flags);
171
172 /* increase idle count */
173 hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_IDLE);
174
175 /* at this point the platform device is:
176 * idle: ret = 0, FLAG_IDLE set, clock stopped
177 */
178 mutex_unlock(&ad->mutex);
179
180out:
181 dev_dbg(dev, "platform_pm_runtime_suspend() [%d] returns %d\n",
182 hwblk, ret);
183
184 return ret;
185}
186
187int platform_pm_runtime_resume(struct device *dev)
188{
189 struct platform_device *pdev = to_platform_device(dev);
190 struct pdev_archdata *ad = &pdev->archdata;
191 int hwblk = ad->hwblk_id;
192 int ret = 0;
193
194 dev_dbg(dev, "platform_pm_runtime_resume() [%d]\n", hwblk);
195
196 /* ignore off-chip platform devices */
197 if (!hwblk)
198 goto out;
199
200 /* interrupt context not allowed */
201 might_sleep();
202
203 /* serialize */
204 mutex_lock(&ad->mutex);
205
206 /* make sure device is removed from idle list */
207 platform_pm_runtime_not_idle(pdev);
208
209 /* decrease idle count */
210 if (!test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags) &&
211 !test_bit(PDEV_ARCHDATA_FLAG_SUSP, &pdev->archdata.flags))
212 hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE);
213
214 /* resume the device if needed */
215 ret = __platform_pm_runtime_resume(pdev);
216
217 /* the driver has been initialized now, so clear the init flag */
218 clear_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
219
220 /* at this point the platform device may be:
221 * resumed: ret = 0, flags = 0, clock started
222 * failed: ret < 0, FLAG_SUSP set, clock stopped
223 */
224 mutex_unlock(&ad->mutex);
225out:
226 dev_dbg(dev, "platform_pm_runtime_resume() [%d] returns %d\n",
227 hwblk, ret);
228
229 return ret;
230}
231
232int platform_pm_runtime_idle(struct device *dev)
233{
234 struct platform_device *pdev = to_platform_device(dev);
235 int hwblk = pdev->archdata.hwblk_id;
236 int ret = 0;
237
238 dev_dbg(dev, "platform_pm_runtime_idle() [%d]\n", hwblk);
239
240 /* ignore off-chip platform devices */
241 if (!hwblk)
242 goto out;
243
244 /* interrupt context not allowed, use pm_runtime_put()! */
245 might_sleep();
246
247 /* suspend synchronously to disable clocks immediately */
248 ret = pm_runtime_suspend(dev);
249out:
250 dev_dbg(dev, "platform_pm_runtime_idle() [%d] done!\n", hwblk);
251 return ret;
252}
253
254static int platform_bus_notify(struct notifier_block *nb,
255 unsigned long action, void *data)
256{
257 struct device *dev = data;
258 struct platform_device *pdev = to_platform_device(dev);
259 int hwblk = pdev->archdata.hwblk_id;
260
261 /* ignore off-chip platform devices */
262 if (!hwblk)
263 return 0;
264
265 switch (action) {
266 case BUS_NOTIFY_ADD_DEVICE:
267 INIT_LIST_HEAD(&pdev->archdata.entry);
268 mutex_init(&pdev->archdata.mutex);
269 /* platform devices without drivers should be disabled */
270 hwblk_enable(hwblk_info, hwblk);
271 hwblk_disable(hwblk_info, hwblk);
272 /* make sure driver re-inits itself once */
273 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
274 break;
275 /* TODO: add BUS_NOTIFY_BIND_DRIVER and increase idle count */
276 case BUS_NOTIFY_BOUND_DRIVER:
277 /* keep track of number of devices in use per hwblk */
278 hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_DEVICES);
279 break;
280 case BUS_NOTIFY_UNBOUND_DRIVER:
281 /* keep track of number of devices in use per hwblk */
282 hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_DEVICES);
283 /* make sure driver re-inits itself once */
284 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
285 break;
286 case BUS_NOTIFY_DEL_DEVICE:
287 break;
288 }
289 return 0;
290}
291
292static struct notifier_block platform_bus_notifier = {
293 .notifier_call = platform_bus_notify
294};
295
296static int __init sh_pm_runtime_init(void)
297{
298 INIT_WORK(&hwblk_work, platform_pm_runtime_work);
299
300 bus_register_notifier(&platform_bus_type, &platform_bus_notifier);
301 return 0;
302}
303core_initcall(sh_pm_runtime_init);
diff --git a/arch/sh/kernel/cpu/shmobile/sleep.S b/arch/sh/kernel/cpu/shmobile/sleep.S
index baf2d7d46b05..a439e6c7824f 100644
--- a/arch/sh/kernel/cpu/shmobile/sleep.S
+++ b/arch/sh/kernel/cpu/shmobile/sleep.S
@@ -16,19 +16,52 @@
16#include <asm/asm-offsets.h> 16#include <asm/asm-offsets.h>
17#include <asm/suspend.h> 17#include <asm/suspend.h>
18 18
19/*
20 * Kernel mode register usage, see entry.S:
21 * k0 scratch
22 * k1 scratch
23 * k4 scratch
24 */
25#define k0 r0
26#define k1 r1
27#define k4 r4
28
19/* manage self-refresh and enter standby mode. 29/* manage self-refresh and enter standby mode.
20 * this code will be copied to on-chip memory and executed from there. 30 * this code will be copied to on-chip memory and executed from there.
21 */ 31 */
22 32
23 .balign 4096,0,4096 33 .balign 4096,0,4096
24ENTRY(sh_mobile_standby) 34ENTRY(sh_mobile_standby)
35
36 /* save original vbr */
37 stc vbr, r1
38 mova saved_vbr, r0
39 mov.l r1, @r0
40
41 /* point vbr to our on-chip memory page */
42 ldc r5, vbr
43
44 /* save return address */
45 mova saved_spc, r0
46 sts pr, r5
47 mov.l r5, @r0
48
49 /* save sr */
50 mova saved_sr, r0
51 stc sr, r5
52 mov.l r5, @r0
53
54 /* save mode flags */
55 mova saved_mode, r0
56 mov.l r4, @r0
57
58 /* put mode flags in r0 */
25 mov r4, r0 59 mov r4, r0
26 60
27 tst #SUSP_SH_SF, r0 61 tst #SUSP_SH_SF, r0
28 bt skip_set_sf 62 bt skip_set_sf
29#ifdef CONFIG_CPU_SUBTYPE_SH7724 63#ifdef CONFIG_CPU_SUBTYPE_SH7724
30 /* DBSC: put memory in self-refresh mode */ 64 /* DBSC: put memory in self-refresh mode */
31
32 mov.l dben_reg, r4 65 mov.l dben_reg, r4
33 mov.l dben_data0, r1 66 mov.l dben_data0, r1
34 mov.l r1, @r4 67 mov.l r1, @r4
@@ -60,14 +93,6 @@ ENTRY(sh_mobile_standby)
60#endif 93#endif
61 94
62skip_set_sf: 95skip_set_sf:
63 tst #SUSP_SH_SLEEP, r0
64 bt test_standby
65
66 /* set mode to "sleep mode" */
67 bra do_sleep
68 mov #0x00, r1
69
70test_standby:
71 tst #SUSP_SH_STANDBY, r0 96 tst #SUSP_SH_STANDBY, r0
72 bt test_rstandby 97 bt test_rstandby
73 98
@@ -85,77 +110,107 @@ test_rstandby:
85 110
86test_ustandby: 111test_ustandby:
87 tst #SUSP_SH_USTANDBY, r0 112 tst #SUSP_SH_USTANDBY, r0
88 bt done_sleep 113 bt force_sleep
89 114
90 /* set mode to "u-standby mode" */ 115 /* set mode to "u-standby mode" */
91 mov #0x10, r1 116 bra do_sleep
117 mov #0x10, r1
92 118
93 /* fall-through */ 119force_sleep:
120
121 /* set mode to "sleep mode" */
122 mov #0x00, r1
94 123
95do_sleep: 124do_sleep:
96 /* setup and enter selected standby mode */ 125 /* setup and enter selected standby mode */
97 mov.l 5f, r4 126 mov.l 5f, r4
98 mov.l r1, @r4 127 mov.l r1, @r4
128again:
99 sleep 129 sleep
130 bra again
131 nop
132
133restore_jump_vbr:
134 /* setup spc with return address to c code */
135 mov.l saved_spc, k0
136 ldc k0, spc
137
138 /* restore vbr */
139 mov.l saved_vbr, k0
140 ldc k0, vbr
141
142 /* setup ssr with saved sr */
143 mov.l saved_sr, k0
144 ldc k0, ssr
145
146 /* get mode flags */
147 mov.l saved_mode, k0
100 148
101done_sleep: 149done_sleep:
102 /* reset standby mode to sleep mode */ 150 /* reset standby mode to sleep mode */
103 mov.l 5f, r4 151 mov.l 5f, k4
104 mov #0x00, r1 152 mov #0x00, k1
105 mov.l r1, @r4 153 mov.l k1, @k4
106 154
107 tst #SUSP_SH_SF, r0 155 tst #SUSP_SH_SF, k0
108 bt skip_restore_sf 156 bt skip_restore_sf
109 157
110#ifdef CONFIG_CPU_SUBTYPE_SH7724 158#ifdef CONFIG_CPU_SUBTYPE_SH7724
111 /* DBSC: put memory in auto-refresh mode */ 159 /* DBSC: put memory in auto-refresh mode */
160 mov.l dbrfpdn0_reg, k4
161 mov.l dbrfpdn0_data0, k1
162 mov.l k1, @k4
112 163
113 mov.l dbrfpdn0_reg, r4 164 nop /* sleep 140 ns */
114 mov.l dbrfpdn0_data0, r1
115 mov.l r1, @r4
116
117 /* sleep 140 ns */
118 nop
119 nop 165 nop
120 nop 166 nop
121 nop 167 nop
122 168
123 mov.l dbcmdcnt_reg, r4 169 mov.l dbcmdcnt_reg, k4
124 mov.l dbcmdcnt_data0, r1 170 mov.l dbcmdcnt_data0, k1
125 mov.l r1, @r4 171 mov.l k1, @k4
126 172
127 mov.l dbcmdcnt_reg, r4 173 mov.l dbcmdcnt_reg, k4
128 mov.l dbcmdcnt_data1, r1 174 mov.l dbcmdcnt_data1, k1
129 mov.l r1, @r4 175 mov.l k1, @k4
130 176
131 mov.l dben_reg, r4 177 mov.l dben_reg, k4
132 mov.l dben_data1, r1 178 mov.l dben_data1, k1
133 mov.l r1, @r4 179 mov.l k1, @k4
134 180
135 mov.l dbrfpdn0_reg, r4 181 mov.l dbrfpdn0_reg, k4
136 mov.l dbrfpdn0_data2, r1 182 mov.l dbrfpdn0_data2, k1
137 mov.l r1, @r4 183 mov.l k1, @k4
138#else 184#else
139 /* SBSC: set auto-refresh mode */ 185 /* SBSC: set auto-refresh mode */
140 mov.l 1f, r4 186 mov.l 1f, k4
141 mov.l @r4, r2 187 mov.l @k4, k0
142 mov.l 4f, r3 188 mov.l 4f, k1
143 and r3, r2 189 and k1, k0
144 mov.l r2, @r4 190 mov.l k0, @k4
145 mov.l 6f, r4 191 mov.l 6f, k4
146 mov.l 7f, r1 192 mov.l 8f, k0
147 mov.l 8f, r2 193 mov.l @k4, k1
148 mov.l @r4, r3 194 mov #-1, k4
149 mov #-1, r4 195 add k4, k1
150 add r4, r3 196 or k1, k0
151 or r2, r3 197 mov.l 7f, k1
152 mov.l r3, @r1 198 mov.l k0, @k1
153#endif 199#endif
154skip_restore_sf: 200skip_restore_sf:
155 rts 201 /* jump to vbr vector */
202 mov.l saved_vbr, k0
203 mov.l offset_vbr, k4
204 add k4, k0
205 jmp @k0
156 nop 206 nop
157 207
158 .balign 4 208 .balign 4
209saved_mode: .long 0
210saved_spc: .long 0
211saved_sr: .long 0
212saved_vbr: .long 0
213offset_vbr: .long 0x600
159#ifdef CONFIG_CPU_SUBTYPE_SH7724 214#ifdef CONFIG_CPU_SUBTYPE_SH7724
160dben_reg: .long 0xfd000010 /* DBEN */ 215dben_reg: .long 0xfd000010 /* DBEN */
161dben_data0: .long 0 216dben_data0: .long 0
@@ -178,12 +233,12 @@ dbcmdcnt_data1: .long 4
1787: .long 0xfe400018 /* RTCNT */ 2337: .long 0xfe400018 /* RTCNT */
1798: .long 0xa55a0000 2348: .long 0xa55a0000
180 235
236
181/* interrupt vector @ 0x600 */ 237/* interrupt vector @ 0x600 */
182 .balign 0x400,0,0x400 238 .balign 0x400,0,0x400
183 .long 0xdeadbeef 239 .long 0xdeadbeef
184 .balign 0x200,0,0x200 240 .balign 0x200,0,0x200
185 /* sh7722 will end up here in sleep mode */ 241 bra restore_jump_vbr
186 rte
187 nop 242 nop
188sh_mobile_standby_end: 243sh_mobile_standby_end:
189 244
diff --git a/arch/sh/kernel/cpufreq.c b/arch/sh/kernel/cpufreq.c
index e0590ffebd73..dce4f3ff0932 100644
--- a/arch/sh/kernel/cpufreq.c
+++ b/arch/sh/kernel/cpufreq.c
@@ -82,7 +82,8 @@ static int sh_cpufreq_cpu_init(struct cpufreq_policy *policy)
82 82
83 cpuclk = clk_get(NULL, "cpu_clk"); 83 cpuclk = clk_get(NULL, "cpu_clk");
84 if (IS_ERR(cpuclk)) { 84 if (IS_ERR(cpuclk)) {
85 printk(KERN_ERR "cpufreq: couldn't get CPU clk\n"); 85 printk(KERN_ERR "cpufreq: couldn't get CPU#%d clk\n",
86 policy->cpu);
86 return PTR_ERR(cpuclk); 87 return PTR_ERR(cpuclk);
87 } 88 }
88 89
@@ -95,22 +96,21 @@ static int sh_cpufreq_cpu_init(struct cpufreq_policy *policy)
95 policy->min = policy->cpuinfo.min_freq; 96 policy->min = policy->cpuinfo.min_freq;
96 policy->max = policy->cpuinfo.max_freq; 97 policy->max = policy->cpuinfo.max_freq;
97 98
98
99 /* 99 /*
100 * Catch the cases where the clock framework hasn't been wired up 100 * Catch the cases where the clock framework hasn't been wired up
101 * properly to support scaling. 101 * properly to support scaling.
102 */ 102 */
103 if (unlikely(policy->min == policy->max)) { 103 if (unlikely(policy->min == policy->max)) {
104 printk(KERN_ERR "cpufreq: clock framework rate rounding " 104 printk(KERN_ERR "cpufreq: clock framework rate rounding "
105 "not supported on this CPU.\n"); 105 "not supported on CPU#%d.\n", policy->cpu);
106 106
107 clk_put(cpuclk); 107 clk_put(cpuclk);
108 return -EINVAL; 108 return -EINVAL;
109 } 109 }
110 110
111 printk(KERN_INFO "cpufreq: Frequencies - Minimum %u.%03u MHz, " 111 printk(KERN_INFO "cpufreq: CPU#%d Frequencies - Minimum %u.%03u MHz, "
112 "Maximum %u.%03u MHz.\n", 112 "Maximum %u.%03u MHz.\n",
113 policy->min / 1000, policy->min % 1000, 113 policy->cpu, policy->min / 1000, policy->min % 1000,
114 policy->max / 1000, policy->max % 1000); 114 policy->max / 1000, policy->max % 1000);
115 115
116 return 0; 116 return 0;
diff --git a/arch/sh/kernel/dumpstack.c b/arch/sh/kernel/dumpstack.c
new file mode 100644
index 000000000000..6f5ad1513409
--- /dev/null
+++ b/arch/sh/kernel/dumpstack.c
@@ -0,0 +1,123 @@
1/*
2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 * Copyright (C) 2009 Matt Fleming
5 */
6#include <linux/kallsyms.h>
7#include <linux/ftrace.h>
8#include <linux/debug_locks.h>
9#include <asm/unwinder.h>
10#include <asm/stacktrace.h>
11
12void printk_address(unsigned long address, int reliable)
13{
14 printk(" [<%p>] %s%pS\n", (void *) address,
15 reliable ? "" : "? ", (void *) address);
16}
17
18#ifdef CONFIG_FUNCTION_GRAPH_TRACER
19static void
20print_ftrace_graph_addr(unsigned long addr, void *data,
21 const struct stacktrace_ops *ops,
22 struct thread_info *tinfo, int *graph)
23{
24 struct task_struct *task = tinfo->task;
25 unsigned long ret_addr;
26 int index = task->curr_ret_stack;
27
28 if (addr != (unsigned long)return_to_handler)
29 return;
30
31 if (!task->ret_stack || index < *graph)
32 return;
33
34 index -= *graph;
35 ret_addr = task->ret_stack[index].ret;
36
37 ops->address(data, ret_addr, 1);
38
39 (*graph)++;
40}
41#else
42static inline void
43print_ftrace_graph_addr(unsigned long addr, void *data,
44 const struct stacktrace_ops *ops,
45 struct thread_info *tinfo, int *graph)
46{ }
47#endif
48
49void
50stack_reader_dump(struct task_struct *task, struct pt_regs *regs,
51 unsigned long *sp, const struct stacktrace_ops *ops,
52 void *data)
53{
54 struct thread_info *context;
55 int graph = 0;
56
57 context = (struct thread_info *)
58 ((unsigned long)sp & (~(THREAD_SIZE - 1)));
59
60 while (!kstack_end(sp)) {
61 unsigned long addr = *sp++;
62
63 if (__kernel_text_address(addr)) {
64 ops->address(data, addr, 1);
65
66 print_ftrace_graph_addr(addr, data, ops,
67 context, &graph);
68 }
69 }
70}
71
72static void
73print_trace_warning_symbol(void *data, char *msg, unsigned long symbol)
74{
75 printk(data);
76 print_symbol(msg, symbol);
77 printk("\n");
78}
79
80static void print_trace_warning(void *data, char *msg)
81{
82 printk("%s%s\n", (char *)data, msg);
83}
84
85static int print_trace_stack(void *data, char *name)
86{
87 printk("%s <%s> ", (char *)data, name);
88 return 0;
89}
90
91/*
92 * Print one address/symbol entries per line.
93 */
94static void print_trace_address(void *data, unsigned long addr, int reliable)
95{
96 printk(data);
97 printk_address(addr, reliable);
98}
99
100static const struct stacktrace_ops print_trace_ops = {
101 .warning = print_trace_warning,
102 .warning_symbol = print_trace_warning_symbol,
103 .stack = print_trace_stack,
104 .address = print_trace_address,
105};
106
107void show_trace(struct task_struct *tsk, unsigned long *sp,
108 struct pt_regs *regs)
109{
110 if (regs && user_mode(regs))
111 return;
112
113 printk("\nCall trace:\n");
114
115 unwind_stack(tsk, regs, sp, &print_trace_ops, "");
116
117 printk("\n");
118
119 if (!tsk)
120 tsk = current;
121
122 debug_show_held_locks(tsk);
123}
diff --git a/arch/sh/kernel/dwarf.c b/arch/sh/kernel/dwarf.c
new file mode 100644
index 000000000000..bc4d8d75332b
--- /dev/null
+++ b/arch/sh/kernel/dwarf.c
@@ -0,0 +1,972 @@
1/*
2 * Copyright (C) 2009 Matt Fleming <matt@console-pimps.org>
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * This is an implementation of a DWARF unwinder. Its main purpose is
9 * for generating stacktrace information. Based on the DWARF 3
10 * specification from http://www.dwarfstd.org.
11 *
12 * TODO:
13 * - DWARF64 doesn't work.
14 * - Registers with DWARF_VAL_OFFSET rules aren't handled properly.
15 */
16
17/* #define DEBUG */
18#include <linux/kernel.h>
19#include <linux/io.h>
20#include <linux/list.h>
21#include <linux/mempool.h>
22#include <linux/mm.h>
23#include <asm/dwarf.h>
24#include <asm/unwinder.h>
25#include <asm/sections.h>
26#include <asm/unaligned.h>
27#include <asm/dwarf.h>
28#include <asm/stacktrace.h>
29
30/* Reserve enough memory for two stack frames */
31#define DWARF_FRAME_MIN_REQ 2
32/* ... with 4 registers per frame. */
33#define DWARF_REG_MIN_REQ (DWARF_FRAME_MIN_REQ * 4)
34
35static struct kmem_cache *dwarf_frame_cachep;
36static mempool_t *dwarf_frame_pool;
37
38static struct kmem_cache *dwarf_reg_cachep;
39static mempool_t *dwarf_reg_pool;
40
41static LIST_HEAD(dwarf_cie_list);
42static DEFINE_SPINLOCK(dwarf_cie_lock);
43
44static LIST_HEAD(dwarf_fde_list);
45static DEFINE_SPINLOCK(dwarf_fde_lock);
46
47static struct dwarf_cie *cached_cie;
48
49/**
50 * dwarf_frame_alloc_reg - allocate memory for a DWARF register
51 * @frame: the DWARF frame whose list of registers we insert on
52 * @reg_num: the register number
53 *
54 * Allocate space for, and initialise, a dwarf reg from
55 * dwarf_reg_pool and insert it onto the (unsorted) linked-list of
56 * dwarf registers for @frame.
57 *
58 * Return the initialised DWARF reg.
59 */
60static struct dwarf_reg *dwarf_frame_alloc_reg(struct dwarf_frame *frame,
61 unsigned int reg_num)
62{
63 struct dwarf_reg *reg;
64
65 reg = mempool_alloc(dwarf_reg_pool, GFP_ATOMIC);
66 if (!reg) {
67 printk(KERN_WARNING "Unable to allocate a DWARF register\n");
68 /*
69 * Let's just bomb hard here, we have no way to
70 * gracefully recover.
71 */
72 UNWINDER_BUG();
73 }
74
75 reg->number = reg_num;
76 reg->addr = 0;
77 reg->flags = 0;
78
79 list_add(&reg->link, &frame->reg_list);
80
81 return reg;
82}
83
84static void dwarf_frame_free_regs(struct dwarf_frame *frame)
85{
86 struct dwarf_reg *reg, *n;
87
88 list_for_each_entry_safe(reg, n, &frame->reg_list, link) {
89 list_del(&reg->link);
90 mempool_free(reg, dwarf_reg_pool);
91 }
92}
93
94/**
95 * dwarf_frame_reg - return a DWARF register
96 * @frame: the DWARF frame to search in for @reg_num
97 * @reg_num: the register number to search for
98 *
99 * Lookup and return the dwarf reg @reg_num for this frame. Return
100 * NULL if @reg_num is an register invalid number.
101 */
102static struct dwarf_reg *dwarf_frame_reg(struct dwarf_frame *frame,
103 unsigned int reg_num)
104{
105 struct dwarf_reg *reg;
106
107 list_for_each_entry(reg, &frame->reg_list, link) {
108 if (reg->number == reg_num)
109 return reg;
110 }
111
112 return NULL;
113}
114
115/**
116 * dwarf_read_addr - read dwarf data
117 * @src: source address of data
118 * @dst: destination address to store the data to
119 *
120 * Read 'n' bytes from @src, where 'n' is the size of an address on
121 * the native machine. We return the number of bytes read, which
122 * should always be 'n'. We also have to be careful when reading
123 * from @src and writing to @dst, because they can be arbitrarily
124 * aligned. Return 'n' - the number of bytes read.
125 */
126static inline int dwarf_read_addr(unsigned long *src, unsigned long *dst)
127{
128 u32 val = get_unaligned(src);
129 put_unaligned(val, dst);
130 return sizeof(unsigned long *);
131}
132
133/**
134 * dwarf_read_uleb128 - read unsigned LEB128 data
135 * @addr: the address where the ULEB128 data is stored
136 * @ret: address to store the result
137 *
138 * Decode an unsigned LEB128 encoded datum. The algorithm is taken
139 * from Appendix C of the DWARF 3 spec. For information on the
140 * encodings refer to section "7.6 - Variable Length Data". Return
141 * the number of bytes read.
142 */
143static inline unsigned long dwarf_read_uleb128(char *addr, unsigned int *ret)
144{
145 unsigned int result;
146 unsigned char byte;
147 int shift, count;
148
149 result = 0;
150 shift = 0;
151 count = 0;
152
153 while (1) {
154 byte = __raw_readb(addr);
155 addr++;
156 count++;
157
158 result |= (byte & 0x7f) << shift;
159 shift += 7;
160
161 if (!(byte & 0x80))
162 break;
163 }
164
165 *ret = result;
166
167 return count;
168}
169
170/**
171 * dwarf_read_leb128 - read signed LEB128 data
172 * @addr: the address of the LEB128 encoded data
173 * @ret: address to store the result
174 *
175 * Decode signed LEB128 data. The algorithm is taken from Appendix
176 * C of the DWARF 3 spec. Return the number of bytes read.
177 */
178static inline unsigned long dwarf_read_leb128(char *addr, int *ret)
179{
180 unsigned char byte;
181 int result, shift;
182 int num_bits;
183 int count;
184
185 result = 0;
186 shift = 0;
187 count = 0;
188
189 while (1) {
190 byte = __raw_readb(addr);
191 addr++;
192 result |= (byte & 0x7f) << shift;
193 shift += 7;
194 count++;
195
196 if (!(byte & 0x80))
197 break;
198 }
199
200 /* The number of bits in a signed integer. */
201 num_bits = 8 * sizeof(result);
202
203 if ((shift < num_bits) && (byte & 0x40))
204 result |= (-1 << shift);
205
206 *ret = result;
207
208 return count;
209}
210
211/**
212 * dwarf_read_encoded_value - return the decoded value at @addr
213 * @addr: the address of the encoded value
214 * @val: where to write the decoded value
215 * @encoding: the encoding with which we can decode @addr
216 *
217 * GCC emits encoded address in the .eh_frame FDE entries. Decode
218 * the value at @addr using @encoding. The decoded value is written
219 * to @val and the number of bytes read is returned.
220 */
221static int dwarf_read_encoded_value(char *addr, unsigned long *val,
222 char encoding)
223{
224 unsigned long decoded_addr = 0;
225 int count = 0;
226
227 switch (encoding & 0x70) {
228 case DW_EH_PE_absptr:
229 break;
230 case DW_EH_PE_pcrel:
231 decoded_addr = (unsigned long)addr;
232 break;
233 default:
234 pr_debug("encoding=0x%x\n", (encoding & 0x70));
235 UNWINDER_BUG();
236 }
237
238 if ((encoding & 0x07) == 0x00)
239 encoding |= DW_EH_PE_udata4;
240
241 switch (encoding & 0x0f) {
242 case DW_EH_PE_sdata4:
243 case DW_EH_PE_udata4:
244 count += 4;
245 decoded_addr += get_unaligned((u32 *)addr);
246 __raw_writel(decoded_addr, val);
247 break;
248 default:
249 pr_debug("encoding=0x%x\n", encoding);
250 UNWINDER_BUG();
251 }
252
253 return count;
254}
255
256/**
257 * dwarf_entry_len - return the length of an FDE or CIE
258 * @addr: the address of the entry
259 * @len: the length of the entry
260 *
261 * Read the initial_length field of the entry and store the size of
262 * the entry in @len. We return the number of bytes read. Return a
263 * count of 0 on error.
264 */
265static inline int dwarf_entry_len(char *addr, unsigned long *len)
266{
267 u32 initial_len;
268 int count;
269
270 initial_len = get_unaligned((u32 *)addr);
271 count = 4;
272
273 /*
274 * An initial length field value in the range DW_LEN_EXT_LO -
275 * DW_LEN_EXT_HI indicates an extension, and should not be
276 * interpreted as a length. The only extension that we currently
277 * understand is the use of DWARF64 addresses.
278 */
279 if (initial_len >= DW_EXT_LO && initial_len <= DW_EXT_HI) {
280 /*
281 * The 64-bit length field immediately follows the
282 * compulsory 32-bit length field.
283 */
284 if (initial_len == DW_EXT_DWARF64) {
285 *len = get_unaligned((u64 *)addr + 4);
286 count = 12;
287 } else {
288 printk(KERN_WARNING "Unknown DWARF extension\n");
289 count = 0;
290 }
291 } else
292 *len = initial_len;
293
294 return count;
295}
296
297/**
298 * dwarf_lookup_cie - locate the cie
299 * @cie_ptr: pointer to help with lookup
300 */
301static struct dwarf_cie *dwarf_lookup_cie(unsigned long cie_ptr)
302{
303 struct dwarf_cie *cie;
304 unsigned long flags;
305
306 spin_lock_irqsave(&dwarf_cie_lock, flags);
307
308 /*
309 * We've cached the last CIE we looked up because chances are
310 * that the FDE wants this CIE.
311 */
312 if (cached_cie && cached_cie->cie_pointer == cie_ptr) {
313 cie = cached_cie;
314 goto out;
315 }
316
317 list_for_each_entry(cie, &dwarf_cie_list, link) {
318 if (cie->cie_pointer == cie_ptr) {
319 cached_cie = cie;
320 break;
321 }
322 }
323
324 /* Couldn't find the entry in the list. */
325 if (&cie->link == &dwarf_cie_list)
326 cie = NULL;
327out:
328 spin_unlock_irqrestore(&dwarf_cie_lock, flags);
329 return cie;
330}
331
332/**
333 * dwarf_lookup_fde - locate the FDE that covers pc
334 * @pc: the program counter
335 */
336struct dwarf_fde *dwarf_lookup_fde(unsigned long pc)
337{
338 struct dwarf_fde *fde;
339 unsigned long flags;
340
341 spin_lock_irqsave(&dwarf_fde_lock, flags);
342
343 list_for_each_entry(fde, &dwarf_fde_list, link) {
344 unsigned long start, end;
345
346 start = fde->initial_location;
347 end = fde->initial_location + fde->address_range;
348
349 if (pc >= start && pc < end)
350 break;
351 }
352
353 /* Couldn't find the entry in the list. */
354 if (&fde->link == &dwarf_fde_list)
355 fde = NULL;
356
357 spin_unlock_irqrestore(&dwarf_fde_lock, flags);
358
359 return fde;
360}
361
362/**
363 * dwarf_cfa_execute_insns - execute instructions to calculate a CFA
364 * @insn_start: address of the first instruction
365 * @insn_end: address of the last instruction
366 * @cie: the CIE for this function
367 * @fde: the FDE for this function
368 * @frame: the instructions calculate the CFA for this frame
369 * @pc: the program counter of the address we're interested in
370 *
371 * Execute the Call Frame instruction sequence starting at
372 * @insn_start and ending at @insn_end. The instructions describe
373 * how to calculate the Canonical Frame Address of a stackframe.
374 * Store the results in @frame.
375 */
376static int dwarf_cfa_execute_insns(unsigned char *insn_start,
377 unsigned char *insn_end,
378 struct dwarf_cie *cie,
379 struct dwarf_fde *fde,
380 struct dwarf_frame *frame,
381 unsigned long pc)
382{
383 unsigned char insn;
384 unsigned char *current_insn;
385 unsigned int count, delta, reg, expr_len, offset;
386 struct dwarf_reg *regp;
387
388 current_insn = insn_start;
389
390 while (current_insn < insn_end && frame->pc <= pc) {
391 insn = __raw_readb(current_insn++);
392
393 /*
394 * Firstly, handle the opcodes that embed their operands
395 * in the instructions.
396 */
397 switch (DW_CFA_opcode(insn)) {
398 case DW_CFA_advance_loc:
399 delta = DW_CFA_operand(insn);
400 delta *= cie->code_alignment_factor;
401 frame->pc += delta;
402 continue;
403 /* NOTREACHED */
404 case DW_CFA_offset:
405 reg = DW_CFA_operand(insn);
406 count = dwarf_read_uleb128(current_insn, &offset);
407 current_insn += count;
408 offset *= cie->data_alignment_factor;
409 regp = dwarf_frame_alloc_reg(frame, reg);
410 regp->addr = offset;
411 regp->flags |= DWARF_REG_OFFSET;
412 continue;
413 /* NOTREACHED */
414 case DW_CFA_restore:
415 reg = DW_CFA_operand(insn);
416 continue;
417 /* NOTREACHED */
418 }
419
420 /*
421 * Secondly, handle the opcodes that don't embed their
422 * operands in the instruction.
423 */
424 switch (insn) {
425 case DW_CFA_nop:
426 continue;
427 case DW_CFA_advance_loc1:
428 delta = *current_insn++;
429 frame->pc += delta * cie->code_alignment_factor;
430 break;
431 case DW_CFA_advance_loc2:
432 delta = get_unaligned((u16 *)current_insn);
433 current_insn += 2;
434 frame->pc += delta * cie->code_alignment_factor;
435 break;
436 case DW_CFA_advance_loc4:
437 delta = get_unaligned((u32 *)current_insn);
438 current_insn += 4;
439 frame->pc += delta * cie->code_alignment_factor;
440 break;
441 case DW_CFA_offset_extended:
442 count = dwarf_read_uleb128(current_insn, &reg);
443 current_insn += count;
444 count = dwarf_read_uleb128(current_insn, &offset);
445 current_insn += count;
446 offset *= cie->data_alignment_factor;
447 break;
448 case DW_CFA_restore_extended:
449 count = dwarf_read_uleb128(current_insn, &reg);
450 current_insn += count;
451 break;
452 case DW_CFA_undefined:
453 count = dwarf_read_uleb128(current_insn, &reg);
454 current_insn += count;
455 regp = dwarf_frame_alloc_reg(frame, reg);
456 regp->flags |= DWARF_UNDEFINED;
457 break;
458 case DW_CFA_def_cfa:
459 count = dwarf_read_uleb128(current_insn,
460 &frame->cfa_register);
461 current_insn += count;
462 count = dwarf_read_uleb128(current_insn,
463 &frame->cfa_offset);
464 current_insn += count;
465
466 frame->flags |= DWARF_FRAME_CFA_REG_OFFSET;
467 break;
468 case DW_CFA_def_cfa_register:
469 count = dwarf_read_uleb128(current_insn,
470 &frame->cfa_register);
471 current_insn += count;
472 frame->flags |= DWARF_FRAME_CFA_REG_OFFSET;
473 break;
474 case DW_CFA_def_cfa_offset:
475 count = dwarf_read_uleb128(current_insn, &offset);
476 current_insn += count;
477 frame->cfa_offset = offset;
478 break;
479 case DW_CFA_def_cfa_expression:
480 count = dwarf_read_uleb128(current_insn, &expr_len);
481 current_insn += count;
482
483 frame->cfa_expr = current_insn;
484 frame->cfa_expr_len = expr_len;
485 current_insn += expr_len;
486
487 frame->flags |= DWARF_FRAME_CFA_REG_EXP;
488 break;
489 case DW_CFA_offset_extended_sf:
490 count = dwarf_read_uleb128(current_insn, &reg);
491 current_insn += count;
492 count = dwarf_read_leb128(current_insn, &offset);
493 current_insn += count;
494 offset *= cie->data_alignment_factor;
495 regp = dwarf_frame_alloc_reg(frame, reg);
496 regp->flags |= DWARF_REG_OFFSET;
497 regp->addr = offset;
498 break;
499 case DW_CFA_val_offset:
500 count = dwarf_read_uleb128(current_insn, &reg);
501 current_insn += count;
502 count = dwarf_read_leb128(current_insn, &offset);
503 offset *= cie->data_alignment_factor;
504 regp = dwarf_frame_alloc_reg(frame, reg);
505 regp->flags |= DWARF_VAL_OFFSET;
506 regp->addr = offset;
507 break;
508 case DW_CFA_GNU_args_size:
509 count = dwarf_read_uleb128(current_insn, &offset);
510 current_insn += count;
511 break;
512 case DW_CFA_GNU_negative_offset_extended:
513 count = dwarf_read_uleb128(current_insn, &reg);
514 current_insn += count;
515 count = dwarf_read_uleb128(current_insn, &offset);
516 offset *= cie->data_alignment_factor;
517
518 regp = dwarf_frame_alloc_reg(frame, reg);
519 regp->flags |= DWARF_REG_OFFSET;
520 regp->addr = -offset;
521 break;
522 default:
523 pr_debug("unhandled DWARF instruction 0x%x\n", insn);
524 UNWINDER_BUG();
525 break;
526 }
527 }
528
529 return 0;
530}
531
532/**
533 * dwarf_unwind_stack - recursively unwind the stack
534 * @pc: address of the function to unwind
535 * @prev: struct dwarf_frame of the previous stackframe on the callstack
536 *
537 * Return a struct dwarf_frame representing the most recent frame
538 * on the callstack. Each of the lower (older) stack frames are
539 * linked via the "prev" member.
540 */
541struct dwarf_frame * dwarf_unwind_stack(unsigned long pc,
542 struct dwarf_frame *prev)
543{
544 struct dwarf_frame *frame;
545 struct dwarf_cie *cie;
546 struct dwarf_fde *fde;
547 struct dwarf_reg *reg;
548 unsigned long addr;
549
550 /*
551 * If this is the first invocation of this recursive function we
552 * need get the contents of a physical register to get the CFA
553 * in order to begin the virtual unwinding of the stack.
554 *
555 * NOTE: the return address is guaranteed to be setup by the
556 * time this function makes its first function call.
557 */
558 if (!pc && !prev)
559 pc = (unsigned long)current_text_addr();
560
561 frame = mempool_alloc(dwarf_frame_pool, GFP_ATOMIC);
562 if (!frame) {
563 printk(KERN_ERR "Unable to allocate a dwarf frame\n");
564 UNWINDER_BUG();
565 }
566
567 INIT_LIST_HEAD(&frame->reg_list);
568 frame->flags = 0;
569 frame->prev = prev;
570 frame->return_addr = 0;
571
572 fde = dwarf_lookup_fde(pc);
573 if (!fde) {
574 /*
575 * This is our normal exit path - the one that stops the
576 * recursion. There's two reasons why we might exit
577 * here,
578 *
579 * a) pc has no asscociated DWARF frame info and so
580 * we don't know how to unwind this frame. This is
581 * usually the case when we're trying to unwind a
582 * frame that was called from some assembly code
583 * that has no DWARF info, e.g. syscalls.
584 *
585 * b) the DEBUG info for pc is bogus. There's
586 * really no way to distinguish this case from the
587 * case above, which sucks because we could print a
588 * warning here.
589 */
590 goto bail;
591 }
592
593 cie = dwarf_lookup_cie(fde->cie_pointer);
594
595 frame->pc = fde->initial_location;
596
597 /* CIE initial instructions */
598 dwarf_cfa_execute_insns(cie->initial_instructions,
599 cie->instructions_end, cie, fde,
600 frame, pc);
601
602 /* FDE instructions */
603 dwarf_cfa_execute_insns(fde->instructions, fde->end, cie,
604 fde, frame, pc);
605
606 /* Calculate the CFA */
607 switch (frame->flags) {
608 case DWARF_FRAME_CFA_REG_OFFSET:
609 if (prev) {
610 reg = dwarf_frame_reg(prev, frame->cfa_register);
611 UNWINDER_BUG_ON(!reg);
612 UNWINDER_BUG_ON(reg->flags != DWARF_REG_OFFSET);
613
614 addr = prev->cfa + reg->addr;
615 frame->cfa = __raw_readl(addr);
616
617 } else {
618 /*
619 * Again, this is the first invocation of this
620 * recurisve function. We need to physically
621 * read the contents of a register in order to
622 * get the Canonical Frame Address for this
623 * function.
624 */
625 frame->cfa = dwarf_read_arch_reg(frame->cfa_register);
626 }
627
628 frame->cfa += frame->cfa_offset;
629 break;
630 default:
631 UNWINDER_BUG();
632 }
633
634 reg = dwarf_frame_reg(frame, DWARF_ARCH_RA_REG);
635
636 /*
637 * If we haven't seen the return address register or the return
638 * address column is undefined then we must assume that this is
639 * the end of the callstack.
640 */
641 if (!reg || reg->flags == DWARF_UNDEFINED)
642 goto bail;
643
644 UNWINDER_BUG_ON(reg->flags != DWARF_REG_OFFSET);
645
646 addr = frame->cfa + reg->addr;
647 frame->return_addr = __raw_readl(addr);
648
649 return frame;
650
651bail:
652 dwarf_frame_free_regs(frame);
653 mempool_free(frame, dwarf_frame_pool);
654 return NULL;
655}
656
657static int dwarf_parse_cie(void *entry, void *p, unsigned long len,
658 unsigned char *end)
659{
660 struct dwarf_cie *cie;
661 unsigned long flags;
662 int count;
663
664 cie = kzalloc(sizeof(*cie), GFP_KERNEL);
665 if (!cie)
666 return -ENOMEM;
667
668 cie->length = len;
669
670 /*
671 * Record the offset into the .eh_frame section
672 * for this CIE. It allows this CIE to be
673 * quickly and easily looked up from the
674 * corresponding FDE.
675 */
676 cie->cie_pointer = (unsigned long)entry;
677
678 cie->version = *(char *)p++;
679 UNWINDER_BUG_ON(cie->version != 1);
680
681 cie->augmentation = p;
682 p += strlen(cie->augmentation) + 1;
683
684 count = dwarf_read_uleb128(p, &cie->code_alignment_factor);
685 p += count;
686
687 count = dwarf_read_leb128(p, &cie->data_alignment_factor);
688 p += count;
689
690 /*
691 * Which column in the rule table contains the
692 * return address?
693 */
694 if (cie->version == 1) {
695 cie->return_address_reg = __raw_readb(p);
696 p++;
697 } else {
698 count = dwarf_read_uleb128(p, &cie->return_address_reg);
699 p += count;
700 }
701
702 if (cie->augmentation[0] == 'z') {
703 unsigned int length, count;
704 cie->flags |= DWARF_CIE_Z_AUGMENTATION;
705
706 count = dwarf_read_uleb128(p, &length);
707 p += count;
708
709 UNWINDER_BUG_ON((unsigned char *)p > end);
710
711 cie->initial_instructions = p + length;
712 cie->augmentation++;
713 }
714
715 while (*cie->augmentation) {
716 /*
717 * "L" indicates a byte showing how the
718 * LSDA pointer is encoded. Skip it.
719 */
720 if (*cie->augmentation == 'L') {
721 p++;
722 cie->augmentation++;
723 } else if (*cie->augmentation == 'R') {
724 /*
725 * "R" indicates a byte showing
726 * how FDE addresses are
727 * encoded.
728 */
729 cie->encoding = *(char *)p++;
730 cie->augmentation++;
731 } else if (*cie->augmentation == 'P') {
732 /*
733 * "R" indicates a personality
734 * routine in the CIE
735 * augmentation.
736 */
737 UNWINDER_BUG();
738 } else if (*cie->augmentation == 'S') {
739 UNWINDER_BUG();
740 } else {
741 /*
742 * Unknown augmentation. Assume
743 * 'z' augmentation.
744 */
745 p = cie->initial_instructions;
746 UNWINDER_BUG_ON(!p);
747 break;
748 }
749 }
750
751 cie->initial_instructions = p;
752 cie->instructions_end = end;
753
754 /* Add to list */
755 spin_lock_irqsave(&dwarf_cie_lock, flags);
756 list_add_tail(&cie->link, &dwarf_cie_list);
757 spin_unlock_irqrestore(&dwarf_cie_lock, flags);
758
759 return 0;
760}
761
762static int dwarf_parse_fde(void *entry, u32 entry_type,
763 void *start, unsigned long len,
764 unsigned char *end)
765{
766 struct dwarf_fde *fde;
767 struct dwarf_cie *cie;
768 unsigned long flags;
769 int count;
770 void *p = start;
771
772 fde = kzalloc(sizeof(*fde), GFP_KERNEL);
773 if (!fde)
774 return -ENOMEM;
775
776 fde->length = len;
777
778 /*
779 * In a .eh_frame section the CIE pointer is the
780 * delta between the address within the FDE
781 */
782 fde->cie_pointer = (unsigned long)(p - entry_type - 4);
783
784 cie = dwarf_lookup_cie(fde->cie_pointer);
785 fde->cie = cie;
786
787 if (cie->encoding)
788 count = dwarf_read_encoded_value(p, &fde->initial_location,
789 cie->encoding);
790 else
791 count = dwarf_read_addr(p, &fde->initial_location);
792
793 p += count;
794
795 if (cie->encoding)
796 count = dwarf_read_encoded_value(p, &fde->address_range,
797 cie->encoding & 0x0f);
798 else
799 count = dwarf_read_addr(p, &fde->address_range);
800
801 p += count;
802
803 if (fde->cie->flags & DWARF_CIE_Z_AUGMENTATION) {
804 unsigned int length;
805 count = dwarf_read_uleb128(p, &length);
806 p += count + length;
807 }
808
809 /* Call frame instructions. */
810 fde->instructions = p;
811 fde->end = end;
812
813 /* Add to list. */
814 spin_lock_irqsave(&dwarf_fde_lock, flags);
815 list_add_tail(&fde->link, &dwarf_fde_list);
816 spin_unlock_irqrestore(&dwarf_fde_lock, flags);
817
818 return 0;
819}
820
821static void dwarf_unwinder_dump(struct task_struct *task,
822 struct pt_regs *regs,
823 unsigned long *sp,
824 const struct stacktrace_ops *ops,
825 void *data)
826{
827 struct dwarf_frame *frame, *_frame;
828 unsigned long return_addr;
829
830 _frame = NULL;
831 return_addr = 0;
832
833 while (1) {
834 frame = dwarf_unwind_stack(return_addr, _frame);
835
836 if (_frame) {
837 dwarf_frame_free_regs(_frame);
838 mempool_free(_frame, dwarf_frame_pool);
839 }
840
841 _frame = frame;
842
843 if (!frame || !frame->return_addr)
844 break;
845
846 return_addr = frame->return_addr;
847 ops->address(data, return_addr, 1);
848 }
849}
850
851static struct unwinder dwarf_unwinder = {
852 .name = "dwarf-unwinder",
853 .dump = dwarf_unwinder_dump,
854 .rating = 150,
855};
856
857static void dwarf_unwinder_cleanup(void)
858{
859 struct dwarf_cie *cie;
860 struct dwarf_fde *fde;
861
862 /*
863 * Deallocate all the memory allocated for the DWARF unwinder.
864 * Traverse all the FDE/CIE lists and remove and free all the
865 * memory associated with those data structures.
866 */
867 list_for_each_entry(cie, &dwarf_cie_list, link)
868 kfree(cie);
869
870 list_for_each_entry(fde, &dwarf_fde_list, link)
871 kfree(fde);
872
873 kmem_cache_destroy(dwarf_reg_cachep);
874 kmem_cache_destroy(dwarf_frame_cachep);
875}
876
877/**
878 * dwarf_unwinder_init - initialise the dwarf unwinder
879 *
880 * Build the data structures describing the .dwarf_frame section to
881 * make it easier to lookup CIE and FDE entries. Because the
882 * .eh_frame section is packed as tightly as possible it is not
883 * easy to lookup the FDE for a given PC, so we build a list of FDE
884 * and CIE entries that make it easier.
885 */
886static int __init dwarf_unwinder_init(void)
887{
888 u32 entry_type;
889 void *p, *entry;
890 int count, err = 0;
891 unsigned long len;
892 unsigned int c_entries, f_entries;
893 unsigned char *end;
894 INIT_LIST_HEAD(&dwarf_cie_list);
895 INIT_LIST_HEAD(&dwarf_fde_list);
896
897 c_entries = 0;
898 f_entries = 0;
899 entry = &__start_eh_frame;
900
901 dwarf_frame_cachep = kmem_cache_create("dwarf_frames",
902 sizeof(struct dwarf_frame), 0,
903 SLAB_PANIC | SLAB_HWCACHE_ALIGN | SLAB_NOTRACK, NULL);
904
905 dwarf_reg_cachep = kmem_cache_create("dwarf_regs",
906 sizeof(struct dwarf_reg), 0,
907 SLAB_PANIC | SLAB_HWCACHE_ALIGN | SLAB_NOTRACK, NULL);
908
909 dwarf_frame_pool = mempool_create(DWARF_FRAME_MIN_REQ,
910 mempool_alloc_slab,
911 mempool_free_slab,
912 dwarf_frame_cachep);
913
914 dwarf_reg_pool = mempool_create(DWARF_REG_MIN_REQ,
915 mempool_alloc_slab,
916 mempool_free_slab,
917 dwarf_reg_cachep);
918
919 while ((char *)entry < __stop_eh_frame) {
920 p = entry;
921
922 count = dwarf_entry_len(p, &len);
923 if (count == 0) {
924 /*
925 * We read a bogus length field value. There is
926 * nothing we can do here apart from disabling
927 * the DWARF unwinder. We can't even skip this
928 * entry and move to the next one because 'len'
929 * tells us where our next entry is.
930 */
931 goto out;
932 } else
933 p += count;
934
935 /* initial length does not include itself */
936 end = p + len;
937
938 entry_type = get_unaligned((u32 *)p);
939 p += 4;
940
941 if (entry_type == DW_EH_FRAME_CIE) {
942 err = dwarf_parse_cie(entry, p, len, end);
943 if (err < 0)
944 goto out;
945 else
946 c_entries++;
947 } else {
948 err = dwarf_parse_fde(entry, entry_type, p, len, end);
949 if (err < 0)
950 goto out;
951 else
952 f_entries++;
953 }
954
955 entry = (char *)entry + len + 4;
956 }
957
958 printk(KERN_INFO "DWARF unwinder initialised: read %u CIEs, %u FDEs\n",
959 c_entries, f_entries);
960
961 err = unwinder_register(&dwarf_unwinder);
962 if (err)
963 goto out;
964
965 return 0;
966
967out:
968 printk(KERN_ERR "Failed to initialise DWARF unwinder: %d\n", err);
969 dwarf_unwinder_cleanup();
970 return -EINVAL;
971}
972early_initcall(dwarf_unwinder_init);
diff --git a/arch/sh/kernel/early_printk.c b/arch/sh/kernel/early_printk.c
index a952dcf9999d..81a46145ffa5 100644
--- a/arch/sh/kernel/early_printk.c
+++ b/arch/sh/kernel/early_printk.c
@@ -134,7 +134,7 @@ static void scif_sercon_init(char *s)
134 sci_out(&scif_port, SCFCR, 0x0030); /* TTRG=b'11 */ 134 sci_out(&scif_port, SCFCR, 0x0030); /* TTRG=b'11 */
135 sci_out(&scif_port, SCSCR, 0x0030); /* TE, RE */ 135 sci_out(&scif_port, SCSCR, 0x0030); /* TE, RE */
136} 136}
137#elif defined(CONFIG_CPU_SH4) 137#elif defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SH3)
138#define DEFAULT_BAUD 115200 138#define DEFAULT_BAUD 115200
139/* 139/*
140 * Simple SCIF init, primarily aimed at SH7750 and other similar SH-4 140 * Simple SCIF init, primarily aimed at SH7750 and other similar SH-4
@@ -220,8 +220,7 @@ static int __init setup_early_printk(char *buf)
220 early_console = &scif_console; 220 early_console = &scif_console;
221 221
222#if !defined(CONFIG_SH_STANDARD_BIOS) 222#if !defined(CONFIG_SH_STANDARD_BIOS)
223#if defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 223#if defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SH3)
224 defined(CONFIG_CPU_SUBTYPE_SH7721)
225 scif_sercon_init(buf + 6); 224 scif_sercon_init(buf + 6);
226#endif 225#endif
227#endif 226#endif
diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S
index d62359cfbbe2..68d9223b145e 100644
--- a/arch/sh/kernel/entry-common.S
+++ b/arch/sh/kernel/entry-common.S
@@ -43,9 +43,10 @@
43 * syscall # 43 * syscall #
44 * 44 *
45 */ 45 */
46#include <asm/dwarf.h>
46 47
47#if defined(CONFIG_PREEMPT) 48#if defined(CONFIG_PREEMPT)
48# define preempt_stop() cli 49# define preempt_stop() cli ; TRACE_IRQS_OFF
49#else 50#else
50# define preempt_stop() 51# define preempt_stop()
51# define resume_kernel __restore_all 52# define resume_kernel __restore_all
@@ -55,11 +56,7 @@
55 .align 2 56 .align 2
56ENTRY(exception_error) 57ENTRY(exception_error)
57 ! 58 !
58#ifdef CONFIG_TRACE_IRQFLAGS 59 TRACE_IRQS_ON
59 mov.l 2f, r0
60 jsr @r0
61 nop
62#endif
63 sti 60 sti
64 mov.l 1f, r0 61 mov.l 1f, r0
65 jmp @r0 62 jmp @r0
@@ -67,18 +64,15 @@ ENTRY(exception_error)
67 64
68 .align 2 65 .align 2
691: .long do_exception_error 661: .long do_exception_error
70#ifdef CONFIG_TRACE_IRQFLAGS
712: .long trace_hardirqs_on
72#endif
73 67
74 .align 2 68 .align 2
75ret_from_exception: 69ret_from_exception:
70 CFI_STARTPROC simple
71 CFI_DEF_CFA r14, 0
72 CFI_REL_OFFSET 17, 64
73 CFI_REL_OFFSET 15, 0
74 CFI_REL_OFFSET 14, 56
76 preempt_stop() 75 preempt_stop()
77#ifdef CONFIG_TRACE_IRQFLAGS
78 mov.l 4f, r0
79 jsr @r0
80 nop
81#endif
82ENTRY(ret_from_irq) 76ENTRY(ret_from_irq)
83 ! 77 !
84 mov #OFF_SR, r0 78 mov #OFF_SR, r0
@@ -93,6 +87,7 @@ ENTRY(ret_from_irq)
93 nop 87 nop
94ENTRY(resume_kernel) 88ENTRY(resume_kernel)
95 cli 89 cli
90 TRACE_IRQS_OFF
96 mov.l @(TI_PRE_COUNT,r8), r0 ! current_thread_info->preempt_count 91 mov.l @(TI_PRE_COUNT,r8), r0 ! current_thread_info->preempt_count
97 tst r0, r0 92 tst r0, r0
98 bf noresched 93 bf noresched
@@ -103,8 +98,9 @@ need_resched:
103 98
104 mov #OFF_SR, r0 99 mov #OFF_SR, r0
105 mov.l @(r0,r15), r0 ! get status register 100 mov.l @(r0,r15), r0 ! get status register
106 and #0xf0, r0 ! interrupts off (exception path)? 101 shlr r0
107 cmp/eq #0xf0, r0 102 and #(0xf0>>1), r0 ! interrupts off (exception path)?
103 cmp/eq #(0xf0>>1), r0
108 bt noresched 104 bt noresched
109 mov.l 3f, r0 105 mov.l 3f, r0
110 jsr @r0 ! call preempt_schedule_irq 106 jsr @r0 ! call preempt_schedule_irq
@@ -125,13 +121,9 @@ noresched:
125ENTRY(resume_userspace) 121ENTRY(resume_userspace)
126 ! r8: current_thread_info 122 ! r8: current_thread_info
127 cli 123 cli
128#ifdef CONFIG_TRACE_IRQFLAGS 124 TRACE_IRQS_OfF
129 mov.l 5f, r0
130 jsr @r0
131 nop
132#endif
133 mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags 125 mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags
134 tst #_TIF_WORK_MASK, r0 126 tst #(_TIF_WORK_MASK & 0xff), r0
135 bt/s __restore_all 127 bt/s __restore_all
136 tst #_TIF_NEED_RESCHED, r0 128 tst #_TIF_NEED_RESCHED, r0
137 129
@@ -156,14 +148,10 @@ work_resched:
156 jsr @r1 ! schedule 148 jsr @r1 ! schedule
157 nop 149 nop
158 cli 150 cli
159#ifdef CONFIG_TRACE_IRQFLAGS 151 TRACE_IRQS_OFF
160 mov.l 5f, r0
161 jsr @r0
162 nop
163#endif
164 ! 152 !
165 mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags 153 mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags
166 tst #_TIF_WORK_MASK, r0 154 tst #(_TIF_WORK_MASK & 0xff), r0
167 bt __restore_all 155 bt __restore_all
168 bra work_pending 156 bra work_pending
169 tst #_TIF_NEED_RESCHED, r0 157 tst #_TIF_NEED_RESCHED, r0
@@ -172,23 +160,15 @@ work_resched:
1721: .long schedule 1601: .long schedule
1732: .long do_notify_resume 1612: .long do_notify_resume
1743: .long resume_userspace 1623: .long resume_userspace
175#ifdef CONFIG_TRACE_IRQFLAGS
1764: .long trace_hardirqs_on
1775: .long trace_hardirqs_off
178#endif
179 163
180 .align 2 164 .align 2
181syscall_exit_work: 165syscall_exit_work:
182 ! r0: current_thread_info->flags 166 ! r0: current_thread_info->flags
183 ! r8: current_thread_info 167 ! r8: current_thread_info
184 tst #_TIF_WORK_SYSCALL_MASK, r0 168 tst #(_TIF_WORK_SYSCALL_MASK & 0xff), r0
185 bt/s work_pending 169 bt/s work_pending
186 tst #_TIF_NEED_RESCHED, r0 170 tst #_TIF_NEED_RESCHED, r0
187#ifdef CONFIG_TRACE_IRQFLAGS 171 TRACE_IRQS_ON
188 mov.l 5f, r0
189 jsr @r0
190 nop
191#endif
192 sti 172 sti
193 mov r15, r4 173 mov r15, r4
194 mov.l 8f, r0 ! do_syscall_trace_leave 174 mov.l 8f, r0 ! do_syscall_trace_leave
@@ -226,12 +206,25 @@ syscall_trace_entry:
226 mov.l r0, @(OFF_R0,r15) ! Return value 206 mov.l r0, @(OFF_R0,r15) ! Return value
227 207
228__restore_all: 208__restore_all:
229 mov.l 1f, r0 209 mov #OFF_SR, r0
210 mov.l @(r0,r15), r0 ! get status register
211
212 shlr2 r0
213 and #0x3c, r0
214 cmp/eq #0x3c, r0
215 bt 1f
216 TRACE_IRQS_ON
217 bra 2f
218 nop
2191:
220 TRACE_IRQS_OFF
2212:
222 mov.l 3f, r0
230 jmp @r0 223 jmp @r0
231 nop 224 nop
232 225
233 .align 2 226 .align 2
2341: .long restore_all 2273: .long restore_all
235 228
236 .align 2 229 .align 2
237syscall_badsys: ! Bad syscall number 230syscall_badsys: ! Bad syscall number
@@ -259,6 +252,7 @@ debug_trap:
259 nop 252 nop
260 bra __restore_all 253 bra __restore_all
261 nop 254 nop
255 CFI_ENDPROC
262 256
263 .align 2 257 .align 2
2641: .long debug_trap_table 2581: .long debug_trap_table
@@ -304,6 +298,7 @@ ret_from_fork:
304 * system calls and debug traps through their respective jump tables. 298 * system calls and debug traps through their respective jump tables.
305 */ 299 */
306ENTRY(system_call) 300ENTRY(system_call)
301 setup_frame_reg
307#if !defined(CONFIG_CPU_SH2) 302#if !defined(CONFIG_CPU_SH2)
308 mov.l 1f, r9 303 mov.l 1f, r9
309 mov.l @r9, r8 ! Read from TRA (Trap Address) Register 304 mov.l @r9, r8 ! Read from TRA (Trap Address) Register
@@ -321,18 +316,18 @@ ENTRY(system_call)
321 bt/s debug_trap ! it's a debug trap.. 316 bt/s debug_trap ! it's a debug trap..
322 nop 317 nop
323 318
324#ifdef CONFIG_TRACE_IRQFLAGS 319 TRACE_IRQS_ON
325 mov.l 5f, r10
326 jsr @r10
327 nop
328#endif
329 sti 320 sti
330 321
331 ! 322 !
332 get_current_thread_info r8, r10 323 get_current_thread_info r8, r10
333 mov.l @(TI_FLAGS,r8), r8 324 mov.l @(TI_FLAGS,r8), r8
334 mov #_TIF_WORK_SYSCALL_MASK, r10 325 mov #(_TIF_WORK_SYSCALL_MASK & 0xff), r10
326 mov #(_TIF_WORK_SYSCALL_MASK >> 8), r9
335 tst r10, r8 327 tst r10, r8
328 shll8 r9
329 bf syscall_trace_entry
330 tst r9, r8
336 bf syscall_trace_entry 331 bf syscall_trace_entry
337 ! 332 !
338 mov.l 2f, r8 ! Number of syscalls 333 mov.l 2f, r8 ! Number of syscalls
@@ -351,15 +346,15 @@ syscall_call:
351 ! 346 !
352syscall_exit: 347syscall_exit:
353 cli 348 cli
354#ifdef CONFIG_TRACE_IRQFLAGS 349 TRACE_IRQS_OFF
355 mov.l 6f, r0
356 jsr @r0
357 nop
358#endif
359 ! 350 !
360 get_current_thread_info r8, r0 351 get_current_thread_info r8, r0
361 mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags 352 mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags
362 tst #_TIF_ALLWORK_MASK, r0 353 tst #(_TIF_ALLWORK_MASK & 0xff), r0
354 mov #(_TIF_ALLWORK_MASK >> 8), r1
355 bf syscall_exit_work
356 shlr8 r0
357 tst r0, r1
363 bf syscall_exit_work 358 bf syscall_exit_work
364 bra __restore_all 359 bra __restore_all
365 nop 360 nop
@@ -369,9 +364,5 @@ syscall_exit:
369#endif 364#endif
3702: .long NR_syscalls 3652: .long NR_syscalls
3713: .long sys_call_table 3663: .long sys_call_table
372#ifdef CONFIG_TRACE_IRQFLAGS
3735: .long trace_hardirqs_on
3746: .long trace_hardirqs_off
375#endif
3767: .long do_syscall_trace_enter 3677: .long do_syscall_trace_enter
3778: .long do_syscall_trace_leave 3688: .long do_syscall_trace_leave
diff --git a/arch/sh/kernel/ftrace.c b/arch/sh/kernel/ftrace.c
index 066f37dc32a9..a3dcc6d5d253 100644
--- a/arch/sh/kernel/ftrace.c
+++ b/arch/sh/kernel/ftrace.c
@@ -16,9 +16,13 @@
16#include <linux/string.h> 16#include <linux/string.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/kernel.h>
19#include <asm/ftrace.h> 20#include <asm/ftrace.h>
20#include <asm/cacheflush.h> 21#include <asm/cacheflush.h>
22#include <asm/unistd.h>
23#include <trace/syscall.h>
21 24
25#ifdef CONFIG_DYNAMIC_FTRACE
22static unsigned char ftrace_replaced_code[MCOUNT_INSN_SIZE]; 26static unsigned char ftrace_replaced_code[MCOUNT_INSN_SIZE];
23 27
24static unsigned char ftrace_nop[4]; 28static unsigned char ftrace_nop[4];
@@ -131,3 +135,187 @@ int __init ftrace_dyn_arch_init(void *data)
131 135
132 return 0; 136 return 0;
133} 137}
138#endif /* CONFIG_DYNAMIC_FTRACE */
139
140#ifdef CONFIG_FUNCTION_GRAPH_TRACER
141#ifdef CONFIG_DYNAMIC_FTRACE
142extern void ftrace_graph_call(void);
143
144static int ftrace_mod(unsigned long ip, unsigned long old_addr,
145 unsigned long new_addr)
146{
147 unsigned char code[MCOUNT_INSN_SIZE];
148
149 if (probe_kernel_read(code, (void *)ip, MCOUNT_INSN_SIZE))
150 return -EFAULT;
151
152 if (old_addr != __raw_readl((unsigned long *)code))
153 return -EINVAL;
154
155 __raw_writel(new_addr, ip);
156 return 0;
157}
158
159int ftrace_enable_ftrace_graph_caller(void)
160{
161 unsigned long ip, old_addr, new_addr;
162
163 ip = (unsigned long)(&ftrace_graph_call) + GRAPH_INSN_OFFSET;
164 old_addr = (unsigned long)(&skip_trace);
165 new_addr = (unsigned long)(&ftrace_graph_caller);
166
167 return ftrace_mod(ip, old_addr, new_addr);
168}
169
170int ftrace_disable_ftrace_graph_caller(void)
171{
172 unsigned long ip, old_addr, new_addr;
173
174 ip = (unsigned long)(&ftrace_graph_call) + GRAPH_INSN_OFFSET;
175 old_addr = (unsigned long)(&ftrace_graph_caller);
176 new_addr = (unsigned long)(&skip_trace);
177
178 return ftrace_mod(ip, old_addr, new_addr);
179}
180#endif /* CONFIG_DYNAMIC_FTRACE */
181
182/*
183 * Hook the return address and push it in the stack of return addrs
184 * in the current thread info.
185 *
186 * This is the main routine for the function graph tracer. The function
187 * graph tracer essentially works like this:
188 *
189 * parent is the stack address containing self_addr's return address.
190 * We pull the real return address out of parent and store it in
191 * current's ret_stack. Then, we replace the return address on the stack
192 * with the address of return_to_handler. self_addr is the function that
193 * called mcount.
194 *
195 * When self_addr returns, it will jump to return_to_handler which calls
196 * ftrace_return_to_handler. ftrace_return_to_handler will pull the real
197 * return address off of current's ret_stack and jump to it.
198 */
199void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr)
200{
201 unsigned long old;
202 int faulted, err;
203 struct ftrace_graph_ent trace;
204 unsigned long return_hooker = (unsigned long)&return_to_handler;
205
206 if (unlikely(atomic_read(&current->tracing_graph_pause)))
207 return;
208
209 /*
210 * Protect against fault, even if it shouldn't
211 * happen. This tool is too much intrusive to
212 * ignore such a protection.
213 */
214 __asm__ __volatile__(
215 "1: \n\t"
216 "mov.l @%2, %0 \n\t"
217 "2: \n\t"
218 "mov.l %3, @%2 \n\t"
219 "mov #0, %1 \n\t"
220 "3: \n\t"
221 ".section .fixup, \"ax\" \n\t"
222 "4: \n\t"
223 "mov.l 5f, %0 \n\t"
224 "jmp @%0 \n\t"
225 " mov #1, %1 \n\t"
226 ".balign 4 \n\t"
227 "5: .long 3b \n\t"
228 ".previous \n\t"
229 ".section __ex_table,\"a\" \n\t"
230 ".long 1b, 4b \n\t"
231 ".long 2b, 4b \n\t"
232 ".previous \n\t"
233 : "=&r" (old), "=r" (faulted)
234 : "r" (parent), "r" (return_hooker)
235 );
236
237 if (unlikely(faulted)) {
238 ftrace_graph_stop();
239 WARN_ON(1);
240 return;
241 }
242
243 err = ftrace_push_return_trace(old, self_addr, &trace.depth, 0);
244 if (err == -EBUSY) {
245 __raw_writel(old, parent);
246 return;
247 }
248
249 trace.func = self_addr;
250
251 /* Only trace if the calling function expects to */
252 if (!ftrace_graph_entry(&trace)) {
253 current->curr_ret_stack--;
254 __raw_writel(old, parent);
255 }
256}
257#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
258
259#ifdef CONFIG_FTRACE_SYSCALLS
260
261extern unsigned long __start_syscalls_metadata[];
262extern unsigned long __stop_syscalls_metadata[];
263extern unsigned long *sys_call_table;
264
265static struct syscall_metadata **syscalls_metadata;
266
267static struct syscall_metadata *find_syscall_meta(unsigned long *syscall)
268{
269 struct syscall_metadata *start;
270 struct syscall_metadata *stop;
271 char str[KSYM_SYMBOL_LEN];
272
273
274 start = (struct syscall_metadata *)__start_syscalls_metadata;
275 stop = (struct syscall_metadata *)__stop_syscalls_metadata;
276 kallsyms_lookup((unsigned long) syscall, NULL, NULL, NULL, str);
277
278 for ( ; start < stop; start++) {
279 if (start->name && !strcmp(start->name, str))
280 return start;
281 }
282
283 return NULL;
284}
285
286struct syscall_metadata *syscall_nr_to_meta(int nr)
287{
288 if (!syscalls_metadata || nr >= FTRACE_SYSCALL_MAX || nr < 0)
289 return NULL;
290
291 return syscalls_metadata[nr];
292}
293
294void arch_init_ftrace_syscalls(void)
295{
296 int i;
297 struct syscall_metadata *meta;
298 unsigned long **psys_syscall_table = &sys_call_table;
299 static atomic_t refs;
300
301 if (atomic_inc_return(&refs) != 1)
302 goto end;
303
304 syscalls_metadata = kzalloc(sizeof(*syscalls_metadata) *
305 FTRACE_SYSCALL_MAX, GFP_KERNEL);
306 if (!syscalls_metadata) {
307 WARN_ON(1);
308 return;
309 }
310
311 for (i = 0; i < FTRACE_SYSCALL_MAX; i++) {
312 meta = find_syscall_meta(psys_syscall_table[i]);
313 syscalls_metadata[i] = meta;
314 }
315 return;
316
317 /* Paranoid: avoid overflow */
318end:
319 atomic_dec(&refs);
320}
321#endif /* CONFIG_FTRACE_SYSCALLS */
diff --git a/arch/sh/kernel/io.c b/arch/sh/kernel/io.c
index 4f85fffaa557..4770c241c679 100644
--- a/arch/sh/kernel/io.c
+++ b/arch/sh/kernel/io.c
@@ -1,12 +1,9 @@
1/* 1/*
2 * linux/arch/sh/kernel/io.c 2 * arch/sh/kernel/io.c - Machine independent I/O functions.
3 * 3 *
4 * Copyright (C) 2000 Stuart Menefy 4 * Copyright (C) 2000 - 2009 Stuart Menefy
5 * Copyright (C) 2005 Paul Mundt 5 * Copyright (C) 2005 Paul Mundt
6 * 6 *
7 * Provide real functions which expand to whatever the header file defined.
8 * Also definitions of machine independent IO functions.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
12 * for more details. 9 * for more details.
@@ -18,33 +15,87 @@
18 15
19/* 16/*
20 * Copy data from IO memory space to "real" memory space. 17 * Copy data from IO memory space to "real" memory space.
21 * This needs to be optimized.
22 */ 18 */
23void memcpy_fromio(void *to, const volatile void __iomem *from, unsigned long count) 19void memcpy_fromio(void *to, const volatile void __iomem *from, unsigned long count)
24{ 20{
25 unsigned char *p = to; 21 /*
26 while (count) { 22 * Would it be worthwhile doing byte and long transfers first
27 count--; 23 * to try and get aligned?
28 *p = readb(from); 24 */
29 p++; 25#ifdef CONFIG_CPU_SH4
30 from++; 26 if ((count >= 0x20) &&
31 } 27 (((u32)to & 0x1f) == 0) && (((u32)from & 0x3) == 0)) {
28 int tmp2, tmp3, tmp4, tmp5, tmp6;
29
30 __asm__ __volatile__(
31 "1: \n\t"
32 "mov.l @%7+, r0 \n\t"
33 "mov.l @%7+, %2 \n\t"
34 "movca.l r0, @%0 \n\t"
35 "mov.l @%7+, %3 \n\t"
36 "mov.l @%7+, %4 \n\t"
37 "mov.l @%7+, %5 \n\t"
38 "mov.l @%7+, %6 \n\t"
39 "mov.l @%7+, r7 \n\t"
40 "mov.l @%7+, r0 \n\t"
41 "mov.l %2, @(0x04,%0) \n\t"
42 "mov #0x20, %2 \n\t"
43 "mov.l %3, @(0x08,%0) \n\t"
44 "sub %2, %1 \n\t"
45 "mov.l %4, @(0x0c,%0) \n\t"
46 "cmp/hi %1, %2 ! T if 32 > count \n\t"
47 "mov.l %5, @(0x10,%0) \n\t"
48 "mov.l %6, @(0x14,%0) \n\t"
49 "mov.l r7, @(0x18,%0) \n\t"
50 "mov.l r0, @(0x1c,%0) \n\t"
51 "bf.s 1b \n\t"
52 " add #0x20, %0 \n\t"
53 : "=&r" (to), "=&r" (count),
54 "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4),
55 "=&r" (tmp5), "=&r" (tmp6), "=&r" (from)
56 : "7"(from), "0" (to), "1" (count)
57 : "r0", "r7", "t", "memory");
58 }
59#endif
60
61 if ((((u32)to | (u32)from) & 0x3) == 0) {
62 for (; count > 3; count -= 4) {
63 *(u32 *)to = *(volatile u32 *)from;
64 to += 4;
65 from += 4;
66 }
67 }
68
69 for (; count > 0; count--) {
70 *(u8 *)to = *(volatile u8 *)from;
71 to++;
72 from++;
73 }
74
75 mb();
32} 76}
33EXPORT_SYMBOL(memcpy_fromio); 77EXPORT_SYMBOL(memcpy_fromio);
34 78
35/* 79/*
36 * Copy data from "real" memory space to IO memory space. 80 * Copy data from "real" memory space to IO memory space.
37 * This needs to be optimized.
38 */ 81 */
39void memcpy_toio(volatile void __iomem *to, const void *from, unsigned long count) 82void memcpy_toio(volatile void __iomem *to, const void *from, unsigned long count)
40{ 83{
41 const unsigned char *p = from; 84 if ((((u32)to | (u32)from) & 0x3) == 0) {
42 while (count) { 85 for ( ; count > 3; count -= 4) {
43 count--; 86 *(volatile u32 *)to = *(u32 *)from;
44 writeb(*p, to); 87 to += 4;
45 p++; 88 from += 4;
46 to++; 89 }
47 } 90 }
91
92 for (; count > 0; count--) {
93 *(volatile u8 *)to = *(u8 *)from;
94 to++;
95 from++;
96 }
97
98 mb();
48} 99}
49EXPORT_SYMBOL(memcpy_toio); 100EXPORT_SYMBOL(memcpy_toio);
50 101
@@ -62,6 +113,8 @@ void memset_io(volatile void __iomem *dst, int c, unsigned long count)
62} 113}
63EXPORT_SYMBOL(memset_io); 114EXPORT_SYMBOL(memset_io);
64 115
116#ifndef CONFIG_GENERIC_IOMAP
117
65void __iomem *ioport_map(unsigned long port, unsigned int nr) 118void __iomem *ioport_map(unsigned long port, unsigned int nr)
66{ 119{
67 void __iomem *ret; 120 void __iomem *ret;
@@ -79,3 +132,5 @@ void ioport_unmap(void __iomem *addr)
79 sh_mv.mv_ioport_unmap(addr); 132 sh_mv.mv_ioport_unmap(addr);
80} 133}
81EXPORT_SYMBOL(ioport_unmap); 134EXPORT_SYMBOL(ioport_unmap);
135
136#endif /* CONFIG_GENERIC_IOMAP */
diff --git a/arch/sh/kernel/io_generic.c b/arch/sh/kernel/io_generic.c
index 5a7f554d9ca1..4ff507239286 100644
--- a/arch/sh/kernel/io_generic.c
+++ b/arch/sh/kernel/io_generic.c
@@ -73,35 +73,19 @@ u32 generic_inl_p(unsigned long port)
73 73
74void generic_insb(unsigned long port, void *dst, unsigned long count) 74void generic_insb(unsigned long port, void *dst, unsigned long count)
75{ 75{
76 volatile u8 *port_addr; 76 __raw_readsb(__ioport_map(port, 1), dst, count);
77 u8 *buf = dst; 77 dummy_read();
78
79 port_addr = (volatile u8 __force *)__ioport_map(port, 1);
80 while (count--)
81 *buf++ = *port_addr;
82} 78}
83 79
84void generic_insw(unsigned long port, void *dst, unsigned long count) 80void generic_insw(unsigned long port, void *dst, unsigned long count)
85{ 81{
86 volatile u16 *port_addr; 82 __raw_readsw(__ioport_map(port, 2), dst, count);
87 u16 *buf = dst;
88
89 port_addr = (volatile u16 __force *)__ioport_map(port, 2);
90 while (count--)
91 *buf++ = *port_addr;
92
93 dummy_read(); 83 dummy_read();
94} 84}
95 85
96void generic_insl(unsigned long port, void *dst, unsigned long count) 86void generic_insl(unsigned long port, void *dst, unsigned long count)
97{ 87{
98 volatile u32 *port_addr; 88 __raw_readsl(__ioport_map(port, 4), dst, count);
99 u32 *buf = dst;
100
101 port_addr = (volatile u32 __force *)__ioport_map(port, 4);
102 while (count--)
103 *buf++ = *port_addr;
104
105 dummy_read(); 89 dummy_read();
106} 90}
107 91
@@ -145,37 +129,19 @@ void generic_outl_p(u32 b, unsigned long port)
145 */ 129 */
146void generic_outsb(unsigned long port, const void *src, unsigned long count) 130void generic_outsb(unsigned long port, const void *src, unsigned long count)
147{ 131{
148 volatile u8 *port_addr; 132 __raw_writesb(__ioport_map(port, 1), src, count);
149 const u8 *buf = src; 133 dummy_read();
150
151 port_addr = (volatile u8 __force *)__ioport_map(port, 1);
152
153 while (count--)
154 *port_addr = *buf++;
155} 134}
156 135
157void generic_outsw(unsigned long port, const void *src, unsigned long count) 136void generic_outsw(unsigned long port, const void *src, unsigned long count)
158{ 137{
159 volatile u16 *port_addr; 138 __raw_writesw(__ioport_map(port, 2), src, count);
160 const u16 *buf = src;
161
162 port_addr = (volatile u16 __force *)__ioport_map(port, 2);
163
164 while (count--)
165 *port_addr = *buf++;
166
167 dummy_read(); 139 dummy_read();
168} 140}
169 141
170void generic_outsl(unsigned long port, const void *src, unsigned long count) 142void generic_outsl(unsigned long port, const void *src, unsigned long count)
171{ 143{
172 volatile u32 *port_addr; 144 __raw_writesl(__ioport_map(port, 4), src, count);
173 const u32 *buf = src;
174
175 port_addr = (volatile u32 __force *)__ioport_map(port, 4);
176 while (count--)
177 *port_addr = *buf++;
178
179 dummy_read(); 145 dummy_read();
180} 146}
181 147
diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c
index 77dfecb64373..69be603aa2d7 100644
--- a/arch/sh/kernel/io_trapped.c
+++ b/arch/sh/kernel/io_trapped.c
@@ -112,14 +112,15 @@ void __iomem *match_trapped_io_handler(struct list_head *list,
112 struct trapped_io *tiop; 112 struct trapped_io *tiop;
113 struct resource *res; 113 struct resource *res;
114 int k, len; 114 int k, len;
115 unsigned long flags;
115 116
116 spin_lock_irq(&trapped_lock); 117 spin_lock_irqsave(&trapped_lock, flags);
117 list_for_each_entry(tiop, list, list) { 118 list_for_each_entry(tiop, list, list) {
118 voffs = 0; 119 voffs = 0;
119 for (k = 0; k < tiop->num_resources; k++) { 120 for (k = 0; k < tiop->num_resources; k++) {
120 res = tiop->resource + k; 121 res = tiop->resource + k;
121 if (res->start == offset) { 122 if (res->start == offset) {
122 spin_unlock_irq(&trapped_lock); 123 spin_unlock_irqrestore(&trapped_lock, flags);
123 return tiop->virt_base + voffs; 124 return tiop->virt_base + voffs;
124 } 125 }
125 126
@@ -127,7 +128,7 @@ void __iomem *match_trapped_io_handler(struct list_head *list,
127 voffs += roundup(len, PAGE_SIZE); 128 voffs += roundup(len, PAGE_SIZE);
128 } 129 }
129 } 130 }
130 spin_unlock_irq(&trapped_lock); 131 spin_unlock_irqrestore(&trapped_lock, flags);
131 return NULL; 132 return NULL;
132} 133}
133EXPORT_SYMBOL_GPL(match_trapped_io_handler); 134EXPORT_SYMBOL_GPL(match_trapped_io_handler);
@@ -283,7 +284,8 @@ int handle_trapped_io(struct pt_regs *regs, unsigned long address)
283 return 0; 284 return 0;
284 } 285 }
285 286
286 tmp = handle_unaligned_access(instruction, regs, &trapped_io_access); 287 tmp = handle_unaligned_access(instruction, regs,
288 &trapped_io_access, 1);
287 set_fs(oldfs); 289 set_fs(oldfs);
288 return tmp == 0; 290 return tmp == 0;
289} 291}
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index 3d09062f4682..60f8af4497c7 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -114,24 +114,7 @@ asmlinkage int do_IRQ(unsigned int irq, struct pt_regs *regs)
114#endif 114#endif
115 115
116 irq_enter(); 116 irq_enter();
117 117 irq = irq_demux(irq);
118#ifdef CONFIG_DEBUG_STACKOVERFLOW
119 /* Debugging check for stack overflow: is there less than 1KB free? */
120 {
121 long sp;
122
123 __asm__ __volatile__ ("and r15, %0" :
124 "=r" (sp) : "0" (THREAD_SIZE - 1));
125
126 if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
127 printk("do_IRQ: stack overflow: %ld\n",
128 sp - sizeof(struct thread_info));
129 dump_stack();
130 }
131 }
132#endif
133
134 irq = irq_demux(intc_evt2irq(irq));
135 118
136#ifdef CONFIG_IRQSTACKS 119#ifdef CONFIG_IRQSTACKS
137 curctx = (union irq_ctx *)current_thread_info(); 120 curctx = (union irq_ctx *)current_thread_info();
diff --git a/arch/sh/kernel/kgdb.c b/arch/sh/kernel/kgdb.c
index 305aad742aec..3e532d0d4a5c 100644
--- a/arch/sh/kernel/kgdb.c
+++ b/arch/sh/kernel/kgdb.c
@@ -15,8 +15,6 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <asm/cacheflush.h> 16#include <asm/cacheflush.h>
17 17
18char in_nmi = 0; /* Set during NMI to prevent re-entry */
19
20/* Macros for single step instruction identification */ 18/* Macros for single step instruction identification */
21#define OPCODE_BT(op) (((op) & 0xff00) == 0x8900) 19#define OPCODE_BT(op) (((op) & 0xff00) == 0x8900)
22#define OPCODE_BF(op) (((op) & 0xff00) == 0x8b00) 20#define OPCODE_BF(op) (((op) & 0xff00) == 0x8b00)
@@ -195,8 +193,6 @@ void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
195 regs->gbr = gdb_regs[GDB_GBR]; 193 regs->gbr = gdb_regs[GDB_GBR];
196 regs->mach = gdb_regs[GDB_MACH]; 194 regs->mach = gdb_regs[GDB_MACH];
197 regs->macl = gdb_regs[GDB_MACL]; 195 regs->macl = gdb_regs[GDB_MACL];
198
199 __asm__ __volatile__ ("ldc %0, vbr" : : "r" (gdb_regs[GDB_VBR]));
200} 196}
201 197
202void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p) 198void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
diff --git a/arch/sh/kernel/localtimer.c b/arch/sh/kernel/localtimer.c
index 96e8eaea1e62..0b04e7d4a9b9 100644
--- a/arch/sh/kernel/localtimer.c
+++ b/arch/sh/kernel/localtimer.c
@@ -22,6 +22,7 @@
22#include <linux/jiffies.h> 22#include <linux/jiffies.h>
23#include <linux/percpu.h> 23#include <linux/percpu.h>
24#include <linux/clockchips.h> 24#include <linux/clockchips.h>
25#include <linux/hardirq.h>
25#include <linux/irq.h> 26#include <linux/irq.h>
26 27
27static DEFINE_PER_CPU(struct clock_event_device, local_clockevent); 28static DEFINE_PER_CPU(struct clock_event_device, local_clockevent);
@@ -33,7 +34,9 @@ void local_timer_interrupt(void)
33{ 34{
34 struct clock_event_device *clk = &__get_cpu_var(local_clockevent); 35 struct clock_event_device *clk = &__get_cpu_var(local_clockevent);
35 36
37 irq_enter();
36 clk->event_handler(clk); 38 clk->event_handler(clk);
39 irq_exit();
37} 40}
38 41
39static void dummy_timer_set_mode(enum clock_event_mode mode, 42static void dummy_timer_set_mode(enum clock_event_mode mode,
@@ -46,8 +49,10 @@ void __cpuinit local_timer_setup(unsigned int cpu)
46 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); 49 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
47 50
48 clk->name = "dummy_timer"; 51 clk->name = "dummy_timer";
49 clk->features = CLOCK_EVT_FEAT_DUMMY; 52 clk->features = CLOCK_EVT_FEAT_ONESHOT |
50 clk->rating = 200; 53 CLOCK_EVT_FEAT_PERIODIC |
54 CLOCK_EVT_FEAT_DUMMY;
55 clk->rating = 400;
51 clk->mult = 1; 56 clk->mult = 1;
52 clk->set_mode = dummy_timer_set_mode; 57 clk->set_mode = dummy_timer_set_mode;
53 clk->broadcast = smp_timer_broadcast; 58 clk->broadcast = smp_timer_broadcast;
diff --git a/arch/sh/kernel/nmi_debug.c b/arch/sh/kernel/nmi_debug.c
new file mode 100644
index 000000000000..ff0abbd1e652
--- /dev/null
+++ b/arch/sh/kernel/nmi_debug.c
@@ -0,0 +1,77 @@
1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <linux/delay.h>
9#include <linux/kdebug.h>
10#include <linux/notifier.h>
11#include <linux/sched.h>
12#include <linux/hardirq.h>
13
14enum nmi_action {
15 NMI_SHOW_STATE = 1 << 0,
16 NMI_SHOW_REGS = 1 << 1,
17 NMI_DIE = 1 << 2,
18 NMI_DEBOUNCE = 1 << 3,
19};
20
21static unsigned long nmi_actions;
22
23static int nmi_debug_notify(struct notifier_block *self,
24 unsigned long val, void *data)
25{
26 struct die_args *args = data;
27
28 if (likely(val != DIE_NMI))
29 return NOTIFY_DONE;
30
31 if (nmi_actions & NMI_SHOW_STATE)
32 show_state();
33 if (nmi_actions & NMI_SHOW_REGS)
34 show_regs(args->regs);
35 if (nmi_actions & NMI_DEBOUNCE)
36 mdelay(10);
37 if (nmi_actions & NMI_DIE)
38 return NOTIFY_BAD;
39
40 return NOTIFY_OK;
41}
42
43static struct notifier_block nmi_debug_nb = {
44 .notifier_call = nmi_debug_notify,
45};
46
47static int __init nmi_debug_setup(char *str)
48{
49 char *p, *sep;
50
51 register_die_notifier(&nmi_debug_nb);
52
53 if (*str != '=')
54 return 0;
55
56 for (p = str + 1; *p; p = sep + 1) {
57 sep = strchr(p, ',');
58 if (sep)
59 *sep = 0;
60 if (strcmp(p, "state") == 0)
61 nmi_actions |= NMI_SHOW_STATE;
62 else if (strcmp(p, "regs") == 0)
63 nmi_actions |= NMI_SHOW_REGS;
64 else if (strcmp(p, "debounce") == 0)
65 nmi_actions |= NMI_DEBOUNCE;
66 else if (strcmp(p, "die") == 0)
67 nmi_actions |= NMI_DIE;
68 else
69 printk(KERN_WARNING "NMI: Unrecognized action `%s'\n",
70 p);
71 if (!sep)
72 break;
73 }
74
75 return 0;
76}
77__setup("nmi_debug", nmi_debug_setup);
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 92d7740faab1..0673c4746be3 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -23,6 +23,7 @@
23#include <linux/tick.h> 23#include <linux/tick.h>
24#include <linux/reboot.h> 24#include <linux/reboot.h>
25#include <linux/fs.h> 25#include <linux/fs.h>
26#include <linux/ftrace.h>
26#include <linux/preempt.h> 27#include <linux/preempt.h>
27#include <asm/uaccess.h> 28#include <asm/uaccess.h>
28#include <asm/mmu_context.h> 29#include <asm/mmu_context.h>
@@ -31,15 +32,35 @@
31#include <asm/ubc.h> 32#include <asm/ubc.h>
32#include <asm/fpu.h> 33#include <asm/fpu.h>
33#include <asm/syscalls.h> 34#include <asm/syscalls.h>
35#include <asm/watchdog.h>
34 36
35int ubc_usercnt = 0; 37int ubc_usercnt = 0;
36 38
39#ifdef CONFIG_32BIT
40static void watchdog_trigger_immediate(void)
41{
42 sh_wdt_write_cnt(0xFF);
43 sh_wdt_write_csr(0xC2);
44}
45
46void machine_restart(char * __unused)
47{
48 local_irq_disable();
49
50 /* Use watchdog timer to trigger reset */
51 watchdog_trigger_immediate();
52
53 while (1)
54 cpu_sleep();
55}
56#else
37void machine_restart(char * __unused) 57void machine_restart(char * __unused)
38{ 58{
39 /* SR.BL=1 and invoke address error to let CPU reset (manual reset) */ 59 /* SR.BL=1 and invoke address error to let CPU reset (manual reset) */
40 asm volatile("ldc %0, sr\n\t" 60 asm volatile("ldc %0, sr\n\t"
41 "mov.l @%1, %0" : : "r" (0x10000000), "r" (0x80000001)); 61 "mov.l @%1, %0" : : "r" (0x10000000), "r" (0x80000001));
42} 62}
63#endif
43 64
44void machine_halt(void) 65void machine_halt(void)
45{ 66{
@@ -264,8 +285,8 @@ static void ubc_set_tracing(int asid, unsigned long pc)
264 * switch_to(x,y) should switch tasks from x to y. 285 * switch_to(x,y) should switch tasks from x to y.
265 * 286 *
266 */ 287 */
267struct task_struct *__switch_to(struct task_struct *prev, 288__notrace_funcgraph struct task_struct *
268 struct task_struct *next) 289__switch_to(struct task_struct *prev, struct task_struct *next)
269{ 290{
270#if defined(CONFIG_SH_FPU) 291#if defined(CONFIG_SH_FPU)
271 unlazy_fpu(prev, task_pt_regs(prev)); 292 unlazy_fpu(prev, task_pt_regs(prev));
diff --git a/arch/sh/kernel/process_64.c b/arch/sh/kernel/process_64.c
index 24de74214940..1192398ef582 100644
--- a/arch/sh/kernel/process_64.c
+++ b/arch/sh/kernel/process_64.c
@@ -425,7 +425,6 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
425 struct task_struct *p, struct pt_regs *regs) 425 struct task_struct *p, struct pt_regs *regs)
426{ 426{
427 struct pt_regs *childregs; 427 struct pt_regs *childregs;
428 unsigned long long se; /* Sign extension */
429 428
430#ifdef CONFIG_SH_FPU 429#ifdef CONFIG_SH_FPU
431 if(last_task_used_math == current) { 430 if(last_task_used_math == current) {
@@ -441,11 +440,19 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
441 440
442 *childregs = *regs; 441 *childregs = *regs;
443 442
443 /*
444 * Sign extend the edited stack.
445 * Note that thread.pc and thread.pc will stay
446 * 32-bit wide and context switch must take care
447 * of NEFF sign extension.
448 */
444 if (user_mode(regs)) { 449 if (user_mode(regs)) {
445 childregs->regs[15] = usp; 450 childregs->regs[15] = neff_sign_extend(usp);
446 p->thread.uregs = childregs; 451 p->thread.uregs = childregs;
447 } else { 452 } else {
448 childregs->regs[15] = (unsigned long)task_stack_page(p) + THREAD_SIZE; 453 childregs->regs[15] =
454 neff_sign_extend((unsigned long)task_stack_page(p) +
455 THREAD_SIZE);
449 } 456 }
450 457
451 childregs->regs[9] = 0; /* Set return value for child */ 458 childregs->regs[9] = 0; /* Set return value for child */
@@ -454,17 +461,6 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
454 p->thread.sp = (unsigned long) childregs; 461 p->thread.sp = (unsigned long) childregs;
455 p->thread.pc = (unsigned long) ret_from_fork; 462 p->thread.pc = (unsigned long) ret_from_fork;
456 463
457 /*
458 * Sign extend the edited stack.
459 * Note that thread.pc and thread.pc will stay
460 * 32-bit wide and context switch must take care
461 * of NEFF sign extension.
462 */
463
464 se = childregs->regs[15];
465 se = (se & NEFF_SIGN) ? (se | NEFF_MASK) : se;
466 childregs->regs[15] = se;
467
468 return 0; 464 return 0;
469} 465}
470 466
diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c
index 3392e835a374..9be35f348093 100644
--- a/arch/sh/kernel/ptrace_32.c
+++ b/arch/sh/kernel/ptrace_32.c
@@ -34,6 +34,9 @@
34#include <asm/syscalls.h> 34#include <asm/syscalls.h>
35#include <asm/fpu.h> 35#include <asm/fpu.h>
36 36
37#define CREATE_TRACE_POINTS
38#include <trace/events/syscalls.h>
39
37/* 40/*
38 * This routine will get a word off of the process kernel stack. 41 * This routine will get a word off of the process kernel stack.
39 */ 42 */
@@ -459,6 +462,9 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
459 */ 462 */
460 ret = -1L; 463 ret = -1L;
461 464
465 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
466 trace_sys_enter(regs, regs->regs[0]);
467
462 if (unlikely(current->audit_context)) 468 if (unlikely(current->audit_context))
463 audit_syscall_entry(audit_arch(), regs->regs[3], 469 audit_syscall_entry(audit_arch(), regs->regs[3],
464 regs->regs[4], regs->regs[5], 470 regs->regs[4], regs->regs[5],
@@ -475,6 +481,9 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
475 audit_syscall_exit(AUDITSC_RESULT(regs->regs[0]), 481 audit_syscall_exit(AUDITSC_RESULT(regs->regs[0]),
476 regs->regs[0]); 482 regs->regs[0]);
477 483
484 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
485 trace_sys_exit(regs, regs->regs[0]);
486
478 step = test_thread_flag(TIF_SINGLESTEP); 487 step = test_thread_flag(TIF_SINGLESTEP);
479 if (step || test_thread_flag(TIF_SYSCALL_TRACE)) 488 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
480 tracehook_report_syscall_exit(regs, step); 489 tracehook_report_syscall_exit(regs, step);
diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c
index 695097438f02..952da83903da 100644
--- a/arch/sh/kernel/ptrace_64.c
+++ b/arch/sh/kernel/ptrace_64.c
@@ -40,6 +40,9 @@
40#include <asm/syscalls.h> 40#include <asm/syscalls.h>
41#include <asm/fpu.h> 41#include <asm/fpu.h>
42 42
43#define CREATE_TRACE_POINTS
44#include <trace/events/syscalls.h>
45
43/* This mask defines the bits of the SR which the user is not allowed to 46/* This mask defines the bits of the SR which the user is not allowed to
44 change, which are everything except S, Q, M, PR, SZ, FR. */ 47 change, which are everything except S, Q, M, PR, SZ, FR. */
45#define SR_MASK (0xffff8cfd) 48#define SR_MASK (0xffff8cfd)
@@ -438,6 +441,9 @@ asmlinkage long long do_syscall_trace_enter(struct pt_regs *regs)
438 */ 441 */
439 ret = -1LL; 442 ret = -1LL;
440 443
444 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
445 trace_sys_enter(regs, regs->regs[9]);
446
441 if (unlikely(current->audit_context)) 447 if (unlikely(current->audit_context))
442 audit_syscall_entry(audit_arch(), regs->regs[1], 448 audit_syscall_entry(audit_arch(), regs->regs[1],
443 regs->regs[2], regs->regs[3], 449 regs->regs[2], regs->regs[3],
@@ -452,6 +458,9 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
452 audit_syscall_exit(AUDITSC_RESULT(regs->regs[9]), 458 audit_syscall_exit(AUDITSC_RESULT(regs->regs[9]),
453 regs->regs[9]); 459 regs->regs[9]);
454 460
461 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
462 trace_sys_exit(regs, regs->regs[9]);
463
455 if (test_thread_flag(TIF_SYSCALL_TRACE)) 464 if (test_thread_flag(TIF_SYSCALL_TRACE))
456 tracehook_report_syscall_exit(regs, 0); 465 tracehook_report_syscall_exit(regs, 0);
457} 466}
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index dd38338553ef..f9d44f8e0df6 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -30,6 +30,7 @@
30#include <linux/clk.h> 30#include <linux/clk.h>
31#include <linux/delay.h> 31#include <linux/delay.h>
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <linux/lmb.h>
33#include <asm/uaccess.h> 34#include <asm/uaccess.h>
34#include <asm/io.h> 35#include <asm/io.h>
35#include <asm/page.h> 36#include <asm/page.h>
@@ -48,6 +49,7 @@
48struct sh_cpuinfo cpu_data[NR_CPUS] __read_mostly = { 49struct sh_cpuinfo cpu_data[NR_CPUS] __read_mostly = {
49 [0] = { 50 [0] = {
50 .type = CPU_SH_NONE, 51 .type = CPU_SH_NONE,
52 .family = CPU_FAMILY_UNKNOWN,
51 .loops_per_jiffy = 10000000, 53 .loops_per_jiffy = 10000000,
52 }, 54 },
53}; 55};
@@ -233,39 +235,45 @@ void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
233void __init setup_bootmem_allocator(unsigned long free_pfn) 235void __init setup_bootmem_allocator(unsigned long free_pfn)
234{ 236{
235 unsigned long bootmap_size; 237 unsigned long bootmap_size;
238 unsigned long bootmap_pages, bootmem_paddr;
239 u64 total_pages = (lmb_end_of_DRAM() - __MEMORY_START) >> PAGE_SHIFT;
240 int i;
241
242 bootmap_pages = bootmem_bootmap_pages(total_pages);
243
244 bootmem_paddr = lmb_alloc(bootmap_pages << PAGE_SHIFT, PAGE_SIZE);
236 245
237 /* 246 /*
238 * Find a proper area for the bootmem bitmap. After this 247 * Find a proper area for the bootmem bitmap. After this
239 * bootstrap step all allocations (until the page allocator 248 * bootstrap step all allocations (until the page allocator
240 * is intact) must be done via bootmem_alloc(). 249 * is intact) must be done via bootmem_alloc().
241 */ 250 */
242 bootmap_size = init_bootmem_node(NODE_DATA(0), free_pfn, 251 bootmap_size = init_bootmem_node(NODE_DATA(0),
252 bootmem_paddr >> PAGE_SHIFT,
243 min_low_pfn, max_low_pfn); 253 min_low_pfn, max_low_pfn);
244 254
245 __add_active_range(0, min_low_pfn, max_low_pfn); 255 /* Add active regions with valid PFNs. */
246 register_bootmem_low_pages(); 256 for (i = 0; i < lmb.memory.cnt; i++) {
247 257 unsigned long start_pfn, end_pfn;
248 node_set_online(0); 258 start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT;
259 end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i);
260 __add_active_range(0, start_pfn, end_pfn);
261 }
249 262
250 /* 263 /*
251 * Reserve the kernel text and 264 * Add all physical memory to the bootmem map and mark each
252 * Reserve the bootmem bitmap. We do this in two steps (first step 265 * area as present.
253 * was init_bootmem()), because this catches the (definitely buggy)
254 * case of us accidentally initializing the bootmem allocator with
255 * an invalid RAM area.
256 */ 266 */
257 reserve_bootmem(__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET, 267 register_bootmem_low_pages();
258 (PFN_PHYS(free_pfn) + bootmap_size + PAGE_SIZE - 1) -
259 (__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET),
260 BOOTMEM_DEFAULT);
261 268
262 /* 269 /* Reserve the sections we're already using. */
263 * Reserve physical pages below CONFIG_ZERO_PAGE_OFFSET. 270 for (i = 0; i < lmb.reserved.cnt; i++)
264 */ 271 reserve_bootmem(lmb.reserved.region[i].base,
265 if (CONFIG_ZERO_PAGE_OFFSET != 0) 272 lmb_size_bytes(&lmb.reserved, i),
266 reserve_bootmem(__MEMORY_START, CONFIG_ZERO_PAGE_OFFSET,
267 BOOTMEM_DEFAULT); 273 BOOTMEM_DEFAULT);
268 274
275 node_set_online(0);
276
269 sparse_memory_present_with_active_regions(0); 277 sparse_memory_present_with_active_regions(0);
270 278
271#ifdef CONFIG_BLK_DEV_INITRD 279#ifdef CONFIG_BLK_DEV_INITRD
@@ -296,12 +304,37 @@ void __init setup_bootmem_allocator(unsigned long free_pfn)
296static void __init setup_memory(void) 304static void __init setup_memory(void)
297{ 305{
298 unsigned long start_pfn; 306 unsigned long start_pfn;
307 u64 base = min_low_pfn << PAGE_SHIFT;
308 u64 size = (max_low_pfn << PAGE_SHIFT) - base;
299 309
300 /* 310 /*
301 * Partially used pages are not usable - thus 311 * Partially used pages are not usable - thus
302 * we are rounding upwards: 312 * we are rounding upwards:
303 */ 313 */
304 start_pfn = PFN_UP(__pa(_end)); 314 start_pfn = PFN_UP(__pa(_end));
315
316 lmb_add(base, size);
317
318 /*
319 * Reserve the kernel text and
320 * Reserve the bootmem bitmap. We do this in two steps (first step
321 * was init_bootmem()), because this catches the (definitely buggy)
322 * case of us accidentally initializing the bootmem allocator with
323 * an invalid RAM area.
324 */
325 lmb_reserve(__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET,
326 (PFN_PHYS(start_pfn) + PAGE_SIZE - 1) -
327 (__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET));
328
329 /*
330 * Reserve physical pages below CONFIG_ZERO_PAGE_OFFSET.
331 */
332 if (CONFIG_ZERO_PAGE_OFFSET != 0)
333 lmb_reserve(__MEMORY_START, CONFIG_ZERO_PAGE_OFFSET);
334
335 lmb_analyze();
336 lmb_dump_all();
337
305 setup_bootmem_allocator(start_pfn); 338 setup_bootmem_allocator(start_pfn);
306} 339}
307#else 340#else
@@ -372,10 +405,14 @@ void __init setup_arch(char **cmdline_p)
372 if (!memory_end) 405 if (!memory_end)
373 memory_end = memory_start + __MEMORY_SIZE; 406 memory_end = memory_start + __MEMORY_SIZE;
374 407
375#ifdef CONFIG_CMDLINE_BOOL 408#ifdef CONFIG_CMDLINE_OVERWRITE
376 strlcpy(command_line, CONFIG_CMDLINE, sizeof(command_line)); 409 strlcpy(command_line, CONFIG_CMDLINE, sizeof(command_line));
377#else 410#else
378 strlcpy(command_line, COMMAND_LINE, sizeof(command_line)); 411 strlcpy(command_line, COMMAND_LINE, sizeof(command_line));
412#ifdef CONFIG_CMDLINE_EXTEND
413 strlcat(command_line, " ", sizeof(command_line));
414 strlcat(command_line, CONFIG_CMDLINE, sizeof(command_line));
415#endif
379#endif 416#endif
380 417
381 /* Save unparsed command line copy for /proc/cmdline */ 418 /* Save unparsed command line copy for /proc/cmdline */
@@ -402,6 +439,7 @@ void __init setup_arch(char **cmdline_p)
402 nodes_clear(node_online_map); 439 nodes_clear(node_online_map);
403 440
404 /* Setup bootmem with available RAM */ 441 /* Setup bootmem with available RAM */
442 lmb_init();
405 setup_memory(); 443 setup_memory();
406 sparse_init(); 444 sparse_init();
407 445
@@ -448,7 +486,7 @@ static const char *cpu_name[] = {
448 [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770", 486 [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
449 [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781", 487 [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
450 [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785", 488 [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
451 [CPU_SH7786] = "SH7786", 489 [CPU_SH7786] = "SH7786", [CPU_SH7757] = "SH7757",
452 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3", 490 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
453 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103", 491 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
454 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723", 492 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
diff --git a/arch/sh/kernel/sh_ksyms_32.c b/arch/sh/kernel/sh_ksyms_32.c
index fcc5de31f83b..8dbe26b17c44 100644
--- a/arch/sh/kernel/sh_ksyms_32.c
+++ b/arch/sh/kernel/sh_ksyms_32.c
@@ -101,20 +101,14 @@ EXPORT_SYMBOL(flush_cache_range);
101EXPORT_SYMBOL(flush_dcache_page); 101EXPORT_SYMBOL(flush_dcache_page);
102#endif 102#endif
103 103
104#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \ 104#ifdef CONFIG_MCOUNT
105 (defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)) 105DECLARE_EXPORT(mcount);
106EXPORT_SYMBOL(clear_user_page);
107#endif
108
109#ifdef CONFIG_FUNCTION_TRACER
110EXPORT_SYMBOL(mcount);
111#endif 106#endif
112EXPORT_SYMBOL(csum_partial); 107EXPORT_SYMBOL(csum_partial);
113EXPORT_SYMBOL(csum_partial_copy_generic); 108EXPORT_SYMBOL(csum_partial_copy_generic);
114#ifdef CONFIG_IPV6 109#ifdef CONFIG_IPV6
115EXPORT_SYMBOL(csum_ipv6_magic); 110EXPORT_SYMBOL(csum_ipv6_magic);
116#endif 111#endif
117EXPORT_SYMBOL(clear_page);
118EXPORT_SYMBOL(copy_page); 112EXPORT_SYMBOL(copy_page);
119EXPORT_SYMBOL(__clear_user); 113EXPORT_SYMBOL(__clear_user);
120EXPORT_SYMBOL(_ebss); 114EXPORT_SYMBOL(_ebss);
diff --git a/arch/sh/kernel/sh_ksyms_64.c b/arch/sh/kernel/sh_ksyms_64.c
index f5bd156ea504..d008e17eb257 100644
--- a/arch/sh/kernel/sh_ksyms_64.c
+++ b/arch/sh/kernel/sh_ksyms_64.c
@@ -30,14 +30,6 @@ extern int dump_fpu(struct pt_regs *, elf_fpregset_t *);
30EXPORT_SYMBOL(dump_fpu); 30EXPORT_SYMBOL(dump_fpu);
31EXPORT_SYMBOL(kernel_thread); 31EXPORT_SYMBOL(kernel_thread);
32 32
33#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU)
34EXPORT_SYMBOL(clear_user_page);
35#endif
36
37#ifndef CONFIG_CACHE_OFF
38EXPORT_SYMBOL(flush_dcache_page);
39#endif
40
41#ifdef CONFIG_VT 33#ifdef CONFIG_VT
42EXPORT_SYMBOL(screen_info); 34EXPORT_SYMBOL(screen_info);
43#endif 35#endif
@@ -52,7 +44,6 @@ EXPORT_SYMBOL(__get_user_asm_l);
52EXPORT_SYMBOL(__get_user_asm_q); 44EXPORT_SYMBOL(__get_user_asm_q);
53EXPORT_SYMBOL(__strnlen_user); 45EXPORT_SYMBOL(__strnlen_user);
54EXPORT_SYMBOL(__strncpy_from_user); 46EXPORT_SYMBOL(__strncpy_from_user);
55EXPORT_SYMBOL(clear_page);
56EXPORT_SYMBOL(__clear_user); 47EXPORT_SYMBOL(__clear_user);
57EXPORT_SYMBOL(copy_page); 48EXPORT_SYMBOL(copy_page);
58EXPORT_SYMBOL(__copy_user); 49EXPORT_SYMBOL(__copy_user);
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index 04a21883f327..6729703547a1 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -41,6 +41,16 @@ struct fdpic_func_descriptor {
41}; 41};
42 42
43/* 43/*
44 * The following define adds a 64 byte gap between the signal
45 * stack frame and previous contents of the stack. This allows
46 * frame unwinding in a function epilogue but only if a frame
47 * pointer is used in the function. This is necessary because
48 * current gcc compilers (<4.3) do not generate unwind info on
49 * SH for function epilogues.
50 */
51#define UNWINDGUARD 64
52
53/*
44 * Atomically swap in the new signal mask, and wait for a signal. 54 * Atomically swap in the new signal mask, and wait for a signal.
45 */ 55 */
46asmlinkage int 56asmlinkage int
@@ -327,7 +337,7 @@ get_sigframe(struct k_sigaction *ka, unsigned long sp, size_t frame_size)
327 sp = current->sas_ss_sp + current->sas_ss_size; 337 sp = current->sas_ss_sp + current->sas_ss_size;
328 } 338 }
329 339
330 return (void __user *)((sp - frame_size) & -8ul); 340 return (void __user *)((sp - (frame_size+UNWINDGUARD)) & -8ul);
331} 341}
332 342
333/* These symbols are defined with the addresses in the vsyscall page. 343/* These symbols are defined with the addresses in the vsyscall page.
diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c
index 9e5c9b1d7e98..74793c80a57a 100644
--- a/arch/sh/kernel/signal_64.c
+++ b/arch/sh/kernel/signal_64.c
@@ -561,13 +561,11 @@ static int setup_frame(int sig, struct k_sigaction *ka,
561 /* Set up to return from userspace. If provided, use a stub 561 /* Set up to return from userspace. If provided, use a stub
562 already in userspace. */ 562 already in userspace. */
563 if (ka->sa.sa_flags & SA_RESTORER) { 563 if (ka->sa.sa_flags & SA_RESTORER) {
564 DEREF_REG_PR = (unsigned long) ka->sa.sa_restorer | 0x1;
565
566 /* 564 /*
567 * On SH5 all edited pointers are subject to NEFF 565 * On SH5 all edited pointers are subject to NEFF
568 */ 566 */
569 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? 567 DEREF_REG_PR = neff_sign_extend((unsigned long)
570 (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; 568 ka->sa.sa_restorer | 0x1);
571 } else { 569 } else {
572 /* 570 /*
573 * Different approach on SH5. 571 * Different approach on SH5.
@@ -580,9 +578,8 @@ static int setup_frame(int sig, struct k_sigaction *ka,
580 * . being code, linker turns ShMedia bit on, always 578 * . being code, linker turns ShMedia bit on, always
581 * dereference index -1. 579 * dereference index -1.
582 */ 580 */
583 DEREF_REG_PR = (unsigned long) frame->retcode | 0x01; 581 DEREF_REG_PR = neff_sign_extend((unsigned long)
584 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? 582 frame->retcode | 0x01);
585 (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
586 583
587 if (__copy_to_user(frame->retcode, 584 if (__copy_to_user(frame->retcode,
588 (void *)((unsigned long)sa_default_restorer & (~1)), 16) != 0) 585 (void *)((unsigned long)sa_default_restorer & (~1)), 16) != 0)
@@ -596,9 +593,7 @@ static int setup_frame(int sig, struct k_sigaction *ka,
596 * Set up registers for signal handler. 593 * Set up registers for signal handler.
597 * All edited pointers are subject to NEFF. 594 * All edited pointers are subject to NEFF.
598 */ 595 */
599 regs->regs[REG_SP] = (unsigned long) frame; 596 regs->regs[REG_SP] = neff_sign_extend((unsigned long)frame);
600 regs->regs[REG_SP] = (regs->regs[REG_SP] & NEFF_SIGN) ?
601 (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP];
602 regs->regs[REG_ARG1] = signal; /* Arg for signal handler */ 597 regs->regs[REG_ARG1] = signal; /* Arg for signal handler */
603 598
604 /* FIXME: 599 /* FIXME:
@@ -613,8 +608,7 @@ static int setup_frame(int sig, struct k_sigaction *ka,
613 regs->regs[REG_ARG2] = (unsigned long long)(unsigned long)(signed long)&frame->sc; 608 regs->regs[REG_ARG2] = (unsigned long long)(unsigned long)(signed long)&frame->sc;
614 regs->regs[REG_ARG3] = (unsigned long long)(unsigned long)(signed long)&frame->sc; 609 regs->regs[REG_ARG3] = (unsigned long long)(unsigned long)(signed long)&frame->sc;
615 610
616 regs->pc = (unsigned long) ka->sa.sa_handler; 611 regs->pc = neff_sign_extend((unsigned long)ka->sa.sa_handler);
617 regs->pc = (regs->pc & NEFF_SIGN) ? (regs->pc | NEFF_MASK) : regs->pc;
618 612
619 set_fs(USER_DS); 613 set_fs(USER_DS);
620 614
@@ -676,13 +670,11 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
676 /* Set up to return from userspace. If provided, use a stub 670 /* Set up to return from userspace. If provided, use a stub
677 already in userspace. */ 671 already in userspace. */
678 if (ka->sa.sa_flags & SA_RESTORER) { 672 if (ka->sa.sa_flags & SA_RESTORER) {
679 DEREF_REG_PR = (unsigned long) ka->sa.sa_restorer | 0x1;
680
681 /* 673 /*
682 * On SH5 all edited pointers are subject to NEFF 674 * On SH5 all edited pointers are subject to NEFF
683 */ 675 */
684 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? 676 DEREF_REG_PR = neff_sign_extend((unsigned long)
685 (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; 677 ka->sa.sa_restorer | 0x1);
686 } else { 678 } else {
687 /* 679 /*
688 * Different approach on SH5. 680 * Different approach on SH5.
@@ -695,15 +687,14 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
695 * . being code, linker turns ShMedia bit on, always 687 * . being code, linker turns ShMedia bit on, always
696 * dereference index -1. 688 * dereference index -1.
697 */ 689 */
698 690 DEREF_REG_PR = neff_sign_extend((unsigned long)
699 DEREF_REG_PR = (unsigned long) frame->retcode | 0x01; 691 frame->retcode | 0x01);
700 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ?
701 (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
702 692
703 if (__copy_to_user(frame->retcode, 693 if (__copy_to_user(frame->retcode,
704 (void *)((unsigned long)sa_default_rt_restorer & (~1)), 16) != 0) 694 (void *)((unsigned long)sa_default_rt_restorer & (~1)), 16) != 0)
705 goto give_sigsegv; 695 goto give_sigsegv;
706 696
697 /* Cohere the trampoline with the I-cache. */
707 flush_icache_range(DEREF_REG_PR-1, DEREF_REG_PR-1+15); 698 flush_icache_range(DEREF_REG_PR-1, DEREF_REG_PR-1+15);
708 } 699 }
709 700
@@ -711,14 +702,11 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
711 * Set up registers for signal handler. 702 * Set up registers for signal handler.
712 * All edited pointers are subject to NEFF. 703 * All edited pointers are subject to NEFF.
713 */ 704 */
714 regs->regs[REG_SP] = (unsigned long) frame; 705 regs->regs[REG_SP] = neff_sign_extend((unsigned long)frame);
715 regs->regs[REG_SP] = (regs->regs[REG_SP] & NEFF_SIGN) ?
716 (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP];
717 regs->regs[REG_ARG1] = signal; /* Arg for signal handler */ 706 regs->regs[REG_ARG1] = signal; /* Arg for signal handler */
718 regs->regs[REG_ARG2] = (unsigned long long)(unsigned long)(signed long)&frame->info; 707 regs->regs[REG_ARG2] = (unsigned long long)(unsigned long)(signed long)&frame->info;
719 regs->regs[REG_ARG3] = (unsigned long long)(unsigned long)(signed long)&frame->uc.uc_mcontext; 708 regs->regs[REG_ARG3] = (unsigned long long)(unsigned long)(signed long)&frame->uc.uc_mcontext;
720 regs->pc = (unsigned long) ka->sa.sa_handler; 709 regs->pc = neff_sign_extend((unsigned long)ka->sa.sa_handler);
721 regs->pc = (regs->pc & NEFF_SIGN) ? (regs->pc | NEFF_MASK) : regs->pc;
722 710
723 set_fs(USER_DS); 711 set_fs(USER_DS);
724 712
diff --git a/arch/sh/kernel/stacktrace.c b/arch/sh/kernel/stacktrace.c
index 1a2a5eb76e41..c2e45c48409c 100644
--- a/arch/sh/kernel/stacktrace.c
+++ b/arch/sh/kernel/stacktrace.c
@@ -13,47 +13,93 @@
13#include <linux/stacktrace.h> 13#include <linux/stacktrace.h>
14#include <linux/thread_info.h> 14#include <linux/thread_info.h>
15#include <linux/module.h> 15#include <linux/module.h>
16#include <asm/unwinder.h>
16#include <asm/ptrace.h> 17#include <asm/ptrace.h>
18#include <asm/stacktrace.h>
19
20static void save_stack_warning(void *data, char *msg)
21{
22}
23
24static void
25save_stack_warning_symbol(void *data, char *msg, unsigned long symbol)
26{
27}
28
29static int save_stack_stack(void *data, char *name)
30{
31 return 0;
32}
17 33
18/* 34/*
19 * Save stack-backtrace addresses into a stack_trace buffer. 35 * Save stack-backtrace addresses into a stack_trace buffer.
20 */ 36 */
37static void save_stack_address(void *data, unsigned long addr, int reliable)
38{
39 struct stack_trace *trace = data;
40
41 if (!reliable)
42 return;
43
44 if (trace->skip > 0) {
45 trace->skip--;
46 return;
47 }
48
49 if (trace->nr_entries < trace->max_entries)
50 trace->entries[trace->nr_entries++] = addr;
51}
52
53static const struct stacktrace_ops save_stack_ops = {
54 .warning = save_stack_warning,
55 .warning_symbol = save_stack_warning_symbol,
56 .stack = save_stack_stack,
57 .address = save_stack_address,
58};
59
21void save_stack_trace(struct stack_trace *trace) 60void save_stack_trace(struct stack_trace *trace)
22{ 61{
23 unsigned long *sp = (unsigned long *)current_stack_pointer; 62 unsigned long *sp = (unsigned long *)current_stack_pointer;
24 63
25 while (!kstack_end(sp)) { 64 unwind_stack(current, NULL, sp, &save_stack_ops, trace);
26 unsigned long addr = *sp++; 65 if (trace->nr_entries < trace->max_entries)
27 66 trace->entries[trace->nr_entries++] = ULONG_MAX;
28 if (__kernel_text_address(addr)) {
29 if (trace->skip > 0)
30 trace->skip--;
31 else
32 trace->entries[trace->nr_entries++] = addr;
33 if (trace->nr_entries >= trace->max_entries)
34 break;
35 }
36 }
37} 67}
38EXPORT_SYMBOL_GPL(save_stack_trace); 68EXPORT_SYMBOL_GPL(save_stack_trace);
39 69
70static void
71save_stack_address_nosched(void *data, unsigned long addr, int reliable)
72{
73 struct stack_trace *trace = (struct stack_trace *)data;
74
75 if (!reliable)
76 return;
77
78 if (in_sched_functions(addr))
79 return;
80
81 if (trace->skip > 0) {
82 trace->skip--;
83 return;
84 }
85
86 if (trace->nr_entries < trace->max_entries)
87 trace->entries[trace->nr_entries++] = addr;
88}
89
90static const struct stacktrace_ops save_stack_ops_nosched = {
91 .warning = save_stack_warning,
92 .warning_symbol = save_stack_warning_symbol,
93 .stack = save_stack_stack,
94 .address = save_stack_address_nosched,
95};
96
40void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) 97void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
41{ 98{
42 unsigned long *sp = (unsigned long *)tsk->thread.sp; 99 unsigned long *sp = (unsigned long *)tsk->thread.sp;
43 100
44 while (!kstack_end(sp)) { 101 unwind_stack(current, NULL, sp, &save_stack_ops_nosched, trace);
45 unsigned long addr = *sp++; 102 if (trace->nr_entries < trace->max_entries)
46 103 trace->entries[trace->nr_entries++] = ULONG_MAX;
47 if (__kernel_text_address(addr)) {
48 if (in_sched_functions(addr))
49 break;
50 if (trace->skip > 0)
51 trace->skip--;
52 else
53 trace->entries[trace->nr_entries++] = addr;
54 if (trace->nr_entries >= trace->max_entries)
55 break;
56 }
57 }
58} 104}
59EXPORT_SYMBOL_GPL(save_stack_trace_tsk); 105EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
diff --git a/arch/sh/kernel/sys_sh.c b/arch/sh/kernel/sys_sh.c
index 90d00e47264d..8aa5d1ceaf14 100644
--- a/arch/sh/kernel/sys_sh.c
+++ b/arch/sh/kernel/sys_sh.c
@@ -25,6 +25,8 @@
25#include <asm/syscalls.h> 25#include <asm/syscalls.h>
26#include <asm/uaccess.h> 26#include <asm/uaccess.h>
27#include <asm/unistd.h> 27#include <asm/unistd.h>
28#include <asm/cacheflush.h>
29#include <asm/cachectl.h>
28 30
29static inline long 31static inline long
30do_mmap2(unsigned long addr, unsigned long len, unsigned long prot, 32do_mmap2(unsigned long addr, unsigned long len, unsigned long prot,
@@ -179,6 +181,47 @@ asmlinkage int sys_ipc(uint call, int first, int second,
179 return -EINVAL; 181 return -EINVAL;
180} 182}
181 183
184/* sys_cacheflush -- flush (part of) the processor cache. */
185asmlinkage int sys_cacheflush(unsigned long addr, unsigned long len, int op)
186{
187 struct vm_area_struct *vma;
188
189 if ((op <= 0) || (op > (CACHEFLUSH_D_PURGE|CACHEFLUSH_I)))
190 return -EINVAL;
191
192 /*
193 * Verify that the specified address region actually belongs
194 * to this process.
195 */
196 if (addr + len < addr)
197 return -EFAULT;
198
199 down_read(&current->mm->mmap_sem);
200 vma = find_vma (current->mm, addr);
201 if (vma == NULL || addr < vma->vm_start || addr + len > vma->vm_end) {
202 up_read(&current->mm->mmap_sem);
203 return -EFAULT;
204 }
205
206 switch (op & CACHEFLUSH_D_PURGE) {
207 case CACHEFLUSH_D_INVAL:
208 __flush_invalidate_region((void *)addr, len);
209 break;
210 case CACHEFLUSH_D_WB:
211 __flush_wback_region((void *)addr, len);
212 break;
213 case CACHEFLUSH_D_PURGE:
214 __flush_purge_region((void *)addr, len);
215 break;
216 }
217
218 if (op & CACHEFLUSH_I)
219 flush_cache_all();
220
221 up_read(&current->mm->mmap_sem);
222 return 0;
223}
224
182asmlinkage int sys_uname(struct old_utsname __user *name) 225asmlinkage int sys_uname(struct old_utsname __user *name)
183{ 226{
184 int err; 227 int err;
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index f9e21fa2f592..16ba225ede89 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -139,7 +139,7 @@ ENTRY(sys_call_table)
139 .long sys_clone /* 120 */ 139 .long sys_clone /* 120 */
140 .long sys_setdomainname 140 .long sys_setdomainname
141 .long sys_newuname 141 .long sys_newuname
142 .long sys_ni_syscall /* sys_modify_ldt */ 142 .long sys_cacheflush /* x86: sys_modify_ldt */
143 .long sys_adjtimex 143 .long sys_adjtimex
144 .long sys_mprotect /* 125 */ 144 .long sys_mprotect /* 125 */
145 .long sys_sigprocmask 145 .long sys_sigprocmask
diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S
index bf420b616ae0..af6fb7410c21 100644
--- a/arch/sh/kernel/syscalls_64.S
+++ b/arch/sh/kernel/syscalls_64.S
@@ -143,7 +143,7 @@ sys_call_table:
143 .long sys_clone /* 120 */ 143 .long sys_clone /* 120 */
144 .long sys_setdomainname 144 .long sys_setdomainname
145 .long sys_newuname 145 .long sys_newuname
146 .long sys_ni_syscall /* sys_modify_ldt */ 146 .long sys_cacheflush /* x86: sys_modify_ldt */
147 .long sys_adjtimex 147 .long sys_adjtimex
148 .long sys_mprotect /* 125 */ 148 .long sys_mprotect /* 125 */
149 .long sys_sigprocmask 149 .long sys_sigprocmask
diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c
index 0e0e8581cf7a..953fa1613312 100644
--- a/arch/sh/kernel/time.c
+++ b/arch/sh/kernel/time.c
@@ -21,6 +21,7 @@
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <linux/rtc.h> 22#include <linux/rtc.h>
23#include <asm/clock.h> 23#include <asm/clock.h>
24#include <asm/hwblk.h>
24#include <asm/rtc.h> 25#include <asm/rtc.h>
25 26
26/* Dummy RTC ops */ 27/* Dummy RTC ops */
@@ -89,21 +90,8 @@ module_init(rtc_generic_init);
89 90
90void (*board_time_init)(void); 91void (*board_time_init)(void);
91 92
92void __init time_init(void) 93static void __init sh_late_time_init(void)
93{ 94{
94 if (board_time_init)
95 board_time_init();
96
97 clk_init();
98
99 rtc_sh_get_time(&xtime);
100 set_normalized_timespec(&wall_to_monotonic,
101 -xtime.tv_sec, -xtime.tv_nsec);
102
103#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
104 local_timer_setup(smp_processor_id());
105#endif
106
107 /* 95 /*
108 * Make sure all compiled-in early timers register themselves. 96 * Make sure all compiled-in early timers register themselves.
109 * 97 *
@@ -116,3 +104,18 @@ void __init time_init(void)
116 early_platform_driver_register_all("earlytimer"); 104 early_platform_driver_register_all("earlytimer");
117 early_platform_driver_probe("earlytimer", 2, 0); 105 early_platform_driver_probe("earlytimer", 2, 0);
118} 106}
107
108void __init time_init(void)
109{
110 if (board_time_init)
111 board_time_init();
112
113 hwblk_init();
114 clk_init();
115
116 rtc_sh_get_time(&xtime);
117 set_normalized_timespec(&wall_to_monotonic,
118 -xtime.tv_sec, -xtime.tv_nsec);
119
120 late_time_init = sh_late_time_init;
121}
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index b3e0067db358..a8396f36bd14 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -5,18 +5,33 @@
5#include <linux/signal.h> 5#include <linux/signal.h>
6#include <linux/sched.h> 6#include <linux/sched.h>
7#include <linux/uaccess.h> 7#include <linux/uaccess.h>
8#include <linux/hardirq.h>
9#include <asm/unwinder.h>
8#include <asm/system.h> 10#include <asm/system.h>
9 11
10#ifdef CONFIG_BUG 12#ifdef CONFIG_BUG
11static void handle_BUG(struct pt_regs *regs) 13void handle_BUG(struct pt_regs *regs)
12{ 14{
15 const struct bug_entry *bug;
16 unsigned long bugaddr = regs->pc;
13 enum bug_trap_type tt; 17 enum bug_trap_type tt;
14 tt = report_bug(regs->pc, regs); 18
19 if (!is_valid_bugaddr(bugaddr))
20 goto invalid;
21
22 bug = find_bug(bugaddr);
23
24 /* Switch unwinders when unwind_stack() is called */
25 if (bug->flags & BUGFLAG_UNWINDER)
26 unwinder_faulted = 1;
27
28 tt = report_bug(bugaddr, regs);
15 if (tt == BUG_TRAP_TYPE_WARN) { 29 if (tt == BUG_TRAP_TYPE_WARN) {
16 regs->pc += instruction_size(regs->pc); 30 regs->pc += instruction_size(bugaddr);
17 return; 31 return;
18 } 32 }
19 33
34invalid:
20 die("Kernel BUG", regs, TRAPA_BUG_OPCODE & 0xff); 35 die("Kernel BUG", regs, TRAPA_BUG_OPCODE & 0xff);
21} 36}
22 37
@@ -28,8 +43,10 @@ int is_valid_bugaddr(unsigned long addr)
28 return 0; 43 return 0;
29 if (probe_kernel_address((insn_size_t *)addr, opcode)) 44 if (probe_kernel_address((insn_size_t *)addr, opcode))
30 return 0; 45 return 0;
46 if (opcode == TRAPA_BUG_OPCODE)
47 return 1;
31 48
32 return opcode == TRAPA_BUG_OPCODE; 49 return 0;
33} 50}
34#endif 51#endif
35 52
@@ -75,3 +92,23 @@ BUILD_TRAP_HANDLER(bug)
75 92
76 force_sig(SIGTRAP, current); 93 force_sig(SIGTRAP, current);
77} 94}
95
96BUILD_TRAP_HANDLER(nmi)
97{
98 TRAP_HANDLER_DECL;
99
100 nmi_enter();
101
102 switch (notify_die(DIE_NMI, "NMI", regs, 0, vec & 0xff, SIGINT)) {
103 case NOTIFY_OK:
104 case NOTIFY_STOP:
105 break;
106 case NOTIFY_BAD:
107 die("Fatal Non-Maskable Interrupt", regs, SIGINT);
108 default:
109 printk(KERN_ALERT "Got NMI, but nobody cared. Ignoring...\n");
110 break;
111 }
112
113 nmi_exit();
114}
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index 2b772776fcda..6aba9af79eaf 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -24,6 +24,7 @@
24#include <linux/kdebug.h> 24#include <linux/kdebug.h>
25#include <linux/kexec.h> 25#include <linux/kexec.h>
26#include <linux/limits.h> 26#include <linux/limits.h>
27#include <linux/proc_fs.h>
27#include <asm/system.h> 28#include <asm/system.h>
28#include <asm/uaccess.h> 29#include <asm/uaccess.h>
29#include <asm/fpu.h> 30#include <asm/fpu.h>
@@ -44,6 +45,85 @@
44#define TRAP_ILLEGAL_SLOT_INST 13 45#define TRAP_ILLEGAL_SLOT_INST 13
45#endif 46#endif
46 47
48static unsigned long se_user;
49static unsigned long se_sys;
50static unsigned long se_half;
51static unsigned long se_word;
52static unsigned long se_dword;
53static unsigned long se_multi;
54/* bitfield: 1: warn 2: fixup 4: signal -> combinations 2|4 && 1|2|4 are not
55 valid! */
56static int se_usermode = 3;
57/* 0: no warning 1: print a warning message */
58static int se_kernmode_warn = 1;
59
60#ifdef CONFIG_PROC_FS
61static const char *se_usermode_action[] = {
62 "ignored",
63 "warn",
64 "fixup",
65 "fixup+warn",
66 "signal",
67 "signal+warn"
68};
69
70static int
71proc_alignment_read(char *page, char **start, off_t off, int count, int *eof,
72 void *data)
73{
74 char *p = page;
75 int len;
76
77 p += sprintf(p, "User:\t\t%lu\n", se_user);
78 p += sprintf(p, "System:\t\t%lu\n", se_sys);
79 p += sprintf(p, "Half:\t\t%lu\n", se_half);
80 p += sprintf(p, "Word:\t\t%lu\n", se_word);
81 p += sprintf(p, "DWord:\t\t%lu\n", se_dword);
82 p += sprintf(p, "Multi:\t\t%lu\n", se_multi);
83 p += sprintf(p, "User faults:\t%i (%s)\n", se_usermode,
84 se_usermode_action[se_usermode]);
85 p += sprintf(p, "Kernel faults:\t%i (fixup%s)\n", se_kernmode_warn,
86 se_kernmode_warn ? "+warn" : "");
87
88 len = (p - page) - off;
89 if (len < 0)
90 len = 0;
91
92 *eof = (len <= count) ? 1 : 0;
93 *start = page + off;
94
95 return len;
96}
97
98static int proc_alignment_write(struct file *file, const char __user *buffer,
99 unsigned long count, void *data)
100{
101 char mode;
102
103 if (count > 0) {
104 if (get_user(mode, buffer))
105 return -EFAULT;
106 if (mode >= '0' && mode <= '5')
107 se_usermode = mode - '0';
108 }
109 return count;
110}
111
112static int proc_alignment_kern_write(struct file *file, const char __user *buffer,
113 unsigned long count, void *data)
114{
115 char mode;
116
117 if (count > 0) {
118 if (get_user(mode, buffer))
119 return -EFAULT;
120 if (mode >= '0' && mode <= '1')
121 se_kernmode_warn = mode - '0';
122 }
123 return count;
124}
125#endif
126
47static void dump_mem(const char *str, unsigned long bottom, unsigned long top) 127static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
48{ 128{
49 unsigned long p; 129 unsigned long p;
@@ -136,6 +216,7 @@ static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
136 regs->pc = fixup->fixup; 216 regs->pc = fixup->fixup;
137 return; 217 return;
138 } 218 }
219
139 die(str, regs, err); 220 die(str, regs, err);
140 } 221 }
141} 222}
@@ -193,6 +274,13 @@ static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
193 274
194 count = 1<<(instruction&3); 275 count = 1<<(instruction&3);
195 276
277 switch (count) {
278 case 1: se_half += 1; break;
279 case 2: se_word += 1; break;
280 case 4: se_dword += 1; break;
281 case 8: se_multi += 1; break; /* ??? */
282 }
283
196 ret = -EFAULT; 284 ret = -EFAULT;
197 switch (instruction>>12) { 285 switch (instruction>>12) {
198 case 0: /* mov.[bwl] to/from memory via r0+rn */ 286 case 0: /* mov.[bwl] to/from memory via r0+rn */
@@ -358,15 +446,8 @@ static inline int handle_delayslot(struct pt_regs *regs,
358#define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) 446#define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
359#define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) 447#define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
360 448
361/*
362 * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
363 * opcodes..
364 */
365
366static int handle_unaligned_notify_count = 10;
367
368int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, 449int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
369 struct mem_access *ma) 450 struct mem_access *ma, int expected)
370{ 451{
371 u_int rm; 452 u_int rm;
372 int ret, index; 453 int ret, index;
@@ -374,15 +455,13 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
374 index = (instruction>>8)&15; /* 0x0F00 */ 455 index = (instruction>>8)&15; /* 0x0F00 */
375 rm = regs->regs[index]; 456 rm = regs->regs[index];
376 457
377 /* shout about the first ten userspace fixups */ 458 /* shout about fixups */
378 if (user_mode(regs) && handle_unaligned_notify_count>0) { 459 if (!expected && printk_ratelimit())
379 handle_unaligned_notify_count--; 460 printk(KERN_NOTICE "Fixing up unaligned %s access "
380
381 printk(KERN_NOTICE "Fixing up unaligned userspace access "
382 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", 461 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
462 user_mode(regs) ? "userspace" : "kernel",
383 current->comm, task_pid_nr(current), 463 current->comm, task_pid_nr(current),
384 (void *)regs->pc, instruction); 464 (void *)regs->pc, instruction);
385 }
386 465
387 ret = -EFAULT; 466 ret = -EFAULT;
388 switch (instruction&0xF000) { 467 switch (instruction&0xF000) {
@@ -538,6 +617,36 @@ asmlinkage void do_address_error(struct pt_regs *regs,
538 617
539 local_irq_enable(); 618 local_irq_enable();
540 619
620 se_user += 1;
621
622#ifndef CONFIG_CPU_SH2A
623 set_fs(USER_DS);
624 if (copy_from_user(&instruction, (u16 *)(regs->pc & ~1), 2)) {
625 set_fs(oldfs);
626 goto uspace_segv;
627 }
628 set_fs(oldfs);
629
630 /* shout about userspace fixups */
631 if (se_usermode & 1)
632 printk(KERN_NOTICE "Unaligned userspace access "
633 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
634 current->comm, current->pid, (void *)regs->pc,
635 instruction);
636#endif
637
638 if (se_usermode & 2)
639 goto fixup;
640
641 if (se_usermode & 4)
642 goto uspace_segv;
643 else {
644 /* ignore */
645 regs->pc += instruction_size(instruction);
646 return;
647 }
648
649fixup:
541 /* bad PC is not something we can fix */ 650 /* bad PC is not something we can fix */
542 if (regs->pc & 1) { 651 if (regs->pc & 1) {
543 si_code = BUS_ADRALN; 652 si_code = BUS_ADRALN;
@@ -545,17 +654,8 @@ asmlinkage void do_address_error(struct pt_regs *regs,
545 } 654 }
546 655
547 set_fs(USER_DS); 656 set_fs(USER_DS);
548 if (copy_from_user(&instruction, (void __user *)(regs->pc),
549 sizeof(instruction))) {
550 /* Argh. Fault on the instruction itself.
551 This should never happen non-SMP
552 */
553 set_fs(oldfs);
554 goto uspace_segv;
555 }
556
557 tmp = handle_unaligned_access(instruction, regs, 657 tmp = handle_unaligned_access(instruction, regs,
558 &user_mem_access); 658 &user_mem_access, 0);
559 set_fs(oldfs); 659 set_fs(oldfs);
560 660
561 if (tmp==0) 661 if (tmp==0)
@@ -571,6 +671,14 @@ uspace_segv:
571 info.si_addr = (void __user *)address; 671 info.si_addr = (void __user *)address;
572 force_sig_info(SIGBUS, &info, current); 672 force_sig_info(SIGBUS, &info, current);
573 } else { 673 } else {
674 se_sys += 1;
675
676 if (se_kernmode_warn)
677 printk(KERN_NOTICE "Unaligned kernel access "
678 "on behalf of \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
679 current->comm, current->pid, (void *)regs->pc,
680 instruction);
681
574 if (regs->pc & 1) 682 if (regs->pc & 1)
575 die("unaligned program counter", regs, error_code); 683 die("unaligned program counter", regs, error_code);
576 684
@@ -584,7 +692,8 @@ uspace_segv:
584 die("insn faulting in do_address_error", regs, 0); 692 die("insn faulting in do_address_error", regs, 0);
585 } 693 }
586 694
587 handle_unaligned_access(instruction, regs, &user_mem_access); 695 handle_unaligned_access(instruction, regs,
696 &user_mem_access, 0);
588 set_fs(oldfs); 697 set_fs(oldfs);
589 } 698 }
590} 699}
@@ -858,30 +967,6 @@ void __init trap_init(void)
858 per_cpu_trap_init(); 967 per_cpu_trap_init();
859} 968}
860 969
861void show_trace(struct task_struct *tsk, unsigned long *sp,
862 struct pt_regs *regs)
863{
864 unsigned long addr;
865
866 if (regs && user_mode(regs))
867 return;
868
869 printk("\nCall trace:\n");
870
871 while (!kstack_end(sp)) {
872 addr = *sp++;
873 if (kernel_text_address(addr))
874 print_ip_sym(addr);
875 }
876
877 printk("\n");
878
879 if (!tsk)
880 tsk = current;
881
882 debug_show_held_locks(tsk);
883}
884
885void show_stack(struct task_struct *tsk, unsigned long *sp) 970void show_stack(struct task_struct *tsk, unsigned long *sp)
886{ 971{
887 unsigned long stack; 972 unsigned long stack;
@@ -904,3 +989,38 @@ void dump_stack(void)
904 show_stack(NULL, NULL); 989 show_stack(NULL, NULL);
905} 990}
906EXPORT_SYMBOL(dump_stack); 991EXPORT_SYMBOL(dump_stack);
992
993#ifdef CONFIG_PROC_FS
994/*
995 * This needs to be done after sysctl_init, otherwise sys/ will be
996 * overwritten. Actually, this shouldn't be in sys/ at all since
997 * it isn't a sysctl, and it doesn't contain sysctl information.
998 * We now locate it in /proc/cpu/alignment instead.
999 */
1000static int __init alignment_init(void)
1001{
1002 struct proc_dir_entry *dir, *res;
1003
1004 dir = proc_mkdir("cpu", NULL);
1005 if (!dir)
1006 return -ENOMEM;
1007
1008 res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, dir);
1009 if (!res)
1010 return -ENOMEM;
1011
1012 res->read_proc = proc_alignment_read;
1013 res->write_proc = proc_alignment_write;
1014
1015 res = create_proc_entry("kernel_alignment", S_IWUSR | S_IRUGO, dir);
1016 if (!res)
1017 return -ENOMEM;
1018
1019 res->read_proc = proc_alignment_read;
1020 res->write_proc = proc_alignment_kern_write;
1021
1022 return 0;
1023}
1024
1025fs_initcall(alignment_init);
1026#endif
diff --git a/arch/sh/kernel/unwinder.c b/arch/sh/kernel/unwinder.c
new file mode 100644
index 000000000000..468889d958f4
--- /dev/null
+++ b/arch/sh/kernel/unwinder.c
@@ -0,0 +1,164 @@
1/*
2 * Copyright (C) 2009 Matt Fleming
3 *
4 * Based, in part, on kernel/time/clocksource.c.
5 *
6 * This file provides arbitration code for stack unwinders.
7 *
8 * Multiple stack unwinders can be available on a system, usually with
9 * the most accurate unwinder being the currently active one.
10 */
11#include <linux/errno.h>
12#include <linux/list.h>
13#include <linux/spinlock.h>
14#include <linux/module.h>
15#include <asm/unwinder.h>
16#include <asm/atomic.h>
17
18/*
19 * This is the most basic stack unwinder an architecture can
20 * provide. For architectures without reliable frame pointers, e.g.
21 * RISC CPUs, it can be implemented by looking through the stack for
22 * addresses that lie within the kernel text section.
23 *
24 * Other CPUs, e.g. x86, can use their frame pointer register to
25 * construct more accurate stack traces.
26 */
27static struct list_head unwinder_list;
28static struct unwinder stack_reader = {
29 .name = "stack-reader",
30 .dump = stack_reader_dump,
31 .rating = 50,
32 .list = {
33 .next = &unwinder_list,
34 .prev = &unwinder_list,
35 },
36};
37
38/*
39 * "curr_unwinder" points to the stack unwinder currently in use. This
40 * is the unwinder with the highest rating.
41 *
42 * "unwinder_list" is a linked-list of all available unwinders, sorted
43 * by rating.
44 *
45 * All modifications of "curr_unwinder" and "unwinder_list" must be
46 * performed whilst holding "unwinder_lock".
47 */
48static struct unwinder *curr_unwinder = &stack_reader;
49
50static struct list_head unwinder_list = {
51 .next = &stack_reader.list,
52 .prev = &stack_reader.list,
53};
54
55static DEFINE_SPINLOCK(unwinder_lock);
56
57/**
58 * select_unwinder - Select the best registered stack unwinder.
59 *
60 * Private function. Must hold unwinder_lock when called.
61 *
62 * Select the stack unwinder with the best rating. This is useful for
63 * setting up curr_unwinder.
64 */
65static struct unwinder *select_unwinder(void)
66{
67 struct unwinder *best;
68
69 if (list_empty(&unwinder_list))
70 return NULL;
71
72 best = list_entry(unwinder_list.next, struct unwinder, list);
73 if (best == curr_unwinder)
74 return NULL;
75
76 return best;
77}
78
79/*
80 * Enqueue the stack unwinder sorted by rating.
81 */
82static int unwinder_enqueue(struct unwinder *ops)
83{
84 struct list_head *tmp, *entry = &unwinder_list;
85
86 list_for_each(tmp, &unwinder_list) {
87 struct unwinder *o;
88
89 o = list_entry(tmp, struct unwinder, list);
90 if (o == ops)
91 return -EBUSY;
92 /* Keep track of the place, where to insert */
93 if (o->rating >= ops->rating)
94 entry = tmp;
95 }
96 list_add(&ops->list, entry);
97
98 return 0;
99}
100
101/**
102 * unwinder_register - Used to install new stack unwinder
103 * @u: unwinder to be registered
104 *
105 * Install the new stack unwinder on the unwinder list, which is sorted
106 * by rating.
107 *
108 * Returns -EBUSY if registration fails, zero otherwise.
109 */
110int unwinder_register(struct unwinder *u)
111{
112 unsigned long flags;
113 int ret;
114
115 spin_lock_irqsave(&unwinder_lock, flags);
116 ret = unwinder_enqueue(u);
117 if (!ret)
118 curr_unwinder = select_unwinder();
119 spin_unlock_irqrestore(&unwinder_lock, flags);
120
121 return ret;
122}
123
124int unwinder_faulted = 0;
125
126/*
127 * Unwind the call stack and pass information to the stacktrace_ops
128 * functions. Also handle the case where we need to switch to a new
129 * stack dumper because the current one faulted unexpectedly.
130 */
131void unwind_stack(struct task_struct *task, struct pt_regs *regs,
132 unsigned long *sp, const struct stacktrace_ops *ops,
133 void *data)
134{
135 unsigned long flags;
136
137 /*
138 * The problem with unwinders with high ratings is that they are
139 * inherently more complicated than the simple ones with lower
140 * ratings. We are therefore more likely to fault in the
141 * complicated ones, e.g. hitting BUG()s. If we fault in the
142 * code for the current stack unwinder we try to downgrade to
143 * one with a lower rating.
144 *
145 * Hopefully this will give us a semi-reliable stacktrace so we
146 * can diagnose why curr_unwinder->dump() faulted.
147 */
148 if (unwinder_faulted) {
149 spin_lock_irqsave(&unwinder_lock, flags);
150
151 /* Make sure no one beat us to changing the unwinder */
152 if (unwinder_faulted && !list_is_singular(&unwinder_list)) {
153 list_del(&curr_unwinder->list);
154 curr_unwinder = select_unwinder();
155
156 unwinder_faulted = 0;
157 }
158
159 spin_unlock_irqrestore(&unwinder_lock, flags);
160 }
161
162 curr_unwinder->dump(task, regs, sp, ops, data);
163}
164EXPORT_SYMBOL_GPL(unwind_stack);
diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S
index 0ce254bca92f..a1e4ec24f1f5 100644
--- a/arch/sh/kernel/vmlinux.lds.S
+++ b/arch/sh/kernel/vmlinux.lds.S
@@ -12,7 +12,7 @@ OUTPUT_ARCH(sh)
12 12
13#include <asm/thread_info.h> 13#include <asm/thread_info.h>
14#include <asm/cache.h> 14#include <asm/cache.h>
15#include <asm-generic/vmlinux.lds.h> 15#include <asm/vmlinux.lds.h>
16 16
17ENTRY(_start) 17ENTRY(_start)
18SECTIONS 18SECTIONS
@@ -50,12 +50,7 @@ SECTIONS
50 _etext = .; /* End of text section */ 50 _etext = .; /* End of text section */
51 } = 0x0009 51 } = 0x0009
52 52
53 . = ALIGN(16); /* Exception table */ 53 EXCEPTION_TABLE(16)
54 __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
55 __start___ex_table = .;
56 *(__ex_table)
57 __stop___ex_table = .;
58 }
59 54
60 NOTES 55 NOTES
61 RO_DATA(PAGE_SIZE) 56 RO_DATA(PAGE_SIZE)
@@ -71,69 +66,16 @@ SECTIONS
71 __uncached_end = .; 66 __uncached_end = .;
72 } 67 }
73 68
74 . = ALIGN(THREAD_SIZE); 69 RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
75 .data : AT(ADDR(.data) - LOAD_OFFSET) { /* Data */
76 *(.data.init_task)
77
78 . = ALIGN(L1_CACHE_BYTES);
79 *(.data.cacheline_aligned)
80
81 . = ALIGN(L1_CACHE_BYTES);
82 *(.data.read_mostly)
83
84 . = ALIGN(PAGE_SIZE);
85 *(.data.page_aligned)
86
87 __nosave_begin = .;
88 *(.data.nosave)
89 . = ALIGN(PAGE_SIZE);
90 __nosave_end = .;
91
92 DATA_DATA
93 CONSTRUCTORS
94 }
95 70
96 _edata = .; /* End of data section */ 71 _edata = .; /* End of data section */
97 72
98 . = ALIGN(PAGE_SIZE); /* Init code and data */ 73 DWARF_EH_FRAME
99 .init.text : AT(ADDR(.init.text) - LOAD_OFFSET) {
100 __init_begin = .;
101 _sinittext = .;
102 INIT_TEXT
103 _einittext = .;
104 }
105
106 .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) { INIT_DATA }
107
108 . = ALIGN(16);
109 .init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) {
110 __setup_start = .;
111 *(.init.setup)
112 __setup_end = .;
113 }
114
115 .initcall.init : AT(ADDR(.initcall.init) - LOAD_OFFSET) {
116 __initcall_start = .;
117 INITCALLS
118 __initcall_end = .;
119 }
120
121 .con_initcall.init : AT(ADDR(.con_initcall.init) - LOAD_OFFSET) {
122 __con_initcall_start = .;
123 *(.con_initcall.init)
124 __con_initcall_end = .;
125 }
126
127 SECURITY_INIT
128 74
129#ifdef CONFIG_BLK_DEV_INITRD 75 . = ALIGN(PAGE_SIZE); /* Init code and data */
130 . = ALIGN(PAGE_SIZE); 76 __init_begin = .;
131 .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) { 77 INIT_TEXT_SECTION(PAGE_SIZE)
132 __initramfs_start = .; 78 INIT_DATA_SECTION(16)
133 *(.init.ramfs)
134 __initramfs_end = .;
135 }
136#endif
137 79
138 . = ALIGN(4); 80 . = ALIGN(4);
139 .machvec.init : AT(ADDR(.machvec.init) - LOAD_OFFSET) { 81 .machvec.init : AT(ADDR(.machvec.init) - LOAD_OFFSET) {
@@ -152,25 +94,13 @@ SECTIONS
152 .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) { EXIT_DATA } 94 .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) { EXIT_DATA }
153 95
154 . = ALIGN(PAGE_SIZE); 96 . = ALIGN(PAGE_SIZE);
155 .bss : AT(ADDR(.bss) - LOAD_OFFSET) { 97 __init_end = .;
156 __init_end = .; 98 BSS_SECTION(0, PAGE_SIZE, 4)
157 __bss_start = .; /* BSS */ 99 _ebss = .; /* uClinux MTD sucks */
158 *(.bss.page_aligned) 100 _end = . ;
159 *(.bss)
160 *(COMMON)
161 . = ALIGN(4);
162 _ebss = .; /* uClinux MTD sucks */
163 _end = . ;
164 }
165 101
166 STABS_DEBUG 102 STABS_DEBUG
167 DWARF_DEBUG 103 DWARF_DEBUG
168 104
169 /*
170 * When something in the kernel is NOT compiled as a module, the
171 * module cleanup code and data are put into these segments. Both
172 * can then be thrown away, as cleanup code is never called unless
173 * it's a module.
174 */
175 DISCARDS 105 DISCARDS
176} 106}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-31 19:47:31 -0500