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authorPaul Mundt <lethal@linux-sh.org>2008-10-03 16:25:52 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-10-03 16:25:52 -0400
commit14866543ad22014a0b12e10657a917eb6b487248 (patch)
tree178f36abc7615347626ec28ee2bd0efffe5500ac /arch/sh/kernel/io_generic.c
parentbc0f424faa11a2017ba725bb8c5fc481ece7b440 (diff)
sh: More I/O routine overhauling.
This tidies up a lot of the PIO/MMIO split. No in-tree platforms were making use of the MMIO overloading through the machvec (nor have any of them been in some time), so we just kill all of that off. The ISA I/O routine wrapping remains unaffected, which remains the only special casing outside of the iomap API that boards need to think about. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/io_generic.c')
-rw-r--r--arch/sh/kernel/io_generic.c61
1 files changed, 13 insertions, 48 deletions
diff --git a/arch/sh/kernel/io_generic.c b/arch/sh/kernel/io_generic.c
index f1b214d3bce3..5a7f554d9ca1 100644
--- a/arch/sh/kernel/io_generic.c
+++ b/arch/sh/kernel/io_generic.c
@@ -19,38 +19,33 @@
19/* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a 19/* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a
20 * workaround. */ 20 * workaround. */
21/* I'm not sure SH7709 has this kind of bug */ 21/* I'm not sure SH7709 has this kind of bug */
22#define dummy_read() ctrl_inb(0xba000000) 22#define dummy_read() __raw_readb(0xba000000)
23#else 23#else
24#define dummy_read() 24#define dummy_read()
25#endif 25#endif
26 26
27unsigned long generic_io_base; 27unsigned long generic_io_base;
28 28
29static inline void delay(void)
30{
31 ctrl_inw(0xa0000000);
32}
33
34u8 generic_inb(unsigned long port) 29u8 generic_inb(unsigned long port)
35{ 30{
36 return ctrl_inb((unsigned long __force)__ioport_map(port, 1)); 31 return __raw_readb(__ioport_map(port, 1));
37} 32}
38 33
39u16 generic_inw(unsigned long port) 34u16 generic_inw(unsigned long port)
40{ 35{
41 return ctrl_inw((unsigned long __force)__ioport_map(port, 2)); 36 return __raw_readw(__ioport_map(port, 2));
42} 37}
43 38
44u32 generic_inl(unsigned long port) 39u32 generic_inl(unsigned long port)
45{ 40{
46 return ctrl_inl((unsigned long __force)__ioport_map(port, 4)); 41 return __raw_readl(__ioport_map(port, 4));
47} 42}
48 43
49u8 generic_inb_p(unsigned long port) 44u8 generic_inb_p(unsigned long port)
50{ 45{
51 unsigned long v = generic_inb(port); 46 unsigned long v = generic_inb(port);
52 47
53 delay(); 48 ctrl_delay();
54 return v; 49 return v;
55} 50}
56 51
@@ -58,7 +53,7 @@ u16 generic_inw_p(unsigned long port)
58{ 53{
59 unsigned long v = generic_inw(port); 54 unsigned long v = generic_inw(port);
60 55
61 delay(); 56 ctrl_delay();
62 return v; 57 return v;
63} 58}
64 59
@@ -66,7 +61,7 @@ u32 generic_inl_p(unsigned long port)
66{ 61{
67 unsigned long v = generic_inl(port); 62 unsigned long v = generic_inl(port);
68 63
69 delay(); 64 ctrl_delay();
70 return v; 65 return v;
71} 66}
72 67
@@ -112,35 +107,35 @@ void generic_insl(unsigned long port, void *dst, unsigned long count)
112 107
113void generic_outb(u8 b, unsigned long port) 108void generic_outb(u8 b, unsigned long port)
114{ 109{
115 ctrl_outb(b, (unsigned long __force)__ioport_map(port, 1)); 110 __raw_writeb(b, __ioport_map(port, 1));
116} 111}
117 112
118void generic_outw(u16 b, unsigned long port) 113void generic_outw(u16 b, unsigned long port)
119{ 114{
120 ctrl_outw(b, (unsigned long __force)__ioport_map(port, 2)); 115 __raw_writew(b, __ioport_map(port, 2));
121} 116}
122 117
123void generic_outl(u32 b, unsigned long port) 118void generic_outl(u32 b, unsigned long port)
124{ 119{
125 ctrl_outl(b, (unsigned long __force)__ioport_map(port, 4)); 120 __raw_writel(b, __ioport_map(port, 4));
126} 121}
127 122
128void generic_outb_p(u8 b, unsigned long port) 123void generic_outb_p(u8 b, unsigned long port)
129{ 124{
130 generic_outb(b, port); 125 generic_outb(b, port);
131 delay(); 126 ctrl_delay();
132} 127}
133 128
134void generic_outw_p(u16 b, unsigned long port) 129void generic_outw_p(u16 b, unsigned long port)
135{ 130{
136 generic_outw(b, port); 131 generic_outw(b, port);
137 delay(); 132 ctrl_delay();
138} 133}
139 134
140void generic_outl_p(u32 b, unsigned long port) 135void generic_outl_p(u32 b, unsigned long port)
141{ 136{
142 generic_outl(b, port); 137 generic_outl(b, port);
143 delay(); 138 ctrl_delay();
144} 139}
145 140
146/* 141/*
@@ -184,36 +179,6 @@ void generic_outsl(unsigned long port, const void *src, unsigned long count)
184 dummy_read(); 179 dummy_read();
185} 180}
186 181
187u8 generic_readb(void __iomem *addr)
188{
189 return ctrl_inb((unsigned long __force)addr);
190}
191
192u16 generic_readw(void __iomem *addr)
193{
194 return ctrl_inw((unsigned long __force)addr);
195}
196
197u32 generic_readl(void __iomem *addr)
198{
199 return ctrl_inl((unsigned long __force)addr);
200}
201
202void generic_writeb(u8 b, void __iomem *addr)
203{
204 ctrl_outb(b, (unsigned long __force)addr);
205}
206
207void generic_writew(u16 b, void __iomem *addr)
208{
209 ctrl_outw(b, (unsigned long __force)addr);
210}
211
212void generic_writel(u32 b, void __iomem *addr)
213{
214 ctrl_outl(b, (unsigned long __force)addr);
215}
216
217void __iomem *generic_ioport_map(unsigned long addr, unsigned int size) 182void __iomem *generic_ioport_map(unsigned long addr, unsigned int size)
218{ 183{
219 return (void __iomem *)(addr + generic_io_base); 184 return (void __iomem *)(addr + generic_io_base);