diff options
author | Paul Mundt <lethal@linux-sh.org> | 2007-09-21 05:32:32 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2007-09-21 05:32:32 -0400 |
commit | aba1030a7e529ec9fe47a8cfc06d12a39180fa71 (patch) | |
tree | a28de7f7b89610246fddf488f042b58c66101b95 /arch/sh/kernel/head.S | |
parent | f18d533e3cd476aedf41fe1e6e9dc3e0a2446bba (diff) |
sh: Bring SMP support back from the dead.
There was a very preliminary bunch of SMP code scattered around for the
SH7604 microcontrollers from way back when, and it has mostly suffered
bitrot since then. With the tree already having been slowly getting
prepped for SMP, this plugs in most of the remaining platform-independent
bits.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/head.S')
-rw-r--r-- | arch/sh/kernel/head.S | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/arch/sh/kernel/head.S b/arch/sh/kernel/head.S index 0bccc0ca5a0f..3338239717f1 100644 --- a/arch/sh/kernel/head.S +++ b/arch/sh/kernel/head.S | |||
@@ -54,8 +54,8 @@ ENTRY(_stext) | |||
54 | mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF | 54 | mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF |
55 | ldc r0, sr | 55 | ldc r0, sr |
56 | ! Initialize global interrupt mask | 56 | ! Initialize global interrupt mask |
57 | mov #0, r0 | ||
58 | #ifdef CONFIG_CPU_HAS_SR_RB | 57 | #ifdef CONFIG_CPU_HAS_SR_RB |
58 | mov #0, r0 | ||
59 | ldc r0, r6_bank | 59 | ldc r0, r6_bank |
60 | #endif | 60 | #endif |
61 | 61 | ||
@@ -72,15 +72,18 @@ ENTRY(_stext) | |||
72 | ! | 72 | ! |
73 | mov.l 2f, r0 | 73 | mov.l 2f, r0 |
74 | mov r0, r15 ! Set initial r15 (stack pointer) | 74 | mov r0, r15 ! Set initial r15 (stack pointer) |
75 | mov #(THREAD_SIZE >> 10), r1 | ||
76 | shll8 r1 ! r1 = THREAD_SIZE | ||
77 | shll2 r1 | ||
78 | sub r1, r0 ! | ||
79 | #ifdef CONFIG_CPU_HAS_SR_RB | 75 | #ifdef CONFIG_CPU_HAS_SR_RB |
76 | mov.l 7f, r0 | ||
80 | ldc r0, r7_bank ! ... and initial thread_info | 77 | ldc r0, r7_bank ! ... and initial thread_info |
81 | #endif | 78 | #endif |
82 | 79 | ||
83 | ! Clear BSS area | 80 | ! Clear BSS area |
81 | #ifdef CONFIG_SMP | ||
82 | mov.l 3f, r0 | ||
83 | cmp/eq #0, r0 ! skip clear if set to zero | ||
84 | bt 10f | ||
85 | #endif | ||
86 | |||
84 | mov.l 3f, r1 | 87 | mov.l 3f, r1 |
85 | add #4, r1 | 88 | add #4, r1 |
86 | mov.l 4f, r2 | 89 | mov.l 4f, r2 |
@@ -89,13 +92,14 @@ ENTRY(_stext) | |||
89 | bf/s 9b ! while (r1 < r2) | 92 | bf/s 9b ! while (r1 < r2) |
90 | mov.l r0,@-r2 | 93 | mov.l r0,@-r2 |
91 | 94 | ||
95 | 10: | ||
92 | ! Additional CPU initialization | 96 | ! Additional CPU initialization |
93 | mov.l 6f, r0 | 97 | mov.l 6f, r0 |
94 | jsr @r0 | 98 | jsr @r0 |
95 | nop | 99 | nop |
96 | 100 | ||
97 | SYNCO() ! Wait for pending instructions.. | 101 | SYNCO() ! Wait for pending instructions.. |
98 | 102 | ||
99 | ! Start kernel | 103 | ! Start kernel |
100 | mov.l 5f, r0 | 104 | mov.l 5f, r0 |
101 | jmp @r0 | 105 | jmp @r0 |
@@ -107,8 +111,10 @@ ENTRY(_stext) | |||
107 | #else | 111 | #else |
108 | 1: .long 0x400080F0 ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF | 112 | 1: .long 0x400080F0 ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF |
109 | #endif | 113 | #endif |
114 | ENTRY(stack_start) | ||
110 | 2: .long init_thread_union+THREAD_SIZE | 115 | 2: .long init_thread_union+THREAD_SIZE |
111 | 3: .long __bss_start | 116 | 3: .long __bss_start |
112 | 4: .long _end | 117 | 4: .long _end |
113 | 5: .long start_kernel | 118 | 5: .long start_kernel |
114 | 6: .long sh_cpu_init | 119 | 6: .long sh_cpu_init |
120 | 7: .long init_thread_union | ||