diff options
author | Paul Mundt <lethal@linux-sh.org> | 2006-02-01 06:06:01 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-02-01 11:53:19 -0500 |
commit | 091904ae5fc6f018680f83d71301ceac4f39d77f (patch) | |
tree | b82aa37495fd2378509730683a7607df29d49280 /arch/sh/kernel/entry.S | |
parent | 134ed1420eb5a3dd9827aa185dd37fe2dd0ab4d5 (diff) |
[PATCH] sh: Move TRA/EXPEVT/INTEVT definitions for reuse
Currently entry.S is home to these definitions, so we move them somewhere more
sensible. IPR IRQ handling depends on being to read from INTEVT.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/sh/kernel/entry.S')
-rw-r--r-- | arch/sh/kernel/entry.S | 18 |
1 files changed, 1 insertions, 17 deletions
diff --git a/arch/sh/kernel/entry.S b/arch/sh/kernel/entry.S index fb6368159dd0..a440d36ee618 100644 --- a/arch/sh/kernel/entry.S +++ b/arch/sh/kernel/entry.S | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/config.h> | 16 | #include <linux/config.h> |
17 | #include <asm/asm-offsets.h> | 17 | #include <asm/asm-offsets.h> |
18 | #include <asm/thread_info.h> | 18 | #include <asm/thread_info.h> |
19 | #include <asm/cpu/mmu_context.h> | ||
19 | #include <asm/unistd.h> | 20 | #include <asm/unistd.h> |
20 | 21 | ||
21 | #if !defined(CONFIG_NFSD) && !defined(CONFIG_NFSD_MODULE) | 22 | #if !defined(CONFIG_NFSD) && !defined(CONFIG_NFSD_MODULE) |
@@ -75,23 +76,6 @@ | |||
75 | ENOSYS = 38 | 76 | ENOSYS = 38 |
76 | EINVAL = 22 | 77 | EINVAL = 22 |
77 | 78 | ||
78 | #if defined(CONFIG_CPU_SH3) | ||
79 | TRA = 0xffffffd0 | ||
80 | EXPEVT = 0xffffffd4 | ||
81 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | ||
82 | defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) | ||
83 | INTEVT = 0xa4000000 ! INTEVTE2(0xa4000000) | ||
84 | #else | ||
85 | INTEVT = 0xffffffd8 | ||
86 | #endif | ||
87 | MMU_TEA = 0xfffffffc ! TLB Exception Address Register | ||
88 | #elif defined(CONFIG_CPU_SH4) | ||
89 | TRA = 0xff000020 | ||
90 | EXPEVT = 0xff000024 | ||
91 | INTEVT = 0xff000028 | ||
92 | MMU_TEA = 0xff00000c ! TLB Exception Address Register | ||
93 | #endif | ||
94 | |||
95 | #if defined(CONFIG_KGDB_NMI) | 79 | #if defined(CONFIG_KGDB_NMI) |
96 | NMI_VEC = 0x1c0 ! Must catch early for debounce | 80 | NMI_VEC = 0x1c0 ! Must catch early for debounce |
97 | #endif | 81 | #endif |