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authorMagnus Damm <damm@opensource.se>2011-01-06 06:10:09 -0500
committerPaul Mundt <lethal@linux-sh.org>2011-01-12 00:36:48 -0500
commit3a0f4c78999f9e8c1b66ddb98c8326be4b33cb49 (patch)
tree3c5157785d249d52725cba96f28c6532e234a82a /arch/sh/kernel/cpu
parente8a50ae37fcbe9e29cfbe1d1c3dc8eccee9fbb35 (diff)
sh: sh7343 Enable SDIO IRQs
This patch enables interrupt generation for SDIO IRQs of the SDHI block on the sh7343 processor. Use together with a recent SDHI driver using TMIO_MMC_SDIO_IRQ and with the MMC_CAP_SDIO_IRQ flag in the board code. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu')
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c25
1 files changed, 14 insertions, 11 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 3681cafdb4af..b8e5bc80aa4a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -360,6 +360,8 @@ void __init plat_early_device_setup(void)
360 360
361enum { 361enum {
362 UNUSED = 0, 362 UNUSED = 0,
363 ENABLED,
364 DISABLED,
363 365
364 /* interrupt sources */ 366 /* interrupt sources */
365 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 367 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -375,15 +377,13 @@ enum {
375 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 377 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
376 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 378 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
377 SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 379 SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
378 IRDA, 380 IRDA, SDHI, CMT, TSIF, SIU,
379 SDHI0, SDHI1, SDHI2, SDHI3,
380 CMT, TSIF, SIU,
381 TMU0, TMU1, TMU2, 381 TMU0, TMU1, TMU2,
382 JPU, LCDC, 382 JPU, LCDC,
383 383
384 /* interrupt groups */ 384 /* interrupt groups */
385 385
386 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB, 386 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB,
387}; 387};
388 388
389static struct intc_vect vectors[] __initdata = { 389static struct intc_vect vectors[] __initdata = {
@@ -412,8 +412,8 @@ static struct intc_vect vectors[] __initdata = {
412 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 412 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
413 INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20), 413 INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
414 INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60), 414 INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
415 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 415 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
416 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 416 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
417 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 417 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
418 INTC_VECT(SIU, 0xf80), 418 INTC_VECT(SIU, 0xf80),
419 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 419 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
@@ -431,7 +431,6 @@ static struct intc_group groups[] __initdata = {
431 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 431 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
432 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 432 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
433 INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI), 433 INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
434 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
435 INTC_GROUP(USB, USBI0, USBI1), 434 INTC_GROUP(USB, USBI0, USBI1),
436}; 435};
437 436
@@ -452,7 +451,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
452 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 451 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
453 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 452 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
454 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 453 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
455 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, 454 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
456 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 455 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
457 { 0, 0, 0, CMT, 0, USBI1, USBI0 } }, 456 { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
458 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 457 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -488,9 +487,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
488 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 487 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
489}; 488};
490 489
491static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups, 490static struct intc_desc intc_desc __initdata = {
492 mask_registers, prio_registers, sense_registers, 491 .name = "sh7343",
493 ack_registers); 492 .force_enable = ENABLED,
493 .force_disable = DISABLED,
494 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
495 prio_registers, sense_registers, ack_registers),
496};
494 497
495void __init plat_irq_setup(void) 498void __init plat_irq_setup(void)
496{ 499{