Merge branch 'sh-latest' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* 'sh-latest' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6:
  sh: include Migo-R TS driver in Migo-R defconfig
  sh: correct definitions to access stack pointers
  sh: Tidy up SH-4A unaligned load support.
  dma: shdma: NMI support.
  sh: mach-sdk7786: Handle baseboard NMI source selection.
  sh: mach-rsk: Add polled GPIO buttons support for RSK+7203.
  sh: Break out cpuinfo_op procfs bits.
  sh: Enable optional gpiolib for all CPUs with pinmux tables.
  sh: migrate SH_CLK_MD to mode pin API.
  sh: machvec IO death.

6 files changed, 189 insertions, 44 deletions

diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index 4edcb60a1355..d49c2135fd48 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -20,4 +20,4 @@ obj-$(CONFIG_SH_CLK_CPG_LEGACY)	+= clock-cpg.o
 obj-$(CONFIG_SH_FPU)            += fpu.o
 obj-$(CONFIG_SH_FPU_EMU)        += fpu.o
 
-obj-y   += irq/ init.o clock.o hwblk.o
+obj-y   += irq/ init.o clock.o hwblk.o proc.o
diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c
new file mode 100644
index 000000000000..e80a936f409a
--- /dev/null
+++ b/arch/sh/kernel/cpu/proc.c
@@ -0,0 +1,148 @@
+#include <linux/seq_file.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/machvec.h>
+#include <asm/processor.h>
+
+static const char *cpu_name[] = {
+        [CPU_SH7201]    = "SH7201",
+        [CPU_SH7203]    = "SH7203",     [CPU_SH7263]    = "SH7263",
+        [CPU_SH7206]    = "SH7206",     [CPU_SH7619]    = "SH7619",
+        [CPU_SH7705]    = "SH7705",     [CPU_SH7706]    = "SH7706",
+        [CPU_SH7707]    = "SH7707",     [CPU_SH7708]    = "SH7708",
+        [CPU_SH7709]    = "SH7709",     [CPU_SH7710]    = "SH7710",
+        [CPU_SH7712]    = "SH7712",     [CPU_SH7720]    = "SH7720",
+        [CPU_SH7721]    = "SH7721",     [CPU_SH7729]    = "SH7729",
+        [CPU_SH7750]    = "SH7750",     [CPU_SH7750S]   = "SH7750S",
+        [CPU_SH7750R]   = "SH7750R",    [CPU_SH7751]    = "SH7751",
+        [CPU_SH7751R]   = "SH7751R",    [CPU_SH7760]    = "SH7760",
+        [CPU_SH4_202]   = "SH4-202",    [CPU_SH4_501]   = "SH4-501",
+        [CPU_SH7763]    = "SH7763",     [CPU_SH7770]    = "SH7770",
+        [CPU_SH7780]    = "SH7780",     [CPU_SH7781]    = "SH7781",
+        [CPU_SH7343]    = "SH7343",     [CPU_SH7785]    = "SH7785",
+        [CPU_SH7786]    = "SH7786",     [CPU_SH7757]    = "SH7757",
+        [CPU_SH7722]    = "SH7722",     [CPU_SHX3]      = "SH-X3",
+        [CPU_SH5_101]   = "SH5-101",    [CPU_SH5_103]   = "SH5-103",
+        [CPU_MXG]       = "MX-G",       [CPU_SH7723]    = "SH7723",
+        [CPU_SH7366]    = "SH7366",     [CPU_SH7724]    = "SH7724",
+        [CPU_SH_NONE]   = "Unknown"
+};
+
+const char *get_cpu_subtype(struct sh_cpuinfo *c)
+{
+        return cpu_name[c->type];
+}
+EXPORT_SYMBOL(get_cpu_subtype);
+
+#ifdef CONFIG_PROC_FS
+/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
+static const char *cpu_flags[] = {
+        "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
+        "ptea", "llsc", "l2", "op32", "pteaex", NULL
+};
+
+static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
+{
+        unsigned long i;
+
+        seq_printf(m, "cpu flags\t:");
+
+        if (!c->flags) {
+                seq_printf(m, " %s\n", cpu_flags[0]);
+                return;
+        }
+
+        for (i = 0; cpu_flags[i]; i++)
+                if ((c->flags & (1 << i)))
+                        seq_printf(m, " %s", cpu_flags[i+1]);
+
+        seq_printf(m, "\n");
+}
+
+static void show_cacheinfo(struct seq_file *m, const char *type,
+                           struct cache_info info)
+{
+        unsigned int cache_size;
+
+        cache_size = info.ways * info.sets * info.linesz;
+
+        seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
+                   type, cache_size >> 10, info.ways);
+}
+
+/*
+ *      Get CPU information for use by the procfs.
+ */
+static int show_cpuinfo(struct seq_file *m, void *v)
+{
+        struct sh_cpuinfo *c = v;
+        unsigned int cpu = c - cpu_data;
+
+        if (!cpu_online(cpu))
+                return 0;
+
+        if (cpu == 0)
+                seq_printf(m, "machine\t\t: %s\n", get_system_type());
+        else
+                seq_printf(m, "\n");
+
+        seq_printf(m, "processor\t: %d\n", cpu);
+        seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
+        seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
+        if (c->cut_major == -1)
+                seq_printf(m, "cut\t\t: unknown\n");
+        else if (c->cut_minor == -1)
+                seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
+        else
+                seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
+
+        show_cpuflags(m, c);
+
+        seq_printf(m, "cache type\t: ");
+
+        /*
+         * Check for what type of cache we have, we support both the
+         * unified cache on the SH-2 and SH-3, as well as the harvard
+         * style cache on the SH-4.
+         */
+        if (c->icache.flags & SH_CACHE_COMBINED) {
+                seq_printf(m, "unified\n");
+                show_cacheinfo(m, "cache", c->icache);
+        } else {
+                seq_printf(m, "split (harvard)\n");
+                show_cacheinfo(m, "icache", c->icache);
+                show_cacheinfo(m, "dcache", c->dcache);
+        }
+
+        /* Optional secondary cache */
+        if (c->flags & CPU_HAS_L2_CACHE)
+                show_cacheinfo(m, "scache", c->scache);
+
+        seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);
+
+        seq_printf(m, "bogomips\t: %lu.%02lu\n",
+                     c->loops_per_jiffy/(500000/HZ),
+                     (c->loops_per_jiffy/(5000/HZ)) % 100);
+
+        return 0;
+}
+
+static void *c_start(struct seq_file *m, loff_t *pos)
+{
+        return *pos < NR_CPUS ? cpu_data + *pos : NULL;
+}
+static void *c_next(struct seq_file *m, void *v, loff_t *pos)
+{
+        ++*pos;
+        return c_start(m, pos);
+}
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+const struct seq_operations cpuinfo_op = {
+        .start  = c_start,
+        .next   = c_next,
+        .stop   = c_stop,
+        .show   = show_cpuinfo,
+};
+#endif /* CONFIG_PROC_FS */
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index 0c9f24d7a02f..5b7f12e58a8d 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -14,24 +14,18 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/io.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
-#include <asm/io.h>
+#include <asm/processor.h>
 
 static const int pll1rate[] = {1,2};
 static const int pfc_divisors[] = {1,2,0,4};
-
-#if (CONFIG_SH_CLK_MD == 1) || (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 5) || (CONFIG_SH_CLK_MD == 6)
-#define PLL2 (2)
-#else
-#error "Illigal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
+        clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
 }
 
 static struct clk_ops sh7619_master_clk_ops = {
@@ -70,6 +64,14 @@ static struct clk_ops *sh7619_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN2 | MODE_PIN0) ||
+            test_mode_pin(MODE_PIN2 | MODE_PIN1))
+                pll2_mult = 2;
+        else if (test_mode_pin(MODE_PIN0) || test_mode_pin(MODE_PIN1))
+                pll2_mult = 4;
+
+        BUG_ON(!pll2_mult);
+
         if (idx < ARRAY_SIZE(sh7619_clk_ops))
                 *ops = sh7619_clk_ops[idx];
 }
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index c509c40cba4b..1174e2d96c03 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -22,19 +22,12 @@ static const int pll1rate[]={1,2,3,4,6,8};
 static const int pfc_divisors[]={1,2,3,4,6,8,12};
 #define ifc_divisors pfc_divisors
 
-#if (CONFIG_SH_CLK_MD == 0)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (2)
-#elif (CONFIG_SH_CLK_MD == 3)
-#define PLL2 (1)
-#else
-#error "Illegal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate = 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
+        clk->rate = 10000000 * pll2_mult *
+               pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7201_master_clk_ops = {
@@ -80,6 +73,13 @@ static struct clk_ops *sh7201_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
+                pll2_mult = 1;
+        else if (test_mode_pin(MODE_PIN1))
+                pll2_mult = 2;
+        else
+                pll2_mult = 4;
+
         if (idx < ARRAY_SIZE(sh7201_clk_ops))
                 *ops = sh7201_clk_ops[idx];
 }
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index 7e75d8f79502..95a008e8b735 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -25,21 +25,11 @@ static const int pll1rate[]={8,12,16,0};
 static const int pfc_divisors[]={1,2,3,4,6,8,12};
 #define ifc_divisors pfc_divisors
 
-#if (CONFIG_SH_CLK_MD == 0)
-#define PLL2 (1)
-#elif (CONFIG_SH_CLK_MD == 1)
-#define PLL2 (2)
-#elif (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 3)
-#define PLL2 (4)
-#else
-#error "Illegal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * PLL2 ;
+        clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
 }
 
 static struct clk_ops sh7203_master_clk_ops = {
@@ -79,6 +69,13 @@ static struct clk_ops *sh7203_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN1))
+                pll2_mult = 4;
+        else if (test_mode_pin(MODE_PIN0))
+                pll2_mult = 2;
+        else
+                pll2_mult = 1;
+
         if (idx < ARRAY_SIZE(sh7203_clk_ops))
                 *ops = sh7203_clk_ops[idx];
 }
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index b27a5e2687ab..3c314d7cd6e6 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -22,19 +22,11 @@ static const int pll1rate[]={1,2,3,4,6,8};
 static const int pfc_divisors[]={1,2,3,4,6,8,12};
 #define ifc_divisors pfc_divisors
 
-#if (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 6)
-#define PLL2 (2)
-#elif (CONFIG_SH_CLK_MD == 7)
-#define PLL2 (1)
-#else
-#error "Illigal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
+        clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7206_master_clk_ops = {
@@ -79,7 +71,13 @@ static struct clk_ops *sh7206_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
+                pll2_mult = 1;
+        else if (test_mode_pin(MODE_PIN2 | MODE_PIN1))
+                pll2_mult = 2;
+        else if (test_mode_pin(MODE_PIN1))
+                pll2_mult = 4;
+
         if (idx < ARRAY_SIZE(sh7206_clk_ops))
                 *ops = sh7206_clk_ops[idx];
 }
-