diff options
author | Paul Mundt <lethal@linux-sh.org> | 2012-05-18 00:52:22 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2012-05-18 00:52:22 -0400 |
commit | f454314cff21155192d7358a9e890d7834078094 (patch) | |
tree | b58a976e81666a46c72710b7b719fe416f2ad357 /arch/sh/kernel/cpu | |
parent | ea3235d96297e7e99deec8419bd9568606d89996 (diff) |
sh: sh7770 evt2irq migration.
Migrate SH7770 to evt2irq() backed hwirq lookups.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7770.c | 39 |
1 files changed, 20 insertions, 19 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c index 2c6aa22cf5f6..256ea7a45164 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c | |||
@@ -12,6 +12,7 @@ | |||
12 | #include <linux/serial.h> | 12 | #include <linux/serial.h> |
13 | #include <linux/serial_sci.h> | 13 | #include <linux/serial_sci.h> |
14 | #include <linux/sh_timer.h> | 14 | #include <linux/sh_timer.h> |
15 | #include <linux/sh_intc.h> | ||
15 | #include <linux/io.h> | 16 | #include <linux/io.h> |
16 | 17 | ||
17 | static struct plat_sci_port scif0_platform_data = { | 18 | static struct plat_sci_port scif0_platform_data = { |
@@ -20,7 +21,7 @@ static struct plat_sci_port scif0_platform_data = { | |||
20 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 21 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
21 | .scbrr_algo_id = SCBRR_ALGO_2, | 22 | .scbrr_algo_id = SCBRR_ALGO_2, |
22 | .type = PORT_SCIF, | 23 | .type = PORT_SCIF, |
23 | .irqs = { 61, 61, 61, 61 }, | 24 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)), |
24 | }; | 25 | }; |
25 | 26 | ||
26 | static struct platform_device scif0_device = { | 27 | static struct platform_device scif0_device = { |
@@ -37,7 +38,7 @@ static struct plat_sci_port scif1_platform_data = { | |||
37 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 38 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
38 | .scbrr_algo_id = SCBRR_ALGO_2, | 39 | .scbrr_algo_id = SCBRR_ALGO_2, |
39 | .type = PORT_SCIF, | 40 | .type = PORT_SCIF, |
40 | .irqs = { 62, 62, 62, 62 }, | 41 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)), |
41 | }; | 42 | }; |
42 | 43 | ||
43 | static struct platform_device scif1_device = { | 44 | static struct platform_device scif1_device = { |
@@ -54,7 +55,7 @@ static struct plat_sci_port scif2_platform_data = { | |||
54 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 55 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
55 | .scbrr_algo_id = SCBRR_ALGO_2, | 56 | .scbrr_algo_id = SCBRR_ALGO_2, |
56 | .type = PORT_SCIF, | 57 | .type = PORT_SCIF, |
57 | .irqs = { 63, 63, 63, 63 }, | 58 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)), |
58 | }; | 59 | }; |
59 | 60 | ||
60 | static struct platform_device scif2_device = { | 61 | static struct platform_device scif2_device = { |
@@ -71,7 +72,7 @@ static struct plat_sci_port scif3_platform_data = { | |||
71 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 72 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
72 | .scbrr_algo_id = SCBRR_ALGO_2, | 73 | .scbrr_algo_id = SCBRR_ALGO_2, |
73 | .type = PORT_SCIF, | 74 | .type = PORT_SCIF, |
74 | .irqs = { 64, 64, 64, 64 }, | 75 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa00)), |
75 | }; | 76 | }; |
76 | 77 | ||
77 | static struct platform_device scif3_device = { | 78 | static struct platform_device scif3_device = { |
@@ -88,7 +89,7 @@ static struct plat_sci_port scif4_platform_data = { | |||
88 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 89 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
89 | .scbrr_algo_id = SCBRR_ALGO_2, | 90 | .scbrr_algo_id = SCBRR_ALGO_2, |
90 | .type = PORT_SCIF, | 91 | .type = PORT_SCIF, |
91 | .irqs = { 65, 65, 65, 65 }, | 92 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa20)), |
92 | }; | 93 | }; |
93 | 94 | ||
94 | static struct platform_device scif4_device = { | 95 | static struct platform_device scif4_device = { |
@@ -105,7 +106,7 @@ static struct plat_sci_port scif5_platform_data = { | |||
105 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 106 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
106 | .scbrr_algo_id = SCBRR_ALGO_2, | 107 | .scbrr_algo_id = SCBRR_ALGO_2, |
107 | .type = PORT_SCIF, | 108 | .type = PORT_SCIF, |
108 | .irqs = { 66, 66, 66, 66 }, | 109 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa40)), |
109 | }; | 110 | }; |
110 | 111 | ||
111 | static struct platform_device scif5_device = { | 112 | static struct platform_device scif5_device = { |
@@ -122,7 +123,7 @@ static struct plat_sci_port scif6_platform_data = { | |||
122 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 123 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
123 | .scbrr_algo_id = SCBRR_ALGO_2, | 124 | .scbrr_algo_id = SCBRR_ALGO_2, |
124 | .type = PORT_SCIF, | 125 | .type = PORT_SCIF, |
125 | .irqs = { 67, 67, 67, 67 }, | 126 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa60)), |
126 | }; | 127 | }; |
127 | 128 | ||
128 | static struct platform_device scif6_device = { | 129 | static struct platform_device scif6_device = { |
@@ -139,7 +140,7 @@ static struct plat_sci_port scif7_platform_data = { | |||
139 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 140 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
140 | .scbrr_algo_id = SCBRR_ALGO_2, | 141 | .scbrr_algo_id = SCBRR_ALGO_2, |
141 | .type = PORT_SCIF, | 142 | .type = PORT_SCIF, |
142 | .irqs = { 68, 68, 68, 68 }, | 143 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa80)), |
143 | }; | 144 | }; |
144 | 145 | ||
145 | static struct platform_device scif7_device = { | 146 | static struct platform_device scif7_device = { |
@@ -156,7 +157,7 @@ static struct plat_sci_port scif8_platform_data = { | |||
156 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 157 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
157 | .scbrr_algo_id = SCBRR_ALGO_2, | 158 | .scbrr_algo_id = SCBRR_ALGO_2, |
158 | .type = PORT_SCIF, | 159 | .type = PORT_SCIF, |
159 | .irqs = { 69, 69, 69, 69 }, | 160 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xaa0)), |
160 | }; | 161 | }; |
161 | 162 | ||
162 | static struct platform_device scif8_device = { | 163 | static struct platform_device scif8_device = { |
@@ -173,7 +174,7 @@ static struct plat_sci_port scif9_platform_data = { | |||
173 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 174 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
174 | .scbrr_algo_id = SCBRR_ALGO_2, | 175 | .scbrr_algo_id = SCBRR_ALGO_2, |
175 | .type = PORT_SCIF, | 176 | .type = PORT_SCIF, |
176 | .irqs = { 70, 70, 70, 70 }, | 177 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xac0)), |
177 | }; | 178 | }; |
178 | 179 | ||
179 | static struct platform_device scif9_device = { | 180 | static struct platform_device scif9_device = { |
@@ -197,7 +198,7 @@ static struct resource tmu0_resources[] = { | |||
197 | .flags = IORESOURCE_MEM, | 198 | .flags = IORESOURCE_MEM, |
198 | }, | 199 | }, |
199 | [1] = { | 200 | [1] = { |
200 | .start = 16, | 201 | .start = evt2irq(0x400), |
201 | .flags = IORESOURCE_IRQ, | 202 | .flags = IORESOURCE_IRQ, |
202 | }, | 203 | }, |
203 | }; | 204 | }; |
@@ -225,7 +226,7 @@ static struct resource tmu1_resources[] = { | |||
225 | .flags = IORESOURCE_MEM, | 226 | .flags = IORESOURCE_MEM, |
226 | }, | 227 | }, |
227 | [1] = { | 228 | [1] = { |
228 | .start = 17, | 229 | .start = evt2irq(0x420), |
229 | .flags = IORESOURCE_IRQ, | 230 | .flags = IORESOURCE_IRQ, |
230 | }, | 231 | }, |
231 | }; | 232 | }; |
@@ -252,7 +253,7 @@ static struct resource tmu2_resources[] = { | |||
252 | .flags = IORESOURCE_MEM, | 253 | .flags = IORESOURCE_MEM, |
253 | }, | 254 | }, |
254 | [1] = { | 255 | [1] = { |
255 | .start = 18, | 256 | .start = evt2irq(0x440), |
256 | .flags = IORESOURCE_IRQ, | 257 | .flags = IORESOURCE_IRQ, |
257 | }, | 258 | }, |
258 | }; | 259 | }; |
@@ -279,7 +280,7 @@ static struct resource tmu3_resources[] = { | |||
279 | .flags = IORESOURCE_MEM, | 280 | .flags = IORESOURCE_MEM, |
280 | }, | 281 | }, |
281 | [1] = { | 282 | [1] = { |
282 | .start = 19, | 283 | .start = evt2irq(0x460), |
283 | .flags = IORESOURCE_IRQ, | 284 | .flags = IORESOURCE_IRQ, |
284 | }, | 285 | }, |
285 | }; | 286 | }; |
@@ -306,7 +307,7 @@ static struct resource tmu4_resources[] = { | |||
306 | .flags = IORESOURCE_MEM, | 307 | .flags = IORESOURCE_MEM, |
307 | }, | 308 | }, |
308 | [1] = { | 309 | [1] = { |
309 | .start = 20, | 310 | .start = evt2irq(0x480), |
310 | .flags = IORESOURCE_IRQ, | 311 | .flags = IORESOURCE_IRQ, |
311 | }, | 312 | }, |
312 | }; | 313 | }; |
@@ -333,7 +334,7 @@ static struct resource tmu5_resources[] = { | |||
333 | .flags = IORESOURCE_MEM, | 334 | .flags = IORESOURCE_MEM, |
334 | }, | 335 | }, |
335 | [1] = { | 336 | [1] = { |
336 | .start = 21, | 337 | .start = evt2irq(0x4a0), |
337 | .flags = IORESOURCE_IRQ, | 338 | .flags = IORESOURCE_IRQ, |
338 | }, | 339 | }, |
339 | }; | 340 | }; |
@@ -360,7 +361,7 @@ static struct resource tmu6_resources[] = { | |||
360 | .flags = IORESOURCE_MEM, | 361 | .flags = IORESOURCE_MEM, |
361 | }, | 362 | }, |
362 | [1] = { | 363 | [1] = { |
363 | .start = 22, | 364 | .start = evt2irq(0x4c0), |
364 | .flags = IORESOURCE_IRQ, | 365 | .flags = IORESOURCE_IRQ, |
365 | }, | 366 | }, |
366 | }; | 367 | }; |
@@ -387,7 +388,7 @@ static struct resource tmu7_resources[] = { | |||
387 | .flags = IORESOURCE_MEM, | 388 | .flags = IORESOURCE_MEM, |
388 | }, | 389 | }, |
389 | [1] = { | 390 | [1] = { |
390 | .start = 23, | 391 | .start = evt2irq(0x4e0), |
391 | .flags = IORESOURCE_IRQ, | 392 | .flags = IORESOURCE_IRQ, |
392 | }, | 393 | }, |
393 | }; | 394 | }; |
@@ -414,7 +415,7 @@ static struct resource tmu8_resources[] = { | |||
414 | .flags = IORESOURCE_MEM, | 415 | .flags = IORESOURCE_MEM, |
415 | }, | 416 | }, |
416 | [1] = { | 417 | [1] = { |
417 | .start = 24, | 418 | .start = evt2irq(0x500), |
418 | .flags = IORESOURCE_IRQ, | 419 | .flags = IORESOURCE_IRQ, |
419 | }, | 420 | }, |
420 | }; | 421 | }; |