diff options
author | Paul Mundt <lethal@linux-sh.org> | 2012-05-17 23:57:59 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2012-05-17 23:57:59 -0400 |
commit | 933b954386dd6c8d04a0a406827e8c3febc619a5 (patch) | |
tree | a7250540625fe40b79af87fe62a09af7d1617c09 /arch/sh/kernel/cpu | |
parent | 29b53e375b7e7ca148cc6faab523a5bb920af833 (diff) |
sh: sh7723 evt2irq migration.
Migrate SH7723 to evt2irq() backed hwirq lookups.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7723.c | 47 |
1 files changed, 24 insertions, 23 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index a188c9ea4393..28d6fd835fe0 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c | |||
@@ -15,6 +15,7 @@ | |||
15 | #include <linux/uio_driver.h> | 15 | #include <linux/uio_driver.h> |
16 | #include <linux/usb/r8a66597.h> | 16 | #include <linux/usb/r8a66597.h> |
17 | #include <linux/sh_timer.h> | 17 | #include <linux/sh_timer.h> |
18 | #include <linux/sh_intc.h> | ||
18 | #include <linux/io.h> | 19 | #include <linux/io.h> |
19 | #include <asm/clock.h> | 20 | #include <asm/clock.h> |
20 | #include <asm/mmzone.h> | 21 | #include <asm/mmzone.h> |
@@ -28,7 +29,7 @@ static struct plat_sci_port scif0_platform_data = { | |||
28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 29 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
29 | .scbrr_algo_id = SCBRR_ALGO_2, | 30 | .scbrr_algo_id = SCBRR_ALGO_2, |
30 | .type = PORT_SCIF, | 31 | .type = PORT_SCIF, |
31 | .irqs = { 80, 80, 80, 80 }, | 32 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), |
32 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 33 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
33 | }; | 34 | }; |
34 | 35 | ||
@@ -47,7 +48,7 @@ static struct plat_sci_port scif1_platform_data = { | |||
47 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 48 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
48 | .scbrr_algo_id = SCBRR_ALGO_2, | 49 | .scbrr_algo_id = SCBRR_ALGO_2, |
49 | .type = PORT_SCIF, | 50 | .type = PORT_SCIF, |
50 | .irqs = { 81, 81, 81, 81 }, | 51 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), |
51 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 52 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
52 | }; | 53 | }; |
53 | 54 | ||
@@ -66,7 +67,7 @@ static struct plat_sci_port scif2_platform_data = { | |||
66 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 67 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
67 | .scbrr_algo_id = SCBRR_ALGO_2, | 68 | .scbrr_algo_id = SCBRR_ALGO_2, |
68 | .type = PORT_SCIF, | 69 | .type = PORT_SCIF, |
69 | .irqs = { 82, 82, 82, 82 }, | 70 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), |
70 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 71 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
71 | }; | 72 | }; |
72 | 73 | ||
@@ -85,7 +86,7 @@ static struct plat_sci_port scif3_platform_data = { | |||
85 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 86 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
86 | .scbrr_algo_id = SCBRR_ALGO_3, | 87 | .scbrr_algo_id = SCBRR_ALGO_3, |
87 | .type = PORT_SCIFA, | 88 | .type = PORT_SCIFA, |
88 | .irqs = { 56, 56, 56, 56 }, | 89 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), |
89 | }; | 90 | }; |
90 | 91 | ||
91 | static struct platform_device scif3_device = { | 92 | static struct platform_device scif3_device = { |
@@ -103,7 +104,7 @@ static struct plat_sci_port scif4_platform_data = { | |||
103 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 104 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
104 | .scbrr_algo_id = SCBRR_ALGO_3, | 105 | .scbrr_algo_id = SCBRR_ALGO_3, |
105 | .type = PORT_SCIFA, | 106 | .type = PORT_SCIFA, |
106 | .irqs = { 88, 88, 88, 88 }, | 107 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), |
107 | }; | 108 | }; |
108 | 109 | ||
109 | static struct platform_device scif4_device = { | 110 | static struct platform_device scif4_device = { |
@@ -121,7 +122,7 @@ static struct plat_sci_port scif5_platform_data = { | |||
121 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 122 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
122 | .scbrr_algo_id = SCBRR_ALGO_3, | 123 | .scbrr_algo_id = SCBRR_ALGO_3, |
123 | .type = PORT_SCIFA, | 124 | .type = PORT_SCIFA, |
124 | .irqs = { 109, 109, 109, 109 }, | 125 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), |
125 | }; | 126 | }; |
126 | 127 | ||
127 | static struct platform_device scif5_device = { | 128 | static struct platform_device scif5_device = { |
@@ -135,7 +136,7 @@ static struct platform_device scif5_device = { | |||
135 | static struct uio_info vpu_platform_data = { | 136 | static struct uio_info vpu_platform_data = { |
136 | .name = "VPU5", | 137 | .name = "VPU5", |
137 | .version = "0", | 138 | .version = "0", |
138 | .irq = 60, | 139 | .irq = evt2irq(0x980), |
139 | }; | 140 | }; |
140 | 141 | ||
141 | static struct resource vpu_resources[] = { | 142 | static struct resource vpu_resources[] = { |
@@ -163,7 +164,7 @@ static struct platform_device vpu_device = { | |||
163 | static struct uio_info veu0_platform_data = { | 164 | static struct uio_info veu0_platform_data = { |
164 | .name = "VEU2H", | 165 | .name = "VEU2H", |
165 | .version = "0", | 166 | .version = "0", |
166 | .irq = 54, | 167 | .irq = evt2irq(0x8c0), |
167 | }; | 168 | }; |
168 | 169 | ||
169 | static struct resource veu0_resources[] = { | 170 | static struct resource veu0_resources[] = { |
@@ -191,7 +192,7 @@ static struct platform_device veu0_device = { | |||
191 | static struct uio_info veu1_platform_data = { | 192 | static struct uio_info veu1_platform_data = { |
192 | .name = "VEU2H", | 193 | .name = "VEU2H", |
193 | .version = "0", | 194 | .version = "0", |
194 | .irq = 27, | 195 | .irq = evt2irq(0x560), |
195 | }; | 196 | }; |
196 | 197 | ||
197 | static struct resource veu1_resources[] = { | 198 | static struct resource veu1_resources[] = { |
@@ -230,7 +231,7 @@ static struct resource cmt_resources[] = { | |||
230 | .flags = IORESOURCE_MEM, | 231 | .flags = IORESOURCE_MEM, |
231 | }, | 232 | }, |
232 | [1] = { | 233 | [1] = { |
233 | .start = 104, | 234 | .start = evt2irq(0xf00), |
234 | .flags = IORESOURCE_IRQ, | 235 | .flags = IORESOURCE_IRQ, |
235 | }, | 236 | }, |
236 | }; | 237 | }; |
@@ -258,7 +259,7 @@ static struct resource tmu0_resources[] = { | |||
258 | .flags = IORESOURCE_MEM, | 259 | .flags = IORESOURCE_MEM, |
259 | }, | 260 | }, |
260 | [1] = { | 261 | [1] = { |
261 | .start = 16, | 262 | .start = evt2irq(0x400), |
262 | .flags = IORESOURCE_IRQ, | 263 | .flags = IORESOURCE_IRQ, |
263 | }, | 264 | }, |
264 | }; | 265 | }; |
@@ -286,7 +287,7 @@ static struct resource tmu1_resources[] = { | |||
286 | .flags = IORESOURCE_MEM, | 287 | .flags = IORESOURCE_MEM, |
287 | }, | 288 | }, |
288 | [1] = { | 289 | [1] = { |
289 | .start = 17, | 290 | .start = evt2irq(0x420), |
290 | .flags = IORESOURCE_IRQ, | 291 | .flags = IORESOURCE_IRQ, |
291 | }, | 292 | }, |
292 | }; | 293 | }; |
@@ -313,7 +314,7 @@ static struct resource tmu2_resources[] = { | |||
313 | .flags = IORESOURCE_MEM, | 314 | .flags = IORESOURCE_MEM, |
314 | }, | 315 | }, |
315 | [1] = { | 316 | [1] = { |
316 | .start = 18, | 317 | .start = evt2irq(0x440), |
317 | .flags = IORESOURCE_IRQ, | 318 | .flags = IORESOURCE_IRQ, |
318 | }, | 319 | }, |
319 | }; | 320 | }; |
@@ -340,7 +341,7 @@ static struct resource tmu3_resources[] = { | |||
340 | .flags = IORESOURCE_MEM, | 341 | .flags = IORESOURCE_MEM, |
341 | }, | 342 | }, |
342 | [1] = { | 343 | [1] = { |
343 | .start = 57, | 344 | .start = evt2irq(0x920), |
344 | .flags = IORESOURCE_IRQ, | 345 | .flags = IORESOURCE_IRQ, |
345 | }, | 346 | }, |
346 | }; | 347 | }; |
@@ -367,7 +368,7 @@ static struct resource tmu4_resources[] = { | |||
367 | .flags = IORESOURCE_MEM, | 368 | .flags = IORESOURCE_MEM, |
368 | }, | 369 | }, |
369 | [1] = { | 370 | [1] = { |
370 | .start = 58, | 371 | .start = evt2irq(0x940), |
371 | .flags = IORESOURCE_IRQ, | 372 | .flags = IORESOURCE_IRQ, |
372 | }, | 373 | }, |
373 | }; | 374 | }; |
@@ -394,7 +395,7 @@ static struct resource tmu5_resources[] = { | |||
394 | .flags = IORESOURCE_MEM, | 395 | .flags = IORESOURCE_MEM, |
395 | }, | 396 | }, |
396 | [1] = { | 397 | [1] = { |
397 | .start = 57, | 398 | .start = evt2irq(0x920), |
398 | .flags = IORESOURCE_IRQ, | 399 | .flags = IORESOURCE_IRQ, |
399 | }, | 400 | }, |
400 | }; | 401 | }; |
@@ -417,17 +418,17 @@ static struct resource rtc_resources[] = { | |||
417 | }, | 418 | }, |
418 | [1] = { | 419 | [1] = { |
419 | /* Period IRQ */ | 420 | /* Period IRQ */ |
420 | .start = 69, | 421 | .start = evt2irq(0xaa0), |
421 | .flags = IORESOURCE_IRQ, | 422 | .flags = IORESOURCE_IRQ, |
422 | }, | 423 | }, |
423 | [2] = { | 424 | [2] = { |
424 | /* Carry IRQ */ | 425 | /* Carry IRQ */ |
425 | .start = 70, | 426 | .start = evt2irq(0xac0), |
426 | .flags = IORESOURCE_IRQ, | 427 | .flags = IORESOURCE_IRQ, |
427 | }, | 428 | }, |
428 | [3] = { | 429 | [3] = { |
429 | /* Alarm IRQ */ | 430 | /* Alarm IRQ */ |
430 | .start = 68, | 431 | .start = evt2irq(0xa80), |
431 | .flags = IORESOURCE_IRQ, | 432 | .flags = IORESOURCE_IRQ, |
432 | }, | 433 | }, |
433 | }; | 434 | }; |
@@ -450,8 +451,8 @@ static struct resource sh7723_usb_host_resources[] = { | |||
450 | .flags = IORESOURCE_MEM, | 451 | .flags = IORESOURCE_MEM, |
451 | }, | 452 | }, |
452 | [1] = { | 453 | [1] = { |
453 | .start = 65, | 454 | .start = evt2irq(0xa20), |
454 | .end = 65, | 455 | .end = evt2irq(0xa20), |
455 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, | 456 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, |
456 | }, | 457 | }, |
457 | }; | 458 | }; |
@@ -476,8 +477,8 @@ static struct resource iic_resources[] = { | |||
476 | .flags = IORESOURCE_MEM, | 477 | .flags = IORESOURCE_MEM, |
477 | }, | 478 | }, |
478 | [1] = { | 479 | [1] = { |
479 | .start = 96, | 480 | .start = evt2irq(0xe00), |
480 | .end = 99, | 481 | .end = evt2irq(0xe60), |
481 | .flags = IORESOURCE_IRQ, | 482 | .flags = IORESOURCE_IRQ, |
482 | }, | 483 | }, |
483 | }; | 484 | }; |