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authorJames Bottomley <jejb@mulgrave.il.steeleye.com>2007-05-31 00:57:05 -0400
committerJames Bottomley <jejb@mulgrave.il.steeleye.com>2007-05-31 00:57:05 -0400
commit5bc65793cbf8da0d35f19ef025dda22887e79e80 (patch)
tree8291998abd73055de6f487fafa174ee2a5d3afee /arch/sh/kernel/cpu
parent6edae708bf77e012d855a7e2c7766f211d234f4f (diff)
parent3f0a6766e0cc5a577805732e5adb50a585c58175 (diff)
[SCSI] Merge up to linux-2.6 head
Conflicts: drivers/scsi/jazz_esp.c Same changes made by both SCSI and SPARC trees: problem with UTF-8 conversion in the copyright. Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'arch/sh/kernel/cpu')
-rw-r--r--arch/sh/kernel/cpu/clock.c7
-rw-r--r--arch/sh/kernel/cpu/irq/maskreg.c2
-rw-r--r--arch/sh/kernel/cpu/sh4/fpu.c2
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c34
5 files changed, 33 insertions, 14 deletions
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 014f318f5a05..63251549e9a8 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -278,6 +278,11 @@ arch_init_clk_ops(struct clk_ops **ops, int type)
278{ 278{
279} 279}
280 280
281void __init __attribute__ ((weak))
282arch_clk_init(void)
283{
284}
285
281static int show_clocks(char *buf, char **start, off_t off, 286static int show_clocks(char *buf, char **start, off_t off,
282 int len, int *eof, void *data) 287 int len, int *eof, void *data)
283{ 288{
@@ -314,6 +319,8 @@ int __init clk_init(void)
314 ret |= clk_register(clk); 319 ret |= clk_register(clk);
315 } 320 }
316 321
322 arch_clk_init();
323
317 /* Kick the child clocks.. */ 324 /* Kick the child clocks.. */
318 propagate_rate(&master_clk); 325 propagate_rate(&master_clk);
319 propagate_rate(&bus_clk); 326 propagate_rate(&bus_clk);
diff --git a/arch/sh/kernel/cpu/irq/maskreg.c b/arch/sh/kernel/cpu/irq/maskreg.c
index 492db31b3cab..978992e367a5 100644
--- a/arch/sh/kernel/cpu/irq/maskreg.c
+++ b/arch/sh/kernel/cpu/irq/maskreg.c
@@ -38,7 +38,7 @@ static struct hw_interrupt_type maskreg_irq_type = {
38 .end = end_maskreg_irq 38 .end = end_maskreg_irq
39}; 39};
40 40
41/* actual implementatin */ 41/* actual implementation */
42static unsigned int startup_maskreg_irq(unsigned int irq) 42static unsigned int startup_maskreg_irq(unsigned int irq)
43{ 43{
44 enable_maskreg_irq(irq); 44 enable_maskreg_irq(irq);
diff --git a/arch/sh/kernel/cpu/sh4/fpu.c b/arch/sh/kernel/cpu/sh4/fpu.c
index d61dd599169f..c5a4fc77fa06 100644
--- a/arch/sh/kernel/cpu/sh4/fpu.c
+++ b/arch/sh/kernel/cpu/sh4/fpu.c
@@ -138,7 +138,7 @@ restore_fpu(struct task_struct *tsk)
138/* 138/*
139 * Load the FPU with signalling NANS. This bit pattern we're using 139 * Load the FPU with signalling NANS. This bit pattern we're using
140 * has the property that no matter wether considered as single or as 140 * has the property that no matter wether considered as single or as
141 * double precission represents signaling NANS. 141 * double precision represents signaling NANS.
142 */ 142 */
143 143
144static void 144static void
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 6f8f458912c7..03b14cf78ddf 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -106,6 +106,7 @@ static struct ipr_data sh7750_ipr_map[] = {
106 { 38, 2, 8, 7 }, /* DMAC DMAE */ 106 { 38, 2, 8, 7 }, /* DMAC DMAE */
107}; 107};
108 108
109#ifdef CONFIG_CPU_SUBTYPE_SH7751
109static struct ipr_data sh7751_ipr_map[] = { 110static struct ipr_data sh7751_ipr_map[] = {
110 { 44, 2, 8, 7 }, /* DMAC DMTE4 */ 111 { 44, 2, 8, 7 }, /* DMAC DMTE4 */
111 { 45, 2, 8, 7 }, /* DMAC DMTE5 */ 112 { 45, 2, 8, 7 }, /* DMAC DMTE5 */
@@ -117,6 +118,7 @@ static struct ipr_data sh7751_ipr_map[] = {
117 /*{ 72, INTPRI00, 8, ? },*/ /* TMU3 TUNI */ 118 /*{ 72, INTPRI00, 8, ? },*/ /* TMU3 TUNI */
118 /*{ 76, INTPRI00, 12, ? },*/ /* TMU4 TUNI */ 119 /*{ 76, INTPRI00, 12, ? },*/ /* TMU4 TUNI */
119}; 120};
121#endif
120 122
121static unsigned long ipr_offsets[] = { 123static unsigned long ipr_offsets[] = {
122 0xffd00004UL, /* 0: IPRA */ 124 0xffd00004UL, /* 0: IPRA */
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 29090035bc5b..51b386d454de 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -17,7 +17,6 @@
17#include <asm/clock.h> 17#include <asm/clock.h>
18#include <asm/freq.h> 18#include <asm/freq.h>
19 19
20#define SH7722_PLL_FREQ (32000000/8)
21#define N (-1) 20#define N (-1)
22#define NM (-2) 21#define NM (-2)
23#define ROUND_NEAREST 0 22#define ROUND_NEAREST 0
@@ -141,28 +140,36 @@ static void adjust_clocks(int originate, int *l, unsigned long v[],
141*/ 140*/
142static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 }; 141static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
143 142
143static void master_clk_recalc(struct clk *clk)
144{
145 unsigned frqcr = ctrl_inl(FRQCR);
146
147 clk->rate = CONFIG_SH_PCLK_FREQ * (((frqcr >> 24) & 0x1f) + 1);
148}
149
144static void master_clk_init(struct clk *clk) 150static void master_clk_init(struct clk *clk)
145{ 151{
146 clk_set_rate(clk, clk_get_rate(clk)); 152 clk->parent = NULL;
153 clk->flags |= CLK_RATE_PROPAGATES;
154 clk->rate = CONFIG_SH_PCLK_FREQ;
155 master_clk_recalc(clk);
147} 156}
148 157
149static void master_clk_recalc(struct clk *clk) 158
159static void module_clk_recalc(struct clk *clk)
150{ 160{
151 unsigned long frqcr = ctrl_inl(FRQCR); 161 unsigned long frqcr = ctrl_inl(FRQCR);
152 162
153 clk->rate = CONFIG_SH_PCLK_FREQ * (1 + (frqcr >> 24 & 0xF)); 163 clk->rate = clk->parent->rate / (((frqcr >> 24) & 0x1f) + 1);
154} 164}
155 165
156static int master_clk_setrate(struct clk *clk, unsigned long rate, int id) 166static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
157{ 167{
158 int div = rate / SH7722_PLL_FREQ; 168 int div = rate / clk->rate;
159 int master_divs[] = { 2, 3, 4, 6, 8, 16 }; 169 int master_divs[] = { 2, 3, 4, 6, 8, 16 };
160 int index; 170 int index;
161 unsigned long frqcr; 171 unsigned long frqcr;
162 172
163 if (rate < SH7722_PLL_FREQ * 2)
164 return -EINVAL;
165
166 for (index = 1; index < ARRAY_SIZE(master_divs); index++) 173 for (index = 1; index < ARRAY_SIZE(master_divs); index++)
167 if (div >= master_divs[index - 1] && div < master_divs[index]) 174 if (div >= master_divs[index - 1] && div < master_divs[index])
168 break; 175 break;
@@ -185,6 +192,10 @@ static struct clk_ops sh7722_master_clk_ops = {
185 .set_rate = master_clk_setrate, 192 .set_rate = master_clk_setrate,
186}; 193};
187 194
195static struct clk_ops sh7722_module_clk_ops = {
196 .recalc = module_clk_recalc,
197};
198
188struct frqcr_context { 199struct frqcr_context {
189 unsigned mask; 200 unsigned mask;
190 unsigned shift; 201 unsigned shift;
@@ -489,7 +500,7 @@ static void sh7722_siu_recalc(struct clk *clk)
489 500
490 if (siu < 0) 501 if (siu < 0)
491 return /* siu */ ; 502 return /* siu */ ;
492 BUG_ON(siu > 1); 503 BUG_ON(siu > 2);
493 r = ctrl_inl(sh7722_siu_regs[siu]); 504 r = ctrl_inl(sh7722_siu_regs[siu]);
494 clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF]; 505 clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF];
495} 506}
@@ -571,7 +582,7 @@ static struct clk *sh7722_clocks[] = {
571 */ 582 */
572struct clk_ops *onchip_ops[] = { 583struct clk_ops *onchip_ops[] = {
573 &sh7722_master_clk_ops, 584 &sh7722_master_clk_ops,
574 &sh7722_frqcr_clk_ops, 585 &sh7722_module_clk_ops,
575 &sh7722_frqcr_clk_ops, 586 &sh7722_frqcr_clk_ops,
576 &sh7722_frqcr_clk_ops, 587 &sh7722_frqcr_clk_ops,
577}; 588};
@@ -583,7 +594,7 @@ arch_init_clk_ops(struct clk_ops **ops, int type)
583 *ops = onchip_ops[type]; 594 *ops = onchip_ops[type];
584} 595}
585 596
586int __init sh7722_clock_init(void) 597int __init arch_clk_init(void)
587{ 598{
588 struct clk *master; 599 struct clk *master;
589 int i; 600 int i;
@@ -597,4 +608,3 @@ int __init sh7722_clock_init(void)
597 clk_put(master); 608 clk_put(master);
598 return 0; 609 return 0;
599} 610}
600arch_initcall(sh7722_clock_init);