Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into common/serial-rework

Conflicts:
	arch/sh/kernel/cpu/sh2/setup-sh7619.c
	arch/sh/kernel/cpu/sh2a/setup-mxg.c
	arch/sh/kernel/cpu/sh2a/setup-sh7201.c
	arch/sh/kernel/cpu/sh2a/setup-sh7203.c
	arch/sh/kernel/cpu/sh2a/setup-sh7206.c
	arch/sh/kernel/cpu/sh3/setup-sh7705.c
	arch/sh/kernel/cpu/sh3/setup-sh770x.c
	arch/sh/kernel/cpu/sh3/setup-sh7710.c
	arch/sh/kernel/cpu/sh3/setup-sh7720.c
	arch/sh/kernel/cpu/sh4/setup-sh4-202.c
	arch/sh/kernel/cpu/sh4/setup-sh7750.c
	arch/sh/kernel/cpu/sh4/setup-sh7760.c
	arch/sh/kernel/cpu/sh4a/setup-sh7343.c
	arch/sh/kernel/cpu/sh4a/setup-sh7366.c
	arch/sh/kernel/cpu/sh4a/setup-sh7722.c
	arch/sh/kernel/cpu/sh4a/setup-sh7723.c
	arch/sh/kernel/cpu/sh4a/setup-sh7724.c
	arch/sh/kernel/cpu/sh4a/setup-sh7763.c
	arch/sh/kernel/cpu/sh4a/setup-sh7770.c
	arch/sh/kernel/cpu/sh4a/setup-sh7780.c
	arch/sh/kernel/cpu/sh4a/setup-sh7785.c
	arch/sh/kernel/cpu/sh4a/setup-sh7786.c
	arch/sh/kernel/cpu/sh4a/setup-shx3.c
	arch/sh/kernel/cpu/sh5/setup-sh5.c
	drivers/serial/sh-sci.c
	drivers/serial/sh-sci.h
	include/linux/serial_sci.h

95 files changed, 11132 insertions, 3710 deletions

diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index eecad7cbd61e..d49c2135fd48 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -15,8 +15,9 @@ obj-$(CONFIG_ARCH_SHMOBILE)	+= shmobile/
 
 # Common interfaces.
 
-obj-$(CONFIG_UBC_WAKEUP)        += ubc.o
 obj-$(CONFIG_SH_ADC)            += adc.o
-obj-$(CONFIG_SH_CLK_CPG)        += clock-cpg.o
+obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
+obj-$(CONFIG_SH_FPU)            += fpu.o
+obj-$(CONFIG_SH_FPU_EMU)        += fpu.o
 
-obj-y   += irq/ init.o clock.o
+obj-y   += irq/ init.o clock.o hwblk.o proc.o
diff --git a/arch/sh/kernel/cpu/adc.c b/arch/sh/kernel/cpu/adc.c
index da3d6877f93d..d307571d54b6 100644
--- a/arch/sh/kernel/cpu/adc.c
+++ b/arch/sh/kernel/cpu/adc.c
@@ -18,19 +18,19 @@ int adc_single(unsigned int channel)
 
         off = (channel & 0x03) << 2;
 
-        csr = ctrl_inb(ADCSR);
+        csr = __raw_readb(ADCSR);
         csr = channel | ADCSR_ADST | ADCSR_CKS;
-        ctrl_outb(csr, ADCSR);
+        __raw_writeb(csr, ADCSR);
 
         do {
-                csr = ctrl_inb(ADCSR);
+                csr = __raw_readb(ADCSR);
         } while ((csr & ADCSR_ADF) == 0);
 
         csr &= ~(ADCSR_ADF | ADCSR_ADST);
-        ctrl_outb(csr, ADCSR);
+        __raw_writeb(csr, ADCSR);
 
-        return (((ctrl_inb(ADDRAH + off) << 8) |
-                ctrl_inb(ADDRAL + off)) >> 6);
+        return (((__raw_readb(ADDRAH + off) << 8) |
+                __raw_readb(ADDRAL + off)) >> 6);
 }
 
 EXPORT_SYMBOL(adc_single);
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
index 6dfe2cced3fc..dd0e0f211359 100644
--- a/arch/sh/kernel/cpu/clock-cpg.c
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -2,223 +2,25 @@
 #include <linux/compiler.h>
 #include <linux/slab.h>
 #include <linux/io.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 
-static int sh_clk_mstp32_enable(struct clk *clk)
-{
-        __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
-                     clk->enable_reg);
-        return 0;
-}
-
-static void sh_clk_mstp32_disable(struct clk *clk)
-{
-        __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
-                     clk->enable_reg);
-}
-
-static struct clk_ops sh_clk_mstp32_clk_ops = {
-        .enable         = sh_clk_mstp32_enable,
-        .disable        = sh_clk_mstp32_disable,
-        .recalc         = followparent_recalc,
-};
-
-int __init sh_clk_mstp32_register(struct clk *clks, int nr)
-{
-        struct clk *clkp;
-        int ret = 0;
-        int k;
-
-        for (k = 0; !ret && (k < nr); k++) {
-                clkp = clks + k;
-                clkp->ops = &sh_clk_mstp32_clk_ops;
-                ret |= clk_register(clkp);
-        }
-
-        return ret;
-}
-
-static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
-{
-        return clk_rate_table_round(clk, clk->freq_table, rate);
-}
-
-static int sh_clk_div6_divisors[64] = {
-        1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
-        17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
-        33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
-        49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
-};
-
-static struct clk_div_mult_table sh_clk_div6_table = {
-        .divisors = sh_clk_div6_divisors,
-        .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
-};
-
-static unsigned long sh_clk_div6_recalc(struct clk *clk)
-{
-        struct clk_div_mult_table *table = &sh_clk_div6_table;
-        unsigned int idx;
-
-        clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
-                             table, NULL);
-
-        idx = __raw_readl(clk->enable_reg) & 0x003f;
-
-        return clk->freq_table[idx].frequency;
-}
-
-static int sh_clk_div6_set_rate(struct clk *clk,
-                                unsigned long rate, int algo_id)
-{
-        unsigned long value;
-        int idx;
-
-        idx = clk_rate_table_find(clk, clk->freq_table, rate);
-        if (idx < 0)
-                return idx;
-
-        value = __raw_readl(clk->enable_reg);
-        value &= ~0x3f;
-        value |= idx;
-        __raw_writel(value, clk->enable_reg);
-        return 0;
-}
-
-static int sh_clk_div6_enable(struct clk *clk)
-{
-        unsigned long value;
-        int ret;
-
-        ret = sh_clk_div6_set_rate(clk, clk->rate, 0);
-        if (ret == 0) {
-                value = __raw_readl(clk->enable_reg);
-                value &= ~0x100; /* clear stop bit to enable clock */
-                __raw_writel(value, clk->enable_reg);
-        }
-        return ret;
-}
-
-static void sh_clk_div6_disable(struct clk *clk)
-{
-        unsigned long value;
-
-        value = __raw_readl(clk->enable_reg);
-        value |= 0x100; /* stop clock */
-        value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
-        __raw_writel(value, clk->enable_reg);
-}
-
-static struct clk_ops sh_clk_div6_clk_ops = {
-        .recalc         = sh_clk_div6_recalc,
-        .round_rate     = sh_clk_div_round_rate,
-        .set_rate       = sh_clk_div6_set_rate,
-        .enable         = sh_clk_div6_enable,
-        .disable        = sh_clk_div6_disable,
-};
-
-int __init sh_clk_div6_register(struct clk *clks, int nr)
-{
-        struct clk *clkp;
-        void *freq_table;
-        int nr_divs = sh_clk_div6_table.nr_divisors;
-        int freq_table_size = sizeof(struct cpufreq_frequency_table);
-        int ret = 0;
-        int k;
-
-        freq_table_size *= (nr_divs + 1);
-        freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
-        if (!freq_table) {
-                pr_err("sh_clk_div6_register: unable to alloc memory\n");
-                return -ENOMEM;
-        }
-
-        for (k = 0; !ret && (k < nr); k++) {
-                clkp = clks + k;
-
-                clkp->ops = &sh_clk_div6_clk_ops;
-                clkp->id = -1;
-                clkp->freq_table = freq_table + (k * freq_table_size);
-                clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
-
-                ret = clk_register(clkp);
-        }
-
-        return ret;
-}
-
-static unsigned long sh_clk_div4_recalc(struct clk *clk)
-{
-        struct clk_div_mult_table *table = clk->priv;
-        unsigned int idx;
-
-        clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
-                             table, &clk->arch_flags);
-
-        idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
-
-        return clk->freq_table[idx].frequency;
-}
-
-static struct clk_ops sh_clk_div4_clk_ops = {
-        .recalc         = sh_clk_div4_recalc,
-        .round_rate     = sh_clk_div_round_rate,
-};
-
-int __init sh_clk_div4_register(struct clk *clks, int nr,
-                                struct clk_div_mult_table *table)
-{
-        struct clk *clkp;
-        void *freq_table;
-        int nr_divs = table->nr_divisors;
-        int freq_table_size = sizeof(struct cpufreq_frequency_table);
-        int ret = 0;
-        int k;
-
-        freq_table_size *= (nr_divs + 1);
-        freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
-        if (!freq_table) {
-                pr_err("sh_clk_div4_register: unable to alloc memory\n");
-                return -ENOMEM;
-        }
-
-        for (k = 0; !ret && (k < nr); k++) {
-                clkp = clks + k;
-
-                clkp->ops = &sh_clk_div4_clk_ops;
-                clkp->id = -1;
-                clkp->priv = table;
-
-                clkp->freq_table = freq_table + (k * freq_table_size);
-                clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
-
-                ret = clk_register(clkp);
-        }
-
-        return ret;
-}
-
-#ifdef CONFIG_SH_CLK_CPG_LEGACY
 static struct clk master_clk = {
-        .name           = "master_clk",
         .flags          = CLK_ENABLE_ON_INIT,
         .rate           = CONFIG_SH_PCLK_FREQ,
 };
 
 static struct clk peripheral_clk = {
-        .name           = "peripheral_clk",
         .parent         = &master_clk,
         .flags          = CLK_ENABLE_ON_INIT,
 };
 
 static struct clk bus_clk = {
-        .name           = "bus_clk",
         .parent         = &master_clk,
         .flags          = CLK_ENABLE_ON_INIT,
 };
 
 static struct clk cpu_clk = {
-        .name           = "cpu_clk",
         .parent         = &master_clk,
         .flags          = CLK_ENABLE_ON_INIT,
 };
@@ -233,6 +35,16 @@ static struct clk *onchip_clocks[] = {
         &cpu_clk,
 };
 
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("master_clk", &master_clk),
+        CLKDEV_CON_ID("peripheral_clk", &peripheral_clk),
+        CLKDEV_CON_ID("bus_clk", &bus_clk),
+        CLKDEV_CON_ID("cpu_clk", &cpu_clk),
+};
+
 int __init __deprecated cpg_clk_init(void)
 {
         int i, ret = 0;
@@ -244,6 +56,13 @@ int __init __deprecated cpg_clk_init(void)
                         ret |= clk_register(clk);
         }
 
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        clk_add_alias("tmu_fck", NULL, "peripheral_clk", NULL);
+        clk_add_alias("mtu2_fck", NULL, "peripheral_clk", NULL);
+        clk_add_alias("cmt_fck", NULL, "peripheral_clk", NULL);
+        clk_add_alias("sci_ick", NULL, "peripheral_clk", NULL);
+
         return ret;
 }
 
@@ -255,4 +74,3 @@ int __init __weak arch_clk_init(void)
 {
         return cpg_clk_init();
 }
-#endif /* CONFIG_SH_CPG_CLK_LEGACY */
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index f3a46be2ae81..4187cf4fe185 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -10,558 +10,16 @@
  *
  *  Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
  *
- *  With clkdev bits:
- *
- *      Copyright (C) 2008 Russell King.
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/list.h>
-#include <linux/kobject.h>
-#include <linux/sysdev.h>
-#include <linux/seq_file.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/debugfs.h>
-#include <linux/cpufreq.h>
+#include <linux/clk.h>
 #include <asm/clock.h>
 #include <asm/machvec.h>
 
-static LIST_HEAD(clock_list);
-static DEFINE_SPINLOCK(clock_lock);
-static DEFINE_MUTEX(clock_list_sem);
-
-void clk_rate_table_build(struct clk *clk,
-                          struct cpufreq_frequency_table *freq_table,
-                          int nr_freqs,
-                          struct clk_div_mult_table *src_table,
-                          unsigned long *bitmap)
-{
-        unsigned long mult, div;
-        unsigned long freq;
-        int i;
-
-        for (i = 0; i < nr_freqs; i++) {
-                div = 1;
-                mult = 1;
-
-                if (src_table->divisors && i < src_table->nr_divisors)
-                        div = src_table->divisors[i];
-
-                if (src_table->multipliers && i < src_table->nr_multipliers)
-                        mult = src_table->multipliers[i];
-
-                if (!div || !mult || (bitmap && !test_bit(i, bitmap)))
-                        freq = CPUFREQ_ENTRY_INVALID;
-                else
-                        freq = clk->parent->rate * mult / div;
-
-                freq_table[i].index = i;
-                freq_table[i].frequency = freq;
-        }
-
-        /* Termination entry */
-        freq_table[i].index = i;
-        freq_table[i].frequency = CPUFREQ_TABLE_END;
-}
-
-long clk_rate_table_round(struct clk *clk,
-                          struct cpufreq_frequency_table *freq_table,
-                          unsigned long rate)
-{
-        unsigned long rate_error, rate_error_prev = ~0UL;
-        unsigned long rate_best_fit = rate;
-        unsigned long highest, lowest;
-        int i;
-
-        highest = lowest = 0;
-
-        for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
-                unsigned long freq = freq_table[i].frequency;
-
-                if (freq == CPUFREQ_ENTRY_INVALID)
-                        continue;
-
-                if (freq > highest)
-                        highest = freq;
-                if (freq < lowest)
-                        lowest = freq;
-
-                rate_error = abs(freq - rate);
-                if (rate_error < rate_error_prev) {
-                        rate_best_fit = freq;
-                        rate_error_prev = rate_error;
-                }
-
-                if (rate_error == 0)
-                        break;
-        }
-
-        if (rate >= highest)
-                rate_best_fit = highest;
-        if (rate <= lowest)
-                rate_best_fit = lowest;
-
-        return rate_best_fit;
-}
-
-int clk_rate_table_find(struct clk *clk,
-                        struct cpufreq_frequency_table *freq_table,
-                        unsigned long rate)
-{
-        int i;
-
-        for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
-                unsigned long freq = freq_table[i].frequency;
-
-                if (freq == CPUFREQ_ENTRY_INVALID)
-                        continue;
-
-                if (freq == rate)
-                        return i;
-        }
-
-        return -ENOENT;
-}
-
-/* Used for clocks that always have same value as the parent clock */
-unsigned long followparent_recalc(struct clk *clk)
-{
-        return clk->parent ? clk->parent->rate : 0;
-}
-
-int clk_reparent(struct clk *child, struct clk *parent)
-{
-        list_del_init(&child->sibling);
-        if (parent)
-                list_add(&child->sibling, &parent->children);
-        child->parent = parent;
-
-        /* now do the debugfs renaming to reattach the child
-           to the proper parent */
-
-        return 0;
-}
-
-/* Propagate rate to children */
-void propagate_rate(struct clk *tclk)
-{
-        struct clk *clkp;
-
-        list_for_each_entry(clkp, &tclk->children, sibling) {
-                if (clkp->ops && clkp->ops->recalc)
-                        clkp->rate = clkp->ops->recalc(clkp);
-
-                propagate_rate(clkp);
-        }
-}
-
-static void __clk_disable(struct clk *clk)
-{
-        if (clk->usecount == 0) {
-                printk(KERN_ERR "Trying disable clock %s with 0 usecount\n",
-                       clk->name);
-                WARN_ON(1);
-                return;
-        }
-
-        if (!(--clk->usecount)) {
-                if (likely(clk->ops && clk->ops->disable))
-                        clk->ops->disable(clk);
-                if (likely(clk->parent))
-                        __clk_disable(clk->parent);
-        }
-}
-
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-
-        if (!clk)
-                return;
-
-        spin_lock_irqsave(&clock_lock, flags);
-        __clk_disable(clk);
-        spin_unlock_irqrestore(&clock_lock, flags);
-}
-EXPORT_SYMBOL_GPL(clk_disable);
-
-static int __clk_enable(struct clk *clk)
-{
-        int ret = 0;
-
-        if (clk->usecount++ == 0) {
-                if (clk->parent) {
-                        ret = __clk_enable(clk->parent);
-                        if (unlikely(ret))
-                                goto err;
-                }
-
-                if (clk->ops && clk->ops->enable) {
-                        ret = clk->ops->enable(clk);
-                        if (ret) {
-                                if (clk->parent)
-                                        __clk_disable(clk->parent);
-                                goto err;
-                        }
-                }
-        }
-
-        return ret;
-err:
-        clk->usecount--;
-        return ret;
-}
-
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-        int ret;
-
-        if (!clk)
-                return -EINVAL;
-
-        spin_lock_irqsave(&clock_lock, flags);
-        ret = __clk_enable(clk);
-        spin_unlock_irqrestore(&clock_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL_GPL(clk_enable);
-
-static LIST_HEAD(root_clks);
-
-/**
- * recalculate_root_clocks - recalculate and propagate all root clocks
- *
- * Recalculates all root clocks (clocks with no parent), which if the
- * clock's .recalc is set correctly, should also propagate their rates.
- * Called at init.
- */
-void recalculate_root_clocks(void)
-{
-        struct clk *clkp;
-
-        list_for_each_entry(clkp, &root_clks, sibling) {
-                if (clkp->ops && clkp->ops->recalc)
-                        clkp->rate = clkp->ops->recalc(clkp);
-                propagate_rate(clkp);
-        }
-}
-
-int clk_register(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-
-        /*
-         * trap out already registered clocks
-         */
-        if (clk->node.next || clk->node.prev)
-                return 0;
-
-        mutex_lock(&clock_list_sem);
-
-        INIT_LIST_HEAD(&clk->children);
-        clk->usecount = 0;
-
-        if (clk->parent)
-                list_add(&clk->sibling, &clk->parent->children);
-        else
-                list_add(&clk->sibling, &root_clks);
-
-        list_add(&clk->node, &clock_list);
-        if (clk->ops && clk->ops->init)
-                clk->ops->init(clk);
-        mutex_unlock(&clock_list_sem);
-
-        return 0;
-}
-EXPORT_SYMBOL_GPL(clk_register);
-
-void clk_unregister(struct clk *clk)
-{
-        mutex_lock(&clock_list_sem);
-        list_del(&clk->sibling);
-        list_del(&clk->node);
-        mutex_unlock(&clock_list_sem);
-}
-EXPORT_SYMBOL_GPL(clk_unregister);
-
-static void clk_enable_init_clocks(void)
-{
-        struct clk *clkp;
-
-        list_for_each_entry(clkp, &clock_list, node)
-                if (clkp->flags & CLK_ENABLE_ON_INIT)
-                        clk_enable(clkp);
-}
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-EXPORT_SYMBOL_GPL(clk_get_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        return clk_set_rate_ex(clk, rate, 0);
-}
-EXPORT_SYMBOL_GPL(clk_set_rate);
-
-int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
-{
-        int ret = -EOPNOTSUPP;
-        unsigned long flags;
-
-        spin_lock_irqsave(&clock_lock, flags);
-
-        if (likely(clk->ops && clk->ops->set_rate)) {
-                ret = clk->ops->set_rate(clk, rate, algo_id);
-                if (ret != 0)
-                        goto out_unlock;
-        } else {
-                clk->rate = rate;
-                ret = 0;
-        }
-
-        if (clk->ops && clk->ops->recalc)
-                clk->rate = clk->ops->recalc(clk);
-
-        propagate_rate(clk);
-
-out_unlock:
-        spin_unlock_irqrestore(&clock_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL_GPL(clk_set_rate_ex);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        unsigned long flags;
-        int ret = -EINVAL;
-
-        if (!parent || !clk)
-                return ret;
-        if (clk->parent == parent)
-                return 0;
-
-        spin_lock_irqsave(&clock_lock, flags);
-        if (clk->usecount == 0) {
-                if (clk->ops->set_parent)
-                        ret = clk->ops->set_parent(clk, parent);
-                else
-                        ret = clk_reparent(clk, parent);
-
-                if (ret == 0) {
-                        pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
-                                 clk->name, clk->parent->name, clk->rate);
-                        if (clk->ops->recalc)
-                                clk->rate = clk->ops->recalc(clk);
-                        propagate_rate(clk);
-                }
-        } else
-                ret = -EBUSY;
-        spin_unlock_irqrestore(&clock_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL_GPL(clk_set_parent);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
-        return clk->parent;
-}
-EXPORT_SYMBOL_GPL(clk_get_parent);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        if (likely(clk->ops && clk->ops->round_rate)) {
-                unsigned long flags, rounded;
-
-                spin_lock_irqsave(&clock_lock, flags);
-                rounded = clk->ops->round_rate(clk, rate);
-                spin_unlock_irqrestore(&clock_lock, flags);
-
-                return rounded;
-        }
-
-        return clk_get_rate(clk);
-}
-EXPORT_SYMBOL_GPL(clk_round_rate);
-
-/*
- * Find the correct struct clk for the device and connection ID.
- * We do slightly fuzzy matching here:
- *  An entry with a NULL ID is assumed to be a wildcard.
- *  If an entry has a device ID, it must match
- *  If an entry has a connection ID, it must match
- * Then we take the most specific entry - with the following
- * order of precidence: dev+con > dev only > con only.
- */
-static struct clk *clk_find(const char *dev_id, const char *con_id)
-{
-        struct clk_lookup *p;
-        struct clk *clk = NULL;
-        int match, best = 0;
-
-        list_for_each_entry(p, &clock_list, node) {
-                match = 0;
-                if (p->dev_id) {
-                        if (!dev_id || strcmp(p->dev_id, dev_id))
-                                continue;
-                        match += 2;
-                }
-                if (p->con_id) {
-                        if (!con_id || strcmp(p->con_id, con_id))
-                                continue;
-                        match += 1;
-                }
-                if (match == 0)
-                        continue;
-
-                if (match > best) {
-                        clk = p->clk;
-                        best = match;
-                }
-        }
-        return clk;
-}
-
-struct clk *clk_get_sys(const char *dev_id, const char *con_id)
-{
-        struct clk *clk;
-
-        mutex_lock(&clock_list_sem);
-        clk = clk_find(dev_id, con_id);
-        mutex_unlock(&clock_list_sem);
-
-        return clk ? clk : ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL_GPL(clk_get_sys);
-
-/*
- * Returns a clock. Note that we first try to use device id on the bus
- * and clock name. If this fails, we try to use clock name only.
- */
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        const char *dev_id = dev ? dev_name(dev) : NULL;
-        struct clk *p, *clk = ERR_PTR(-ENOENT);
-        int idno;
-
-        clk = clk_get_sys(dev_id, id);
-        if (clk && !IS_ERR(clk))
-                return clk;
-
-        if (dev == NULL || dev->bus != &platform_bus_type)
-                idno = -1;
-        else
-                idno = to_platform_device(dev)->id;
-
-        mutex_lock(&clock_list_sem);
-        list_for_each_entry(p, &clock_list, node) {
-                if (p->id == idno &&
-                    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        goto found;
-                }
-        }
-
-        list_for_each_entry(p, &clock_list, node) {
-                if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        break;
-                }
-        }
-
-found:
-        mutex_unlock(&clock_list_sem);
-
-        return clk;
-}
-EXPORT_SYMBOL_GPL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-        if (clk && !IS_ERR(clk))
-                module_put(clk->owner);
-}
-EXPORT_SYMBOL_GPL(clk_put);
-
-#ifdef CONFIG_PM
-static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
-{
-        static pm_message_t prev_state;
-        struct clk *clkp;
-
-        switch (state.event) {
-        case PM_EVENT_ON:
-                /* Resumeing from hibernation */
-                if (prev_state.event != PM_EVENT_FREEZE)
-                        break;
-
-                list_for_each_entry(clkp, &clock_list, node) {
-                        if (likely(clkp->ops)) {
-                                unsigned long rate = clkp->rate;
-
-                                if (likely(clkp->ops->set_parent))
-                                        clkp->ops->set_parent(clkp,
-                                                clkp->parent);
-                                if (likely(clkp->ops->set_rate))
-                                        clkp->ops->set_rate(clkp,
-                                                rate, NO_CHANGE);
-                                else if (likely(clkp->ops->recalc))
-                                        clkp->rate = clkp->ops->recalc(clkp);
-                        }
-                }
-                break;
-        case PM_EVENT_FREEZE:
-                break;
-        case PM_EVENT_SUSPEND:
-                break;
-        }
-
-        prev_state = state;
-        return 0;
-}
-
-static int clks_sysdev_resume(struct sys_device *dev)
-{
-        return clks_sysdev_suspend(dev, PMSG_ON);
-}
-
-static struct sysdev_class clks_sysdev_class = {
-        .name = "clks",
-};
-
-static struct sysdev_driver clks_sysdev_driver = {
-        .suspend = clks_sysdev_suspend,
-        .resume = clks_sysdev_resume,
-};
-
-static struct sys_device clks_sysdev_dev = {
-        .cls = &clks_sysdev_class,
-};
-
-static int __init clk_sysdev_init(void)
-{
-        sysdev_class_register(&clks_sysdev_class);
-        sysdev_driver_register(&clks_sysdev_class, &clks_sysdev_driver);
-        sysdev_register(&clks_sysdev_dev);
-
-        return 0;
-}
-subsys_initcall(clk_sysdev_init);
-#endif
-
 int __init clk_init(void)
 {
         int ret;
@@ -590,90 +48,4 @@ int __init clk_init(void)
         return ret;
 }
 
-/*
- *      debugfs support to trace clock tree hierarchy and attributes
- */
-static struct dentry *clk_debugfs_root;
-
-static int clk_debugfs_register_one(struct clk *c)
-{
-        int err;
-        struct dentry *d, *child;
-        struct clk *pa = c->parent;
-        char s[255];
-        char *p = s;
-
-        p += sprintf(p, "%s", c->name);
-        if (c->id >= 0)
-                sprintf(p, ":%d", c->id);
-        d = debugfs_create_dir(s, pa ? pa->dentry : clk_debugfs_root);
-        if (!d)
-                return -ENOMEM;
-        c->dentry = d;
-
-        d = debugfs_create_u8("usecount", S_IRUGO, c->dentry, (u8 *)&c->usecount);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        d = debugfs_create_u32("rate", S_IRUGO, c->dentry, (u32 *)&c->rate);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        d = debugfs_create_x32("flags", S_IRUGO, c->dentry, (u32 *)&c->flags);
-        if (!d) {
-                err = -ENOMEM;
-                goto err_out;
-        }
-        return 0;
-
-err_out:
-        d = c->dentry;
-        list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
-                debugfs_remove(child);
-        debugfs_remove(c->dentry);
-        return err;
-}
-
-static int clk_debugfs_register(struct clk *c)
-{
-        int err;
-        struct clk *pa = c->parent;
 
-        if (pa && !pa->dentry) {
-                err = clk_debugfs_register(pa);
-                if (err)
-                        return err;
-        }
-
-        if (!c->dentry) {
-                err = clk_debugfs_register_one(c);
-                if (err)
-                        return err;
-        }
-        return 0;
-}
-
-static int __init clk_debugfs_init(void)
-{
-        struct clk *c;
-        struct dentry *d;
-        int err;
-
-        d = debugfs_create_dir("clock", NULL);
-        if (!d)
-                return -ENOMEM;
-        clk_debugfs_root = d;
-
-        list_for_each_entry(c, &clock_list, node) {
-                err = clk_debugfs_register(c);
-                if (err)
-                        goto err_out;
-        }
-        return 0;
-err_out:
-        debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */
-        return err;
-}
-late_initcall(clk_debugfs_init);
diff --git a/arch/sh/kernel/cpu/fpu.c b/arch/sh/kernel/cpu/fpu.c
new file mode 100644
index 000000000000..7f1b70cace35
--- /dev/null
+++ b/arch/sh/kernel/cpu/fpu.c
@@ -0,0 +1,85 @@
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <asm/processor.h>
+#include <asm/fpu.h>
+
+int init_fpu(struct task_struct *tsk)
+{
+        if (tsk_used_math(tsk)) {
+                if ((boot_cpu_data.flags & CPU_HAS_FPU) && tsk == current)
+                        unlazy_fpu(tsk, task_pt_regs(tsk));
+                return 0;
+        }
+
+        /*
+         * Memory allocation at the first usage of the FPU and other state.
+         */
+        if (!tsk->thread.xstate) {
+                tsk->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
+                                                      GFP_KERNEL);
+                if (!tsk->thread.xstate)
+                        return -ENOMEM;
+        }
+
+        if (boot_cpu_data.flags & CPU_HAS_FPU) {
+                struct sh_fpu_hard_struct *fp = &tsk->thread.xstate->hardfpu;
+                memset(fp, 0, xstate_size);
+                fp->fpscr = FPSCR_INIT;
+        } else {
+                struct sh_fpu_soft_struct *fp = &tsk->thread.xstate->softfpu;
+                memset(fp, 0, xstate_size);
+                fp->fpscr = FPSCR_INIT;
+        }
+
+        set_stopped_child_used_math(tsk);
+        return 0;
+}
+
+#ifdef CONFIG_SH_FPU
+void __fpu_state_restore(void)
+{
+        struct task_struct *tsk = current;
+
+        restore_fpu(tsk);
+
+        task_thread_info(tsk)->status |= TS_USEDFPU;
+        tsk->fpu_counter++;
+}
+
+void fpu_state_restore(struct pt_regs *regs)
+{
+        struct task_struct *tsk = current;
+
+        if (unlikely(!user_mode(regs))) {
+                printk(KERN_ERR "BUG: FPU is used in kernel mode.\n");
+                BUG();
+                return;
+        }
+
+        if (!tsk_used_math(tsk)) {
+                local_irq_enable();
+                /*
+                 * does a slab alloc which can sleep
+                 */
+                if (init_fpu(tsk)) {
+                        /*
+                         * ran out of memory!
+                         */
+                        do_group_exit(SIGKILL);
+                        return;
+                }
+                local_irq_disable();
+        }
+
+        grab_fpu(regs);
+
+        __fpu_state_restore();
+}
+
+BUILD_TRAP_HANDLER(fpu_state_restore)
+{
+        TRAP_HANDLER_DECL;
+
+        fpu_state_restore(regs);
+}
+#endif /* CONFIG_SH_FPU */
diff --git a/arch/sh/kernel/cpu/hwblk.c b/arch/sh/kernel/cpu/hwblk.c
new file mode 100644
index 000000000000..3e985aae5d91
--- /dev/null
+++ b/arch/sh/kernel/cpu/hwblk.c
@@ -0,0 +1,159 @@
+#include <linux/clk.h>
+#include <linux/compiler.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <asm/suspend.h>
+#include <asm/hwblk.h>
+#include <asm/clock.h>
+
+static DEFINE_SPINLOCK(hwblk_lock);
+
+static void hwblk_area_mod_cnt(struct hwblk_info *info,
+                               int area, int counter, int value, int goal)
+{
+        struct hwblk_area *hap = info->areas + area;
+
+        hap->cnt[counter] += value;
+
+        if (hap->cnt[counter] != goal)
+                return;
+
+        if (hap->flags & HWBLK_AREA_FLAG_PARENT)
+                hwblk_area_mod_cnt(info, hap->parent, counter, value, goal);
+}
+
+
+static int __hwblk_mod_cnt(struct hwblk_info *info, int hwblk,
+                          int counter, int value, int goal)
+{
+        struct hwblk *hp = info->hwblks + hwblk;
+
+        hp->cnt[counter] += value;
+        if (hp->cnt[counter] == goal)
+                hwblk_area_mod_cnt(info, hp->area, counter, value, goal);
+
+        return hp->cnt[counter];
+}
+
+static void hwblk_mod_cnt(struct hwblk_info *info, int hwblk,
+                          int counter, int value, int goal)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&hwblk_lock, flags);
+        __hwblk_mod_cnt(info, hwblk, counter, value, goal);
+        spin_unlock_irqrestore(&hwblk_lock, flags);
+}
+
+void hwblk_cnt_inc(struct hwblk_info *info, int hwblk, int counter)
+{
+        hwblk_mod_cnt(info, hwblk, counter, 1, 1);
+}
+
+void hwblk_cnt_dec(struct hwblk_info *info, int hwblk, int counter)
+{
+        hwblk_mod_cnt(info, hwblk, counter, -1, 0);
+}
+
+void hwblk_enable(struct hwblk_info *info, int hwblk)
+{
+        struct hwblk *hp = info->hwblks + hwblk;
+        unsigned long tmp;
+        unsigned long flags;
+        int ret;
+
+        spin_lock_irqsave(&hwblk_lock, flags);
+
+        ret = __hwblk_mod_cnt(info, hwblk, HWBLK_CNT_USAGE, 1, 1);
+        if (ret == 1) {
+                tmp = __raw_readl(hp->mstp);
+                tmp &= ~(1 << hp->bit);
+                __raw_writel(tmp, hp->mstp);
+        }
+
+        spin_unlock_irqrestore(&hwblk_lock, flags);
+}
+
+void hwblk_disable(struct hwblk_info *info, int hwblk)
+{
+        struct hwblk *hp = info->hwblks + hwblk;
+        unsigned long tmp;
+        unsigned long flags;
+        int ret;
+
+        spin_lock_irqsave(&hwblk_lock, flags);
+
+        ret = __hwblk_mod_cnt(info, hwblk, HWBLK_CNT_USAGE, -1, 0);
+        if (ret == 0) {
+                tmp = __raw_readl(hp->mstp);
+                tmp |= 1 << hp->bit;
+                __raw_writel(tmp, hp->mstp);
+        }
+
+        spin_unlock_irqrestore(&hwblk_lock, flags);
+}
+
+struct hwblk_info *hwblk_info;
+
+int __init hwblk_register(struct hwblk_info *info)
+{
+        hwblk_info = info;
+        return 0;
+}
+
+int __init __weak arch_hwblk_init(void)
+{
+        return 0;
+}
+
+int __weak arch_hwblk_sleep_mode(void)
+{
+        return SUSP_SH_SLEEP;
+}
+
+int __init hwblk_init(void)
+{
+        return arch_hwblk_init();
+}
+
+/* allow clocks to enable and disable hardware blocks */
+static int sh_hwblk_clk_enable(struct clk *clk)
+{
+        if (!hwblk_info)
+                return -ENOENT;
+
+        hwblk_enable(hwblk_info, clk->arch_flags);
+        return 0;
+}
+
+static void sh_hwblk_clk_disable(struct clk *clk)
+{
+        if (hwblk_info)
+                hwblk_disable(hwblk_info, clk->arch_flags);
+}
+
+static struct clk_ops sh_hwblk_clk_ops = {
+        .enable         = sh_hwblk_clk_enable,
+        .disable        = sh_hwblk_clk_disable,
+        .recalc         = followparent_recalc,
+};
+
+int __init sh_hwblk_clk_register(struct clk *clks, int nr)
+{
+        struct clk *clkp;
+        int ret = 0;
+        int k;
+
+        for (k = 0; !ret && (k < nr); k++) {
+                clkp = clks + k;
+
+                /* skip over clocks using hwblk 0 (HWBLK_UNKNOWN) */
+                if (!clkp->arch_flags)
+                        continue;
+
+                clkp->ops = &sh_hwblk_clk_ops;
+                ret |= clk_register(clkp);
+        }
+
+        return ret;
+}
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index ad85421099cd..fac742e514ee 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -3,7 +3,7 @@
  *
  * CPU init code
  *
- * Copyright (C) 2002 - 2007  Paul Mundt
+ * Copyright (C) 2002 - 2009  Paul Mundt
  * Copyright (C) 2003  Richard Curnow
  *
  * This file is subject to the terms and conditions of the GNU General Public
@@ -24,22 +24,32 @@
 #include <asm/elf.h>
 #include <asm/io.h>
 #include <asm/smp.h>
-#ifdef CONFIG_SUPERH32
-#include <asm/ubc.h>
+#include <asm/sh_bios.h>
+
+#ifdef CONFIG_SH_FPU
+#define cpu_has_fpu     1
+#else
+#define cpu_has_fpu     0
+#endif
+
+#ifdef CONFIG_SH_DSP
+#define cpu_has_dsp     1
+#else
+#define cpu_has_dsp     0
 #endif
 
 /*
  * Generic wrapper for command line arguments to disable on-chip
  * peripherals (nofpu, nodsp, and so forth).
  */
-#define onchip_setup(x)                         \
-static int x##_disabled __initdata = 0;         \
-                                                \
-static int __init x##_setup(char *opts)         \
-{                                               \
-        x##_disabled = 1;                       \
-        return 1;                               \
-}                                               \
+#define onchip_setup(x)                                 \
+static int x##_disabled __cpuinitdata = !cpu_has_##x;   \
+                                                        \
+static int __cpuinit x##_setup(char *opts)                      \
+{                                                       \
+        x##_disabled = 1;                               \
+        return 1;                                       \
+}                                                       \
 __setup("no" __stringify(x), x##_setup);
 
 onchip_setup(fpu);
@@ -49,21 +59,47 @@ onchip_setup(dsp);
 #define CPUOPM          0xff2f0000
 #define CPUOPM_RABD     (1 << 5)
 
-static void __init speculative_execution_init(void)
+static void __cpuinit speculative_execution_init(void)
 {
         /* Clear RABD */
-        ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
+        __raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
 
         /* Flush the update */
-        (void)ctrl_inl(CPUOPM);
+        (void)__raw_readl(CPUOPM);
         ctrl_barrier();
 }
 #else
 #define speculative_execution_init()    do { } while (0)
 #endif
 
+#ifdef CONFIG_CPU_SH4A
+#define EXPMASK                 0xff2f0004
+#define EXPMASK_RTEDS           (1 << 0)
+#define EXPMASK_BRDSSLP         (1 << 1)
+#define EXPMASK_MMCAW           (1 << 4)
+
+static void __cpuinit expmask_init(void)
+{
+        unsigned long expmask = __raw_readl(EXPMASK);
+
+        /*
+         * Future proofing.
+         *
+         * Disable support for slottable sleep instruction, non-nop
+         * instructions in the rte delay slot, and associative writes to
+         * the memory-mapped cache array.
+         */
+        expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP | EXPMASK_MMCAW);
+
+        __raw_writel(expmask, EXPMASK);
+        ctrl_barrier();
+}
+#else
+#define expmask_init()  do { } while (0)
+#endif
+
 /* 2nd-level cache init */
-void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void)
+void __attribute__ ((weak)) l2_cache_init(void)
 {
 }
 
@@ -71,12 +107,12 @@ void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void)
  * Generic first-level cache init
  */
 #ifdef CONFIG_SUPERH32
-static void __uses_jump_to_uncached cache_init(void)
+static void cache_init(void)
 {
         unsigned long ccr, flags;
 
         jump_to_uncached();
-        ccr = ctrl_inl(CCR);
+        ccr = __raw_readl(CCR);
 
         /*
          * At this point we don't know whether the cache is enabled or not - a
@@ -120,7 +156,7 @@ static void __uses_jump_to_uncached cache_init(void)
                         for (addr = addrstart;
                              addr < addrstart + waysize;
                              addr += current_cpu_data.dcache.linesz)
-                                ctrl_outl(0, addr);
+                                __raw_writel(0, addr);
 
                         addrstart += current_cpu_data.dcache.way_incr;
                 } while (--ways);
@@ -153,7 +189,7 @@ static void __uses_jump_to_uncached cache_init(void)
 
         l2_cache_init();
 
-        ctrl_outl(flags, CCR);
+        __raw_writel(flags, CCR);
         back_to_cached();
 }
 #else
@@ -181,8 +217,20 @@ static void detect_cache_shape(void)
                 l2_cache_shape = -1; /* No S-cache */
 }
 
+static void __cpuinit fpu_init(void)
+{
+        /* Disable the FPU */
+        if (fpu_disabled && (current_cpu_data.flags & CPU_HAS_FPU)) {
+                printk("FPU Disabled\n");
+                current_cpu_data.flags &= ~CPU_HAS_FPU;
+        }
+
+        disable_fpu();
+        clear_used_math();
+}
+
 #ifdef CONFIG_SH_DSP
-static void __init release_dsp(void)
+static void __cpuinit release_dsp(void)
 {
         unsigned long sr;
 
@@ -196,7 +244,7 @@ static void __init release_dsp(void)
         );
 }
 
-static void __init dsp_init(void)
+static void __cpuinit dsp_init(void)
 {
         unsigned long sr;
 
@@ -218,34 +266,41 @@ static void __init dsp_init(void)
         if (sr & SR_DSP)
                 current_cpu_data.flags |= CPU_HAS_DSP;
 
+        /* Disable the DSP */
+        if (dsp_disabled && (current_cpu_data.flags & CPU_HAS_DSP)) {
+                printk("DSP Disabled\n");
+                current_cpu_data.flags &= ~CPU_HAS_DSP;
+        }
+
         /* Now that we've determined the DSP status, clear the DSP bit. */
         release_dsp();
 }
+#else
+static inline void __cpuinit dsp_init(void) { }
 #endif /* CONFIG_SH_DSP */
 
 /**
- * sh_cpu_init
+ * cpu_init
  *
- * This is our initial entry point for each CPU, and is invoked on the boot
- * CPU prior to calling start_kernel(). For SMP, a combination of this and
- * start_secondary() will bring up each processor to a ready state prior
- * to hand forking the idle loop.
+ * This is our initial entry point for each CPU, and is invoked on the
+ * boot CPU prior to calling start_kernel(). For SMP, a combination of
+ * this and start_secondary() will bring up each processor to a ready
+ * state prior to hand forking the idle loop.
  *
- * We do all of the basic processor init here, including setting up the
- * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is
- * hit (and subsequently platform_setup()) things like determining the
- * CPU subtype and initial configuration will all be done.
+ * We do all of the basic processor init here, including setting up
+ * the caches, FPU, DSP, etc. By the time start_kernel() is hit (and
+ * subsequently platform_setup()) things like determining the CPU
+ * subtype and initial configuration will all be done.
  *
  * Each processor family is still responsible for doing its own probing
- * and cache configuration in detect_cpu_and_cache_system().
+ * and cache configuration in cpu_probe().
  */
-
-asmlinkage void __init sh_cpu_init(void)
+asmlinkage void __cpuinit cpu_init(void)
 {
         current_thread_info()->cpu = hard_smp_processor_id();
 
         /* First, probe the CPU */
-        detect_cpu_and_cache_system();
+        cpu_probe();
 
         if (current_cpu_data.type == CPU_SH_NONE)
                 panic("Unknown CPU");
@@ -268,28 +323,16 @@ asmlinkage void __init sh_cpu_init(void)
         cache_init();
 
         if (raw_smp_processor_id() == 0) {
-#ifdef CONFIG_MMU
                 shm_align_mask = max_t(unsigned long,
                                        current_cpu_data.dcache.way_size - 1,
                                        PAGE_SIZE - 1);
-#endif
 
                 /* Boot CPU sets the cache shape */
                 detect_cache_shape();
         }
 
-        /* Disable the FPU */
-        if (fpu_disabled) {
-                printk("FPU Disabled\n");
-                current_cpu_data.flags &= ~CPU_HAS_FPU;
-                disable_fpu();
-        }
-
-        /* FPU initialization */
-        if ((current_cpu_data.flags & CPU_HAS_FPU)) {
-                clear_thread_flag(TIF_USEDFPU);
-                clear_used_math();
-        }
+        fpu_init();
+        dsp_init();
 
         /*
          * Initialize the per-CPU ASID cache very early, since the
@@ -297,28 +340,26 @@ asmlinkage void __init sh_cpu_init(void)
          */
         current_cpu_data.asid_cache = NO_CONTEXT;
 
-#ifdef CONFIG_SH_DSP
-        /* Probe for DSP */
-        dsp_init();
+        current_cpu_data.phys_bits = __in_29bit_mode() ? 29 : 32;
 
-        /* Disable the DSP */
-        if (dsp_disabled) {
-                printk("DSP Disabled\n");
-                current_cpu_data.flags &= ~CPU_HAS_DSP;
-                release_dsp();
-        }
-#endif
+        speculative_execution_init();
+        expmask_init();
 
-        /*
-         * Some brain-damaged loaders decided it would be a good idea to put
-         * the UBC to sleep. This causes some issues when it comes to things
-         * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB.  So ..
-         * we wake it up and hope that all is well.
-         */
-#ifdef CONFIG_SUPERH32
-        if (raw_smp_processor_id() == 0)
-                ubc_wakeup();
-#endif
+        /* Do the rest of the boot processor setup */
+        if (raw_smp_processor_id() == 0) {
+                /* Save off the BIOS VBR, if there is one */
+                sh_bios_vbr_init();
 
-        speculative_execution_init();
+                /*
+                 * Setup VBR for boot CPU. Secondary CPUs do this through
+                 * start_secondary().
+                 */
+                per_cpu_trap_init();
+
+                /*
+                 * Boot processor to setup the FP and extended state
+                 * context info.
+                 */
+                init_thread_xstate();
+        }
 }
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c
index 6b5d191eec3a..32c825c9488e 100644
--- a/arch/sh/kernel/cpu/irq/imask.c
+++ b/arch/sh/kernel/cpu/irq/imask.c
@@ -51,16 +51,20 @@ static inline void set_interrupt_registers(int ip)
                      : "t");
 }
 
-static void mask_imask_irq(unsigned int irq)
+static void mask_imask_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
+
         clear_bit(irq, imask_mask);
         if (interrupt_priority < IMASK_PRIORITY - irq)
                 interrupt_priority = IMASK_PRIORITY - irq;
         set_interrupt_registers(interrupt_priority);
 }
 
-static void unmask_imask_irq(unsigned int irq)
+static void unmask_imask_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
+
         set_bit(irq, imask_mask);
         interrupt_priority = IMASK_PRIORITY -
                 find_first_zero_bit(imask_mask, IMASK_PRIORITY);
@@ -68,10 +72,10 @@ static void unmask_imask_irq(unsigned int irq)
 }
 
 static struct irq_chip imask_irq_chip = {
-        .typename       = "SR.IMASK",
-        .mask           = mask_imask_irq,
-        .unmask         = unmask_imask_irq,
-        .mask_ack       = mask_imask_irq,
+        .name           = "SR.IMASK",
+        .irq_mask       = mask_imask_irq,
+        .irq_unmask     = unmask_imask_irq,
+        .irq_mask_ack   = mask_imask_irq,
 };
 
 void make_imask_irq(unsigned int irq)
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c
index 6c092f1f5557..5af48f8357e5 100644
--- a/arch/sh/kernel/cpu/irq/intc-sh5.c
+++ b/arch/sh/kernel/cpu/irq/intc-sh5.c
@@ -76,39 +76,11 @@ int intc_evt_to_irq[(0xE20/0x20)+1] = {
 };
 
 static unsigned long intc_virt;
-
-static unsigned int startup_intc_irq(unsigned int irq);
-static void shutdown_intc_irq(unsigned int irq);
-static void enable_intc_irq(unsigned int irq);
-static void disable_intc_irq(unsigned int irq);
-static void mask_and_ack_intc(unsigned int);
-static void end_intc_irq(unsigned int irq);
-
-static struct irq_chip intc_irq_type = {
-        .typename = "INTC",
-        .startup = startup_intc_irq,
-        .shutdown = shutdown_intc_irq,
-        .enable = enable_intc_irq,
-        .disable = disable_intc_irq,
-        .ack = mask_and_ack_intc,
-        .end = end_intc_irq
-};
-
 static int irlm;                /* IRL mode */
 
-static unsigned int startup_intc_irq(unsigned int irq)
-{
-        enable_intc_irq(irq);
-        return 0; /* never anything pending */
-}
-
-static void shutdown_intc_irq(unsigned int irq)
-{
-        disable_intc_irq(irq);
-}
-
-static void enable_intc_irq(unsigned int irq)
+static void enable_intc_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned long reg;
         unsigned long bitmask;
 
@@ -123,11 +95,12 @@ static void enable_intc_irq(unsigned int irq)
                 bitmask = 1 << (irq - 32);
         }
 
-        ctrl_outl(bitmask, reg);
+        __raw_writel(bitmask, reg);
 }
 
-static void disable_intc_irq(unsigned int irq)
+static void disable_intc_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned long reg;
         unsigned long bitmask;
 
@@ -139,18 +112,14 @@ static void disable_intc_irq(unsigned int irq)
                 bitmask = 1 << (irq - 32);
         }
 
-        ctrl_outl(bitmask, reg);
-}
-
-static void mask_and_ack_intc(unsigned int irq)
-{
-        disable_intc_irq(irq);
+        __raw_writel(bitmask, reg);
 }
 
-static void end_intc_irq(unsigned int irq)
-{
-        enable_intc_irq(irq);
-}
+static struct irq_chip intc_irq_type = {
+        .name = "INTC",
+        .irq_enable = enable_intc_irq,
+        .irq_disable = disable_intc_irq,
+};
 
 void __init plat_irq_setup(void)
 {
@@ -170,11 +139,11 @@ void __init plat_irq_setup(void)
 
 
         /* Disable all interrupts and set all priorities to 0 to avoid trouble */
-        ctrl_outl(-1, INTC_INTDSB_0);
-        ctrl_outl(-1, INTC_INTDSB_1);
+        __raw_writel(-1, INTC_INTDSB_0);
+        __raw_writel(-1, INTC_INTDSB_1);
 
         for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8)
-                ctrl_outl( NO_PRIORITY, reg);
+                __raw_writel( NO_PRIORITY, reg);
 
 
 #ifdef CONFIG_SH_CAYMAN
@@ -199,7 +168,7 @@ void __init plat_irq_setup(void)
                         reg = INTC_ICR_SET;
                         i = IRQ_IRL0;
                 }
-                ctrl_outl(INTC_ICR_IRLM, reg);
+                __raw_writel(INTC_ICR_IRLM, reg);
 
                 /* Set interrupt priorities according to platform description */
                 for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) {
@@ -207,7 +176,7 @@ void __init plat_irq_setup(void)
                                 ((i % INTC_INTPRI_PPREG) * 4);
                         if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
                                 /* Upon the 7th, set Priority Register */
-                                ctrl_outl(data, reg);
+                                __raw_writel(data, reg);
                                 data = 0;
                                 reg += 8;
                         }
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 808d99a48efb..7516c35ee514 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -17,30 +17,32 @@
  * for more details.
  */
 #include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
 #include <linux/topology.h>
 
-static inline struct ipr_desc *get_ipr_desc(unsigned int irq)
+static inline struct ipr_desc *get_ipr_desc(struct irq_data *data)
 {
-        struct irq_chip *chip = get_irq_chip(irq);
-        return (void *)((char *)chip - offsetof(struct ipr_desc, chip));
+        struct irq_chip *chip = irq_data_get_irq_chip(data);
+        return container_of(chip, struct ipr_desc, chip);
 }
 
-static void disable_ipr_irq(unsigned int irq)
+static void disable_ipr_irq(struct irq_data *data)
 {
-        struct ipr_data *p = get_irq_chip_data(irq);
-        unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
+        struct ipr_data *p = irq_data_get_irq_chip_data(data);
+        unsigned long addr = get_ipr_desc(data)->ipr_offsets[p->ipr_idx];
         /* Set the priority in IPR to 0 */
         __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr);
+        (void)__raw_readw(addr);        /* Read back to flush write posting */
 }
 
-static void enable_ipr_irq(unsigned int irq)
+static void enable_ipr_irq(struct irq_data *data)
 {
-        struct ipr_data *p = get_irq_chip_data(irq);
-        unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
+        struct ipr_data *p = irq_data_get_irq_chip_data(data);
+        unsigned long addr = get_ipr_desc(data)->ipr_offsets[p->ipr_idx];
         /* Set priority in IPR back to original value */
         __raw_writew(__raw_readw(addr) | (p->priority << p->shift), addr);
 }
@@ -54,19 +56,18 @@ void register_ipr_controller(struct ipr_desc *desc)
 {
         int i;
 
-        desc->chip.mask = disable_ipr_irq;
-        desc->chip.unmask = enable_ipr_irq;
-        desc->chip.mask_ack = disable_ipr_irq;
+        desc->chip.irq_mask = disable_ipr_irq;
+        desc->chip.irq_unmask = enable_ipr_irq;
 
         for (i = 0; i < desc->nr_irqs; i++) {
                 struct ipr_data *p = desc->ipr_data + i;
-                struct irq_desc *irq_desc;
+                int res;
 
                 BUG_ON(p->ipr_idx >= desc->nr_offsets);
                 BUG_ON(!desc->ipr_offsets[p->ipr_idx]);
 
-                irq_desc = irq_to_desc_alloc_node(p->irq, numa_node_id());
-                if (unlikely(!irq_desc)) {
+                res = irq_alloc_desc_at(p->irq, numa_node_id());
+                if (unlikely(res != p->irq && res != -EEXIST)) {
                         printk(KERN_INFO "can not get irq_desc for %d\n",
                                p->irq);
                         continue;
@@ -76,7 +77,7 @@ void register_ipr_controller(struct ipr_desc *desc)
                 set_irq_chip_and_handler_name(p->irq, &desc->chip,
                                       handle_level_irq, "level");
                 set_irq_chip_data(p->irq, p);
-                disable_ipr_irq(p->irq);
+                disable_ipr_irq(irq_get_irq_data(p->irq));
         }
 }
 EXPORT_SYMBOL(register_ipr_controller);
diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c
new file mode 100644
index 000000000000..e80a936f409a
--- /dev/null
+++ b/arch/sh/kernel/cpu/proc.c
@@ -0,0 +1,148 @@
+#include <linux/seq_file.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/machvec.h>
+#include <asm/processor.h>
+
+static const char *cpu_name[] = {
+        [CPU_SH7201]    = "SH7201",
+        [CPU_SH7203]    = "SH7203",     [CPU_SH7263]    = "SH7263",
+        [CPU_SH7206]    = "SH7206",     [CPU_SH7619]    = "SH7619",
+        [CPU_SH7705]    = "SH7705",     [CPU_SH7706]    = "SH7706",
+        [CPU_SH7707]    = "SH7707",     [CPU_SH7708]    = "SH7708",
+        [CPU_SH7709]    = "SH7709",     [CPU_SH7710]    = "SH7710",
+        [CPU_SH7712]    = "SH7712",     [CPU_SH7720]    = "SH7720",
+        [CPU_SH7721]    = "SH7721",     [CPU_SH7729]    = "SH7729",
+        [CPU_SH7750]    = "SH7750",     [CPU_SH7750S]   = "SH7750S",
+        [CPU_SH7750R]   = "SH7750R",    [CPU_SH7751]    = "SH7751",
+        [CPU_SH7751R]   = "SH7751R",    [CPU_SH7760]    = "SH7760",
+        [CPU_SH4_202]   = "SH4-202",    [CPU_SH4_501]   = "SH4-501",
+        [CPU_SH7763]    = "SH7763",     [CPU_SH7770]    = "SH7770",
+        [CPU_SH7780]    = "SH7780",     [CPU_SH7781]    = "SH7781",
+        [CPU_SH7343]    = "SH7343",     [CPU_SH7785]    = "SH7785",
+        [CPU_SH7786]    = "SH7786",     [CPU_SH7757]    = "SH7757",
+        [CPU_SH7722]    = "SH7722",     [CPU_SHX3]      = "SH-X3",
+        [CPU_SH5_101]   = "SH5-101",    [CPU_SH5_103]   = "SH5-103",
+        [CPU_MXG]       = "MX-G",       [CPU_SH7723]    = "SH7723",
+        [CPU_SH7366]    = "SH7366",     [CPU_SH7724]    = "SH7724",
+        [CPU_SH_NONE]   = "Unknown"
+};
+
+const char *get_cpu_subtype(struct sh_cpuinfo *c)
+{
+        return cpu_name[c->type];
+}
+EXPORT_SYMBOL(get_cpu_subtype);
+
+#ifdef CONFIG_PROC_FS
+/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
+static const char *cpu_flags[] = {
+        "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
+        "ptea", "llsc", "l2", "op32", "pteaex", NULL
+};
+
+static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
+{
+        unsigned long i;
+
+        seq_printf(m, "cpu flags\t:");
+
+        if (!c->flags) {
+                seq_printf(m, " %s\n", cpu_flags[0]);
+                return;
+        }
+
+        for (i = 0; cpu_flags[i]; i++)
+                if ((c->flags & (1 << i)))
+                        seq_printf(m, " %s", cpu_flags[i+1]);
+
+        seq_printf(m, "\n");
+}
+
+static void show_cacheinfo(struct seq_file *m, const char *type,
+                           struct cache_info info)
+{
+        unsigned int cache_size;
+
+        cache_size = info.ways * info.sets * info.linesz;
+
+        seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
+                   type, cache_size >> 10, info.ways);
+}
+
+/*
+ *      Get CPU information for use by the procfs.
+ */
+static int show_cpuinfo(struct seq_file *m, void *v)
+{
+        struct sh_cpuinfo *c = v;
+        unsigned int cpu = c - cpu_data;
+
+        if (!cpu_online(cpu))
+                return 0;
+
+        if (cpu == 0)
+                seq_printf(m, "machine\t\t: %s\n", get_system_type());
+        else
+                seq_printf(m, "\n");
+
+        seq_printf(m, "processor\t: %d\n", cpu);
+        seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
+        seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
+        if (c->cut_major == -1)
+                seq_printf(m, "cut\t\t: unknown\n");
+        else if (c->cut_minor == -1)
+                seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
+        else
+                seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
+
+        show_cpuflags(m, c);
+
+        seq_printf(m, "cache type\t: ");
+
+        /*
+         * Check for what type of cache we have, we support both the
+         * unified cache on the SH-2 and SH-3, as well as the harvard
+         * style cache on the SH-4.
+         */
+        if (c->icache.flags & SH_CACHE_COMBINED) {
+                seq_printf(m, "unified\n");
+                show_cacheinfo(m, "cache", c->icache);
+        } else {
+                seq_printf(m, "split (harvard)\n");
+                show_cacheinfo(m, "icache", c->icache);
+                show_cacheinfo(m, "dcache", c->dcache);
+        }
+
+        /* Optional secondary cache */
+        if (c->flags & CPU_HAS_L2_CACHE)
+                show_cacheinfo(m, "scache", c->scache);
+
+        seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);
+
+        seq_printf(m, "bogomips\t: %lu.%02lu\n",
+                     c->loops_per_jiffy/(500000/HZ),
+                     (c->loops_per_jiffy/(5000/HZ)) % 100);
+
+        return 0;
+}
+
+static void *c_start(struct seq_file *m, loff_t *pos)
+{
+        return *pos < NR_CPUS ? cpu_data + *pos : NULL;
+}
+static void *c_next(struct seq_file *m, void *v, loff_t *pos)
+{
+        ++*pos;
+        return c_start(m, pos);
+}
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+const struct seq_operations cpuinfo_op = {
+        .start  = c_start,
+        .next   = c_next,
+        .stop   = c_stop,
+        .show   = show_cpuinfo,
+};
+#endif /* CONFIG_PROC_FS */
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index 4fe863170e31..5b7f12e58a8d 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -14,24 +14,18 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/io.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
-#include <asm/io.h>
+#include <asm/processor.h>
 
 static const int pll1rate[] = {1,2};
 static const int pfc_divisors[] = {1,2,0,4};
-
-#if (CONFIG_SH_CLK_MD == 1) || (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 5) || (CONFIG_SH_CLK_MD == 6)
-#define PLL2 (2)
-#else
-#error "Illigal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
+        clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
 }
 
 static struct clk_ops sh7619_master_clk_ops = {
@@ -40,7 +34,7 @@ static struct clk_ops sh7619_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -50,7 +44,7 @@ static struct clk_ops sh7619_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
+        return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
 }
 
 static struct clk_ops sh7619_bus_clk_ops = {
@@ -70,6 +64,14 @@ static struct clk_ops *sh7619_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN2 | MODE_PIN0) ||
+            test_mode_pin(MODE_PIN2 | MODE_PIN1))
+                pll2_mult = 2;
+        else if (test_mode_pin(MODE_PIN0) || test_mode_pin(MODE_PIN1))
+                pll2_mult = 4;
+
+        BUG_ON(!pll2_mult);
+
         if (idx < ARRAY_SIZE(sh7619_clk_ops))
                 *ops = sh7619_clk_ops[idx];
 }
diff --git a/arch/sh/kernel/cpu/sh2/entry.S b/arch/sh/kernel/cpu/sh2/entry.S
index becc54c45692..c8a4331d9b8d 100644
--- a/arch/sh/kernel/cpu/sh2/entry.S
+++ b/arch/sh/kernel/cpu/sh2/entry.S
@@ -227,8 +227,9 @@ ENTRY(sh_bios_handler)
         mov.l   @r15+, r14
         add     #8,r15
         lds.l   @r15+, pr
+        mov.l   @r15+,r15
         rte
-         mov.l  @r15+,r15
+         nop
         .align  2
 1:      .long   gdb_vbr_vector
 #endif /* CONFIG_SH_STANDARD_BIOS */
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index 5916d9096b99..bab8e75958ae 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -13,7 +13,7 @@
 #include <asm/processor.h>
 #include <asm/cache.h>
 
-int __init detect_cpu_and_cache_system(void)
+void __cpuinit cpu_probe(void)
 {
 #if defined(CONFIG_CPU_SUBTYPE_SH7619)
         boot_cpu_data.type                      = CPU_SH7619;
@@ -29,7 +29,5 @@ int __init detect_cpu_and_cache_system(void)
          */
         boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
         boot_cpu_data.icache = boot_cpu_data.dcache;
-
-        return 0;
+        boot_cpu_data.family = CPU_FAMILY_SH2;
 }
-
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 86acede777b9..0f8befccf9fa 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -59,38 +59,54 @@ static struct intc_prio_reg prio_registers[] __initdata = {
 static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
                          NULL, prio_registers, NULL);
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xf8400000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 88, 88, 88, 88 },
-        }, {
-                .mapbase        = 0xf8410000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 92, 92, 92, 92 },
-        }, {
-                .mapbase        = 0xf8420000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 96, 96, 96, 96 },
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xf8400000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 88, 88, 88, 88 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xf8410000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 92, 92, 92, 92 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xf8420000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 96, 96, 96, 96 },
+};
+
+static struct platform_device scif2_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 2,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif2_platform_data,
         },
 };
 
@@ -118,17 +134,14 @@ static struct platform_device eth_device = {
 };
 
 static struct sh_timer_config cmt0_platform_data = {
-        .name = "CMT0",
         .channel_offset = 0x02,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 125,
         .clocksource_rating = 0, /* disabled due to code generation issues */
 };
 
 static struct resource cmt0_resources[] = {
         [0] = {
-                .name   = "CMT0",
                 .start  = 0xf84a0072,
                 .end    = 0xf84a0077,
                 .flags  = IORESOURCE_MEM,
@@ -150,17 +163,14 @@ static struct platform_device cmt0_device = {
 };
 
 static struct sh_timer_config cmt1_platform_data = {
-        .name = "CMT1",
         .channel_offset = 0x08,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clockevent_rating = 125,
         .clocksource_rating = 0, /* disabled due to code generation issues */
 };
 
 static struct resource cmt1_resources[] = {
         [0] = {
-                .name   = "CMT1",
                 .start  = 0xf84a0078,
                 .end    = 0xf84a007d,
                 .flags  = IORESOURCE_MEM,
@@ -182,7 +192,9 @@ static struct platform_device cmt1_device = {
 };
 
 static struct platform_device *sh7619_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &eth_device,
         &cmt0_device,
         &cmt1_device,
@@ -193,7 +205,7 @@ static int __init sh7619_devices_setup(void)
         return platform_add_devices(sh7619_devices,
                                     ARRAY_SIZE(sh7619_devices));
 }
-__initcall(sh7619_devices_setup);
+arch_initcall(sh7619_devices_setup);
 
 void __init plat_irq_setup(void)
 {
@@ -201,6 +213,9 @@ void __init plat_irq_setup(void)
 }
 
 static struct platform_device *sh7619_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &cmt0_device,
         &cmt1_device,
 };
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index 7814c76159a7..1174e2d96c03 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -22,19 +22,12 @@ static const int pll1rate[]={1,2,3,4,6,8};
 static const int pfc_divisors[]={1,2,3,4,6,8,12};
 #define ifc_divisors pfc_divisors
 
-#if (CONFIG_SH_CLK_MD == 0)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (2)
-#elif (CONFIG_SH_CLK_MD == 3)
-#define PLL2 (1)
-#else
-#error "Illegal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        return 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
+        clk->rate = 10000000 * pll2_mult *
+               pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7201_master_clk_ops = {
@@ -43,7 +36,7 @@ static struct clk_ops sh7201_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -53,7 +46,7 @@ static struct clk_ops sh7201_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -63,7 +56,7 @@ static struct clk_ops sh7201_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007);
+        int idx = ((__raw_readw(FREQCR) >> 4) & 0x0007);
         return clk->parent->rate / ifc_divisors[idx];
 }
 
@@ -80,6 +73,13 @@ static struct clk_ops *sh7201_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
+                pll2_mult = 1;
+        else if (test_mode_pin(MODE_PIN1))
+                pll2_mult = 2;
+        else
+                pll2_mult = 4;
+
         if (idx < ARRAY_SIZE(sh7201_clk_ops))
                 *ops = sh7201_clk_ops[idx];
 }
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index 940986965102..95a008e8b735 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -25,21 +25,11 @@ static const int pll1rate[]={8,12,16,0};
 static const int pfc_divisors[]={1,2,3,4,6,8,12};
 #define ifc_divisors pfc_divisors
 
-#if (CONFIG_SH_CLK_MD == 0)
-#define PLL2 (1)
-#elif (CONFIG_SH_CLK_MD == 1)
-#define PLL2 (2)
-#elif (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 3)
-#define PLL2 (4)
-#else
-#error "Illegal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0003] * PLL2 ;
+        clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
 }
 
 static struct clk_ops sh7203_master_clk_ops = {
@@ -48,7 +38,7 @@ static struct clk_ops sh7203_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -58,7 +48,7 @@ static struct clk_ops sh7203_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx-2];
 }
 
@@ -79,6 +69,13 @@ static struct clk_ops *sh7203_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN1))
+                pll2_mult = 4;
+        else if (test_mode_pin(MODE_PIN0))
+                pll2_mult = 2;
+        else
+                pll2_mult = 1;
+
         if (idx < ARRAY_SIZE(sh7203_clk_ops))
                 *ops = sh7203_clk_ops[idx];
 }
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index c2268bdeceeb..3c314d7cd6e6 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -22,19 +22,11 @@ static const int pll1rate[]={1,2,3,4,6,8};
 static const int pfc_divisors[]={1,2,3,4,6,8,12};
 #define ifc_divisors pfc_divisors
 
-#if (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 6)
-#define PLL2 (2)
-#elif (CONFIG_SH_CLK_MD == 7)
-#define PLL2 (1)
-#else
-#error "Illigal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
+        clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7206_master_clk_ops = {
@@ -43,7 +35,7 @@ static struct clk_ops sh7206_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -53,7 +45,7 @@ static struct clk_ops sh7206_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
+        return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7206_bus_clk_ops = {
@@ -62,7 +54,7 @@ static struct clk_ops sh7206_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / ifc_divisors[idx];
 }
 
@@ -79,7 +71,13 @@ static struct clk_ops *sh7206_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
+                pll2_mult = 1;
+        else if (test_mode_pin(MODE_PIN2 | MODE_PIN1))
+                pll2_mult = 2;
+        else if (test_mode_pin(MODE_PIN1))
+                pll2_mult = 4;
+
         if (idx < ARRAY_SIZE(sh7206_clk_ops))
                 *ops = sh7206_clk_ops[idx];
 }
-
diff --git a/arch/sh/kernel/cpu/sh2a/entry.S b/arch/sh/kernel/cpu/sh2a/entry.S
index ab3903eeda5c..222742ddc0d6 100644
--- a/arch/sh/kernel/cpu/sh2a/entry.S
+++ b/arch/sh/kernel/cpu/sh2a/entry.S
@@ -176,8 +176,9 @@ ENTRY(sh_bios_handler)
         movml.l @r15+,r14
         add     #8,r15
         lds.l   @r15+, pr
+        mov.l   @r15+,r15
         rte
-         mov.l  @r15+,r15
+         nop
         .align  2
 1:      .long   gdb_vbr_vector
 #endif /* CONFIG_SH_STANDARD_BIOS */
diff --git a/arch/sh/kernel/cpu/sh2a/fpu.c b/arch/sh/kernel/cpu/sh2a/fpu.c
index 6df2fb98eb30..488d24e0cdf0 100644
--- a/arch/sh/kernel/cpu/sh2a/fpu.c
+++ b/arch/sh/kernel/cpu/sh2a/fpu.c
@@ -25,14 +25,11 @@
 
 /*
  * Save FPU registers onto task structure.
- * Assume called with FPU enabled (SR.FD=0).
  */
-void
-save_fpu(struct task_struct *tsk, struct pt_regs *regs)
+void save_fpu(struct task_struct *tsk)
 {
         unsigned long dummy;
 
-        clear_tsk_thread_flag(tsk, TIF_USEDFPU);
         enable_fpu();
         asm volatile("sts.l     fpul, @-%0\n\t"
                      "sts.l     fpscr, @-%0\n\t"
@@ -54,17 +51,15 @@ save_fpu(struct task_struct *tsk, struct pt_regs *regs)
                      "fmov.s    fr0, @-%0\n\t"
                      "lds       %3, fpscr\n\t"
                      : "=r" (dummy)
-                     : "0" ((char *)(&tsk->thread.fpu.hard.status)),
+                     : "0" ((char *)(&tsk->thread.xstate->hardfpu.status)),
                        "r" (FPSCR_RCHG),
                        "r" (FPSCR_INIT)
                      : "memory");
 
         disable_fpu();
-        release_fpu(regs);
 }
 
-static void
-restore_fpu(struct task_struct *tsk)
+void restore_fpu(struct task_struct *tsk)
 {
         unsigned long dummy;
 
@@ -88,45 +83,12 @@ restore_fpu(struct task_struct *tsk)
                      "lds.l     @%0+, fpscr\n\t"
                      "lds.l     @%0+, fpul\n\t"
                      : "=r" (dummy)
-                     : "0" (&tsk->thread.fpu), "r" (FPSCR_RCHG)
+                     : "0" (tsk->thread.xstate), "r" (FPSCR_RCHG)
                      : "memory");
         disable_fpu();
 }
 
 /*
- * Load the FPU with signalling NANS.  This bit pattern we're using
- * has the property that no matter wether considered as single or as
- * double precission represents signaling NANS.
- */
-
-static void
-fpu_init(void)
-{
-        enable_fpu();
-        asm volatile("lds       %0, fpul\n\t"
-                     "fsts      fpul, fr0\n\t"
-                     "fsts      fpul, fr1\n\t"
-                     "fsts      fpul, fr2\n\t"
-                     "fsts      fpul, fr3\n\t"
-                     "fsts      fpul, fr4\n\t"
-                     "fsts      fpul, fr5\n\t"
-                     "fsts      fpul, fr6\n\t"
-                     "fsts      fpul, fr7\n\t"
-                     "fsts      fpul, fr8\n\t"
-                     "fsts      fpul, fr9\n\t"
-                     "fsts      fpul, fr10\n\t"
-                     "fsts      fpul, fr11\n\t"
-                     "fsts      fpul, fr12\n\t"
-                     "fsts      fpul, fr13\n\t"
-                     "fsts      fpul, fr14\n\t"
-                     "fsts      fpul, fr15\n\t"
-                     "lds       %2, fpscr\n\t"
-                     : /* no output */
-                     : "r" (0), "r" (FPSCR_RCHG), "r" (FPSCR_INIT));
-        disable_fpu();
-}
-
-/*
  *      Emulate arithmetic ops on denormalized number for some FPU insns.
  */
 
@@ -493,9 +455,9 @@ ieee_fpe_handler (struct pt_regs *regs)
         if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */
                 struct task_struct *tsk = current;
 
-                if ((tsk->thread.fpu.hard.fpscr & FPSCR_FPU_ERROR)) {
+                if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_FPU_ERROR)) {
                         /* FPU error */
-                        denormal_to_double (&tsk->thread.fpu.hard,
+                        denormal_to_double (&tsk->thread.xstate->hardfpu,
                                             (finsn >> 8) & 0xf);
                 } else
                         return 0;
@@ -510,9 +472,9 @@ ieee_fpe_handler (struct pt_regs *regs)
 
                 n = (finsn >> 8) & 0xf;
                 m = (finsn >> 4) & 0xf;
-                hx = tsk->thread.fpu.hard.fp_regs[n];
-                hy = tsk->thread.fpu.hard.fp_regs[m];
-                fpscr = tsk->thread.fpu.hard.fpscr;
+                hx = tsk->thread.xstate->hardfpu.fp_regs[n];
+                hy = tsk->thread.xstate->hardfpu.fp_regs[m];
+                fpscr = tsk->thread.xstate->hardfpu.fpscr;
                 prec = fpscr & (1 << 19);
 
                 if ((fpscr & FPSCR_FPU_ERROR)
@@ -522,15 +484,15 @@ ieee_fpe_handler (struct pt_regs *regs)
 
                         /* FPU error because of denormal */
                         llx = ((long long) hx << 32)
-                               | tsk->thread.fpu.hard.fp_regs[n+1];
+                               | tsk->thread.xstate->hardfpu.fp_regs[n+1];
                         lly = ((long long) hy << 32)
-                               | tsk->thread.fpu.hard.fp_regs[m+1];
+                               | tsk->thread.xstate->hardfpu.fp_regs[m+1];
                         if ((hx & 0x7fffffff) >= 0x00100000)
                                 llx = denormal_muld(lly, llx);
                         else
                                 llx = denormal_muld(llx, lly);
-                        tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
-                        tsk->thread.fpu.hard.fp_regs[n+1] = llx & 0xffffffff;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
+                        tsk->thread.xstate->hardfpu.fp_regs[n+1] = llx & 0xffffffff;
                 } else if ((fpscr & FPSCR_FPU_ERROR)
                      && (!prec && ((hx & 0x7fffffff) < 0x00800000
                                    || (hy & 0x7fffffff) < 0x00800000))) {
@@ -539,7 +501,7 @@ ieee_fpe_handler (struct pt_regs *regs)
                                 hx = denormal_mulf(hy, hx);
                         else
                                 hx = denormal_mulf(hx, hy);
-                        tsk->thread.fpu.hard.fp_regs[n] = hx;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
                 } else
                         return 0;
 
@@ -553,9 +515,9 @@ ieee_fpe_handler (struct pt_regs *regs)
 
                 n = (finsn >> 8) & 0xf;
                 m = (finsn >> 4) & 0xf;
-                hx = tsk->thread.fpu.hard.fp_regs[n];
-                hy = tsk->thread.fpu.hard.fp_regs[m];
-                fpscr = tsk->thread.fpu.hard.fpscr;
+                hx = tsk->thread.xstate->hardfpu.fp_regs[n];
+                hy = tsk->thread.xstate->hardfpu.fp_regs[m];
+                fpscr = tsk->thread.xstate->hardfpu.fpscr;
                 prec = fpscr & (1 << 19);
 
                 if ((fpscr & FPSCR_FPU_ERROR)
@@ -565,15 +527,15 @@ ieee_fpe_handler (struct pt_regs *regs)
 
                         /* FPU error because of denormal */
                         llx = ((long long) hx << 32)
-                               | tsk->thread.fpu.hard.fp_regs[n+1];
+                               | tsk->thread.xstate->hardfpu.fp_regs[n+1];
                         lly = ((long long) hy << 32)
-                               | tsk->thread.fpu.hard.fp_regs[m+1];
+                               | tsk->thread.xstate->hardfpu.fp_regs[m+1];
                         if ((finsn & 0xf00f) == 0xf000)
                                 llx = denormal_addd(llx, lly);
                         else
                                 llx = denormal_addd(llx, lly ^ (1LL << 63));
-                        tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
-                        tsk->thread.fpu.hard.fp_regs[n+1] = llx & 0xffffffff;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
+                        tsk->thread.xstate->hardfpu.fp_regs[n+1] = llx & 0xffffffff;
                 } else if ((fpscr & FPSCR_FPU_ERROR)
                      && (!prec && ((hx & 0x7fffffff) < 0x00800000
                                    || (hy & 0x7fffffff) < 0x00800000))) {
@@ -582,7 +544,7 @@ ieee_fpe_handler (struct pt_regs *regs)
                                 hx = denormal_addf(hx, hy);
                         else
                                 hx = denormal_addf(hx, hy ^ 0x80000000);
-                        tsk->thread.fpu.hard.fp_regs[n] = hx;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
                 } else
                         return 0;
 
@@ -598,37 +560,15 @@ BUILD_TRAP_HANDLER(fpu_error)
         struct task_struct *tsk = current;
         TRAP_HANDLER_DECL;
 
-        save_fpu(tsk, regs);
+        __unlazy_fpu(tsk, regs);
         if (ieee_fpe_handler(regs)) {
-                tsk->thread.fpu.hard.fpscr &=
+                tsk->thread.xstate->hardfpu.fpscr &=
                         ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
                 grab_fpu(regs);
                 restore_fpu(tsk);
-                set_tsk_thread_flag(tsk, TIF_USEDFPU);
+                task_thread_info(tsk)->status |= TS_USEDFPU;
                 return;
         }
 
         force_sig(SIGFPE, tsk);
 }
-
-BUILD_TRAP_HANDLER(fpu_state_restore)
-{
-        struct task_struct *tsk = current;
-        TRAP_HANDLER_DECL;
-
-        grab_fpu(regs);
-        if (!user_mode(regs)) {
-                printk(KERN_ERR "BUG: FPU is used in kernel mode.\n");
-                return;
-        }
-
-        if (used_math()) {
-                /* Using the FPU again.  */
-                restore_fpu(tsk);
-        } else  {
-                /* First time FPU user.  */
-                fpu_init();
-                set_used_math();
-        }
-        set_tsk_thread_flag(tsk, TIF_USEDFPU);
-}
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index e098e2f6aa08..48e97a2a0c8d 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -13,8 +13,10 @@
 #include <asm/processor.h>
 #include <asm/cache.h>
 
-int __init detect_cpu_and_cache_system(void)
+void __cpuinit cpu_probe(void)
 {
+        boot_cpu_data.family                    = CPU_FAMILY_SH2A;
+
         /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */
         boot_cpu_data.flags                     |= CPU_HAS_OP32;
 
@@ -49,6 +51,4 @@ int __init detect_cpu_and_cache_system(void)
          * on the cache info.
          */
         boot_cpu_data.icache            = boot_cpu_data.dcache;
-
-        return 0;
 }
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index b2c3bcc01190..949bf2bac28c 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -115,16 +115,13 @@ static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
 static struct sh_timer_config mtu2_0_platform_data = {
-        .name = "MTU2_0",
         .channel_offset = -0x80,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource mtu2_0_resources[] = {
         [0] = {
-                .name   = "MTU2_0",
                 .start  = 0xff801300,
                 .end    = 0xff801326,
                 .flags  = IORESOURCE_MEM,
@@ -146,16 +143,13 @@ static struct platform_device mtu2_0_device = {
 };
 
 static struct sh_timer_config mtu2_1_platform_data = {
-        .name = "MTU2_1",
         .channel_offset = -0x100,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource mtu2_1_resources[] = {
         [0] = {
-                .name   = "MTU2_1",
                 .start  = 0xff801380,
                 .end    = 0xff801390,
                 .flags  = IORESOURCE_MEM,
@@ -177,16 +171,13 @@ static struct platform_device mtu2_1_device = {
 };
 
 static struct sh_timer_config mtu2_2_platform_data = {
-        .name = "MTU2_2",
         .channel_offset = 0x80,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource mtu2_2_resources[] = {
         [0] = {
-                .name   = "MTU2_2",
                 .start  = 0xff801000,
                 .end    = 0xff80100a,
                 .flags  = IORESOURCE_MEM,
@@ -207,29 +198,25 @@ static struct platform_device mtu2_2_device = {
         .num_resources  = ARRAY_SIZE(mtu2_2_resources),
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xff804000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 220, 220, 220, 220 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xff804000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 220, 220, 220, 220 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct platform_device *mxg_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
         &mtu2_0_device,
         &mtu2_1_device,
         &mtu2_2_device,
@@ -240,7 +227,7 @@ static int __init mxg_devices_setup(void)
         return platform_add_devices(mxg_devices,
                                     ARRAY_SIZE(mxg_devices));
 }
-__initcall(mxg_devices_setup);
+arch_initcall(mxg_devices_setup);
 
 void __init plat_irq_setup(void)
 {
@@ -248,6 +235,7 @@ void __init plat_irq_setup(void)
 }
 
 static struct platform_device *mxg_early_devices[] __initdata = {
+        &scif0_device,
         &mtu2_0_device,
         &mtu2_1_device,
         &mtu2_2_device,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 8d44917ce50b..9df558dcdb86 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -177,73 +177,139 @@ static struct intc_mask_reg mask_registers[] __initdata = {
 static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xfffe8000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 180, 180, 180, 180 }
-        }, {
-                .mapbase        = 0xfffe8800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 184, 184, 184, 184 }
-        }, {
-                .mapbase        = 0xfffe9000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 188, 188, 188, 188 }
-        }, {
-                .mapbase        = 0xfffe9800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 192, 192, 192, 192 }
-        }, {
-                .mapbase        = 0xfffea000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 196, 196, 196, 196 }
-        }, {
-                .mapbase        = 0xfffea800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 200, 200, 200, 200 }
-        }, {
-                .mapbase        = 0xfffeb000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 204, 204, 204, 204 }
-        }, {
-                .mapbase        = 0xfffeb800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 208, 208, 208, 208 }
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xfffe8000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 180, 180, 180, 180 }
+};
+
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xfffe8800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 184, 184, 184, 184 }
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xfffe9000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 188, 188, 188, 188 }
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xfffe9800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 192, 192, 192, 192 }
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xfffea000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 196, 196, 196, 196 }
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xfffea800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 200, 200, 200, 200 }
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
+static struct plat_sci_port scif6_platform_data = {
+        .mapbase        = 0xfffeb000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 204, 204, 204, 204 }
+};
+
+static struct platform_device scif6_device = {
+        .name           = "sh-sci",
+        .id             = 6,
+        .dev            = {
+                .platform_data  = &scif6_platform_data,
+        },
+};
+
+static struct plat_sci_port scif7_platform_data = {
+        .mapbase        = 0xfffeb800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 208, 208, 208, 208 }
+};
+
+static struct platform_device scif7_device = {
+        .name           = "sh-sci",
+        .id             = 7,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif7_platform_data,
         },
 };
 
@@ -268,16 +334,13 @@ static struct platform_device rtc_device = {
 };
 
 static struct sh_timer_config mtu2_0_platform_data = {
-        .name = "MTU2_0",
         .channel_offset = -0x80,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource mtu2_0_resources[] = {
         [0] = {
-                .name   = "MTU2_0",
                 .start  = 0xfffe4300,
                 .end    = 0xfffe4326,
                 .flags  = IORESOURCE_MEM,
@@ -299,16 +362,13 @@ static struct platform_device mtu2_0_device = {
 };
 
 static struct sh_timer_config mtu2_1_platform_data = {
-        .name = "MTU2_1",
         .channel_offset = -0x100,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource mtu2_1_resources[] = {
         [0] = {
-                .name   = "MTU2_1",
                 .start  = 0xfffe4380,
                 .end    = 0xfffe4390,
                 .flags  = IORESOURCE_MEM,
@@ -330,16 +390,13 @@ static struct platform_device mtu2_1_device = {
 };
 
 static struct sh_timer_config mtu2_2_platform_data = {
-        .name = "MTU2_2",
         .channel_offset = 0x80,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource mtu2_2_resources[] = {
         [0] = {
-                .name   = "MTU2_2",
                 .start  = 0xfffe4000,
                 .end    = 0xfffe400a,
                 .flags  = IORESOURCE_MEM,
@@ -361,7 +418,14 @@ static struct platform_device mtu2_2_device = {
 };
 
 static struct platform_device *sh7201_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &scif7_device,
         &rtc_device,
         &mtu2_0_device,
         &mtu2_1_device,
@@ -373,7 +437,7 @@ static int __init sh7201_devices_setup(void)
         return platform_add_devices(sh7201_devices,
                                     ARRAY_SIZE(sh7201_devices));
 }
-__initcall(sh7201_devices_setup);
+arch_initcall(sh7201_devices_setup);
 
 void __init plat_irq_setup(void)
 {
@@ -381,6 +445,14 @@ void __init plat_irq_setup(void)
 }
 
 static struct platform_device *sh7201_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &scif7_device,
         &mtu2_0_device,
         &mtu2_1_device,
         &mtu2_2_device,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index a78d2a219f3b..a43124e608c3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -173,60 +173,83 @@ static struct intc_mask_reg mask_registers[] __initdata = {
 static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xfffe8000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           =  { 192, 192, 192, 192 },
-        }, {
-                .mapbase        = 0xfffe8800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           =  { 196, 196, 196, 196 },
-        }, {
-                .mapbase        = 0xfffe9000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           =  { 200, 200, 200, 200 },
-        }, {
-                .mapbase        = 0xfffe9800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           =  { 204, 204, 204, 204 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xfffe8000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           =  { 192, 192, 192, 192 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xfffe8800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           =  { 196, 196, 196, 196 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xfffe9000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           =  { 200, 200, 200, 200 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xfffe9800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           =  { 204, 204, 204, 204 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif3_platform_data,
         },
 };
 
 static struct sh_timer_config cmt0_platform_data = {
-        .name = "CMT0",
         .channel_offset = 0x02,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 125,
         .clocksource_rating = 0, /* disabled due to code generation issues */
 };
 
 static struct resource cmt0_resources[] = {
         [0] = {
-                .name   = "CMT0",
                 .start  = 0xfffec002,
                 .end    = 0xfffec007,
                 .flags  = IORESOURCE_MEM,
@@ -248,17 +271,14 @@ static struct platform_device cmt0_device = {
 };
 
 static struct sh_timer_config cmt1_platform_data = {
-        .name = "CMT1",
         .channel_offset = 0x08,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clockevent_rating = 125,
         .clocksource_rating = 0, /* disabled due to code generation issues */
 };
 
 static struct resource cmt1_resources[] = {
         [0] = {
-                .name   = "CMT1",
                 .start  = 0xfffec008,
                 .end    = 0xfffec00d,
                 .flags  = IORESOURCE_MEM,
@@ -280,16 +300,13 @@ static struct platform_device cmt1_device = {
 };
 
 static struct sh_timer_config mtu2_0_platform_data = {
-        .name = "MTU2_0",
         .channel_offset = -0x80,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource mtu2_0_resources[] = {
         [0] = {
-                .name   = "MTU2_0",
                 .start  = 0xfffe4300,
                 .end    = 0xfffe4326,
                 .flags  = IORESOURCE_MEM,
@@ -311,16 +328,13 @@ static struct platform_device mtu2_0_device = {
 };
 
 static struct sh_timer_config mtu2_1_platform_data = {
-        .name = "MTU2_1",
         .channel_offset = -0x100,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource mtu2_1_resources[] = {
         [0] = {
-                .name   = "MTU2_1",
                 .start  = 0xfffe4380,
                 .end    = 0xfffe4390,
                 .flags  = IORESOURCE_MEM,
@@ -362,7 +376,10 @@ static struct platform_device rtc_device = {
 };
 
 static struct platform_device *sh7203_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &cmt0_device,
         &cmt1_device,
         &mtu2_0_device,
@@ -375,7 +392,7 @@ static int __init sh7203_devices_setup(void)
         return platform_add_devices(sh7203_devices,
                                     ARRAY_SIZE(sh7203_devices));
 }
-__initcall(sh7203_devices_setup);
+arch_initcall(sh7203_devices_setup);
 
 void __init plat_irq_setup(void)
 {
@@ -383,6 +400,10 @@ void __init plat_irq_setup(void)
 }
 
 static struct platform_device *sh7203_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &cmt0_device,
         &cmt1_device,
         &mtu2_0_device,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index 68b93ed44cc2..5d14f849aea3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -133,60 +133,83 @@ static struct intc_mask_reg mask_registers[] __initdata = {
 static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
                          mask_registers, prio_registers, NULL);
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xfffe8000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 240, 240, 240, 240 },
-        }, {
-                .mapbase        = 0xfffe8800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 244, 244, 244, 244 },
-        }, {
-                .mapbase        = 0xfffe9000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 248, 248, 248, 248 },
-        }, {
-                .mapbase        = 0xfffe9800,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 252, 252, 252, 252 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xfffe8000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 240, 240, 240, 240 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xfffe8800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 244, 244, 244, 244 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xfffe9000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 248, 248, 248, 248 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xfffe9800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 252, 252, 252, 252 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif3_platform_data,
         },
 };
 
 static struct sh_timer_config cmt0_platform_data = {
-        .name = "CMT0",
         .channel_offset = 0x02,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 125,
         .clocksource_rating = 0, /* disabled due to code generation issues */
 };
 
 static struct resource cmt0_resources[] = {
         [0] = {
-                .name   = "CMT0",
                 .start  = 0xfffec002,
                 .end    = 0xfffec007,
                 .flags  = IORESOURCE_MEM,
@@ -208,17 +231,14 @@ static struct platform_device cmt0_device = {
 };
 
 static struct sh_timer_config cmt1_platform_data = {
-        .name = "CMT1",
         .channel_offset = 0x08,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clockevent_rating = 125,
         .clocksource_rating = 0, /* disabled due to code generation issues */
 };
 
 static struct resource cmt1_resources[] = {
         [0] = {
-                .name   = "CMT1",
                 .start  = 0xfffec008,
                 .end    = 0xfffec00d,
                 .flags  = IORESOURCE_MEM,
@@ -240,16 +260,13 @@ static struct platform_device cmt1_device = {
 };
 
 static struct sh_timer_config mtu2_0_platform_data = {
-        .name = "MTU2_0",
         .channel_offset = -0x80,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource mtu2_0_resources[] = {
         [0] = {
-                .name   = "MTU2_0",
                 .start  = 0xfffe4300,
                 .end    = 0xfffe4326,
                 .flags  = IORESOURCE_MEM,
@@ -271,16 +288,13 @@ static struct platform_device mtu2_0_device = {
 };
 
 static struct sh_timer_config mtu2_1_platform_data = {
-        .name = "MTU2_1",
         .channel_offset = -0x100,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource mtu2_1_resources[] = {
         [0] = {
-                .name   = "MTU2_1",
                 .start  = 0xfffe4380,
                 .end    = 0xfffe4390,
                 .flags  = IORESOURCE_MEM,
@@ -302,16 +316,13 @@ static struct platform_device mtu2_1_device = {
 };
 
 static struct sh_timer_config mtu2_2_platform_data = {
-        .name = "MTU2_2",
         .channel_offset = 0x80,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource mtu2_2_resources[] = {
         [0] = {
-                .name   = "MTU2_2",
                 .start  = 0xfffe4000,
                 .end    = 0xfffe400a,
                 .flags  = IORESOURCE_MEM,
@@ -333,7 +344,10 @@ static struct platform_device mtu2_2_device = {
 };
 
 static struct platform_device *sh7206_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &cmt0_device,
         &cmt1_device,
         &mtu2_0_device,
@@ -346,7 +360,7 @@ static int __init sh7206_devices_setup(void)
         return platform_add_devices(sh7206_devices,
                                     ARRAY_SIZE(sh7206_devices));
 }
-__initcall(sh7206_devices_setup);
+arch_initcall(sh7206_devices_setup);
 
 void __init plat_irq_setup(void)
 {
@@ -354,6 +368,10 @@ void __init plat_irq_setup(void)
 }
 
 static struct platform_device *sh7206_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &cmt0_device,
         &cmt1_device,
         &mtu2_0_device,
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh3.c b/arch/sh/kernel/cpu/sh3/clock-sh3.c
index 27b8738f0b09..b78384afac09 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh3.c
@@ -28,7 +28,7 @@ static int pfc_divisors[]    = { 1, 2, 3, 4, 6, 1, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
         clk->rate *= pfc_divisors[idx];
@@ -40,7 +40,7 @@ static struct clk_ops sh3_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
         return clk->parent->rate / pfc_divisors[idx];
@@ -52,7 +52,7 @@ static struct clk_ops sh3_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
 
         return clk->parent->rate / stc_multipliers[idx];
@@ -64,7 +64,7 @@ static struct clk_ops sh3_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
 
         return clk->parent->rate / ifc_divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7705.c b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
index 0ca8f2c3646c..0ecea1451c6f 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
@@ -32,7 +32,7 @@ static int pfc_divisors[]    = { 1, 2, 3, 4, 6, 1, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0003];
+        clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003];
 }
 
 static struct clk_ops sh7705_master_clk_ops = {
@@ -41,7 +41,7 @@ static struct clk_ops sh7705_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = ctrl_inw(FRQCR) & 0x0003;
+        int idx = __raw_readw(FRQCR) & 0x0003;
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -51,7 +51,7 @@ static struct clk_ops sh7705_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8;
+        int idx = (__raw_readw(FRQCR) & 0x0300) >> 8;
         return clk->parent->rate / stc_multipliers[idx];
 }
 
@@ -61,7 +61,7 @@ static struct clk_ops sh7705_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4;
+        int idx = (__raw_readw(FRQCR) & 0x0030) >> 4;
         return clk->parent->rate / ifc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7706.c b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
index 4bf7887d310a..6f9ff8b57dd6 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7706.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
@@ -24,7 +24,7 @@ static int pfc_divisors[]    = { 1, 2, 4, 1, 3, 6, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
         clk->rate *= pfc_divisors[idx];
@@ -36,7 +36,7 @@ static struct clk_ops sh7706_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
         return clk->parent->rate / pfc_divisors[idx];
@@ -48,7 +48,7 @@ static struct clk_ops sh7706_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
 
         return clk->parent->rate / stc_multipliers[idx];
@@ -60,7 +60,7 @@ static struct clk_ops sh7706_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
 
         return clk->parent->rate / ifc_divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7709.c b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
index fa30b6017730..f302ba09e681 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
@@ -22,16 +22,9 @@ static int stc_multipliers[] = { 1, 2, 4, 8, 3, 6, 1, 1 };
 static int ifc_divisors[]    = { 1, 2, 4, 1, 3, 1, 1, 1 };
 static int pfc_divisors[]    = { 1, 2, 4, 1, 3, 6, 1, 1 };
 
-static void set_bus_parent(struct clk *clk)
-{
-        struct clk *bus_clk = clk_get(NULL, "bus_clk");
-        clk->parent = bus_clk;
-        clk_put(bus_clk);
-}
-
 static void master_clk_init(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
         clk->rate *= pfc_divisors[idx];
@@ -43,22 +36,19 @@ static struct clk_ops sh7709_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
         return clk->parent->rate / pfc_divisors[idx];
 }
 
 static struct clk_ops sh7709_module_clk_ops = {
-#ifdef CLOCK_MODE_0_1_2_7
-        .init           = set_bus_parent,
-#endif
         .recalc         = module_clk_recalc,
 };
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = (frqcr & 0x0080) ?
                 ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1;
 
@@ -71,14 +61,13 @@ static struct clk_ops sh7709_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
 
         return clk->parent->rate / ifc_divisors[idx];
 }
 
 static struct clk_ops sh7709_cpu_clk_ops = {
-        .init           = set_bus_parent,
         .recalc         = cpu_clk_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7710.c b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
index 030a58ba18a5..29a87d8946a4 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
@@ -26,7 +26,7 @@ static int md_table[] = { 1, 2, 3, 4, 6, 8, 12 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= md_table[ctrl_inw(FRQCR) & 0x0007];
+        clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007];
 }
 
 static struct clk_ops sh7710_master_clk_ops = {
@@ -35,7 +35,7 @@ static struct clk_ops sh7710_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) & 0x0007);
+        int idx = (__raw_readw(FRQCR) & 0x0007);
         return clk->parent->rate / md_table[idx];
 }
 
@@ -45,7 +45,7 @@ static struct clk_ops sh7710_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) & 0x0700) >> 8;
+        int idx = (__raw_readw(FRQCR) & 0x0700) >> 8;
         return clk->parent->rate / md_table[idx];
 }
 
@@ -55,7 +55,7 @@ static struct clk_ops sh7710_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) & 0x0070) >> 4;
+        int idx = (__raw_readw(FRQCR) & 0x0070) >> 4;
         return clk->parent->rate / md_table[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7712.c b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
index 6428ee6c77ed..b0d0c5203996 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7712.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
@@ -23,7 +23,7 @@ static int divisors[]    = { 1, 2, 3, 4, 6 };
 
 static void master_clk_init(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = (frqcr & 0x0300) >> 8;
 
         clk->rate *= multipliers[idx];
@@ -35,7 +35,7 @@ static struct clk_ops sh7712_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = frqcr & 0x0007;
 
         return clk->parent->rate / divisors[idx];
@@ -47,7 +47,7 @@ static struct clk_ops sh7712_module_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = (frqcr & 0x0030) >> 4;
 
         return clk->parent->rate / divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
index 3cb531f233f2..f6a389c996cb 100644
--- a/arch/sh/kernel/cpu/sh3/entry.S
+++ b/arch/sh/kernel/cpu/sh3/entry.S
@@ -53,10 +53,6 @@
  *      syscall #
  *
  */
-#if defined(CONFIG_KGDB)
-NMI_VEC = 0x1c0                 ! Must catch early for debounce
-#endif
-
 /* Offsets to the stack */
 OFF_R0  =  0            /* Return value. New ABI also arg4 */
 OFF_R1  =  4            /* New ABI: arg5 */
@@ -71,7 +67,6 @@ OFF_PC  =  (16*4)
 OFF_SR  =  (16*4+8)
 OFF_TRA =  (16*4+6*4)
 
-
 #define k0      r0
 #define k1      r1
 #define k2      r2
@@ -113,34 +108,33 @@ OFF_TRA	=  (16*4+6*4)
 #if defined(CONFIG_MMU)
         .align  2
 ENTRY(tlb_miss_load)
-        bra     call_dpf
+        bra     call_handle_tlbmiss
          mov    #0, r5
 
         .align  2
 ENTRY(tlb_miss_store)
-        bra     call_dpf
+        bra     call_handle_tlbmiss
          mov    #1, r5
 
         .align  2
 ENTRY(initial_page_write)
-        bra     call_dpf
-         mov    #1, r5
+        bra     call_handle_tlbmiss
+         mov    #2, r5
 
         .align  2
 ENTRY(tlb_protection_violation_load)
-        bra     call_dpf
+        bra     call_do_page_fault
          mov    #0, r5
 
         .align  2
 ENTRY(tlb_protection_violation_store)
-        bra     call_dpf
+        bra     call_do_page_fault
          mov    #1, r5
 
-call_dpf:
+call_handle_tlbmiss:
         mov.l   1f, r0
         mov     r5, r8
         mov.l   @r0, r6
-        mov     r6, r9
         mov.l   2f, r0
         sts     pr, r10
         jsr     @r0
@@ -151,16 +145,23 @@ call_dpf:
          lds    r10, pr
         rts
          nop
-0:      mov.l   3f, r0
-        mov     r9, r6
+0:
         mov     r8, r5
+call_do_page_fault:
+        mov.l   1f, r0
+        mov.l   @r0, r6
+
+        mov.l   3f, r0
+        mov.l   4f, r1
+        mov     r15, r4
         jmp     @r0
-         mov    r15, r4
+         lds    r1, pr
 
         .align 2
 1:      .long   MMU_TEA
-2:      .long   __do_page_fault
+2:      .long   handle_tlbmiss
 3:      .long   do_page_fault
+4:      .long   ret_from_exception
 
         .align  2
 ENTRY(address_error_load)
@@ -256,7 +257,7 @@ restore_all:
         !
         ! Calculate new SR value
         mov     k3, k2                  ! original SR value
-        mov     #0xf0, k1
+        mov     #0xfffffff0, k1
         extu.b  k1, k1
         not     k1, k1
         and     k1, k2                  ! Mask original SR value
@@ -272,21 +273,12 @@ restore_all:
 6:      or      k0, k2                  ! Set the IMASK-bits
         ldc     k2, ssr
         !
-#if defined(CONFIG_KGDB)
-        ! Clear in_nmi
-        mov.l   6f, k0
-        mov     #0, k1
-        mov.b   k1, @k0
-#endif
         mov     k4, r15
         rte
          nop
 
         .align  2
 5:      .long   0x00001000      ! DSP
-#ifdef CONFIG_KGDB
-6:      .long   in_nmi
-#endif
 7:      .long   0x30000000
 
 ! common exception handler
@@ -304,41 +296,8 @@ ENTRY(vbr_base)
 !
         .balign         256,0,256
 general_exception:
-#ifndef CONFIG_CPU_SUBTYPE_SHX3
         bra     handle_exception
          sts    pr, k3          ! save original pr value in k3
-#else
-        mov.l   1f, k4
-        mov.l   @k4, k4
-
-        ! Is EXPEVT larger than 0x800?
-        mov     #0x8, k0
-        shll8   k0
-        cmp/hs  k0, k4
-        bf      0f
-
-        ! then add 0x580 (k2 is 0xd80 or 0xda0)
-        mov     #0x58, k0
-        shll2   k0
-        shll2   k0
-        add     k0, k4
-0:
-        ! Setup stack and save DSP context (k0 contains original r15 on return)
-        bsr     prepare_stack
-         nop
-
-        ! Save registers / Switch to bank 0
-        mov             k4, k2          ! keep vector in k2
-        mov.l   1f, k4          ! SR bits to clear in k4
-        bsr     save_regs       ! needs original pr value in k3
-         nop
-
-        bra     handle_exception_special
-         nop
-
-        .align  2
-1:      .long   EXPEVT
-#endif
 
 ! prepare_stack()
 ! - roll back gRB
@@ -405,6 +364,8 @@ handle_exception:
          mov.l  @k2, k2         ! read out vector and keep in k2
 
 handle_exception_special:
+        setup_frame_reg
+
         ! Setup return address and jump to exception handler
         mov.l   7f, r9          ! fetch return address
         stc     r2_bank, r0     ! k2 (vector)
@@ -478,23 +439,6 @@ ENTRY(save_low_regs)
 !
         .balign         512,0,512
 ENTRY(handle_interrupt)
-#if defined(CONFIG_KGDB)
-        mov.l   2f, k2
-        ! Debounce (filter nested NMI)
-        mov.l   @k2, k0
-        mov.l   9f, k1
-        cmp/eq  k1, k0
-        bf      11f
-        mov.l   10f, k1
-        tas.b   @k1
-        bt      11f
-        rte
-         nop
-        .align  2
-9:      .long   NMI_VEC
-10:     .long   in_nmi
-11:
-#endif /* defined(CONFIG_KGDB) */
         sts     pr, k3          ! save original pr value in k3
         mova    exception_data, k0
 
@@ -507,13 +451,49 @@ ENTRY(handle_interrupt)
         bsr     save_regs       ! needs original pr value in k3
          mov    #-1, k2         ! default vector kept in k2
 
+        setup_frame_reg
+
+        stc     sr, r0  ! get status register
+        shlr2   r0
+        and     #0x3c, r0
+        cmp/eq  #0x3c, r0
+        bf      9f
+        TRACE_IRQS_OFF
+9:
+
         ! Setup return address and jump to do_IRQ
         mov.l   4f, r9          ! fetch return address
         lds     r9, pr          ! put return address in pr
         mov.l   2f, r4
         mov.l   3f, r9
         mov.l   @r4, r4         ! pass INTEVT vector as arg0
+
+        shlr2   r4
+        shlr    r4
+        mov     r4, r0          ! save vector->jmp table offset for later
+
+        shlr2   r4              ! vector to IRQ# conversion
+        add     #-0x10, r4
+
+        cmp/pz  r4              ! is it a valid IRQ?
+        bt      10f
+
+        /*
+         * We got here as a result of taking the INTEVT path for something
+         * that isn't a valid hard IRQ, therefore we bypass the do_IRQ()
+         * path and special case the event dispatch instead.  This is the
+         * expected path for the NMI (and any other brilliantly implemented
+         * exception), which effectively wants regular exception dispatch
+         * but is unfortunately reported through INTEVT rather than
+         * EXPEVT.  Grr.
+         */
+        mov.l   6f, r9
+        mov.l   @(r0, r9), r9
         jmp     @r9
+         mov    r15, r8         ! trap handlers take saved regs in r8
+
+10:
+        jmp     @r9             ! Off to do_IRQ() we go.
          mov    r15, r5         ! pass saved registers as arg1
 
 ENTRY(exception_none)
diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S
index e5a0de39a2db..99b4d020179a 100644
--- a/arch/sh/kernel/cpu/sh3/ex.S
+++ b/arch/sh/kernel/cpu/sh3/ex.S
@@ -48,10 +48,8 @@ ENTRY(exception_handling_table)
         .long   system_call     ! Unconditional Trap     /* 160 */
         .long   exception_error ! reserved_instruction (filled by trap_init) /* 180 */
         .long   exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/
-ENTRY(nmi_slot)
-        .long   kgdb_handle_exception   /* 1C0 */       ! Allow trap to debugger
-ENTRY(user_break_point_trap)
-        .long   break_point_trap        /* 1E0 */
+        .long   nmi_trap_handler        /* 1C0 */       ! Allow trap to debugger
+        .long   breakpoint_trap_handler /* 1E0 */
 
         /*
          * Pad the remainder of the table out, exceptions residing in far
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index 10f2a760c5ee..bf23c322e164 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -16,7 +16,7 @@
 #include <asm/cache.h>
 #include <asm/io.h>
 
-int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
+void __cpuinit cpu_probe(void)
 {
         unsigned long addr0, addr1, data0, data1, data2, data3;
 
@@ -30,23 +30,23 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
         addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12);
 
         /* First, write back & invalidate */
-        data0  = ctrl_inl(addr0);
-        ctrl_outl(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
-        data1  = ctrl_inl(addr1);
-        ctrl_outl(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
+        data0  = __raw_readl(addr0);
+        __raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
+        data1  = __raw_readl(addr1);
+        __raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
 
         /* Next, check if there's shadow or not */
-        data0 = ctrl_inl(addr0);
+        data0 = __raw_readl(addr0);
         data0 ^= SH_CACHE_VALID;
-        ctrl_outl(data0, addr0);
-        data1 = ctrl_inl(addr1);
+        __raw_writel(data0, addr0);
+        data1 = __raw_readl(addr1);
         data2 = data1 ^ SH_CACHE_VALID;
-        ctrl_outl(data2, addr1);
-        data3 = ctrl_inl(addr0);
+        __raw_writel(data2, addr1);
+        data3 = __raw_readl(addr0);
 
         /* Lastly, invaliate them. */
-        ctrl_outl(data0&~SH_CACHE_VALID, addr0);
-        ctrl_outl(data2&~SH_CACHE_VALID, addr1);
+        __raw_writel(data0&~SH_CACHE_VALID, addr0);
+        __raw_writel(data2&~SH_CACHE_VALID, addr1);
 
         back_to_cached();
 
@@ -94,9 +94,9 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
                 boot_cpu_data.dcache.way_incr   = (1 << 13);
                 boot_cpu_data.dcache.entry_mask = 0x1ff0;
                 boot_cpu_data.dcache.sets       = 512;
-                ctrl_outl(CCR_CACHE_32KB, CCR3_REG);
+                __raw_writel(CCR_CACHE_32KB, CCR3_REG);
 #else
-                ctrl_outl(CCR_CACHE_16KB, CCR3_REG);
+                __raw_writel(CCR_CACHE_16KB, CCR3_REG);
 #endif
 #endif
         }
@@ -107,5 +107,5 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
         boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
         boot_cpu_data.icache = boot_cpu_data.dcache;
 
-        return 0;
+        boot_cpu_data.family = CPU_FAMILY_SH3;
 }
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh3.c b/arch/sh/kernel/cpu/sh3/setup-sh3.c
index c98846857855..53be70b98116 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh3.c
@@ -58,7 +58,7 @@ static DECLARE_INTC_DESC_ACK(intc_desc_irq45, "sh3-irq45",
 void __init plat_irq_setup_pins(int mode)
 {
         if (mode == IRQ_MODE_IRQ) {
-                ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
+                __raw_writew(__raw_readw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
                 register_intc_controller(&intc_desc_irq0123);
                 return;
         }
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 27d03d836056..cd2e702feb7e 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -67,32 +67,38 @@ static struct intc_prio_reg prio_registers[] __initdata = {
 static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
                          NULL, prio_registers, NULL);
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xa4410000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_TIE | SCSCR_RIE  | SCSCR_TE |
-                                  SCSCR_RE  | SCSCR_CKE1 | SCSCR_CKE0,
-                .scbrr_algo_id  = SCBRR_ALGO_4,
-                .type           = PORT_SCIF,
-                .irqs           = { 56, 56, 56 },
-        }, {
-                .mapbase        = 0xa4400000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
-                .scbrr_algo_id  = SCBRR_ALGO_4,
-                .type           = PORT_SCIF,
-                .irqs           = { 52, 52, 52 },
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xa4410000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TIE | SCSCR_RIE  | SCSCR_TE |
+                          SCSCR_RE  | SCSCR_CKE1 | SCSCR_CKE0,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { 56, 56, 56 },
+};
+
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xa4400000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { 52, 52, 52 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif1_platform_data,
         },
 };
 
@@ -123,16 +129,13 @@ static struct platform_device rtc_device = {
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x02,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xfffffe94,
                 .end    = 0xfffffe9f,
                 .flags  = IORESOURCE_MEM,
@@ -154,16 +157,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0xe,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xfffffea0,
                 .end    = 0xfffffeab,
                 .flags  = IORESOURCE_MEM,
@@ -185,15 +185,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1a,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xfffffeac,
                 .end    = 0xfffffebb,
                 .flags  = IORESOURCE_MEM,
@@ -215,10 +212,11 @@ static struct platform_device tmu2_device = {
 };
 
 static struct platform_device *sh7705_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
-        &sci_device,
         &rtc_device,
 };
 
@@ -227,9 +225,11 @@ static int __init sh7705_devices_setup(void)
         return platform_add_devices(sh7705_devices,
                                     ARRAY_SIZE(sh7705_devices));
 }
-__initcall(sh7705_devices_setup);
+arch_initcall(sh7705_devices_setup);
 
 static struct platform_device *sh7705_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 83c9a5a39685..4551ad647c2c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -106,62 +106,70 @@ static struct platform_device rtc_device = {
         .resource       = rtc_resources,
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xfffffe80,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_TE | SCSCR_RE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCI,
-                .irqs           = { 23, 23, 23, 0 },
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xfffffe80,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TE | SCSCR_RE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCI,
+        .irqs           = { 23, 23, 23, 0 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
         },
+};
 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
     defined(CONFIG_CPU_SUBTYPE_SH7709)
-        {
-                .mapbase        = 0xa4000150,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_TE | SCSCR_RE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 56, 56, 56, 56 },
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xa4000150,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TE | SCSCR_RE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 56, 56, 56, 56 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
         },
+};
 #endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
     defined(CONFIG_CPU_SUBTYPE_SH7709)
-        {
-                .mapbase        = 0xa4000140,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_TE | SCSCR_RE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_IRDA,
-                .irqs           = { 52, 52, 52, 52 },
-        },
-#endif
-        {
-                .flags = 0,
-        }
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xa4000140,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TE | SCSCR_RE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_IRDA,
+        .irqs           = { 52, 52, 52, 52 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif2_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 2,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif2_platform_data,
         },
 };
+#endif
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x02,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xfffffe94,
                 .end    = 0xfffffe9f,
                 .flags  = IORESOURCE_MEM,
@@ -183,16 +191,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0xe,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xfffffea0,
                 .end    = 0xfffffeab,
                 .flags  = IORESOURCE_MEM,
@@ -214,15 +219,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1a,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xfffffeac,
                 .end    = 0xfffffebb,
                 .flags  = IORESOURCE_MEM,
@@ -244,10 +246,19 @@ static struct platform_device tmu2_device = {
 };
 
 static struct platform_device *sh770x_devices[] __initdata = {
+        &scif0_device,
+#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7709)
+        &scif1_device,
+#endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7709)
+        &scif2_device,
+#endif
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
-        &sci_device,
         &rtc_device,
 };
 
@@ -256,9 +267,19 @@ static int __init sh770x_devices_setup(void)
         return platform_add_devices(sh770x_devices,
                 ARRAY_SIZE(sh770x_devices));
 }
-__initcall(sh770x_devices_setup);
+arch_initcall(sh770x_devices_setup);
 
 static struct platform_device *sh770x_early_devices[] __initdata = {
+        &scif0_device,
+#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7709)
+        &scif1_device,
+#endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7709)
+        &scif2_device,
+#endif
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 9a60ffd34a9f..78f6b01d42c3 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -96,48 +96,50 @@ static struct platform_device rtc_device = {
         },
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xa4400000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
-                                  SCSCR_CKE1 | SCSCR_CKE0,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 52, 52, 52, 52 },
-        }, {
-                .mapbase        = 0xa4410000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
-                                  SCSCR_CKE1 | SCSCR_CKE0,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 56, 56, 56, 56 },
-        }, {
-
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xa4400000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
+                          SCSCR_CKE1 | SCSCR_CKE0,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 52, 52, 52, 52 },
+};
+
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xa4410000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
+                          SCSCR_CKE1 | SCSCR_CKE0,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 56, 56, 56, 56 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif1_platform_data,
         },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x02,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xa412fe94,
                 .end    = 0xa412fe9f,
                 .flags  = IORESOURCE_MEM,
@@ -159,16 +161,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0xe,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xa412fea0,
                 .end    = 0xa412feab,
                 .flags  = IORESOURCE_MEM,
@@ -190,15 +189,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1a,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xa412feac,
                 .end    = 0xa412feb5,
                 .flags  = IORESOURCE_MEM,
@@ -220,10 +216,11 @@ static struct platform_device tmu2_device = {
 };
 
 static struct platform_device *sh7710_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
-        &sci_device,
         &rtc_device,
 };
 
@@ -232,9 +229,11 @@ static int __init sh7710_devices_setup(void)
         return platform_add_devices(sh7710_devices,
                                     ARRAY_SIZE(sh7710_devices));
 }
-__initcall(sh7710_devices_setup);
+arch_initcall(sh7710_devices_setup);
 
 static struct platform_device *sh7710_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 48d50a65db32..365b94a6fcb7 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -48,31 +48,37 @@ static struct platform_device rtc_device = {
         },
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xa4430000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE,
-                .scbrr_algo_id  = SCBRR_ALGO_4,
-                .type           = PORT_SCIF,
-                .irqs           = { 80, 80, 80, 80 },
-        }, {
-                .mapbase        = 0xa4438000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE,
-                .scbrr_algo_id  = SCBRR_ALGO_4,
-                .type           = PORT_SCIF,
-                .irqs           = { 81, 81, 81, 81 },
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xa4430000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { 80, 80, 80, 80 },
+};
+
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xa4438000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
+        .type           = PORT_SCIF,
+        .irqs           = { 81, 81, 81, 81 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif1_platform_data,
         },
 };
 
@@ -128,17 +134,14 @@ static struct platform_device usbf_device = {
 };
 
 static struct sh_timer_config cmt0_platform_data = {
-        .name = "CMT0",
         .channel_offset = 0x10,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 125,
         .clocksource_rating = 125,
 };
 
 static struct resource cmt0_resources[] = {
         [0] = {
-                .name   = "CMT0",
                 .start  = 0x044a0010,
                 .end    = 0x044a001b,
                 .flags  = IORESOURCE_MEM,
@@ -160,15 +163,12 @@ static struct platform_device cmt0_device = {
 };
 
 static struct sh_timer_config cmt1_platform_data = {
-        .name = "CMT1",
         .channel_offset = 0x20,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
 };
 
 static struct resource cmt1_resources[] = {
         [0] = {
-                .name   = "CMT1",
                 .start  = 0x044a0020,
                 .end    = 0x044a002b,
                 .flags  = IORESOURCE_MEM,
@@ -190,15 +190,12 @@ static struct platform_device cmt1_device = {
 };
 
 static struct sh_timer_config cmt2_platform_data = {
-        .name = "CMT2",
         .channel_offset = 0x30,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource cmt2_resources[] = {
         [0] = {
-                .name   = "CMT2",
                 .start  = 0x044a0030,
                 .end    = 0x044a003b,
                 .flags  = IORESOURCE_MEM,
@@ -220,15 +217,12 @@ static struct platform_device cmt2_device = {
 };
 
 static struct sh_timer_config cmt3_platform_data = {
-        .name = "CMT3",
         .channel_offset = 0x40,
         .timer_bit = 3,
-        .clk = "peripheral_clk",
 };
 
 static struct resource cmt3_resources[] = {
         [0] = {
-                .name   = "CMT3",
                 .start  = 0x044a0040,
                 .end    = 0x044a004b,
                 .flags  = IORESOURCE_MEM,
@@ -250,15 +244,12 @@ static struct platform_device cmt3_device = {
 };
 
 static struct sh_timer_config cmt4_platform_data = {
-        .name = "CMT4",
         .channel_offset = 0x50,
         .timer_bit = 4,
-        .clk = "peripheral_clk",
 };
 
 static struct resource cmt4_resources[] = {
         [0] = {
-                .name   = "CMT4",
                 .start  = 0x044a0050,
                 .end    = 0x044a005b,
                 .flags  = IORESOURCE_MEM,
@@ -280,16 +271,13 @@ static struct platform_device cmt4_device = {
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x02,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xa412fe94,
                 .end    = 0xa412fe9f,
                 .flags  = IORESOURCE_MEM,
@@ -311,16 +299,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0xe,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xa412fea0,
                 .end    = 0xa412feab,
                 .flags  = IORESOURCE_MEM,
@@ -342,15 +327,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1a,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xa412feac,
                 .end    = 0xa412feb5,
                 .flags  = IORESOURCE_MEM,
@@ -372,6 +354,8 @@ static struct platform_device tmu2_device = {
 };
 
 static struct platform_device *sh7720_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &cmt0_device,
         &cmt1_device,
         &cmt2_device,
@@ -381,7 +365,6 @@ static struct platform_device *sh7720_devices[] __initdata = {
         &tmu1_device,
         &tmu2_device,
         &rtc_device,
-        &sci_device,
         &usb_ohci_device,
         &usbf_device,
 };
@@ -391,9 +374,11 @@ static int __init sh7720_devices_setup(void)
         return platform_add_devices(sh7720_devices,
                                     ARRAY_SIZE(sh7720_devices));
 }
-__initcall(sh7720_devices_setup);
+arch_initcall(sh7720_devices_setup);
 
 static struct platform_device *sh7720_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &cmt0_device,
         &cmt1_device,
         &cmt2_device,
diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile
index 203b18347b83..3a1dbc709831 100644
--- a/arch/sh/kernel/cpu/sh4/Makefile
+++ b/arch/sh/kernel/cpu/sh4/Makefile
@@ -9,6 +9,11 @@ obj-$(CONFIG_HIBERNATION)		+= $(addprefix ../sh3/, swsusp.o)
 obj-$(CONFIG_SH_FPU)                    += fpu.o softfloat.o
 obj-$(CONFIG_SH_STORE_QUEUES)           += sq.o
 
+# Perf events
+perf-$(CONFIG_CPU_SUBTYPE_SH7750)       := perf_event.o
+perf-$(CONFIG_CPU_SUBTYPE_SH7750S)      := perf_event.o
+perf-$(CONFIG_CPU_SUBTYPE_SH7091)       := perf_event.o
+
 # CPU subtype setup
 obj-$(CONFIG_CPU_SUBTYPE_SH7750)        += setup-sh7750.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7750R)       += setup-sh7750.o
@@ -27,4 +32,5 @@ endif
 # Additional clocks by subtype
 clock-$(CONFIG_CPU_SUBTYPE_SH4_202)     += clock-sh4-202.o
 
-obj-y   += $(clock-y)
+obj-y                                   += $(clock-y)
+obj-$(CONFIG_PERF_EVENTS)               += $(perf-y)
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index 21421e34e7d5..3f6f8e98635c 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -12,9 +12,10 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
-#include <asm/io.h>
 
 #define CPG2_FRQCR3     0xfe0a0018
 
@@ -23,7 +24,7 @@ static int frqcr3_values[]   = { 0, 1, 2, 3, 4, 5, 6  };
 
 static unsigned long emi_clk_recalc(struct clk *clk)
 {
-        int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007;
+        int idx = __raw_readl(CPG2_FRQCR3) & 0x0007;
         return clk->parent->rate / frqcr3_divisors[idx];
 }
 
@@ -45,14 +46,13 @@ static struct clk_ops sh4202_emi_clk_ops = {
 };
 
 static struct clk sh4202_emi_clk = {
-        .name           = "emi_clk",
         .flags          = CLK_ENABLE_ON_INIT,
         .ops            = &sh4202_emi_clk_ops,
 };
 
 static unsigned long femi_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007;
+        int idx = (__raw_readl(CPG2_FRQCR3) >> 3) & 0x0007;
         return clk->parent->rate / frqcr3_divisors[idx];
 }
 
@@ -61,7 +61,6 @@ static struct clk_ops sh4202_femi_clk_ops = {
 };
 
 static struct clk sh4202_femi_clk = {
-        .name           = "femi_clk",
         .flags          = CLK_ENABLE_ON_INIT,
         .ops            = &sh4202_femi_clk_ops,
 };
@@ -82,8 +81,7 @@ static void shoc_clk_init(struct clk *clk)
         for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) {
                 int divisor = frqcr3_divisors[i];
 
-                if (clk->ops->set_rate(clk, clk->parent->rate /
-                                                divisor, 0) == 0)
+                if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0)
                         break;
         }
 
@@ -92,7 +90,7 @@ static void shoc_clk_init(struct clk *clk)
 
 static unsigned long shoc_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007;
+        int idx = (__raw_readl(CPG2_FRQCR3) >> 6) & 0x0007;
         return clk->parent->rate / frqcr3_divisors[idx];
 }
 
@@ -111,7 +109,7 @@ static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id)
+static int shoc_clk_set_rate(struct clk *clk, unsigned long rate)
 {
         unsigned long frqcr3;
         unsigned int tmp;
@@ -122,10 +120,10 @@ static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id)
 
         tmp = frqcr3_lookup(clk, rate);
 
-        frqcr3 = ctrl_inl(CPG2_FRQCR3);
+        frqcr3 = __raw_readl(CPG2_FRQCR3);
         frqcr3 &= ~(0x0007 << 6);
         frqcr3 |= tmp << 6;
-        ctrl_outl(frqcr3, CPG2_FRQCR3);
+        __raw_writel(frqcr3, CPG2_FRQCR3);
 
         clk->rate = clk->parent->rate / frqcr3_divisors[tmp];
 
@@ -139,7 +137,6 @@ static struct clk_ops sh4202_shoc_clk_ops = {
 };
 
 static struct clk sh4202_shoc_clk = {
-        .name           = "shoc_clk",
         .flags          = CLK_ENABLE_ON_INIT,
         .ops            = &sh4202_shoc_clk_ops,
 };
@@ -150,6 +147,15 @@ static struct clk *sh4202_onchip_clocks[] = {
         &sh4202_shoc_clk,
 };
 
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk),
+        CLKDEV_CON_ID("femi_clk", &sh4202_femi_clk),
+        CLKDEV_CON_ID("shoc_clk", &sh4202_shoc_clk),
+};
+
 int __init arch_clk_init(void)
 {
         struct clk *clk;
@@ -167,5 +173,7 @@ int __init arch_clk_init(void)
 
         clk_put(clk);
 
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4.c b/arch/sh/kernel/cpu/sh4/clock-sh4.c
index 73294d9cd049..5add75c1f539 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4.c
@@ -28,7 +28,7 @@ static int pfc_divisors[] = { 2, 3, 4, 6, 8, 2, 2, 2 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0007];
+        clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007];
 }
 
 static struct clk_ops sh4_master_clk_ops = {
@@ -37,7 +37,7 @@ static struct clk_ops sh4_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) & 0x0007);
+        int idx = (__raw_readw(FRQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -47,7 +47,7 @@ static struct clk_ops sh4_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) >> 3) & 0x0007;
+        int idx = (__raw_readw(FRQCR) >> 3) & 0x0007;
         return clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -57,7 +57,7 @@ static struct clk_ops sh4_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) >> 6) & 0x0007;
+        int idx = (__raw_readw(FRQCR) >> 6) & 0x0007;
         return clk->parent->rate / ifc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh4/fpu.c b/arch/sh/kernel/cpu/sh4/fpu.c
index e3ea5411da6d..447482d7f65e 100644
--- a/arch/sh/kernel/cpu/sh4/fpu.c
+++ b/arch/sh/kernel/cpu/sh4/fpu.c
@@ -41,13 +41,11 @@ static unsigned int fpu_exception_flags;
 
 /*
  * Save FPU registers onto task structure.
- * Assume called with FPU enabled (SR.FD=0).
  */
-void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
+void save_fpu(struct task_struct *tsk)
 {
         unsigned long dummy;
 
-        clear_tsk_thread_flag(tsk, TIF_USEDFPU);
         enable_fpu();
         asm volatile ("sts.l    fpul, @-%0\n\t"
                       "sts.l    fpscr, @-%0\n\t"
@@ -87,15 +85,14 @@ void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
                       "fmov.s   fr1, @-%0\n\t"
                       "fmov.s   fr0, @-%0\n\t"
                       "lds      %3, fpscr\n\t":"=r" (dummy)
-                      :"0"((char *)(&tsk->thread.fpu.hard.status)),
+                      :"0"((char *)(&tsk->thread.xstate->hardfpu.status)),
                       "r"(FPSCR_RCHG), "r"(FPSCR_INIT)
                       :"memory");
 
         disable_fpu();
-        release_fpu(regs);
 }
 
-static void restore_fpu(struct task_struct *tsk)
+void restore_fpu(struct task_struct *tsk)
 {
         unsigned long dummy;
 
@@ -138,62 +135,11 @@ static void restore_fpu(struct task_struct *tsk)
                       "lds.l    @%0+, fpscr\n\t"
                       "lds.l    @%0+, fpul\n\t"
                       :"=r" (dummy)
-                      :"0"(&tsk->thread.fpu), "r"(FPSCR_RCHG)
+                      :"0" (tsk->thread.xstate), "r" (FPSCR_RCHG)
                       :"memory");
         disable_fpu();
 }
 
-/*
- * Load the FPU with signalling NANS.  This bit pattern we're using
- * has the property that no matter wether considered as single or as
- * double precision represents signaling NANS.
- */
-
-static void fpu_init(void)
-{
-        enable_fpu();
-        asm volatile (  "lds    %0, fpul\n\t"
-                        "lds    %1, fpscr\n\t"
-                        "fsts   fpul, fr0\n\t"
-                        "fsts   fpul, fr1\n\t"
-                        "fsts   fpul, fr2\n\t"
-                        "fsts   fpul, fr3\n\t"
-                        "fsts   fpul, fr4\n\t"
-                        "fsts   fpul, fr5\n\t"
-                        "fsts   fpul, fr6\n\t"
-                        "fsts   fpul, fr7\n\t"
-                        "fsts   fpul, fr8\n\t"
-                        "fsts   fpul, fr9\n\t"
-                        "fsts   fpul, fr10\n\t"
-                        "fsts   fpul, fr11\n\t"
-                        "fsts   fpul, fr12\n\t"
-                        "fsts   fpul, fr13\n\t"
-                        "fsts   fpul, fr14\n\t"
-                        "fsts   fpul, fr15\n\t"
-                        "frchg\n\t"
-                        "fsts   fpul, fr0\n\t"
-                        "fsts   fpul, fr1\n\t"
-                        "fsts   fpul, fr2\n\t"
-                        "fsts   fpul, fr3\n\t"
-                        "fsts   fpul, fr4\n\t"
-                        "fsts   fpul, fr5\n\t"
-                        "fsts   fpul, fr6\n\t"
-                        "fsts   fpul, fr7\n\t"
-                        "fsts   fpul, fr8\n\t"
-                        "fsts   fpul, fr9\n\t"
-                        "fsts   fpul, fr10\n\t"
-                        "fsts   fpul, fr11\n\t"
-                        "fsts   fpul, fr12\n\t"
-                        "fsts   fpul, fr13\n\t"
-                        "fsts   fpul, fr14\n\t"
-                        "fsts   fpul, fr15\n\t"
-                        "frchg\n\t"
-                        "lds    %2, fpscr\n\t"
-                        :       /* no output */
-                        :"r" (0), "r"(FPSCR_RCHG), "r"(FPSCR_INIT));
-        disable_fpu();
-}
-
 /**
  *      denormal_to_double - Given denormalized float number,
  *                           store double float
@@ -285,10 +231,9 @@ static int ieee_fpe_handler(struct pt_regs *regs)
                 /* fcnvsd */
                 struct task_struct *tsk = current;
 
-                save_fpu(tsk, regs);
-                if ((tsk->thread.fpu.hard.fpscr & FPSCR_CAUSE_ERROR))
+                if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_CAUSE_ERROR))
                         /* FPU error */
-                        denormal_to_double(&tsk->thread.fpu.hard,
+                        denormal_to_double(&tsk->thread.xstate->hardfpu,
                                            (finsn >> 8) & 0xf);
                 else
                         return 0;
@@ -304,9 +249,9 @@ static int ieee_fpe_handler(struct pt_regs *regs)
 
                 n = (finsn >> 8) & 0xf;
                 m = (finsn >> 4) & 0xf;
-                hx = tsk->thread.fpu.hard.fp_regs[n];
-                hy = tsk->thread.fpu.hard.fp_regs[m];
-                fpscr = tsk->thread.fpu.hard.fpscr;
+                hx = tsk->thread.xstate->hardfpu.fp_regs[n];
+                hy = tsk->thread.xstate->hardfpu.fp_regs[m];
+                fpscr = tsk->thread.xstate->hardfpu.fpscr;
                 prec = fpscr & FPSCR_DBL_PRECISION;
 
                 if ((fpscr & FPSCR_CAUSE_ERROR)
@@ -316,18 +261,18 @@ static int ieee_fpe_handler(struct pt_regs *regs)
 
                         /* FPU error because of denormal (doubles) */
                         llx = ((long long)hx << 32)
-                            | tsk->thread.fpu.hard.fp_regs[n + 1];
+                            | tsk->thread.xstate->hardfpu.fp_regs[n + 1];
                         lly = ((long long)hy << 32)
-                            | tsk->thread.fpu.hard.fp_regs[m + 1];
+                            | tsk->thread.xstate->hardfpu.fp_regs[m + 1];
                         llx = float64_mul(llx, lly);
-                        tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
-                        tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
+                        tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
                 } else if ((fpscr & FPSCR_CAUSE_ERROR)
                            && (!prec && ((hx & 0x7fffffff) < 0x00800000
                                          || (hy & 0x7fffffff) < 0x00800000))) {
                         /* FPU error because of denormal (floats) */
                         hx = float32_mul(hx, hy);
-                        tsk->thread.fpu.hard.fp_regs[n] = hx;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
                 } else
                         return 0;
 
@@ -342,9 +287,9 @@ static int ieee_fpe_handler(struct pt_regs *regs)
 
                 n = (finsn >> 8) & 0xf;
                 m = (finsn >> 4) & 0xf;
-                hx = tsk->thread.fpu.hard.fp_regs[n];
-                hy = tsk->thread.fpu.hard.fp_regs[m];
-                fpscr = tsk->thread.fpu.hard.fpscr;
+                hx = tsk->thread.xstate->hardfpu.fp_regs[n];
+                hy = tsk->thread.xstate->hardfpu.fp_regs[m];
+                fpscr = tsk->thread.xstate->hardfpu.fpscr;
                 prec = fpscr & FPSCR_DBL_PRECISION;
 
                 if ((fpscr & FPSCR_CAUSE_ERROR)
@@ -354,15 +299,15 @@ static int ieee_fpe_handler(struct pt_regs *regs)
 
                         /* FPU error because of denormal (doubles) */
                         llx = ((long long)hx << 32)
-                            | tsk->thread.fpu.hard.fp_regs[n + 1];
+                            | tsk->thread.xstate->hardfpu.fp_regs[n + 1];
                         lly = ((long long)hy << 32)
-                            | tsk->thread.fpu.hard.fp_regs[m + 1];
+                            | tsk->thread.xstate->hardfpu.fp_regs[m + 1];
                         if ((finsn & 0xf00f) == 0xf000)
                                 llx = float64_add(llx, lly);
                         else
                                 llx = float64_sub(llx, lly);
-                        tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
-                        tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
+                        tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
                 } else if ((fpscr & FPSCR_CAUSE_ERROR)
                            && (!prec && ((hx & 0x7fffffff) < 0x00800000
                                          || (hy & 0x7fffffff) < 0x00800000))) {
@@ -371,7 +316,7 @@ static int ieee_fpe_handler(struct pt_regs *regs)
                                 hx = float32_add(hx, hy);
                         else
                                 hx = float32_sub(hx, hy);
-                        tsk->thread.fpu.hard.fp_regs[n] = hx;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
                 } else
                         return 0;
 
@@ -386,9 +331,9 @@ static int ieee_fpe_handler(struct pt_regs *regs)
 
                 n = (finsn >> 8) & 0xf;
                 m = (finsn >> 4) & 0xf;
-                hx = tsk->thread.fpu.hard.fp_regs[n];
-                hy = tsk->thread.fpu.hard.fp_regs[m];
-                fpscr = tsk->thread.fpu.hard.fpscr;
+                hx = tsk->thread.xstate->hardfpu.fp_regs[n];
+                hy = tsk->thread.xstate->hardfpu.fp_regs[m];
+                fpscr = tsk->thread.xstate->hardfpu.fpscr;
                 prec = fpscr & FPSCR_DBL_PRECISION;
 
                 if ((fpscr & FPSCR_CAUSE_ERROR)
@@ -398,20 +343,20 @@ static int ieee_fpe_handler(struct pt_regs *regs)
 
                         /* FPU error because of denormal (doubles) */
                         llx = ((long long)hx << 32)
-                            | tsk->thread.fpu.hard.fp_regs[n + 1];
+                            | tsk->thread.xstate->hardfpu.fp_regs[n + 1];
                         lly = ((long long)hy << 32)
-                            | tsk->thread.fpu.hard.fp_regs[m + 1];
+                            | tsk->thread.xstate->hardfpu.fp_regs[m + 1];
 
                         llx = float64_div(llx, lly);
 
-                        tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
-                        tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
+                        tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
                 } else if ((fpscr & FPSCR_CAUSE_ERROR)
                            && (!prec && ((hx & 0x7fffffff) < 0x00800000
                                          || (hy & 0x7fffffff) < 0x00800000))) {
                         /* FPU error because of denormal (floats) */
                         hx = float32_div(hx, hy);
-                        tsk->thread.fpu.hard.fp_regs[n] = hx;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
                 } else
                         return 0;
 
@@ -424,17 +369,17 @@ static int ieee_fpe_handler(struct pt_regs *regs)
                 unsigned int hx;
 
                 m = (finsn >> 8) & 0x7;
-                hx = tsk->thread.fpu.hard.fp_regs[m];
+                hx = tsk->thread.xstate->hardfpu.fp_regs[m];
 
-                if ((tsk->thread.fpu.hard.fpscr & FPSCR_CAUSE_ERROR)
+                if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_CAUSE_ERROR)
                         && ((hx & 0x7fffffff) < 0x00100000)) {
                         /* subnormal double to float conversion */
                         long long llx;
 
-                        llx = ((long long)tsk->thread.fpu.hard.fp_regs[m] << 32)
-                            | tsk->thread.fpu.hard.fp_regs[m + 1];
+                        llx = ((long long)tsk->thread.xstate->hardfpu.fp_regs[m] << 32)
+                            | tsk->thread.xstate->hardfpu.fp_regs[m + 1];
 
-                        tsk->thread.fpu.hard.fpul = float64_to_float32(llx);
+                        tsk->thread.xstate->hardfpu.fpul = float64_to_float32(llx);
                 } else
                         return 0;
 
@@ -453,7 +398,7 @@ void float_raise(unsigned int flags)
 int float_rounding_mode(void)
 {
         struct task_struct *tsk = current;
-        int roundingMode = FPSCR_ROUNDING_MODE(tsk->thread.fpu.hard.fpscr);
+        int roundingMode = FPSCR_ROUNDING_MODE(tsk->thread.xstate->hardfpu.fpscr);
         return roundingMode;
 }
 
@@ -462,19 +407,19 @@ BUILD_TRAP_HANDLER(fpu_error)
         struct task_struct *tsk = current;
         TRAP_HANDLER_DECL;
 
-        save_fpu(tsk, regs);
+        __unlazy_fpu(tsk, regs);
         fpu_exception_flags = 0;
         if (ieee_fpe_handler(regs)) {
-                tsk->thread.fpu.hard.fpscr &=
+                tsk->thread.xstate->hardfpu.fpscr &=
                     ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
-                tsk->thread.fpu.hard.fpscr |= fpu_exception_flags;
+                tsk->thread.xstate->hardfpu.fpscr |= fpu_exception_flags;
                 /* Set the FPSCR flag as well as cause bits - simply
                  * replicate the cause */
-                tsk->thread.fpu.hard.fpscr |= (fpu_exception_flags >> 10);
+                tsk->thread.xstate->hardfpu.fpscr |= (fpu_exception_flags >> 10);
                 grab_fpu(regs);
                 restore_fpu(tsk);
-                set_tsk_thread_flag(tsk, TIF_USEDFPU);
-                if ((((tsk->thread.fpu.hard.fpscr & FPSCR_ENABLE_MASK) >> 7) &
+                task_thread_info(tsk)->status |= TS_USEDFPU;
+                if ((((tsk->thread.xstate->hardfpu.fpscr & FPSCR_ENABLE_MASK) >> 7) &
                      (fpu_exception_flags >> 2)) == 0) {
                         return;
                 }
@@ -482,25 +427,3 @@ BUILD_TRAP_HANDLER(fpu_error)
 
         force_sig(SIGFPE, tsk);
 }
-
-BUILD_TRAP_HANDLER(fpu_state_restore)
-{
-        struct task_struct *tsk = current;
-        TRAP_HANDLER_DECL;
-
-        grab_fpu(regs);
-        if (!user_mode(regs)) {
-                printk(KERN_ERR "BUG: FPU is used in kernel mode.\n");
-                return;
-        }
-
-        if (used_math()) {
-                /* Using the FPU again.  */
-                restore_fpu(tsk);
-        } else {
-                /* First time FPU user.  */
-                fpu_init();
-                set_used_math();
-        }
-        set_tsk_thread_flag(tsk, TIF_USEDFPU);
-}
diff --git a/arch/sh/kernel/cpu/sh4/perf_event.c b/arch/sh/kernel/cpu/sh4/perf_event.c
new file mode 100644
index 000000000000..748955df018d
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4/perf_event.c
@@ -0,0 +1,253 @@
+/*
+ * Performance events support for SH7750-style performance counters
+ *
+ *  Copyright (C) 2009  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/perf_event.h>
+#include <asm/processor.h>
+
+#define PM_CR_BASE      0xff000084      /* 16-bit */
+#define PM_CTR_BASE     0xff100004      /* 32-bit */
+
+#define PMCR(n)         (PM_CR_BASE + ((n) * 0x04))
+#define PMCTRH(n)       (PM_CTR_BASE + 0x00 + ((n) * 0x08))
+#define PMCTRL(n)       (PM_CTR_BASE + 0x04 + ((n) * 0x08))
+
+#define PMCR_PMM_MASK   0x0000003f
+
+#define PMCR_CLKF       0x00000100
+#define PMCR_PMCLR      0x00002000
+#define PMCR_PMST       0x00004000
+#define PMCR_PMEN       0x00008000
+
+static struct sh_pmu sh7750_pmu;
+
+/*
+ * There are a number of events supported by each counter (33 in total).
+ * Since we have 2 counters, each counter will take the event code as it
+ * corresponds to the PMCR PMM setting. Each counter can be configured
+ * independently.
+ *
+ *      Event Code      Description
+ *      ----------      -----------
+ *
+ *      0x01            Operand read access
+ *      0x02            Operand write access
+ *      0x03            UTLB miss
+ *      0x04            Operand cache read miss
+ *      0x05            Operand cache write miss
+ *      0x06            Instruction fetch (w/ cache)
+ *      0x07            Instruction TLB miss
+ *      0x08            Instruction cache miss
+ *      0x09            All operand accesses
+ *      0x0a            All instruction accesses
+ *      0x0b            OC RAM operand access
+ *      0x0d            On-chip I/O space access
+ *      0x0e            Operand access (r/w)
+ *      0x0f            Operand cache miss (r/w)
+ *      0x10            Branch instruction
+ *      0x11            Branch taken
+ *      0x12            BSR/BSRF/JSR
+ *      0x13            Instruction execution
+ *      0x14            Instruction execution in parallel
+ *      0x15            FPU Instruction execution
+ *      0x16            Interrupt
+ *      0x17            NMI
+ *      0x18            trapa instruction execution
+ *      0x19            UBCA match
+ *      0x1a            UBCB match
+ *      0x21            Instruction cache fill
+ *      0x22            Operand cache fill
+ *      0x23            Elapsed time
+ *      0x24            Pipeline freeze by I-cache miss
+ *      0x25            Pipeline freeze by D-cache miss
+ *      0x27            Pipeline freeze by branch instruction
+ *      0x28            Pipeline freeze by CPU register
+ *      0x29            Pipeline freeze by FPU
+ */
+
+static const int sh7750_general_events[] = {
+        [PERF_COUNT_HW_CPU_CYCLES]              = 0x0023,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = 0x000a,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x0006,       /* I-cache */
+        [PERF_COUNT_HW_CACHE_MISSES]            = 0x0008,       /* I-cache */
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x0010,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = -1,
+        [PERF_COUNT_HW_BUS_CYCLES]              = -1,
+};
+
+#define C(x)    PERF_COUNT_HW_CACHE_##x
+
+static const int sh7750_cache_events
+                        [PERF_COUNT_HW_CACHE_MAX]
+                        [PERF_COUNT_HW_CACHE_OP_MAX]
+                        [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+        [ C(L1D) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0001,
+                        [ C(RESULT_MISS)   ] = 0x0004,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0002,
+                        [ C(RESULT_MISS)   ] = 0x0005,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+
+        [ C(L1I) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0006,
+                        [ C(RESULT_MISS)   ] = 0x0008,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+
+        [ C(LL) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+
+        [ C(DTLB) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0x0003,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+
+        [ C(ITLB) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0x0007,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+        },
+
+        [ C(BPU) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+        },
+};
+
+static int sh7750_event_map(int event)
+{
+        return sh7750_general_events[event];
+}
+
+static u64 sh7750_pmu_read(int idx)
+{
+        return (u64)((u64)(__raw_readl(PMCTRH(idx)) & 0xffff) << 32) |
+                           __raw_readl(PMCTRL(idx));
+}
+
+static void sh7750_pmu_disable(struct hw_perf_event *hwc, int idx)
+{
+        unsigned int tmp;
+
+        tmp = __raw_readw(PMCR(idx));
+        tmp &= ~(PMCR_PMM_MASK | PMCR_PMEN);
+        __raw_writew(tmp, PMCR(idx));
+}
+
+static void sh7750_pmu_enable(struct hw_perf_event *hwc, int idx)
+{
+        __raw_writew(__raw_readw(PMCR(idx)) | PMCR_PMCLR, PMCR(idx));
+        __raw_writew(hwc->config | PMCR_PMEN | PMCR_PMST, PMCR(idx));
+}
+
+static void sh7750_pmu_disable_all(void)
+{
+        int i;
+
+        for (i = 0; i < sh7750_pmu.num_events; i++)
+                __raw_writew(__raw_readw(PMCR(i)) & ~PMCR_PMEN, PMCR(i));
+}
+
+static void sh7750_pmu_enable_all(void)
+{
+        int i;
+
+        for (i = 0; i < sh7750_pmu.num_events; i++)
+                __raw_writew(__raw_readw(PMCR(i)) | PMCR_PMEN, PMCR(i));
+}
+
+static struct sh_pmu sh7750_pmu = {
+        .name           = "sh7750",
+        .num_events     = 2,
+        .event_map      = sh7750_event_map,
+        .max_events     = ARRAY_SIZE(sh7750_general_events),
+        .raw_event_mask = PMCR_PMM_MASK,
+        .cache_events   = &sh7750_cache_events,
+        .read           = sh7750_pmu_read,
+        .disable        = sh7750_pmu_disable,
+        .enable         = sh7750_pmu_enable,
+        .disable_all    = sh7750_pmu_disable_all,
+        .enable_all     = sh7750_pmu_enable_all,
+};
+
+static int __init sh7750_pmu_init(void)
+{
+        /*
+         * Make sure this CPU actually has perf counters.
+         */
+        if (!(boot_cpu_data.flags & CPU_HAS_PERF_COUNTER)) {
+                pr_notice("HW perf events unsupported, software events only.\n");
+                return -ENODEV;
+        }
+
+        return register_sh_pmu(&sh7750_pmu);
+}
+early_initcall(sh7750_pmu_init);
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 6c78d0a9c857..b93458f33b74 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -15,7 +15,7 @@
 #include <asm/processor.h>
 #include <asm/cache.h>
 
-int __init detect_cpu_and_cache_system(void)
+void __cpuinit cpu_probe(void)
 {
         unsigned long pvr, prr, cvr;
         unsigned long size;
@@ -28,9 +28,9 @@ int __init detect_cpu_and_cache_system(void)
                 [9] = (1 << 16)
         };
 
-        pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
-        prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
-        cvr = (ctrl_inl(CCN_CVR));
+        pvr = (__raw_readl(CCN_PVR) >> 8) & 0xffffff;
+        prr = (__raw_readl(CCN_PRR) >> 4) & 0xff;
+        cvr = (__raw_readl(CCN_CVR));
 
         /*
          * Setup some sane SH-4 defaults for the icache
@@ -57,8 +57,12 @@ int __init detect_cpu_and_cache_system(void)
          * Setup some generic flags we can probe on SH-4A parts
          */
         if (((pvr >> 16) & 0xff) == 0x10) {
-                if ((cvr & 0x10000000) == 0)
+                boot_cpu_data.family = CPU_FAMILY_SH4A;
+
+                if ((cvr & 0x10000000) == 0) {
                         boot_cpu_data.flags |= CPU_HAS_DSP;
+                        boot_cpu_data.family = CPU_FAMILY_SH4AL_DSP;
+                }
 
                 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER;
                 boot_cpu_data.cut_major = pvr & 0x7f;
@@ -67,10 +71,11 @@ int __init detect_cpu_and_cache_system(void)
                 boot_cpu_data.dcache.ways = 4;
         } else {
                 /* And some SH-4 defaults.. */
-                boot_cpu_data.flags |= CPU_HAS_PTEA;
+                boot_cpu_data.flags |= CPU_HAS_PTEA | CPU_HAS_FPU;
+                boot_cpu_data.family = CPU_FAMILY_SH4;
         }
 
-        /* FPU detection works for everyone */
+        /* FPU detection works for almost everyone */
         if ((cvr & 0x20000000))
                 boot_cpu_data.flags |= CPU_HAS_FPU;
 
@@ -119,6 +124,7 @@ int __init detect_cpu_and_cache_system(void)
                 boot_cpu_data.type = CPU_SH7785;
                 break;
         case 0x4004:
+        case 0x4005:
                 boot_cpu_data.type = CPU_SH7786;
                 boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
                 break;
@@ -139,8 +145,15 @@ int __init detect_cpu_and_cache_system(void)
                 }
                 break;
         case 0x300b:
-                boot_cpu_data.type = CPU_SH7724;
-                boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
+                switch (prr) {
+                case 0x20:
+                        boot_cpu_data.type = CPU_SH7724;
+                        boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
+                        break;
+                case 0x10:
+                        boot_cpu_data.type = CPU_SH7757;
+                        break;
+                }
                 break;
         case 0x4000:    /* 1st cut */
         case 0x4001:    /* 2nd cut */
@@ -148,6 +161,7 @@ int __init detect_cpu_and_cache_system(void)
                 break;
         case 0x700:
                 boot_cpu_data.type = CPU_SH4_501;
+                boot_cpu_data.flags &= ~CPU_HAS_FPU;
                 boot_cpu_data.icache.ways = 2;
                 boot_cpu_data.dcache.ways = 2;
                 break;
@@ -173,9 +187,6 @@ int __init detect_cpu_and_cache_system(void)
                 boot_cpu_data.dcache.ways = 2;
 
                 break;
-        default:
-                boot_cpu_data.type = CPU_SH_NONE;
-                break;
         }
 
         /*
@@ -218,7 +229,7 @@ int __init detect_cpu_and_cache_system(void)
                          * Size calculation is much more sensible
                          * than it is for the L1.
                          *
-                         * Sizes are 128KB, 258KB, 512KB, and 1MB.
+                         * Sizes are 128KB, 256KB, 512KB, and 1MB.
                          */
                         size = (cvr & 0xf) << 17;
 
@@ -240,6 +251,4 @@ int __init detect_cpu_and_cache_system(void)
                                  boot_cpu_data.scache.linesz);
                 }
         }
-
-        return 0;
 }
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index ec2104b49ef7..5b2833159b7d 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -15,38 +15,31 @@
 #include <linux/sh_timer.h>
 #include <linux/io.h>
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe80000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 41, 43, 42 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe80000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 41, 43, 42 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif0_platform_data,
         },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -68,16 +61,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -99,15 +89,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002f,
                 .flags  = IORESOURCE_MEM,
@@ -129,7 +116,7 @@ static struct platform_device tmu2_device = {
 };
 
 static struct platform_device *sh4202_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -140,9 +127,10 @@ static int __init sh4202_devices_setup(void)
         return platform_add_devices(sh4202_devices,
                                     ARRAY_SIZE(sh4202_devices));
 }
-__initcall(sh4202_devices_setup);
+arch_initcall(sh4202_devices_setup);
 
 static struct platform_device *sh4202_early_devices[] __initdata = {
+        &scif0_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -203,7 +191,7 @@ void __init plat_irq_setup_pins(int mode)
 {
         switch (mode) {
         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
-                ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
+                __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
                 register_intc_controller(&intc_desc_irlm);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 51a945e0d72c..c2b0aaaedcae 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -39,16 +39,17 @@ static struct platform_device rtc_device = {
 static struct plat_sci_port sci_platform_data = {
         .mapbase        = 0xffe00000,
         .flags          = UPF_BOOT_AUTOCONF,
-        .type           = PORT_SCI,
         .scscr          = SCSCR_TE | SCSCR_RE,
         .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCI,
         .irqs           = { 23, 23, 23, 0 },
 };
 
 static struct platform_device sci_device = {
         .name           = "sh-sci",
+        .id             = 0,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &sci_platform_data,
         },
 };
 
@@ -63,22 +64,20 @@ static struct plat_sci_port scif_platform_data = {
 
 static struct platform_device scif_device = {
         .name           = "sh-sci",
+        .id             = 1,
         .dev            = {
-                .platform_data  = scif_platform_data,
+                .platform_data  = &scif_platform_data,
         },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -100,16 +99,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -131,15 +127,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002f,
                 .flags  = IORESOURCE_MEM,
@@ -166,15 +159,12 @@ static struct platform_device tmu2_device = {
         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 
 static struct sh_timer_config tmu3_platform_data = {
-        .name = "TMU3",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu3_resources[] = {
         [0] = {
-                .name   = "TMU3",
                 .start  = 0xfe100008,
                 .end    = 0xfe100013,
                 .flags  = IORESOURCE_MEM,
@@ -196,15 +186,12 @@ static struct platform_device tmu3_device = {
 };
 
 static struct sh_timer_config tmu4_platform_data = {
-        .name = "TMU4",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu4_resources[] = {
         [0] = {
-                .name   = "TMU4",
                 .start  = 0xfe100014,
                 .end    = 0xfe10001f,
                 .flags  = IORESOURCE_MEM,
@@ -243,7 +230,6 @@ static struct platform_device *sh7750_devices[] __initdata = {
 static int __init sh7750_devices_setup(void)
 {
         if (mach_is_rts7751r2d()) {
-                scif_platform_data.scscr |= SCSCR_CKE1;
                 platform_register_device(&scif_device);
         } else {
                 platform_register_device(&sci_device);
@@ -253,7 +239,7 @@ static int __init sh7750_devices_setup(void)
         return platform_add_devices(sh7750_devices,
                                     ARRAY_SIZE(sh7750_devices));
 }
-__initcall(sh7750_devices_setup);
+arch_initcall(sh7750_devices_setup);
 
 static struct platform_device *sh7750_early_devices[] __initdata = {
         &tmu0_device,
@@ -269,6 +255,14 @@ static struct platform_device *sh7750_early_devices[] __initdata = {
 
 void __init plat_early_device_setup(void)
 {
+        if (mach_is_rts7751r2d()) {
+                scif_platform_data.scscr |= SCSCR_CKE1;
+                early_platform_add_devices(&scif_device, 1);
+        } else {
+                early_platform_add_devices(&sci_device, 1);
+                early_platform_add_devices(&scif_device, 1);
+        }
+
         early_platform_add_devices(sh7750_early_devices,
                                    ARRAY_SIZE(sh7750_early_devices));
 }
@@ -449,7 +443,7 @@ void __init plat_irq_setup_pins(int mode)
 
         switch (mode) {
         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
-                ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
+                __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
                 register_intc_controller(&intc_desc_irlm);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index cee660fe1d90..78bbf232e391 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -126,59 +126,82 @@ static struct intc_vect vectors_irq[] __initdata = {
 static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
                          mask_registers, prio_registers, NULL);
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xfe600000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 52, 53, 55, 54 },
-        }, {
-                .mapbase        = 0xfe610000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 72, 73, 75, 74 },
-        }, {
-                .mapbase        = 0xfe620000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 76, 77, 79, 78 },
-        }, {
-                .mapbase        = 0xfe480000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCI,
-                .irqs           = { 80, 81, 82, 0 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xfe600000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 52, 53, 55, 54 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xfe610000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .irqs           = { 72, 73, 75, 74 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xfe620000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 76, 77, 79, 78 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xfe480000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCI,
+        .irqs           = { 80, 81, 82, 0 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif3_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 3,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif3_platform_data,
         },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -200,16 +223,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -231,15 +251,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002f,
                 .flags  = IORESOURCE_MEM,
@@ -262,7 +279,10 @@ static struct platform_device tmu2_device = {
 
 
 static struct platform_device *sh7760_devices[] __initdata = {
-        &sci_device,
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -273,9 +293,13 @@ static int __init sh7760_devices_setup(void)
         return platform_add_devices(sh7760_devices,
                                     ARRAY_SIZE(sh7760_devices));
 }
-__initcall(sh7760_devices_setup);
+arch_initcall(sh7760_devices_setup);
 
 static struct platform_device *sh7760_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -294,7 +318,7 @@ void __init plat_irq_setup_pins(int mode)
 {
         switch (mode) {
         case IRQ_MODE_IRQ:
-                ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
+                __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
                 register_intc_controller(&intc_desc_irq);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c
index 8a8a993f55ea..14726eef1ce0 100644
--- a/arch/sh/kernel/cpu/sh4/sq.c
+++ b/arch/sh/kernel/cpu/sh4/sq.c
@@ -43,9 +43,9 @@ static unsigned long *sq_bitmap;
 
 #define store_queue_barrier()                   \
 do {                                            \
-        (void)ctrl_inl(P4SEG_STORE_QUE);        \
-        ctrl_outl(0, P4SEG_STORE_QUE + 0);      \
-        ctrl_outl(0, P4SEG_STORE_QUE + 8);      \
+        (void)__raw_readl(P4SEG_STORE_QUE);     \
+        __raw_writel(0, P4SEG_STORE_QUE + 0);   \
+        __raw_writel(0, P4SEG_STORE_QUE + 8);   \
 } while (0);
 
 /**
@@ -100,7 +100,7 @@ static inline void sq_mapping_list_del(struct sq_mapping *map)
         spin_unlock_irq(&sq_mapping_lock);
 }
 
-static int __sq_remap(struct sq_mapping *map, unsigned long flags)
+static int __sq_remap(struct sq_mapping *map, pgprot_t prot)
 {
 #if defined(CONFIG_MMU)
         struct vm_struct *vma;
@@ -113,7 +113,7 @@ static int __sq_remap(struct sq_mapping *map, unsigned long flags)
 
         if (ioremap_page_range((unsigned long)vma->addr,
                                (unsigned long)vma->addr + map->size,
-                               vma->phys_addr, __pgprot(flags))) {
+                               vma->phys_addr, prot)) {
                 vunmap(vma->addr);
                 return -EAGAIN;
         }
@@ -123,8 +123,8 @@ static int __sq_remap(struct sq_mapping *map, unsigned long flags)
          * straightforward, as we can just load up each queue's QACR with
          * the physical address appropriately masked.
          */
-        ctrl_outl(((map->addr >> 26) << 2) & 0x1c, SQ_QACR0);
-        ctrl_outl(((map->addr >> 26) << 2) & 0x1c, SQ_QACR1);
+        __raw_writel(((map->addr >> 26) << 2) & 0x1c, SQ_QACR0);
+        __raw_writel(((map->addr >> 26) << 2) & 0x1c, SQ_QACR1);
 #endif
 
         return 0;
@@ -135,14 +135,14 @@ static int __sq_remap(struct sq_mapping *map, unsigned long flags)
  * @phys: Physical address of mapping.
  * @size: Length of mapping.
  * @name: User invoking mapping.
- * @flags: Protection flags.
+ * @prot: Protection bits.
  *
  * Remaps the physical address @phys through the next available store queue
  * address of @size length. @name is logged at boot time as well as through
  * the sysfs interface.
  */
 unsigned long sq_remap(unsigned long phys, unsigned int size,
-                       const char *name, unsigned long flags)
+                       const char *name, pgprot_t prot)
 {
         struct sq_mapping *map;
         unsigned long end;
@@ -177,7 +177,7 @@ unsigned long sq_remap(unsigned long phys, unsigned int size,
 
         map->sq_addr = P4SEG_STORE_QUE + (page << PAGE_SHIFT);
 
-        ret = __sq_remap(map, pgprot_val(PAGE_KERNEL_NOCACHE) | flags);
+        ret = __sq_remap(map, prot);
         if (unlikely(ret != 0))
                 goto out;
 
@@ -309,8 +309,7 @@ static ssize_t mapping_store(const char *buf, size_t count)
                 return -EIO;
 
         if (likely(len)) {
-                int ret = sq_remap(base, len, "Userspace",
-                                   pgprot_val(PAGE_SHARED));
+                int ret = sq_remap(base, len, "Userspace", PAGE_SHARED);
                 if (ret < 0)
                         return ret;
         } else
@@ -327,7 +326,7 @@ static struct attribute *sq_sysfs_attrs[] = {
         NULL,
 };
 
-static struct sysfs_ops sq_sysfs_ops = {
+static const struct sysfs_ops sq_sysfs_ops = {
         .show   = sq_sysfs_show,
         .store  = sq_sysfs_store,
 };
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index ebdd391d5f42..cc122b1d3035 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -3,31 +3,33 @@
 #
 
 # CPU subtype setup
+obj-$(CONFIG_CPU_SUBTYPE_SH7757)        += setup-sh7757.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7763)        += setup-sh7763.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7770)        += setup-sh7770.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7780)        += setup-sh7780.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7785)        += setup-sh7785.o
-obj-$(CONFIG_CPU_SUBTYPE_SH7786)        += setup-sh7786.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7786)        += setup-sh7786.o intc-shx3.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7343)        += setup-sh7343.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7722)        += setup-sh7722.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7723)        += setup-sh7723.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7724)        += setup-sh7724.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7366)        += setup-sh7366.o
-obj-$(CONFIG_CPU_SUBTYPE_SHX3)          += setup-shx3.o
+obj-$(CONFIG_CPU_SUBTYPE_SHX3)          += setup-shx3.o intc-shx3.o
 
 # SMP setup
 smp-$(CONFIG_CPU_SHX3)                  := smp-shx3.o
 
 # Primary on-chip clocks (common)
+clock-$(CONFIG_CPU_SUBTYPE_SH7757)      := clock-sh7757.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7763)      := clock-sh7763.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7770)      := clock-sh7770.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7780)      := clock-sh7780.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7785)      := clock-sh7785.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7786)      := clock-sh7786.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7343)      := clock-sh7343.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7722)      := clock-sh7722.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7723)      := clock-sh7723.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7724)      := clock-sh7724.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7722)      := clock-sh7722.o hwblk-sh7722.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7723)      := clock-sh7723.o hwblk-sh7723.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7724)      := clock-sh7724.o hwblk-sh7724.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7366)      := clock-sh7366.o
 clock-$(CONFIG_CPU_SUBTYPE_SHX3)        := clock-shx3.o
 
@@ -35,9 +37,13 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3)	:= clock-shx3.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7722)     := pinmux-sh7722.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7723)     := pinmux-sh7723.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7724)     := pinmux-sh7724.o
+pinmux-$(CONFIG_CPU_SUBTYPE_SH7757)     := pinmux-sh7757.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7785)     := pinmux-sh7785.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7786)     := pinmux-sh7786.o
+pinmux-$(CONFIG_CPU_SUBTYPE_SHX3)       := pinmux-shx3.o
 
-obj-y                           += $(clock-y)
-obj-$(CONFIG_SMP)               += $(smp-y)
-obj-$(CONFIG_GENERIC_GPIO)      += $(pinmux-y)
+obj-y                                   += $(clock-y)
+obj-$(CONFIG_SMP)                       += $(smp-y)
+obj-$(CONFIG_GENERIC_GPIO)              += $(pinmux-y)
+obj-$(CONFIG_PERF_EVENTS)               += perf_event.o
+obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += ubc.o
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 0ee3ee861252..93c646072c1b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 
 /* SH7343 registers */
@@ -36,8 +37,6 @@
 
 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
 static struct clk r_clk = {
-        .name           = "rclk",
-        .id             = -1,
         .rate           = 32768,
 };
 
@@ -46,8 +45,6 @@ static struct clk r_clk = {
  * from the platform code.
  */
 struct clk extal_clk = {
-        .name           = "extal",
-        .id             = -1,
         .rate           = 33333333,
 };
 
@@ -69,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
 };
 
 static struct clk dll_clk = {
-        .name           = "dll_clk",
-        .id             = -1,
         .ops            = &dll_clk_ops,
         .parent         = &r_clk,
         .flags          = CLK_ENABLE_ON_INIT,
@@ -91,8 +86,6 @@ static struct clk_ops pll_clk_ops = {
 };
 
 static struct clk pll_clk = {
-        .name           = "pll_clk",
-        .id             = -1,
         .ops            = &pll_clk_ops,
         .flags          = CLK_ENABLE_ON_INIT,
 };
@@ -107,82 +100,182 @@ struct clk *main_clks[] = {
 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
         .multipliers = multipliers,
         .nr_multipliers = ARRAY_SIZE(multipliers),
 };
 
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
        DIV4_SIUA, DIV4_SIUB, DIV4_NR };
 
-#define DIV4(_str, _reg, _bit, _mask, _flags) \
-  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 
 struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
-        [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
-        [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
+        [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
+        [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
+        [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
 };
 
-struct clk div6_clks[] = {
-        SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
+enum { DIV6_V, DIV6_NR };
+
+struct clk div6_clks[DIV6_NR] = {
+        [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
+};
+
+#define MSTP(_parent, _reg, _bit, _flags) \
+  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
+
+enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
+       MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
+       MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
+       MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001,
+       MSTP109, MSTP108, MSTP100,
+       MSTP225, MSTP224, MSTP218, MSTP217, MSTP216,
+       MSTP214, MSTP213, MSTP212, MSTP211, MSTP208,
+       MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+       MSTP_NR };
+
+static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
+        [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
+        [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
+        [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
+        [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
+        [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
+        [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
+        [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
+        [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
+        [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
+        [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
+        [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
+        [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
+        [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
+        [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
+        [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
+        [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
+        [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
+        [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
+        [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
+        [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
+        [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
+        [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
+
+        [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
+        [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
+
+        [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
+        [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
+        [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
+        [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
+        [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
+        [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
+        [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
+        [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
+        [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
+        [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
+        [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
+        [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
+        [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
+        [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
+        [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
+        [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
+        [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
 };
 
-#define MSTP(_str, _parent, _reg, _bit, _flags) \
-  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
-
-static struct clk mstp_clks[] = {
-        MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
-        MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
-        MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
-        MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
-        MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
-        MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
-        MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
-        MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
-        MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
-        MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
-        MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
-        MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
-        MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
-        MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
-        MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
-        MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
-        MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
-        MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
-        MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
-        MSTP("scif3", &div4_clks[DIV4_P], MSTPCR0, 4, 0),
-        MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0),
-        MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
-        MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
-
-        MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
-        MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0),
-
-        MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0),
-        MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
-        MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
-        MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
-        MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0),
-        MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
-        MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0),
-        MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0),
-        MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
-        MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
-        MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
-        MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
-        MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
-        MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
-        MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
-        MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
-        MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("rclk", &r_clk),
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("dll_clk", &dll_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+        CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
+        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+        CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
+        CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
+
+        /* DIV6 clocks */
+        CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
+
+        /* MSTP32 clocks */
+        CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
+        CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
+        CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
+        CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
+        CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
+        CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
+        CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
+        CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
+        CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
+        CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
+        CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
+        CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
+        CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
+        CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
+        CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
+        CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
+        {
+                /* SCIF0 */
+                .dev_id         = "sh-sci.0",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP007],
+        }, {
+                /* SCIF1 */
+                .dev_id         = "sh-sci.1",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP006],
+        }, {
+                /* SCIF2 */
+                .dev_id         = "sh-sci.2",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP005],
+        }, {
+                /* SCIF3 */
+                .dev_id         = "sh-sci.3",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP004],
+        },
+        CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]),
+        CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]),
+        CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]),
+        CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
+        CLKDEV_CON_ID("i2c1", &mstp_clks[MSTP108]),
+        CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]),
+        CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]),
+        CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
+        CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
+        CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]),
+        CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]),
+        CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]),
+        CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]),
+        CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
+        CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]),
+        CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]),
+        CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
+        CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
+        CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
+        CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
+        CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
+        CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
 };
 
 int __init arch_clk_init(void)
@@ -198,14 +291,16 @@ int __init arch_clk_init(void)
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
         if (!ret)
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 
         if (!ret)
-                ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 
         if (!ret)
-                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index a95ebaba095c..049dc0628ccc 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 
 /* SH7366 registers */
@@ -36,8 +37,6 @@
 
 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
 static struct clk r_clk = {
-        .name           = "rclk",
-        .id             = -1,
         .rate           = 32768,
 };
 
@@ -46,8 +45,6 @@ static struct clk r_clk = {
  * from the platform code.
  */
 struct clk extal_clk = {
-        .name           = "extal",
-        .id             = -1,
         .rate           = 33333333,
 };
 
@@ -69,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
 };
 
 static struct clk dll_clk = {
-        .name           = "dll_clk",
-        .id             = -1,
         .ops            = &dll_clk_ops,
         .parent         = &r_clk,
         .flags          = CLK_ENABLE_ON_INIT,
@@ -94,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
 };
 
 static struct clk pll_clk = {
-        .name           = "pll_clk",
-        .id             = -1,
         .ops            = &pll_clk_ops,
         .flags          = CLK_ENABLE_ON_INIT,
 };
@@ -110,79 +103,168 @@ struct clk *main_clks[] = {
 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
         .multipliers = multipliers,
         .nr_multipliers = ARRAY_SIZE(multipliers),
 };
 
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
        DIV4_SIUA, DIV4_SIUB, DIV4_NR };
 
-#define DIV4(_str, _reg, _bit, _mask, _flags) \
-  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 
 struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
-        [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
-        [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
-        [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
+        [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
+        [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
+        [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
+        [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
 };
 
-struct clk div6_clks[] = {
-        SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
+enum { DIV6_V, DIV6_NR };
+
+struct clk div6_clks[DIV6_NR] = {
+        [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
 };
 
-#define MSTP(_str, _parent, _reg, _bit, _flags) \
-  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
+#define MSTP(_parent, _reg, _bit, _flags) \
+  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
+
+enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
+       MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
+       MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
+       MSTP007, MSTP006, MSTP005, MSTP002, MSTP001,
+       MSTP109, MSTP100,
+       MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217,
+       MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+       MSTP_NR };
 
-static struct clk mstp_clks[] = {
+static struct clk mstp_clks[MSTP_NR] = {
         /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
-        MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
-        MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
-        MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
-        MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
-        MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
-        MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
-        MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
-        MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
-        MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
-        MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
-        MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
-        MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
-        MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
-        MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
-        MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
-        MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
-        MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
-        MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
-        MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
-        MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
-        MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
-
-        MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
-
-        MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0),
-        MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0),
-        MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
-        MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0),
-        MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0),
-        MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
-        MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
-        MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
-        MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0),
-        MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
-        MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
-        MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
-        MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
-        MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
-        MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
-        MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
+        [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
+        [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
+        [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
+        [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
+        [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
+        [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
+        [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
+        [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
+        [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
+        [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
+        [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
+        [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
+        [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
+        [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
+        [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
+        [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
+        [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
+        [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
+        [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
+        [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
+        [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
+
+        [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
+
+        [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
+        [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
+        [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
+        [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
+        [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
+        [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
+        [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
+        [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
+        [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
+        [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
+        [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
+        [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
+        [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
+        [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
+        [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
+};
+
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("rclk", &r_clk),
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("dll_clk", &dll_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+        CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
+        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+        CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
+        CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
+
+        /* DIV6 clocks */
+        CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
+
+        /* MSTP32 clocks */
+        CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
+        CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
+        CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
+        CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
+        CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
+        CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
+        CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
+        CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
+        CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
+        CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
+        CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
+        CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
+        CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
+        CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
+        CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
+        CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
+        {
+                /* SCIF0 */
+                .dev_id         = "sh-sci.0",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP007],
+        }, {
+                /* SCIF1 */
+                .dev_id         = "sh-sci.1",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP006],
+        }, {
+                /* SCIF2 */
+                .dev_id         = "sh-sci.2",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP005],
+        },
+        CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]),
+        CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]),
+        CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
+        CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]),
+        CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]),
+        CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]),
+        CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]),
+        CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]),
+        CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
+        CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
+        CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
+        CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]),
+        CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
+        CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
+        CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
+        CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
+        CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
+        CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
 };
 
 int __init arch_clk_init(void)
@@ -198,14 +280,16 @@ int __init arch_clk_init(void)
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
         if (!ret)
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 
         if (!ret)
-                ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 
         if (!ret)
-                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 40f859354f79..9d23a36f0647 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -21,7 +21,10 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
+#include <asm/hwblk.h>
+#include <cpu/sh7722.h>
 
 /* SH7722 registers */
 #define FRQCR           0xa4150000
@@ -30,15 +33,10 @@
 #define SCLKBCR         0xa415000c
 #define IRDACLKCR       0xa4150018
 #define PLLCR           0xa4150024
-#define MSTPCR0         0xa4150030
-#define MSTPCR1         0xa4150034
-#define MSTPCR2         0xa4150038
 #define DLLFRQ          0xa4150050
 
 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
 static struct clk r_clk = {
-        .name           = "rclk",
-        .id             = -1,
         .rate           = 32768,
 };
 
@@ -47,8 +45,6 @@ static struct clk r_clk = {
  * from the platform code.
  */
 struct clk extal_clk = {
-        .name           = "extal",
-        .id             = -1,
         .rate           = 33333333,
 };
 
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
 };
 
 static struct clk dll_clk = {
-        .name           = "dll_clk",
-        .id             = -1,
         .ops            = &dll_clk_ops,
         .parent         = &r_clk,
         .flags          = CLK_ENABLE_ON_INIT,
@@ -95,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
 };
 
 static struct clk pll_clk = {
-        .name           = "pll_clk",
-        .id             = -1,
         .ops            = &pll_clk_ops,
         .flags          = CLK_ENABLE_ON_INIT,
 };
@@ -111,64 +103,153 @@ struct clk *main_clks[] = {
 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
         .multipliers = multipliers,
         .nr_multipliers = ARRAY_SIZE(multipliers),
 };
 
-enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
-       DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 
-#define DIV4(_str, _reg, _bit, _mask, _flags) \
-  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
 
 struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
-        [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
-        [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
-        [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
-        [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
-        [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
+        [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
+        [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
+};
+
+enum { DIV4_IRDA, DIV4_ENABLE_NR };
+
+struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
+        [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
+};
+
+enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
+
+struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
+        [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
+        [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
+};
+
+enum { DIV6_V, DIV6_NR };
+
+struct clk div6_clks[DIV6_NR] = {
+        [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
 };
 
-struct clk div6_clks[] = {
-        SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
+static struct clk mstp_clks[HWBLK_NR] = {
+        SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
+        SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
+        SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
+
+        SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
+
+        SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
+        SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
 };
 
-#define MSTP(_str, _parent, _reg, _bit, _flags) \
-  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
-
-static struct clk mstp_clks[] = {
-        MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
-        MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
-        MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
-        MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
-        MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
-        MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
-        MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
-        MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
-        MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
-
-        MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
-        MSTP("rtc0", &r_clk, MSTPCR1, 8, 0),
-
-        MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
-        MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
-        MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
-        MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 9, 0),
-        MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
-        MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
-        MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
-        MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
-        MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
-        MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
-        MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
-        MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("rclk", &r_clk),
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("dll_clk", &dll_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+        CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
+        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+        CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
+        CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
+        CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
+
+        /* DIV6 clocks */
+        CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
+
+        /* MSTP clocks */
+        CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
+        CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
+        {
+                /* TMU0 */
+                .dev_id         = "sh_tmu.0",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU],
+        }, {
+                /* TMU1 */
+                .dev_id         = "sh_tmu.1",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU],
+        }, {
+                /* TMU2 */
+                .dev_id         = "sh_tmu.2",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU],
+        },
+        CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
+        CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
+        CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
+        {
+                /* SCIF0 */
+                .dev_id         = "sh-sci.0",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF0],
+        }, {
+                /* SCIF1 */
+                .dev_id         = "sh-sci.1",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF1],
+        }, {
+                /* SCIF2 */
+                .dev_id         = "sh-sci.2",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF2],
+        },
+        CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
+        CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
+        CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
+        CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
+        CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
+        CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
+        CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
+        CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
+        CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
+        CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
+        CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
+        CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
+        CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
+        CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
 };
 
 int __init arch_clk_init(void)
@@ -184,14 +265,24 @@ int __init arch_clk_init(void)
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
         if (!ret)
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 
         if (!ret)
-                ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+                ret = sh_clk_div4_enable_register(div4_enable_clks,
+                                        DIV4_ENABLE_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div4_reparent_register(div4_reparent_clks,
+                                        DIV4_REPARENT_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 
         if (!ret)
-                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+                ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
 
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index e67c2678b8ae..55493cd5bd8f 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -21,7 +21,11 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
+#include <asm/hwblk.h>
+#include <cpu/sh7723.h>
 
 /* SH7723 registers */
 #define FRQCR           0xa4150000
@@ -30,15 +34,10 @@
 #define SCLKBCR         0xa415000c
 #define IRDACLKCR       0xa4150018
 #define PLLCR           0xa4150024
-#define MSTPCR0         0xa4150030
-#define MSTPCR1         0xa4150034
-#define MSTPCR2         0xa4150038
 #define DLLFRQ          0xa4150050
 
 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
 static struct clk r_clk = {
-        .name           = "rclk",
-        .id             = -1,
         .rate           = 32768,
 };
 
@@ -47,8 +46,6 @@ static struct clk r_clk = {
  * from the platform code.
  */
 struct clk extal_clk = {
-        .name           = "extal",
-        .id             = -1,
         .rate           = 33333333,
 };
 
@@ -70,8 +67,6 @@ static struct clk_ops dll_clk_ops = {
 };
 
 static struct clk dll_clk = {
-        .name           = "dll_clk",
-        .id             = -1,
         .ops            = &dll_clk_ops,
         .parent         = &r_clk,
         .flags          = CLK_ENABLE_ON_INIT,
@@ -95,8 +90,6 @@ static struct clk_ops pll_clk_ops = {
 };
 
 static struct clk pll_clk = {
-        .name           = "pll_clk",
-        .id             = -1,
         .ops            = &pll_clk_ops,
         .flags          = CLK_ENABLE_ON_INIT,
 };
@@ -111,89 +104,228 @@ struct clk *main_clks[] = {
 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
         .multipliers = multipliers,
         .nr_multipliers = ARRAY_SIZE(multipliers),
 };
 
-enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
-       DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
+enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
 
-#define DIV4(_str, _reg, _bit, _mask, _flags) \
-  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 
 struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
-        [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
-        [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
-        [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
-        [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
-        [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
-        [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
-        [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
+        [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
+        [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
+        [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
+};
+
+enum { DIV4_IRDA, DIV4_ENABLE_NR };
+
+struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
+        [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
 };
 
-struct clk div6_clks[] = {
-        SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
+enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
+
+struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
+        [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
+        [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
 };
+enum { DIV6_V, DIV6_NR };
 
-#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \
-  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT)
+struct clk div6_clks[DIV6_NR] = {
+        [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
+};
 
 static struct clk mstp_clks[] = {
         /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
-        MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0),
-        MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0),
-        MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0),
-        MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 28, 1, 1, 0),
-        MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0),
-        MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0),
-        MSTP("intc0", &div4_clks[DIV4_I], MSTPCR0, 22, 1, 1, 0),
-        MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1),
-        MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0),
-        MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0),
-        MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0),
-        MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0),
-        MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0),
-        MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0),
-        MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1),
-        MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 11, 0, 1, 0),
-        MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
-        MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0),
-        MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0),
-        MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0),
-        MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0),
-        MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0),
-        MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0),
-        MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0),
-        MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0),
-        MSTP("meram0", &div4_clks[DIV4_SH], MSTPCR0, 0, 1, 1, 0),
-
-        MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0),
-        MSTP("rtc0", &r_clk, MSTPCR1, 8, 0, 0, 0),
-
-        MSTP("atapi0", &div4_clks[DIV4_SH], MSTPCR2, 28, 0, 1, 0),
-        MSTP("adc0", &div4_clks[DIV4_P], MSTPCR2, 27, 0, 1, 0),
-        MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0),
-        MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0),
-        MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0),
-        MSTP("icb0", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1),
-        MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0),
-        MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0),
-        MSTP("keysc0", &r_clk, MSTPCR2, 14, 0, 0, 0),
-        MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 11, 0, 1, 0),
-        MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 10, 0, 1, 1),
-        MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0, 1, 0),
-        MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1),
-        MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1),
-        MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1),
-        MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1),
-        MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1),
-        MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1),
-        MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1),
+        SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
+        SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
+        SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
+        SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0),
+
+        SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
+
+        SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0),
+        SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
+        SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
+};
+
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("rclk", &r_clk),
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("dll_clk", &dll_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+        CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
+        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+        CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
+        CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
+        CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
+
+        /* DIV6 clocks */
+        CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
+
+        /* MSTP clocks */
+        CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
+        CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
+        CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
+        CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
+        CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
+        CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
+        CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
+        CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
+        CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
+        CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
+        CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
+        {
+                /* TMU0 */
+                .dev_id         = "sh_tmu.0",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU0],
+        }, {
+                /* TMU1 */
+                .dev_id         = "sh_tmu.1",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU0],
+        }, {
+                /* TMU2 */
+                .dev_id         = "sh_tmu.2",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU0],
+        },
+        CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
+        CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
+        CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
+        {
+                /* TMU3 */
+                .dev_id         = "sh_tmu.3",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU1],
+        }, {
+                /* TMU4 */
+                .dev_id         = "sh_tmu.4",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU1],
+        }, {
+                /* TMU5 */
+                .dev_id         = "sh_tmu.5",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU1],
+        },
+        CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
+        {
+                /* SCIF0 */
+                .dev_id         = "sh-sci.0",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF0],
+        }, {
+                /* SCIF1 */
+                .dev_id         = "sh-sci.1",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF1],
+        }, {
+                /* SCIF2 */
+                .dev_id         = "sh-sci.2",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF2],
+        }, {
+                /* SCIF3 */
+                .dev_id         = "sh-sci.3",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF3],
+        }, {
+                /* SCIF4 */
+                .dev_id         = "sh-sci.4",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF4],
+        }, {
+                /* SCIF5 */
+                .dev_id         = "sh-sci.5",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF5],
+        },
+        CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
+        CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
+        CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
+        CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
+        CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
+        CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
+        CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]),
+        CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
+        CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
+        CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
+        CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
+        CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
+        CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
+        CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
+        CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
+        CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
+        CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
+        CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
+        CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
+        CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
+        CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
+        CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
+        CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
+        CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
 };
 
 int __init arch_clk_init(void)
@@ -207,16 +339,26 @@ int __init arch_clk_init(void)
                 pll_clk.parent = &extal_clk;
 
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
-                ret = clk_register(main_clks[k]);
+                ret |= clk_register(main_clks[k]);
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 
         if (!ret)
-                ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+                ret = sh_clk_div4_enable_register(div4_enable_clks,
+                                        DIV4_ENABLE_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div4_reparent_register(div4_reparent_clks,
+                                        DIV4_REPARENT_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 
         if (!ret)
-                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+                ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
 
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 5d5c9b952883..d08fa953c88b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -21,7 +21,11 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
+#include <asm/hwblk.h>
+#include <cpu/sh7724.h>
 
 /* SH7724 registers */
 #define FRQCRA          0xa4150000
@@ -31,17 +35,12 @@
 #define FCLKBCR         0xa415000c
 #define IRDACLKCR       0xa4150018
 #define PLLCR           0xa4150024
-#define MSTPCR0         0xa4150030
-#define MSTPCR1         0xa4150034
-#define MSTPCR2         0xa4150038
 #define SPUCLKCR        0xa415003c
 #define FLLFRQ          0xa4150050
 #define LSTATS          0xa4150060
 
 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
 static struct clk r_clk = {
-        .name           = "rclk",
-        .id             = -1,
         .rate           = 32768,
 };
 
@@ -49,9 +48,7 @@ static struct clk r_clk = {
  * Default rate for the root input clock, reset this with clk_set_rate()
  * from the platform code.
  */
-struct clk extal_clk = {
-        .name           = "extal",
-        .id             = -1,
+static struct clk extal_clk = {
         .rate           = 33333333,
 };
 
@@ -75,8 +72,6 @@ static struct clk_ops fll_clk_ops = {
 };
 
 static struct clk fll_clk = {
-        .name           = "fll_clk",
-        .id             = -1,
         .ops            = &fll_clk_ops,
         .parent         = &r_clk,
         .flags          = CLK_ENABLE_ON_INIT,
@@ -97,8 +92,6 @@ static struct clk_ops pll_clk_ops = {
 };
 
 static struct clk pll_clk = {
-        .name           = "pll_clk",
-        .id             = -1,
         .ops            = &pll_clk_ops,
         .flags          = CLK_ENABLE_ON_INIT,
 };
@@ -114,106 +107,282 @@ static struct clk_ops div3_clk_ops = {
 };
 
 static struct clk div3_clk = {
-        .name           = "div3_clk",
-        .id             = -1,
         .ops            = &div3_clk_ops,
         .parent         = &pll_clk,
 };
 
-struct clk *main_clks[] = {
+/* External input clock (pin name: FSIMCKA/FSIMCKB ) */
+struct clk sh7724_fsimcka_clk = {
+};
+
+struct clk sh7724_fsimckb_clk = {
+};
+
+static struct clk *main_clks[] = {
         &r_clk,
         &extal_clk,
         &fll_clk,
         &pll_clk,
         &div3_clk,
+        &sh7724_fsimcka_clk,
+        &sh7724_fsimckb_clk,
 };
 
-static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+
+        /* set KICK bit in FRQCRA to update hardware setting */
+        value = __raw_readl(FRQCRA);
+        value |= (1 << 31);
+        __raw_writel(value, FRQCRA);
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
 };
 
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick = div4_kick,
+};
+
 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
 
-#define DIV4(_str, _reg, _bit, _mask, _flags) \
-  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 
 struct clk div4_clks[DIV4_NR] = {
-        [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
-        [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
-        [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
-        [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0),
-};
-
-struct clk div6_clks[] = {
-        SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0),
-        SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0),
-        SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0),
-        SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0),
-        SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0),
-};
-
-#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \
-  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT)
-
-static struct clk mstp_clks[] = {
-        MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0),
-        MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0),
-        MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0),
-        MSTP("rs0", &div4_clks[DIV4_B], MSTPCR0, 28, 1, 1, 0),
-        MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0),
-        MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 26, 1, 1, 0),
-        MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0),
-        MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 1, 1, 0),
-        MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1),
-        MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0),
-        MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0),
-        MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0),
-        MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0),
-        MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0),
-        MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0),
-        MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1),
-        MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
-        MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0),
-        MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0),
-        MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0),
-        MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0),
-        MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0),
-        MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0),
-        MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0),
-        MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0),
-
-        MSTP("keysc0", &r_clk, MSTPCR1, 12, 0, 0, 0),
-        MSTP("rtc0", &r_clk, MSTPCR1, 11, 0, 0, 0),
-        MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0),
-        MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0, 1, 0),
-
-        MSTP("mmc0", &div4_clks[DIV4_B], MSTPCR2, 29, 0, 1, 0),
-        MSTP("eth0", &div4_clks[DIV4_B], MSTPCR2, 28, 0, 1, 0),
-        MSTP("atapi0", &div4_clks[DIV4_B], MSTPCR2, 26, 0, 1, 0),
-        MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0),
-        MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0),
-        MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0),
-        MSTP("usb1", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1),
-        MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 20, 0, 1, 1),
-        MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 19, 0, 1, 1),
-        MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0),
-        MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0),
-        MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 15, 1, 1, 1),
-        MSTP("ceu1", &div4_clks[DIV4_B], MSTPCR2, 13, 0, 1, 1),
-        MSTP("beu1", &div4_clks[DIV4_B], MSTPCR2, 12, 0, 1, 1),
-        MSTP("2ddmac0", &div4_clks[DIV4_SH], MSTPCR2, 10, 0, 1, 1),
-        MSTP("spu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0, 1, 0),
-        MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1),
-        MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1),
-        MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1),
-        MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1),
-        MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1),
-        MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1),
-        MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1),
+        [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
+        [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
+};
+
+enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR };
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
+        [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
+        [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
+};
+
+enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR };
+
+/* Indices are important - they are the actual src selecting values */
+static struct clk *fclkacr_parent[] = {
+        [0] = &div3_clk,
+        [1] = NULL,
+        [2] = &sh7724_fsimcka_clk,
+        [3] = NULL,
+};
+
+static struct clk *fclkbcr_parent[] = {
+        [0] = &div3_clk,
+        [1] = NULL,
+        [2] = &sh7724_fsimckb_clk,
+        [3] = NULL,
+};
+
+static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
+        [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0,
+                                      fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
+        [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0,
+                                      fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
+};
+
+static struct clk mstp_clks[HWBLK_NR] = {
+        SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
+        SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
+        SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
+        SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
+        SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
+
+        SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
+        SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
+        SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0),
+
+        SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
+        SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0),
+        SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
+        SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
+};
+
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("rclk", &r_clk),
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("fll_clk", &fll_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+        CLKDEV_CON_ID("div3_clk", &div3_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+        CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
+
+        /* DIV6 clocks */
+        CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
+        CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]),
+        CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]),
+        CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
+        CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
+
+        /* MSTP clocks */
+        CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
+        CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
+        CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
+        CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
+        CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
+        CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
+        CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
+        CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
+        CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
+        CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
+        CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
+        CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
+        {
+                /* TMU0 */
+                .dev_id         = "sh_tmu.0",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU0],
+        }, {
+                /* TMU1 */
+                .dev_id         = "sh_tmu.1",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU0],
+        }, {
+                /* TMU2 */
+                .dev_id         = "sh_tmu.2",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU0],
+        }, {
+                /* TMU3 */
+                .dev_id         = "sh_tmu.3",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU1],
+        },
+        CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
+        CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
+        CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
+        {
+                /* TMU4 */
+                .dev_id         = "sh_tmu.4",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU1],
+        }, {
+                /* TMU5 */
+                .dev_id         = "sh_tmu.5",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[HWBLK_TMU1],
+        }, {
+                /* SCIF0 */
+                .dev_id         = "sh-sci.0",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF0],
+        }, {
+                /* SCIF1 */
+                .dev_id         = "sh-sci.1",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF1],
+        }, {
+                /* SCIF2 */
+                .dev_id         = "sh-sci.2",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF2],
+        }, {
+                /* SCIF3 */
+                .dev_id         = "sh-sci.3",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF3],
+        }, {
+                /* SCIF4 */
+                .dev_id         = "sh-sci.4",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF4],
+        }, {
+                /* SCIF5 */
+                .dev_id         = "sh-sci.5",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[HWBLK_SCIF5],
+        },
+        CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
+        CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
+        CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
+        CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
+        CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC0]),
+        CLKDEV_CON_ID("i2c1", &mstp_clks[HWBLK_IIC1]),
+        CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]),
+        CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]),
+        CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
+        CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
+        CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
+        CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
+        CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
+        CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
+        CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
+        CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
+        CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
+        CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
+        CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]),
+        CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
+        CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
+        CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
+        CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
+        CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
+        CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
+        CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]),
+        CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
+        CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
+        CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
 };
 
 int __init arch_clk_init(void)
@@ -229,14 +398,19 @@ int __init arch_clk_init(void)
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
         if (!ret)
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 
         if (!ret)
-                ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+        if (!ret)
+                ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
 
         if (!ret)
-                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+                ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
 
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
new file mode 100644
index 000000000000..e073e3eb4c3d
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -0,0 +1,162 @@
+/*
+ * arch/sh/kernel/cpu/sh4/clock-sh7757.c
+ *
+ * SH7757 support for the clock framework
+ *
+ *  Copyright (C) 2009-2010  Renesas Solutions Corp.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <asm/clock.h>
+#include <asm/freq.h>
+
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk extal_clk = {
+        .rate           = 48000000,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+        int multiplier;
+
+        multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16;
+
+        return clk->parent->rate * multiplier;
+}
+
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+};
+
+static struct clk pll_clk = {
+        .ops            = &pll_clk_ops,
+        .parent         = &extal_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+static struct clk *clks[] = {
+        &extal_clk,
+        &pll_clk,
+};
+
+static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6,
+                               1, 1, 1, 16, 1, 24, 1, 1 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = div2,
+        .nr_divisors = ARRAY_SIZE(div2),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
+enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR };
+
+#define DIV4(_bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
+
+struct clk div4_clks[DIV4_NR] = {
+        /*
+         * P clock is always enable, because some P clock modules is used
+         * by Host PC.
+         */
+        [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
+        [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
+};
+
+#define MSTPCR0         0xffc80030
+#define MSTPCR1         0xffc80034
+
+enum { MSTP004, MSTP000, MSTP114, MSTP113, MSTP112,
+       MSTP111, MSTP110, MSTP103, MSTP102,
+       MSTP_NR };
+
+static struct clk mstp_clks[MSTP_NR] = {
+        /* MSTPCR0 */
+        [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
+        [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
+
+        /* MSTPCR1 */
+        [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
+        [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
+        [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
+        [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
+        [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
+        [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
+        [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
+};
+
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+
+        /* MSTP32 clocks */
+        CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP004]),
+        CLKDEV_CON_ID("riic", &mstp_clks[MSTP000]),
+        {
+                /* TMU0 */
+                .dev_id         = "sh_tmu.0",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP113],
+        }, {
+                /* TMU1 */
+                .dev_id         = "sh_tmu.1",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP114],
+        },
+        {
+                /* SCIF4 (But, ID is 2) */
+                .dev_id         = "sh-sci.2",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP112],
+        }, {
+                /* SCIF3 */
+                .dev_id         = "sh-sci.1",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP111],
+        }, {
+                /* SCIF2 */
+                .dev_id         = "sh-sci.0",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP110],
+        },
+        CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]),
+};
+
+int __init arch_clk_init(void)
+{
+        int i, ret = 0;
+
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                ret |= clk_register(clks[i]);
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
+                                           &div4_table);
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+
+        return ret;
+}
+
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 370cd47642ef..599630fc4d3b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -12,6 +12,8 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 #include <asm/io.h>
@@ -22,7 +24,7 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07];
+        clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07];
 }
 
 static struct clk_ops sh7763_master_clk_ops = {
@@ -31,7 +33,7 @@ static struct clk_ops sh7763_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07);
+        int idx = ((__raw_readl(FRQCR) >> 4) & 0x07);
         return clk->parent->rate / p0fc_divisors[idx];
 }
 
@@ -41,7 +43,7 @@ static struct clk_ops sh7763_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07);
+        int idx = ((__raw_readl(FRQCR) >> 16) & 0x07);
         return clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -68,7 +70,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 
 static unsigned long shyway_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07);
+        int idx = ((__raw_readl(FRQCR) >> 20) & 0x07);
         return clk->parent->rate / cfc_divisors[idx];
 }
 
@@ -77,7 +79,6 @@ static struct clk_ops sh7763_shyway_clk_ops = {
 };
 
 static struct clk sh7763_shyway_clk = {
-        .name           = "shyway_clk",
         .flags          = CLK_ENABLE_ON_INIT,
         .ops            = &sh7763_shyway_clk_ops,
 };
@@ -90,6 +91,13 @@ static struct clk *sh7763_onchip_clocks[] = {
         &sh7763_shyway_clk,
 };
 
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk),
+};
+
 int __init arch_clk_init(void)
 {
         struct clk *clk;
@@ -107,5 +115,7 @@ int __init arch_clk_init(void)
 
         clk_put(clk);
 
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
index e0b896769205..9e3354365d40 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
@@ -21,7 +21,7 @@ static int pfc_divisors[] = { 1, 8, 1,10,12,16, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> 28) & 0x000f];
+        clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f];
 }
 
 static struct clk_ops sh7770_master_clk_ops = {
@@ -30,7 +30,7 @@ static struct clk_ops sh7770_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f);
+        int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -40,7 +40,7 @@ static struct clk_ops sh7770_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQCR) & 0x000f);
+        int idx = (__raw_readl(FRQCR) & 0x000f);
         return clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -50,7 +50,7 @@ static struct clk_ops sh7770_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f);
+        int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f);
         return clk->parent->rate / ifc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index a249d823578e..8894926479a6 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -11,6 +11,8 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 #include <asm/io.h>
@@ -22,7 +24,7 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 6, 1, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pfc_divisors[ctrl_inl(FRQCR) & 0x0003];
+        clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003];
 }
 
 static struct clk_ops sh7780_master_clk_ops = {
@@ -31,7 +33,7 @@ static struct clk_ops sh7780_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQCR) & 0x0003);
+        int idx = (__raw_readl(FRQCR) & 0x0003);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -41,7 +43,7 @@ static struct clk_ops sh7780_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007);
+        int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007);
         return clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -51,7 +53,7 @@ static struct clk_ops sh7780_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001);
+        int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001);
         return clk->parent->rate / ifc_divisors[idx];
 }
 
@@ -74,7 +76,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 
 static unsigned long shyway_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007);
+        int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007);
         return clk->parent->rate / cfc_divisors[idx];
 }
 
@@ -83,7 +85,6 @@ static struct clk_ops sh7780_shyway_clk_ops = {
 };
 
 static struct clk sh7780_shyway_clk = {
-        .name           = "shyway_clk",
         .flags          = CLK_ENABLE_ON_INIT,
         .ops            = &sh7780_shyway_clk_ops,
 };
@@ -96,6 +97,13 @@ static struct clk *sh7780_onchip_clocks[] = {
         &sh7780_shyway_clk,
 };
 
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("shyway_clk", &sh7780_shyway_clk),
+};
+
 int __init arch_clk_init(void)
 {
         struct clk *clk;
@@ -113,5 +121,7 @@ int __init arch_clk_init(void)
 
         clk_put(clk);
 
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 73abfbf2f16d..2d960247f3eb 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -3,7 +3,7 @@
  *
  * SH7785 support for the clock framework
  *
- *  Copyright (C) 2007 - 2009  Paul Mundt
+ *  Copyright (C) 2007 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -14,6 +14,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/cpufreq.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 #include <cpu/sh7785.h>
@@ -23,8 +24,6 @@
  * from the platform code.
  */
 static struct clk extal_clk = {
-        .name           = "extal",
-        .id             = -1,
         .rate           = 33333333,
 };
 
@@ -42,8 +41,6 @@ static struct clk_ops pll_clk_ops = {
 };
 
 static struct clk pll_clk = {
-        .name           = "pll_clk",
-        .id             = -1,
         .ops            = &pll_clk_ops,
         .parent         = &extal_clk,
         .flags          = CLK_ENABLE_ON_INIT,
@@ -57,56 +54,161 @@ static struct clk *clks[] = {
 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
                                24, 32, 36, 48 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = div2,
         .nr_divisors = ARRAY_SIZE(div2),
 };
 
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
         DIV4_DU, DIV4_P, DIV4_NR };
 
-#define DIV4(_str, _bit, _mask, _flags) \
-  SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
+#define DIV4(_bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
 
 struct clk div4_clks[DIV4_NR] = {
-        [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0),
-        [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0),
-        [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0),
-        [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT),
-        [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT),
-        [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT),
-        [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT),
-        [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4(0, 0x0f80, 0),
+        [DIV4_DU] = DIV4(4, 0x0ff0, 0),
+        [DIV4_GA] = DIV4(8, 0x0030, 0),
+        [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
+        [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
+        [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
 };
 
 #define MSTPCR0         0xffc80030
 #define MSTPCR1         0xffc80034
 
-static struct clk mstp_clks[] = {
+enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
+       MSTP021, MSTP020, MSTP017, MSTP016,
+       MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002,
+       MSTP119, MSTP117, MSTP105, MSTP104, MSTP100,
+       MSTP_NR };
+
+static struct clk mstp_clks[MSTP_NR] = {
         /* MSTPCR0 */
-        SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
-        SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
-        SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
-        SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
-        SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
-        SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
-        SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
-        SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
-        SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
-        SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
-        SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0),
-        SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0),
-        SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
-        SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
-        SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0),
-        SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
+        [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
+        [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
+        [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
+        [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
+        [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
+        [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
+        [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
+        [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
+        [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
+        [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
+        [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
+        [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
+        [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
+        [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
+        [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
+        [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
 
         /* MSTPCR1 */
-        SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0),
-        SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0),
-        SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
-        SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
-        SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
+        [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
+        [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
+        [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
+        [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
+        [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
+};
+
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
+        CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]),
+        CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
+        CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+        CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+
+        /* MSTP32 clocks */
+        {
+                /* SCIF5 */
+                .dev_id         = "sh-sci.5",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP029],
+        }, {
+                /* SCIF4 */
+                .dev_id         = "sh-sci.4",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP028],
+        }, {
+                /* SCIF3 */
+                .dev_id         = "sh-sci.3",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP027],
+        }, {
+                /* SCIF2 */
+                .dev_id         = "sh-sci.2",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP026],
+        }, {
+                /* SCIF1 */
+                .dev_id         = "sh-sci.1",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP025],
+        }, {
+                /* SCIF0 */
+                .dev_id         = "sh-sci.0",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP024],
+        },
+        CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
+        CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
+        CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
+        CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
+        CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]),
+        CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]),
+        {
+                /* TMU0 */
+                .dev_id         = "sh_tmu.0",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP008],
+        }, {
+                /* TMU1 */
+                .dev_id         = "sh_tmu.1",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP008],
+        }, {
+                /* TMU2 */
+                .dev_id         = "sh_tmu.2",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP008],
+        }, {
+                /* TMU3 */
+                .dev_id         = "sh_tmu.3",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP009],
+        }, {
+                /* TMU4 */
+                .dev_id         = "sh_tmu.4",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP009],
+        }, {
+                /* TMU5 */
+                .dev_id         = "sh_tmu.5",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP009],
+        },
+        CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]),
+        CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
+        CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
+        CLKDEV_CON_ID("ubc_fck", &mstp_clks[MSTP117]),
+        CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
+        CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
+        CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]),
 };
 
 int __init arch_clk_init(void)
@@ -115,12 +217,14 @@ int __init arch_clk_init(void)
 
         for (i = 0; i < ARRAY_SIZE(clks); i++)
                 ret |= clk_register(clks[i]);
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
 
         if (!ret)
                 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
                                            &div4_table);
         if (!ret)
-                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index a0e8869071ac..42e403be9076 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -3,11 +3,7 @@
  *
  * SH7786 support for the clock framework
  *
- * Copyright (C) 2008, 2009  Renesas Solutions Corp.
- * Kuninori Morimoto <morimoto.kuninori@renesas.com>
- *
- * Based on SH7785
- *  Copyright (C) 2007  Paul Mundt
+ *  Copyright (C) 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -15,127 +11,263 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
-#include <asm/io.h>
 
-static int ifc_divisors[] = { 1, 2, 4, 1 };
-static int sfc_divisors[] = { 1, 1, 4, 1 };
-static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
-                             24, 32, 1, 1, 1, 1, 1, 1 };
-static int mfc_divisors[] = { 1, 1, 4, 1 };
-static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
-                              24, 32, 1, 48, 1, 1, 1, 1 };
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk extal_clk = {
+        .rate           = 33333333,
+};
 
-static void master_clk_init(struct clk *clk)
+static unsigned long pll_recalc(struct clk *clk)
 {
-        clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
-}
+        int multiplier;
 
-static struct clk_ops sh7786_master_clk_ops = {
-        .init           = master_clk_init,
-};
+        /*
+         * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
+         * while modes 3, 4, and 5 use an x32.
+         */
+        multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
 
-static unsigned long module_clk_recalc(struct clk *clk)
-{
-        int idx = (ctrl_inl(FRQMR1) & 0x000f);
-        return clk->parent->rate / pfc_divisors[idx];
+        return clk->parent->rate * multiplier;
 }
 
-static struct clk_ops sh7786_module_clk_ops = {
-        .recalc         = module_clk_recalc,
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
 };
 
-static unsigned long bus_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
-        return clk->parent->rate / bfc_divisors[idx];
-}
+static struct clk pll_clk = {
+        .ops            = &pll_clk_ops,
+        .parent         = &extal_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
 
-static struct clk_ops sh7786_bus_clk_ops = {
-        .recalc         = bus_clk_recalc,
+static struct clk *clks[] = {
+        &extal_clk,
+        &pll_clk,
 };
 
-static unsigned long cpu_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
-        return clk->parent->rate / ifc_divisors[idx];
-}
+static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
+                               24, 32, 36, 48 };
 
-static struct clk_ops sh7786_cpu_clk_ops = {
-        .recalc         = cpu_clk_recalc,
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = div2,
+        .nr_divisors = ARRAY_SIZE(div2),
 };
 
-static struct clk_ops *sh7786_clk_ops[] = {
-        &sh7786_master_clk_ops,
-        &sh7786_module_clk_ops,
-        &sh7786_bus_clk_ops,
-        &sh7786_cpu_clk_ops,
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
-{
-        if (idx < ARRAY_SIZE(sh7786_clk_ops))
-                *ops = sh7786_clk_ops[idx];
-}
+enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
 
-static unsigned long shyway_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
-        return clk->parent->rate / sfc_divisors[idx];
-}
+#define DIV4(_bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
 
-static struct clk_ops sh7786_shyway_clk_ops = {
-        .recalc         = shyway_clk_recalc,
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_P] = DIV4(0, 0x0b40, 0),
+        [DIV4_DU] = DIV4(4, 0x0010, 0),
+        [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
+        [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
 };
 
-static struct clk sh7786_shyway_clk = {
-        .name           = "shyway_clk",
-        .flags          = CLK_ENABLE_ON_INIT,
-        .ops            = &sh7786_shyway_clk_ops,
-};
+#define MSTPCR0         0xffc40030
+#define MSTPCR1         0xffc40034
 
-static unsigned long ddr_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
-        return clk->parent->rate / mfc_divisors[idx];
-}
+enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
+       MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
+       MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
+       MSTP005, MSTP004, MSTP002,
+       MSTP112, MSTP110, MSTP109, MSTP108,
+       MSTP105, MSTP104, MSTP103, MSTP102,
+       MSTP_NR };
 
-static struct clk_ops sh7786_ddr_clk_ops = {
-        .recalc         = ddr_clk_recalc,
-};
+static struct clk mstp_clks[MSTP_NR] = {
+        /* MSTPCR0 */
+        [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
+        [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
+        [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
+        [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
+        [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
+        [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
+        [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
+        [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
+        [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
+        [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
+        [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
+        [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
+        [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
+        [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
+        [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
+        [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
+        [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
+        [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
+        [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
+        [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
+        [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
 
-static struct clk sh7786_ddr_clk = {
-        .name           = "ddr_clk",
-        .flags          = CLK_ENABLE_ON_INIT,
-        .ops            = &sh7786_ddr_clk_ops,
+        /* MSTPCR1 */
+        [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
+        [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
+        [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
+        [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
+        [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
+        [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
+        [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
+        [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
 };
 
-/*
- * Additional SH7786-specific on-chip clocks that aren't already part of the
- * clock framework
- */
-static struct clk *sh7786_onchip_clocks[] = {
-        &sh7786_shyway_clk,
-        &sh7786_ddr_clk,
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
+        CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
+        CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+
+        /* MSTP32 clocks */
+        {
+                /* SCIF5 */
+                .dev_id         = "sh-sci.5",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP029],
+        }, {
+                /* SCIF4 */
+                .dev_id         = "sh-sci.4",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP028],
+        }, {
+                /* SCIF3 */
+                .dev_id         = "sh-sci.3",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP027],
+        }, {
+                /* SCIF2 */
+                .dev_id         = "sh-sci.2",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP026],
+        }, {
+                /* SCIF1 */
+                .dev_id         = "sh-sci.1",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP025],
+        }, {
+                /* SCIF0 */
+                .dev_id         = "sh-sci.0",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP024],
+        },
+        CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
+        CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
+        CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
+        CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
+        CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
+        CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
+        CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
+        CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
+        {
+                /* TMU0 */
+                .dev_id         = "sh_tmu.0",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP008],
+        }, {
+                /* TMU1 */
+                .dev_id         = "sh_tmu.1",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP008],
+        }, {
+                /* TMU2 */
+                .dev_id         = "sh_tmu.2",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP008],
+        }, {
+                /* TMU3 */
+                .dev_id         = "sh_tmu.3",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP009],
+        }, {
+                /* TMU4 */
+                .dev_id         = "sh_tmu.4",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP009],
+        }, {
+                /* TMU5 */
+                .dev_id         = "sh_tmu.5",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP009],
+        }, {
+                /* TMU6 */
+                .dev_id         = "sh_tmu.6",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP010],
+        }, {
+                /* TMU7 */
+                .dev_id         = "sh_tmu.7",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP010],
+        }, {
+                /* TMU8 */
+                .dev_id         = "sh_tmu.8",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP010],
+        }, {
+                /* TMU9 */
+                .dev_id         = "sh_tmu.9",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP011],
+        }, {
+                /* TMU10 */
+                .dev_id         = "sh_tmu.10",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP011],
+        }, {
+                /* TMU11 */
+                .dev_id         = "sh_tmu.11",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP011],
+        },
+        CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
+        CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
+        CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
+        CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
+        CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
+        CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
+        CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
+        CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
+        CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
+        CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
+        CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
 };
 
 int __init arch_clk_init(void)
 {
-        struct clk *clk;
         int i, ret = 0;
 
-        cpg_clk_init();
-
-        clk = clk_get(NULL, "master_clk");
-        for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
-                struct clk *clkp = sh7786_onchip_clocks[i];
-
-                clkp->parent = clk;
-                ret |= clk_register(clkp);
-        }
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                ret |= clk_register(clks[i]);
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
 
-        clk_put(clk);
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
+                                           &div4_table);
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index 23c27d32d982..1afdb93b8ccb 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -5,7 +5,7 @@
  *
  *  Copyright (C) 2006-2007  Renesas Technology Corp.
  *  Copyright (C) 2006-2007  Renesas Solutions Corp.
- *  Copyright (C) 2006-2007  Paul Mundt
+ *  Copyright (C) 2006-2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -13,116 +13,184 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
-#include <asm/io.h>
-
-static int ifc_divisors[] = { 1, 2, 4 ,6 };
-static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
-static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 };
-static int cfc_divisors[] = { 1, 1, 4, 6 };
-
-#define IFC_POS         28
-#define IFC_MSK         0x0003
-#define BFC_MSK         0x000f
-#define PFC_MSK         0x000f
-#define CFC_MSK         0x0003
-#define BFC_POS         16
-#define PFC_POS         0
-#define CFC_POS         20
-
-static void master_clk_init(struct clk *clk)
-{
-        clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK];
-}
 
-static struct clk_ops shx3_master_clk_ops = {
-        .init           = master_clk_init,
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk extal_clk = {
+        .rate           = 16666666,
 };
 
-static unsigned long module_clk_recalc(struct clk *clk)
+static unsigned long pll_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK);
-        return clk->parent->rate / pfc_divisors[idx];
+        /* PLL1 has a fixed x72 multiplier.  */
+        return clk->parent->rate * 72;
 }
 
-static struct clk_ops shx3_module_clk_ops = {
-        .recalc         = module_clk_recalc,
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
 };
 
-static unsigned long bus_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK);
-        return clk->parent->rate / bfc_divisors[idx];
-}
+static struct clk pll_clk = {
+        .ops            = &pll_clk_ops,
+        .parent         = &extal_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
 
-static struct clk_ops shx3_bus_clk_ops = {
-        .recalc         = bus_clk_recalc,
+static struct clk *clks[] = {
+        &extal_clk,
+        &pll_clk,
 };
 
-static unsigned long cpu_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK);
-        return clk->parent->rate / ifc_divisors[idx];
-}
+static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
+                               24, 32, 36, 48 };
 
-static struct clk_ops shx3_cpu_clk_ops = {
-        .recalc         = cpu_clk_recalc,
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = div2,
+        .nr_divisors = ARRAY_SIZE(div2),
 };
 
-static struct clk_ops *shx3_clk_ops[] = {
-        &shx3_master_clk_ops,
-        &shx3_module_clk_ops,
-        &shx3_bus_clk_ops,
-        &shx3_cpu_clk_ops,
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
-{
-        if (idx < ARRAY_SIZE(shx3_clk_ops))
-                *ops = shx3_clk_ops[idx];
-}
+enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR };
 
-static unsigned long shyway_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK);
-        return clk->parent->rate / cfc_divisors[idx];
-}
+#define DIV4(_bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
 
-static struct clk_ops shx3_shyway_clk_ops = {
-        .recalc         = shyway_clk_recalc,
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_P] = DIV4(0, 0x0f80, 0),
+        [DIV4_SHA] = DIV4(4, 0x0ff0, 0),
+        [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
+        [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
 };
 
-static struct clk shx3_shyway_clk = {
-        .name           = "shyway_clk",
-        .flags          = CLK_ENABLE_ON_INIT,
-        .ops            = &shx3_shyway_clk_ops,
+#define MSTPCR0         0xffc00030
+#define MSTPCR1         0xffc00034
+
+enum { MSTP027, MSTP026, MSTP025, MSTP024,
+       MSTP009, MSTP008, MSTP003, MSTP002,
+       MSTP001, MSTP000, MSTP119, MSTP105,
+       MSTP104, MSTP_NR };
+
+static struct clk mstp_clks[MSTP_NR] = {
+        /* MSTPCR0 */
+        [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
+        [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
+        [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
+        [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
+        [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
+        [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
+        [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
+        [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
+        [MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
+        [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
+
+        /* MSTPCR1 */
+        [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
+        [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
+        [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
 };
 
-/*
- * Additional SHx3-specific on-chip clocks that aren't already part of the
- * clock framework
- */
-static struct clk *shx3_onchip_clocks[] = {
-        &shx3_shyway_clk,
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]),
+        CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
+        CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+
+        /* MSTP32 clocks */
+        {
+                /* SCIF3 */
+                .dev_id         = "sh-sci.3",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP027],
+        }, {
+                /* SCIF2 */
+                .dev_id         = "sh-sci.2",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP026],
+        }, {
+                /* SCIF1 */
+                .dev_id         = "sh-sci.1",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP025],
+        }, {
+                /* SCIF0 */
+                .dev_id         = "sh-sci.0",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP024],
+        },
+        CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
+        CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
+        CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),
+        CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),
+        {
+                /* TMU0 */
+                .dev_id         = "sh_tmu.0",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP008],
+        }, {
+                /* TMU1 */
+                .dev_id         = "sh_tmu.1",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP008],
+        }, {
+                /* TMU2 */
+                .dev_id         = "sh_tmu.2",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP008],
+        }, {
+                /* TMU3 */
+                .dev_id         = "sh_tmu.3",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP009],
+        }, {
+                /* TMU4 */
+                .dev_id         = "sh_tmu.4",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP009],
+        }, {
+                /* TMU5 */
+                .dev_id         = "sh_tmu.5",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP009],
+        },
+        CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
+        CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
+        CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
 };
 
 int __init arch_clk_init(void)
 {
-        struct clk *clk;
         int i, ret = 0;
 
-        cpg_clk_init();
-
-        clk = clk_get(NULL, "master_clk");
-        for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {
-                struct clk *clkp = shx3_onchip_clocks[i];
-
-                clkp->parent = clk;
-                ret |= clk_register(clkp);
-        }
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                ret |= clk_register(clks[i]);
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
 
-        clk_put(clk);
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
+                                           &div4_table);
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
new file mode 100644
index 000000000000..a288b5d92341
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
@@ -0,0 +1,106 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
+ *
+ * SH7722 hardware block support
+ *
+ * Copyright (C) 2009 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/suspend.h>
+#include <asm/hwblk.h>
+#include <cpu/sh7722.h>
+
+/* SH7722 registers */
+#define MSTPCR0         0xa4150030
+#define MSTPCR1         0xa4150034
+#define MSTPCR2         0xa4150038
+
+/* SH7722 Power Domains */
+enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
+static struct hwblk_area sh7722_hwblk_area[] = {
+        [CORE_AREA] = HWBLK_AREA(0, 0),
+        [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
+        [SUB_AREA] = HWBLK_AREA(0, 0),
+};
+
+/* Table mapping HWBLK to Module Stop Bit and Power Domain */
+static struct hwblk sh7722_hwblk[HWBLK_NR] = {
+        [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
+        [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
+        [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
+        [HWBLK_URAM] = HWBLK(MSTPCR0, 28, CORE_AREA),
+        [HWBLK_XYMEM] = HWBLK(MSTPCR0, 26, CORE_AREA),
+        [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
+        [HWBLK_DMAC] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
+        [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
+        [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
+        [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
+        [HWBLK_TMU] = HWBLK(MSTPCR0, 15, CORE_AREA),
+        [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
+        [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
+        [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
+        [HWBLK_SCIF0] = HWBLK(MSTPCR0, 7, CORE_AREA),
+        [HWBLK_SCIF1] = HWBLK(MSTPCR0, 6, CORE_AREA),
+        [HWBLK_SCIF2] = HWBLK(MSTPCR0, 5, CORE_AREA),
+        [HWBLK_SIO] = HWBLK(MSTPCR0, 3, CORE_AREA),
+        [HWBLK_SIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
+        [HWBLK_SIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
+
+        [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
+        [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
+
+        [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
+        [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
+        [HWBLK_SDHI] = HWBLK(MSTPCR2, 18, CORE_AREA),
+        [HWBLK_SIM] = HWBLK(MSTPCR2, 16, CORE_AREA),
+        [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
+        [HWBLK_TSIF] = HWBLK(MSTPCR2, 13, SUB_AREA),
+        [HWBLK_USBF] = HWBLK(MSTPCR2, 11, CORE_AREA),
+        [HWBLK_2DG] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
+        [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
+        [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
+        [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
+        [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
+        [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
+        [HWBLK_VEU] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
+        [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
+        [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
+};
+
+static struct hwblk_info sh7722_hwblk_info = {
+        .areas = sh7722_hwblk_area,
+        .nr_areas = ARRAY_SIZE(sh7722_hwblk_area),
+        .hwblks = sh7722_hwblk,
+        .nr_hwblks = ARRAY_SIZE(sh7722_hwblk),
+};
+
+int arch_hwblk_sleep_mode(void)
+{
+        if (!sh7722_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
+                return SUSP_SH_STANDBY | SUSP_SH_SF;
+
+        if (!sh7722_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
+                return SUSP_SH_SLEEP | SUSP_SH_SF;
+
+        return SUSP_SH_SLEEP;
+}
+
+int __init arch_hwblk_init(void)
+{
+        return hwblk_register(&sh7722_hwblk_info);
+}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
new file mode 100644
index 000000000000..a7f4684d2032
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
@@ -0,0 +1,117 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
+ *
+ * SH7723 hardware block support
+ *
+ * Copyright (C) 2009 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/suspend.h>
+#include <asm/hwblk.h>
+#include <cpu/sh7723.h>
+
+/* SH7723 registers */
+#define MSTPCR0         0xa4150030
+#define MSTPCR1         0xa4150034
+#define MSTPCR2         0xa4150038
+
+/* SH7723 Power Domains */
+enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
+static struct hwblk_area sh7723_hwblk_area[] = {
+        [CORE_AREA] = HWBLK_AREA(0, 0),
+        [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
+        [SUB_AREA] = HWBLK_AREA(0, 0),
+};
+
+/* Table mapping HWBLK to Module Stop Bit and Power Domain */
+static struct hwblk sh7723_hwblk[HWBLK_NR] = {
+        [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
+        [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
+        [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
+        [HWBLK_L2C] = HWBLK(MSTPCR0, 28, CORE_AREA),
+        [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
+        [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
+        [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
+        [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
+        [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
+        [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
+        [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
+        [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
+        [HWBLK_SUBC] = HWBLK(MSTPCR0, 16, CORE_AREA),
+        [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
+        [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
+        [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
+        [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
+        [HWBLK_TMU1] = HWBLK(MSTPCR0, 11, CORE_AREA),
+        [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
+        [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
+        [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
+        [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
+        [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
+        [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
+        [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
+        [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
+        [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
+        [HWBLK_MERAM] = HWBLK(MSTPCR0, 0, CORE_AREA),
+
+        [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
+        [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
+
+        [HWBLK_ATAPI] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
+        [HWBLK_ADC] = HWBLK(MSTPCR2, 27, CORE_AREA),
+        [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
+        [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
+        [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
+        [HWBLK_ICB] = HWBLK(MSTPCR2, 21, CORE_AREA_BM),
+        [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
+        [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
+        [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
+        [HWBLK_USB] = HWBLK(MSTPCR2, 11, CORE_AREA),
+        [HWBLK_2DG] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
+        [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
+        [HWBLK_VEU2H1] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
+        [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
+        [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
+        [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
+        [HWBLK_VEU2H0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
+        [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
+        [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
+};
+
+static struct hwblk_info sh7723_hwblk_info = {
+        .areas = sh7723_hwblk_area,
+        .nr_areas = ARRAY_SIZE(sh7723_hwblk_area),
+        .hwblks = sh7723_hwblk,
+        .nr_hwblks = ARRAY_SIZE(sh7723_hwblk),
+};
+
+int arch_hwblk_sleep_mode(void)
+{
+        if (!sh7723_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
+                return SUSP_SH_STANDBY | SUSP_SH_SF;
+
+        if (!sh7723_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
+                return SUSP_SH_SLEEP | SUSP_SH_SF;
+
+        return SUSP_SH_SLEEP;
+}
+
+int __init arch_hwblk_init(void)
+{
+        return hwblk_register(&sh7723_hwblk_info);
+}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
new file mode 100644
index 000000000000..1613ad6013c3
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
@@ -0,0 +1,121 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
+ *
+ * SH7724 hardware block support
+ *
+ * Copyright (C) 2009 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/suspend.h>
+#include <asm/hwblk.h>
+#include <cpu/sh7724.h>
+
+/* SH7724 registers */
+#define MSTPCR0         0xa4150030
+#define MSTPCR1         0xa4150034
+#define MSTPCR2         0xa4150038
+
+/* SH7724 Power Domains */
+enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
+static struct hwblk_area sh7724_hwblk_area[] = {
+        [CORE_AREA] = HWBLK_AREA(0, 0),
+        [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
+        [SUB_AREA] = HWBLK_AREA(0, 0),
+};
+
+/* Table mapping HWBLK to Module Stop Bit and Power Domain */
+static struct hwblk sh7724_hwblk[HWBLK_NR] = {
+        [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
+        [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
+        [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
+        [HWBLK_RSMEM] = HWBLK(MSTPCR0, 28, CORE_AREA),
+        [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
+        [HWBLK_L2C] = HWBLK(MSTPCR0, 26, CORE_AREA),
+        [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
+        [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
+        [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
+        [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
+        [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
+        [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
+        [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
+        [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
+        [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
+        [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
+        [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
+        [HWBLK_TMU1] = HWBLK(MSTPCR0, 10, CORE_AREA),
+        [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
+        [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
+        [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
+        [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
+        [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
+        [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
+        [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
+        [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
+
+        [HWBLK_KEYSC] = HWBLK(MSTPCR1, 12, SUB_AREA),
+        [HWBLK_RTC] = HWBLK(MSTPCR1, 11, SUB_AREA),
+        [HWBLK_IIC0] = HWBLK(MSTPCR1, 9, CORE_AREA),
+        [HWBLK_IIC1] = HWBLK(MSTPCR1, 8, CORE_AREA),
+
+        [HWBLK_MMC] = HWBLK(MSTPCR2, 29, CORE_AREA),
+        [HWBLK_ETHER] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
+        [HWBLK_ATAPI] = HWBLK(MSTPCR2, 26, CORE_AREA_BM),
+        [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
+        [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
+        [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
+        [HWBLK_USB1] = HWBLK(MSTPCR2, 21, CORE_AREA),
+        [HWBLK_USB0] = HWBLK(MSTPCR2, 20, CORE_AREA),
+        [HWBLK_2DG] = HWBLK(MSTPCR2, 19, CORE_AREA_BM),
+        [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
+        [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
+        [HWBLK_VEU1] = HWBLK(MSTPCR2, 15, CORE_AREA_BM),
+        [HWBLK_CEU1] = HWBLK(MSTPCR2, 13, CORE_AREA_BM),
+        [HWBLK_BEU1] = HWBLK(MSTPCR2, 12, CORE_AREA_BM),
+        [HWBLK_2DDMAC] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
+        [HWBLK_SPU] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
+        [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
+        [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
+        [HWBLK_BEU0] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
+        [HWBLK_CEU0] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
+        [HWBLK_VEU0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
+        [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
+        [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
+};
+
+static struct hwblk_info sh7724_hwblk_info = {
+        .areas = sh7724_hwblk_area,
+        .nr_areas = ARRAY_SIZE(sh7724_hwblk_area),
+        .hwblks = sh7724_hwblk,
+        .nr_hwblks = ARRAY_SIZE(sh7724_hwblk),
+};
+
+int arch_hwblk_sleep_mode(void)
+{
+        if (!sh7724_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
+                return SUSP_SH_STANDBY | SUSP_SH_SF;
+
+        if (!sh7724_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
+                return SUSP_SH_SLEEP | SUSP_SH_SF;
+
+        return SUSP_SH_SLEEP;
+}
+
+int __init arch_hwblk_init(void)
+{
+        return hwblk_register(&sh7724_hwblk_info);
+}
diff --git a/arch/sh/kernel/cpu/sh4a/intc-shx3.c b/arch/sh/kernel/cpu/sh4a/intc-shx3.c
new file mode 100644
index 000000000000..78c971486b4e
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/intc-shx3.c
@@ -0,0 +1,34 @@
+/*
+ * Shared support for SH-X3 interrupt controllers.
+ *
+ *  Copyright (C) 2009 - 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/init.h>
+
+#define INTACK          0xfe4100b8
+#define INTACKCLR       0xfe4100bc
+#define INTC_USERIMASK  0xfe411000
+
+#ifdef CONFIG_INTC_BALANCING
+unsigned int irq_lookup(unsigned int irq)
+{
+        return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
+}
+
+void irq_finish(unsigned int irq)
+{
+        __raw_writel(irq2evt(irq), INTACKCLR);
+}
+#endif
+
+static int __init shx3_irq_setup(void)
+{
+        return register_intc_userimask(INTC_USERIMASK);
+}
+arch_initcall(shx3_irq_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c
new file mode 100644
index 000000000000..17e6bebfede0
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/perf_event.c
@@ -0,0 +1,287 @@
+/*
+ * Performance events support for SH-4A performance counters
+ *
+ *  Copyright (C) 2009, 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/perf_event.h>
+#include <asm/processor.h>
+
+#define PPC_CCBR(idx)   (0xff200800 + (sizeof(u32) * idx))
+#define PPC_PMCTR(idx)  (0xfc100000 + (sizeof(u32) * idx))
+
+#define CCBR_CIT_MASK   (0x7ff << 6)
+#define CCBR_DUC        (1 << 3)
+#define CCBR_CMDS       (1 << 1)
+#define CCBR_PPCE       (1 << 0)
+
+#ifdef CONFIG_CPU_SHX3
+/*
+ * The PMCAT location for SH-X3 CPUs was quietly moved, while the CCBR
+ * and PMCTR locations remains tentatively constant. This change remains
+ * wholly undocumented, and was simply found through trial and error.
+ *
+ * Early cuts of SH-X3 still appear to use the SH-X/SH-X2 locations, and
+ * it's unclear when this ceased to be the case. For now we always use
+ * the new location (if future parts keep up with this trend then
+ * scanning for them at runtime also remains a viable option.)
+ *
+ * The gap in the register space also suggests that there are other
+ * undocumented counters, so this will need to be revisited at a later
+ * point in time.
+ */
+#define PPC_PMCAT       0xfc100240
+#else
+#define PPC_PMCAT       0xfc100080
+#endif
+
+#define PMCAT_OVF3      (1 << 27)
+#define PMCAT_CNN3      (1 << 26)
+#define PMCAT_CLR3      (1 << 25)
+#define PMCAT_OVF2      (1 << 19)
+#define PMCAT_CLR2      (1 << 17)
+#define PMCAT_OVF1      (1 << 11)
+#define PMCAT_CNN1      (1 << 10)
+#define PMCAT_CLR1      (1 << 9)
+#define PMCAT_OVF0      (1 << 3)
+#define PMCAT_CLR0      (1 << 1)
+
+static struct sh_pmu sh4a_pmu;
+
+/*
+ * Supported raw event codes:
+ *
+ *      Event Code      Description
+ *      ----------      -----------
+ *
+ *      0x0000          number of elapsed cycles
+ *      0x0200          number of elapsed cycles in privileged mode
+ *      0x0280          number of elapsed cycles while SR.BL is asserted
+ *      0x0202          instruction execution
+ *      0x0203          instruction execution in parallel
+ *      0x0204          number of unconditional branches
+ *      0x0208          number of exceptions
+ *      0x0209          number of interrupts
+ *      0x0220          UTLB miss caused by instruction fetch
+ *      0x0222          UTLB miss caused by operand access
+ *      0x02a0          number of ITLB misses
+ *      0x0028          number of accesses to instruction memories
+ *      0x0029          number of accesses to instruction cache
+ *      0x002a          instruction cache miss
+ *      0x022e          number of access to instruction X/Y memory
+ *      0x0030          number of reads to operand memories
+ *      0x0038          number of writes to operand memories
+ *      0x0031          number of operand cache read accesses
+ *      0x0039          number of operand cache write accesses
+ *      0x0032          operand cache read miss
+ *      0x003a          operand cache write miss
+ *      0x0236          number of reads to operand X/Y memory
+ *      0x023e          number of writes to operand X/Y memory
+ *      0x0237          number of reads to operand U memory
+ *      0x023f          number of writes to operand U memory
+ *      0x0337          number of U memory read buffer misses
+ *      0x02b4          number of wait cycles due to operand read access
+ *      0x02bc          number of wait cycles due to operand write access
+ *      0x0033          number of wait cycles due to operand cache read miss
+ *      0x003b          number of wait cycles due to operand cache write miss
+ */
+
+/*
+ * Special reserved bits used by hardware emulators, read values will
+ * vary, but writes must always be 0.
+ */
+#define PMCAT_EMU_CLR_MASK      ((1 << 24) | (1 << 16) | (1 << 8) | (1 << 0))
+
+static const int sh4a_general_events[] = {
+        [PERF_COUNT_HW_CPU_CYCLES]              = 0x0000,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = 0x0202,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x0029,       /* I-cache */
+        [PERF_COUNT_HW_CACHE_MISSES]            = 0x002a,       /* I-cache */
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x0204,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = -1,
+        [PERF_COUNT_HW_BUS_CYCLES]              = -1,
+};
+
+#define C(x)    PERF_COUNT_HW_CACHE_##x
+
+static const int sh4a_cache_events
+                        [PERF_COUNT_HW_CACHE_MAX]
+                        [PERF_COUNT_HW_CACHE_OP_MAX]
+                        [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+        [ C(L1D) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0031,
+                        [ C(RESULT_MISS)   ] = 0x0032,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0039,
+                        [ C(RESULT_MISS)   ] = 0x003a,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+
+        [ C(L1I) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0029,
+                        [ C(RESULT_MISS)   ] = 0x002a,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+
+        [ C(LL) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0030,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0038,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+
+        [ C(DTLB) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0x0222,
+                        [ C(RESULT_MISS)   ] = 0x0220,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+
+        [ C(ITLB) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0x02a0,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+        },
+
+        [ C(BPU) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+        },
+};
+
+static int sh4a_event_map(int event)
+{
+        return sh4a_general_events[event];
+}
+
+static u64 sh4a_pmu_read(int idx)
+{
+        return __raw_readl(PPC_PMCTR(idx));
+}
+
+static void sh4a_pmu_disable(struct hw_perf_event *hwc, int idx)
+{
+        unsigned int tmp;
+
+        tmp = __raw_readl(PPC_CCBR(idx));
+        tmp &= ~(CCBR_CIT_MASK | CCBR_DUC);
+        __raw_writel(tmp, PPC_CCBR(idx));
+}
+
+static void sh4a_pmu_enable(struct hw_perf_event *hwc, int idx)
+{
+        unsigned int tmp;
+
+        tmp = __raw_readl(PPC_PMCAT);
+        tmp &= ~PMCAT_EMU_CLR_MASK;
+        tmp |= idx ? PMCAT_CLR1 : PMCAT_CLR0;
+        __raw_writel(tmp, PPC_PMCAT);
+
+        tmp = __raw_readl(PPC_CCBR(idx));
+        tmp |= (hwc->config << 6) | CCBR_CMDS | CCBR_PPCE;
+        __raw_writel(tmp, PPC_CCBR(idx));
+
+        __raw_writel(__raw_readl(PPC_CCBR(idx)) | CCBR_DUC, PPC_CCBR(idx));
+}
+
+static void sh4a_pmu_disable_all(void)
+{
+        int i;
+
+        for (i = 0; i < sh4a_pmu.num_events; i++)
+                __raw_writel(__raw_readl(PPC_CCBR(i)) & ~CCBR_DUC, PPC_CCBR(i));
+}
+
+static void sh4a_pmu_enable_all(void)
+{
+        int i;
+
+        for (i = 0; i < sh4a_pmu.num_events; i++)
+                __raw_writel(__raw_readl(PPC_CCBR(i)) | CCBR_DUC, PPC_CCBR(i));
+}
+
+static struct sh_pmu sh4a_pmu = {
+        .name           = "sh4a",
+        .num_events     = 2,
+        .event_map      = sh4a_event_map,
+        .max_events     = ARRAY_SIZE(sh4a_general_events),
+        .raw_event_mask = 0x3ff,
+        .cache_events   = &sh4a_cache_events,
+        .read           = sh4a_pmu_read,
+        .disable        = sh4a_pmu_disable,
+        .enable         = sh4a_pmu_enable,
+        .disable_all    = sh4a_pmu_disable_all,
+        .enable_all     = sh4a_pmu_enable_all,
+};
+
+static int __init sh4a_pmu_init(void)
+{
+        /*
+         * Make sure this CPU actually has perf counters.
+         */
+        if (!(boot_cpu_data.flags & CPU_HAS_PERF_COUNTER)) {
+                pr_notice("HW perf events unsupported, software events only.\n");
+                return -ENODEV;
+        }
+
+        return register_sh_pmu(&sh4a_pmu);
+}
+early_initcall(sh4a_pmu_init);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
index cb9d07bd59f8..0688a7502f86 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
@@ -278,6 +278,7 @@ enum {
         HIZA8_LCDC, HIZA8_HIZ,
         HIZA7_LCDC, HIZA7_HIZ,
         HIZA6_LCDC, HIZA6_HIZ,
+        HIZB4_SIUA, HIZB4_HIZ,
         HIZB1_VIO, HIZB1_HIZ,
         HIZB0_VIO, HIZB0_HIZ,
         HIZC15_IRQ7, HIZC15_HIZ,
@@ -546,7 +547,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(VIO_VD2_MARK, PSE3_VIO, MSELB9_VIO2,
                     HIZB0_VIO, FOE_VIO_VD2),
         PINMUX_DATA(VIO_HD2_MARK, PSE3_VIO, MSELB9_VIO2,
-                    HIZB1_VIO, HIZB1_VIO, FCE_VIO_HD2),
+                    HIZB1_VIO, FCE_VIO_HD2),
         PINMUX_DATA(VIO_CLK2_MARK, PSE3_VIO, MSELB9_VIO2,
                     HIZB1_VIO, FRB_VIO_CLK2),
 
@@ -658,14 +659,14 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(SDHICLK_MARK, SDHICLK),
 
         /* SIU - Port A */
-        PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, SIUAOLR_SIOF1_SYNC),
-        PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, SIUAOBT_SIOF1_SCK),
-        PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, SIUAISLD_SIOF1_RXD),
-        PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, SIUAILR_SIOF1_SS2),
-        PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, SIUAIBT_SIOF1_SS1),
-        PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, SIUAOSLD_SIOF1_TXD),
-        PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, PSB1_SIUMCKA, PTK0),
-        PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, PTK0),
+        PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, HIZB4_SIUA, SIUAOLR_SIOF1_SYNC),
+        PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, HIZB4_SIUA, SIUAOBT_SIOF1_SCK),
+        PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, HIZB4_SIUA, SIUAISLD_SIOF1_RXD),
+        PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, HIZB4_SIUA, SIUAILR_SIOF1_SS2),
+        PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, HIZB4_SIUA, SIUAIBT_SIOF1_SS1),
+        PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, HIZB4_SIUA, SIUAOSLD_SIOF1_TXD),
+        PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, HIZB4_SIUA, PSB1_SIUMCKA, PTK0),
+        PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, HIZB4_SIUA, PTK0),
 
         /* SIU - Port B */
         PINMUX_DATA(SIUBOLR_MARK, PSB11_SIUBOLR, SIOSTRB1_SIUBOLR),
@@ -1612,7 +1613,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 0, 0,
                 0, 0,
                 0, 0,
-                0, 0,
+                HIZB4_SIUA, HIZB4_HIZ,
                 0, 0,
                 0, 0,
                 HIZB1_VIO, HIZB1_HIZ,
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
new file mode 100644
index 000000000000..4c74bd04bba4
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
@@ -0,0 +1,2287 @@
+/*
+ * SH7757 (B0 step) Pinmux
+ *
+ *  Copyright (C) 2009-2010  Renesas Solutions Corp.
+ *
+ *  Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * Based on SH7723 Pinmux
+ *  Copyright (C) 2008  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <cpu/sh7757.h>
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+        PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
+        PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+        PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
+        PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
+        PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
+        PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+        PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
+        PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
+        PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
+        PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
+        PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
+        PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
+        PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
+        PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
+        PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
+        PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
+        PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA,
+                   PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
+        PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
+        PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
+        PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
+                   PTL6_DATA, PTL5_DATA, PTL4_DATA,
+        PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
+        PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+        PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
+                   PTN6_DATA, PTN5_DATA, PTN4_DATA,
+        PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
+        PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
+        PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA,
+        PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
+        PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA,
+                   PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
+        PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
+        PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
+        PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
+        PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
+        PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
+        PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
+        PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
+        PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
+        PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
+        PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
+        PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
+        PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
+        PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
+        PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
+        PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
+        PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
+        PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
+        PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
+        PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
+        PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
+        PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
+        PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
+        PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
+        PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
+        PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
+        PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
+        PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN,
+        PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
+        PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
+        PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
+        PTG7_IN, PTG6_IN, PTG5_IN, PTG4_IN,
+        PTG3_IN, PTG2_IN, PTG1_IN, PTG0_IN,
+        PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
+        PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
+        PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN,
+        PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN,
+                 PTJ6_IN, PTJ5_IN, PTJ4_IN,
+        PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
+        PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
+        PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
+                 PTL6_IN, PTL5_IN, PTL4_IN,
+        PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
+        PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
+        PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
+                 PTN6_IN, PTN5_IN, PTN4_IN,
+        PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
+        PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN,
+        PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN,
+        PTP7_IN, PTP6_IN, PTP5_IN, PTP4_IN,
+        PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN,
+                 PTQ6_IN, PTQ5_IN, PTQ4_IN,
+        PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
+        PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
+        PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
+        PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN,
+        PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
+        PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN,
+        PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
+        PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
+        PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
+        PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
+        PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
+        PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
+        PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
+        PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
+        PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
+        PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
+        PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
+        PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
+        PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
+        PINMUX_INPUT_END,
+
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
+        PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
+        PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
+        PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
+        PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU,
+        PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
+        PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU,
+        PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU,
+        PTG7_IN_PU, PTG6_IN_PU,             PTG4_IN_PU,
+        PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
+        PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
+        PTI7_IN_PU, PTI6_IN_PU,             PTI4_IN_PU,
+        PTI3_IN_PU, PTI2_IN_PU, PTI1_IN_PU, PTI0_IN_PU,
+                    PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU,
+        PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
+        PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU,
+        PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
+                    PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU,
+        PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU,
+        PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
+                                            PTN4_IN_PU,
+        PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU,
+        PTO7_IN_PU, PTO6_IN_PU, PTO5_IN_PU, PTO4_IN_PU,
+        PTO3_IN_PU, PTO2_IN_PU, PTO1_IN_PU, PTO0_IN_PU,
+        PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU,
+        PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
+        PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
+        PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
+        PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
+        PTV3_IN_PU, PTV2_IN_PU,
+                                PTW1_IN_PU, PTW0_IN_PU,
+        PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
+        PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
+        PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
+        PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
+        PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU,
+        PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU,
+        PINMUX_INPUT_PULLUP_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
+        PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
+        PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
+        PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
+        PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
+        PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
+        PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
+        PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
+        PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT,
+        PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
+        PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
+        PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
+        PTG7_OUT, PTG6_OUT, PTG5_OUT, PTG4_OUT,
+        PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
+        PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
+        PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
+        PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT,
+        PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT,
+                  PTJ6_OUT, PTJ5_OUT, PTJ4_OUT,
+        PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
+        PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
+        PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
+                  PTL6_OUT, PTL5_OUT, PTL4_OUT,
+        PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
+        PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
+        PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
+                  PTN6_OUT, PTN5_OUT, PTN4_OUT,
+        PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
+        PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT,
+        PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT,
+        PTP7_OUT, PTP6_OUT, PTP5_OUT, PTP4_OUT,
+        PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT,
+                  PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
+        PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
+        PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
+        PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT,
+        PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT,
+        PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
+        PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT,
+        PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
+        PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
+        PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
+        PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
+        PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
+        PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
+        PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
+        PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
+        PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
+        PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
+        PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
+        PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
+        PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
+        PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
+        PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
+        PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
+        PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
+        PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
+        PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
+        PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
+        PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN,
+        PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
+        PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
+        PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
+        PTG7_FN, PTG6_FN, PTG5_FN, PTG4_FN,
+        PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
+        PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
+        PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
+        PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN,
+        PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN,
+                 PTJ6_FN, PTJ5_FN, PTJ4_FN,
+        PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
+        PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
+        PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
+                 PTL6_FN, PTL5_FN, PTL4_FN,
+        PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
+        PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
+        PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
+                 PTN6_FN, PTN5_FN, PTN4_FN,
+        PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
+        PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN,
+        PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN,
+        PTP7_FN, PTP6_FN, PTP5_FN, PTP4_FN,
+        PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN,
+                 PTQ6_FN, PTQ5_FN, PTQ4_FN,
+        PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
+        PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
+        PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
+        PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN,
+        PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
+        PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN,
+        PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
+        PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
+        PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
+        PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
+        PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
+        PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
+        PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
+        PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
+        PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
+        PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
+        PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
+        PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
+        PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
+
+        PS0_15_FN1, PS0_15_FN2,
+        PS0_14_FN1, PS0_14_FN2,
+        PS0_13_FN1, PS0_13_FN2,
+        PS0_12_FN1, PS0_12_FN2,
+        PS0_11_FN1, PS0_11_FN2,
+        PS0_10_FN1, PS0_10_FN2,
+        PS0_9_FN1, PS0_9_FN2,
+        PS0_8_FN1, PS0_8_FN2,
+        PS0_7_FN1, PS0_7_FN2,
+        PS0_6_FN1, PS0_6_FN2,
+        PS0_5_FN1, PS0_5_FN2,
+        PS0_4_FN1, PS0_4_FN2,
+        PS0_3_FN1, PS0_3_FN2,
+        PS0_2_FN1, PS0_2_FN2,
+
+        PS1_10_FN1, PS1_10_FN2,
+        PS1_9_FN1, PS1_9_FN2,
+        PS1_8_FN1, PS1_8_FN2,
+        PS1_2_FN1, PS1_2_FN2,
+
+        PS2_13_FN1, PS2_13_FN2,
+        PS2_12_FN1, PS2_12_FN2,
+        PS2_7_FN1, PS2_7_FN2,
+        PS2_6_FN1, PS2_6_FN2,
+        PS2_5_FN1, PS2_5_FN2,
+        PS2_4_FN1, PS2_4_FN2,
+        PS2_2_FN1, PS2_2_FN2,
+
+        PS3_15_FN1, PS3_15_FN2,
+        PS3_14_FN1, PS3_14_FN2,
+        PS3_13_FN1, PS3_13_FN2,
+        PS3_12_FN1, PS3_12_FN2,
+        PS3_11_FN1, PS3_11_FN2,
+        PS3_10_FN1, PS3_10_FN2,
+        PS3_9_FN1, PS3_9_FN2,
+        PS3_8_FN1, PS3_8_FN2,
+        PS3_7_FN1, PS3_7_FN2,
+        PS3_2_FN1, PS3_2_FN2,
+        PS3_1_FN1, PS3_1_FN2,
+
+        PS4_14_FN1, PS4_14_FN2,
+        PS4_13_FN1, PS4_13_FN2,
+        PS4_12_FN1, PS4_12_FN2,
+        PS4_10_FN1, PS4_10_FN2,
+        PS4_9_FN1, PS4_9_FN2,
+        PS4_8_FN1, PS4_8_FN2,
+        PS4_4_FN1, PS4_4_FN2,
+        PS4_3_FN1, PS4_3_FN2,
+        PS4_2_FN1, PS4_2_FN2,
+        PS4_1_FN1, PS4_1_FN2,
+        PS4_0_FN1, PS4_0_FN2,
+
+        PS5_11_FN1, PS5_11_FN2,
+        PS5_10_FN1, PS5_10_FN2,
+        PS5_9_FN1, PS5_9_FN2,
+        PS5_8_FN1, PS5_8_FN2,
+        PS5_7_FN1, PS5_7_FN2,
+        PS5_6_FN1, PS5_6_FN2,
+        PS5_5_FN1, PS5_5_FN2,
+        PS5_4_FN1, PS5_4_FN2,
+        PS5_3_FN1, PS5_3_FN2,
+        PS5_2_FN1, PS5_2_FN2,
+
+        PS6_15_FN1, PS6_15_FN2,
+        PS6_14_FN1, PS6_14_FN2,
+        PS6_13_FN1, PS6_13_FN2,
+        PS6_12_FN1, PS6_12_FN2,
+        PS6_11_FN1, PS6_11_FN2,
+        PS6_10_FN1, PS6_10_FN2,
+        PS6_9_FN1, PS6_9_FN2,
+        PS6_8_FN1, PS6_8_FN2,
+        PS6_7_FN1, PS6_7_FN2,
+        PS6_6_FN1, PS6_6_FN2,
+        PS6_5_FN1, PS6_5_FN2,
+        PS6_4_FN1, PS6_4_FN2,
+        PS6_3_FN1, PS6_3_FN2,
+        PS6_2_FN1, PS6_2_FN2,
+        PS6_1_FN1, PS6_1_FN2,
+        PS6_0_FN1, PS6_0_FN2,
+
+        PS7_15_FN1, PS7_15_FN2,
+        PS7_14_FN1, PS7_14_FN2,
+        PS7_13_FN1, PS7_13_FN2,
+        PS7_12_FN1, PS7_12_FN2,
+        PS7_11_FN1, PS7_11_FN2,
+        PS7_10_FN1, PS7_10_FN2,
+        PS7_9_FN1, PS7_9_FN2,
+        PS7_8_FN1, PS7_8_FN2,
+        PS7_7_FN1, PS7_7_FN2,
+        PS7_6_FN1, PS7_6_FN2,
+        PS7_5_FN1, PS7_5_FN2,
+        PS7_4_FN1, PS7_4_FN2,
+
+        PS8_15_FN1, PS8_15_FN2,
+        PS8_14_FN1, PS8_14_FN2,
+        PS8_13_FN1, PS8_13_FN2,
+        PS8_12_FN1, PS8_12_FN2,
+        PS8_11_FN1, PS8_11_FN2,
+        PS8_10_FN1, PS8_10_FN2,
+        PS8_9_FN1, PS8_9_FN2,
+        PS8_8_FN1, PS8_8_FN2,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+        /* PTA (mobule: LBSC, RGMII) */
+        BS_MARK,        RDWR_MARK,      WE1_MARK,       RDY_MARK,
+        ET0_MDC_MARK,   ET0_MDIO_MARK,  ET1_MDC_MARK,   ET1_MDIO_MARK,
+
+        /* PTB (mobule: INTC, ONFI, TMU) */
+        IRQ15_MARK,     IRQ14_MARK,     IRQ13_MARK,     IRQ12_MARK,
+        IRQ11_MARK,     IRQ10_MARK,     IRQ9_MARK,      IRQ8_MARK,
+        ON_NRE_MARK,    ON_NWE_MARK,    ON_NWP_MARK,    ON_NCE0_MARK,
+        ON_R_B0_MARK,   ON_ALE_MARK,    ON_CLE_MARK,    TCLK_MARK,
+
+        /* PTC (mobule: IRQ, PWMU) */
+        IRQ7_MARK,      IRQ6_MARK,      IRQ5_MARK,      IRQ4_MARK,
+        IRQ3_MARK,      IRQ2_MARK,      IRQ1_MARK,      IRQ0_MARK,
+        PWMU0_MARK,     PWMU1_MARK,     PWMU2_MARK,     PWMU3_MARK,
+        PWMU4_MARK,     PWMU5_MARK,
+
+        /* PTD (mobule: SPI0, DMAC) */
+        SP0_MOSI_MARK,  SP0_MISO_MARK,  SP0_SCK_MARK,   SP0_SCK_FB_MARK,
+        SP0_SS0_MARK,   SP0_SS1_MARK,   SP0_SS2_MARK,   SP0_SS3_MARK,
+        DREQ0_MARK,     DACK0_MARK,     TEND0_MARK,
+
+        /* PTE (mobule: RMII) */
+        RMII0_CRS_DV_MARK,      RMII0_TXD1_MARK,
+        RMII0_TXD0_MARK,        RMII0_TXEN_MARK,
+        RMII0_REFCLK_MARK,      RMII0_RXD1_MARK,
+        RMII0_RXD0_MARK,        RMII0_RX_ER_MARK,
+
+        /* PTF (mobule: RMII, SerMux) */
+        RMII1_CRS_DV_MARK,      RMII1_TXD1_MARK,
+        RMII1_TXD0_MARK,        RMII1_TXEN_MARK,
+        RMII1_REFCLK_MARK,      RMII1_RXD1_MARK,
+        RMII1_RXD0_MARK,        RMII1_RX_ER_MARK,
+        RAC_RI_MARK,
+
+        /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
+        BOOTFMS_MARK,   BOOTWP_MARK,    A25_MARK,       A24_MARK,
+        SERIRQ_MARK,    WDTOVF_MARK,    LPCPD_MARK,     LDRQ_MARK,
+        MMCCLK_MARK,    MMCCMD_MARK,
+
+        /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
+        SP1_MOSI_MARK,  SP1_MISO_MARK,  SP1_SCK_MARK,   SP1_SCK_FB_MARK,
+        SP1_SS0_MARK,   SP1_SS1_MARK,   WP_MARK,        FMS0_MARK,
+        TEND1_MARK,     DREQ1_MARK,     DACK1_MARK,     ADTRG1_MARK,
+        ADTRG0_MARK,
+
+        /* PTI (mobule: LBSC, SDHI) */
+        D15_MARK,       D14_MARK,       D13_MARK,       D12_MARK,
+        D11_MARK,       D10_MARK,       D9_MARK,        D8_MARK,
+        SD_WP_MARK,     SD_CD_MARK,     SD_CLK_MARK,    SD_CMD_MARK,
+        SD_D3_MARK,     SD_D2_MARK,     SD_D1_MARK,     SD_D0_MARK,
+
+        /* PTJ (mobule: SCIF234) */
+        RTS3_MARK,      CTS3_MARK,      TXD3_MARK,      RXD3_MARK,
+        RTS4_MARK,      RXD4_MARK,      TXD4_MARK,
+
+        /* PTK (mobule: SERMUX, LBSC, SCIF) */
+        COM2_TXD_MARK,  COM2_RXD_MARK,  COM2_RTS_MARK,  COM2_CTS_MARK,
+        COM2_DTR_MARK,  COM2_DSR_MARK,  COM2_DCD_MARK,  CLKOUT_MARK,
+        SCK2_MARK,      SCK4_MARK,      SCK3_MARK,
+
+        /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
+        RAC_RXD_MARK,   RAC_RTS_MARK,   RAC_CTS_MARK,   RAC_DTR_MARK,
+        RAC_DSR_MARK,   RAC_DCD_MARK,   RAC_TXD_MARK,   RXD2_MARK,
+        CS5_MARK,       CS6_MARK,       AUDSYNC_MARK,   AUDCK_MARK,
+        TXD2_MARK,
+
+        /* PTM (mobule: LBSC, IIC) */
+        CS4_MARK,       RD_MARK,        WE0_MARK,       CS0_MARK,
+        SDA6_MARK,      SCL6_MARK,      SDA7_MARK,      SCL7_MARK,
+
+        /* PTN (mobule: USB, JMC, SGPIO, WDT) */
+        VBUS_EN_MARK,   VBUS_OC_MARK,   JMCTCK_MARK,    JMCTMS_MARK,
+        JMCTDO_MARK,    JMCTDI_MARK,    JMCTRST_MARK,
+        SGPIO1_CLK_MARK,        SGPIO1_LOAD_MARK,       SGPIO1_DI_MARK,
+        SGPIO1_DO_MARK,         SUB_CLKIN_MARK,
+
+        /* PTO (mobule: SGPIO, SerMux) */
+        SGPIO0_CLK_MARK,        SGPIO0_LOAD_MARK,       SGPIO0_DI_MARK,
+        SGPIO0_DO_MARK,         SGPIO2_CLK_MARK,        SGPIO2_LOAD_MARK,
+        SGPIO2_DI_MARK,         SGPIO2_DO_MARK,
+        COM1_TXD_MARK,  COM1_RXD_MARK,  COM1_RTS_MARK,  COM1_CTS_MARK,
+
+        /* PTQ (mobule: LPC) */
+        LAD3_MARK,      LAD2_MARK,      LAD1_MARK,      LAD0_MARK,
+        LFRAME_MARK,    LRESET_MARK,    LCLK_MARK,
+
+        /* PTR (mobule: GRA, IIC) */
+        DDC3_MARK,      DDC2_MARK,      SDA2_MARK,      SCL2_MARK,
+        SDA1_MARK,      SCL1_MARK,      SDA0_MARK,      SCL0_MARK,
+        SDA8_MARK,      SCL8_MARK,
+
+        /* PTS (mobule: GRA, IIC) */
+        DDC1_MARK,      DDC0_MARK,      SDA5_MARK,      SCL5_MARK,
+        SDA4_MARK,      SCL4_MARK,      SDA3_MARK,      SCL3_MARK,
+        SDA9_MARK,      SCL9_MARK,
+
+        /* PTT (mobule: PWMX, AUD) */
+        PWMX7_MARK,     PWMX6_MARK,     PWMX5_MARK,     PWMX4_MARK,
+        PWMX3_MARK,     PWMX2_MARK,     PWMX1_MARK,     PWMX0_MARK,
+        AUDATA3_MARK,   AUDATA2_MARK,   AUDATA1_MARK,   AUDATA0_MARK,
+        STATUS1_MARK,   STATUS0_MARK,
+
+        /* PTU (mobule: LPC, APM) */
+        LGPIO7_MARK,    LGPIO6_MARK,    LGPIO5_MARK,    LGPIO4_MARK,
+        LGPIO3_MARK,    LGPIO2_MARK,    LGPIO1_MARK,    LGPIO0_MARK,
+        APMONCTL_O_MARK,        APMPWBTOUT_O_MARK,      APMSCI_O_MARK,
+        APMVDDON_MARK,  APMSLPBTN_MARK, APMPWRBTN_MARK, APMS5N_MARK,
+        APMS3N_MARK,
+
+        /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
+        A23_MARK,       A22_MARK,       A21_MARK,       A20_MARK,
+        A19_MARK,       A18_MARK,       A17_MARK,       A16_MARK,
+        COM2_RI_MARK,           R_SPI_MOSI_MARK,        R_SPI_MISO_MARK,
+        R_SPI_RSPCK_MARK,       R_SPI_SSL0_MARK,        R_SPI_SSL1_MARK,
+        EVENT7_MARK,    EVENT6_MARK,    VBIOS_DI_MARK,  VBIOS_DO_MARK,
+        VBIOS_CLK_MARK, VBIOS_CS_MARK,
+
+        /* PTW (mobule: LBSC, EVC, SCIF) */
+        A15_MARK,       A14_MARK,       A13_MARK,       A12_MARK,
+        A11_MARK,       A10_MARK,       A9_MARK,        A8_MARK,
+        EVENT5_MARK,    EVENT4_MARK,    EVENT3_MARK,    EVENT2_MARK,
+        EVENT1_MARK,    EVENT0_MARK,    CTS4_MARK,      CTS2_MARK,
+
+        /* PTX (mobule: LBSC, SCIF, SIM) */
+        A7_MARK,        A6_MARK,        A5_MARK,        A4_MARK,
+        A3_MARK,        A2_MARK,        A1_MARK,        A0_MARK,
+        RTS2_MARK,      SIM_D_MARK,     SIM_CLK_MARK,   SIM_RST_MARK,
+
+        /* PTY (mobule: LBSC) */
+        D7_MARK,        D6_MARK,        D5_MARK,        D4_MARK,
+        D3_MARK,        D2_MARK,        D1_MARK,        D0_MARK,
+
+        /* PTZ (mobule: eMMC, ONFI) */
+        MMCDAT7_MARK,   MMCDAT6_MARK,   MMCDAT5_MARK,   MMCDAT4_MARK,
+        MMCDAT3_MARK,   MMCDAT2_MARK,   MMCDAT1_MARK,   MMCDAT0_MARK,
+        ON_DQ7_MARK,    ON_DQ6_MARK,    ON_DQ5_MARK,    ON_DQ4_MARK,
+        ON_DQ3_MARK,    ON_DQ2_MARK,    ON_DQ1_MARK,    ON_DQ0_MARK,
+
+        PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+        /* PTA GPIO */
+        PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
+        PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
+        PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
+        PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT),
+        PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT),
+        PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT),
+        PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT),
+        PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT),
+
+        /* PTB GPIO */
+        PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
+        PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
+        PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
+        PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
+        PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
+        PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
+        PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
+        PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
+
+        /* PTC GPIO */
+        PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT),
+        PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT),
+        PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT),
+        PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
+        PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
+        PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
+        PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT),
+        PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
+
+        /* PTD GPIO */
+        PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT),
+        PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT),
+        PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT),
+        PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT),
+        PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT),
+        PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT),
+        PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT),
+        PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
+
+        /* PTE GPIO */
+        PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT),
+        PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT),
+        PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT),
+        PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
+        PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
+        PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT),
+        PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT),
+        PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT),
+
+        /* PTF GPIO */
+        PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT),
+        PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT),
+        PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT),
+        PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT),
+        PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT),
+        PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT),
+        PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT),
+        PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT),
+
+        /* PTG GPIO */
+        PINMUX_DATA(PTG7_DATA, PTG7_IN, PTG7_OUT),
+        PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT),
+        PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT),
+        PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT),
+        PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT),
+        PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT),
+        PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT),
+        PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT),
+
+        /* PTH GPIO */
+        PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT),
+        PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT),
+        PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT),
+        PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT),
+        PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT),
+        PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT),
+        PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT),
+        PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT),
+
+        /* PTI GPIO */
+        PINMUX_DATA(PTI7_DATA, PTI7_IN, PTI7_OUT),
+        PINMUX_DATA(PTI6_DATA, PTI6_IN, PTI6_OUT),
+        PINMUX_DATA(PTI5_DATA, PTI5_IN, PTI5_OUT),
+        PINMUX_DATA(PTI4_DATA, PTI4_IN, PTI4_OUT),
+        PINMUX_DATA(PTI3_DATA, PTI3_IN, PTI3_OUT),
+        PINMUX_DATA(PTI2_DATA, PTI2_IN, PTI2_OUT),
+        PINMUX_DATA(PTI1_DATA, PTI1_IN, PTI1_OUT),
+        PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT),
+
+        /* PTJ GPIO */
+        PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT),
+        PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT),
+        PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT),
+        PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT),
+        PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT),
+        PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT),
+        PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT),
+
+        /* PTK GPIO */
+        PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT),
+        PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT),
+        PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT),
+        PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT),
+        PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT),
+        PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT),
+        PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT),
+        PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
+
+        /* PTL GPIO */
+        PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
+        PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
+        PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
+        PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT),
+        PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT),
+        PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT),
+        PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT),
+
+        /* PTM GPIO */
+        PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT),
+        PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT),
+        PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT),
+        PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT),
+        PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT),
+        PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT),
+        PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
+
+        /* PTN GPIO */
+        PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT),
+        PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT),
+        PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT),
+        PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT),
+        PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT),
+        PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT),
+        PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT),
+
+        /* PTO GPIO */
+        PINMUX_DATA(PTO7_DATA, PTO7_IN, PTO7_OUT),
+        PINMUX_DATA(PTO6_DATA, PTO6_IN, PTO6_OUT),
+        PINMUX_DATA(PTO5_DATA, PTO5_IN, PTO5_OUT),
+        PINMUX_DATA(PTO4_DATA, PTO4_IN, PTO4_OUT),
+        PINMUX_DATA(PTO3_DATA, PTO3_IN, PTO3_OUT),
+        PINMUX_DATA(PTO2_DATA, PTO2_IN, PTO2_OUT),
+        PINMUX_DATA(PTO1_DATA, PTO1_IN, PTO1_OUT),
+        PINMUX_DATA(PTO0_DATA, PTO0_IN, PTO0_OUT),
+
+        /* PTQ GPIO */
+        PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT),
+        PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT),
+        PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT),
+        PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT),
+        PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT),
+        PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT),
+        PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT),
+
+        /* PTR GPIO */
+        PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT),
+        PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT),
+        PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT),
+        PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT),
+        PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT),
+        PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT),
+        PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT),
+        PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT),
+
+        /* PTS GPIO */
+        PINMUX_DATA(PTS7_DATA, PTS7_IN, PTS7_OUT),
+        PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT),
+        PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT),
+        PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT),
+        PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT),
+        PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT),
+        PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT),
+        PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
+
+        /* PTT GPIO */
+        PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT),
+        PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT),
+        PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT),
+        PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
+        PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
+        PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT),
+        PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT),
+        PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT),
+
+        /* PTU GPIO */
+        PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT),
+        PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT),
+        PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT),
+        PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT),
+        PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT),
+        PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT),
+        PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT),
+        PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT),
+
+        /* PTV GPIO */
+        PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT),
+        PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT),
+        PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT),
+        PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT),
+        PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT),
+        PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT),
+        PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT),
+        PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT),
+
+        /* PTW GPIO */
+        PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT),
+        PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT),
+        PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT),
+        PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT),
+        PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT),
+        PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT),
+        PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT),
+        PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT),
+
+        /* PTX GPIO */
+        PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT),
+        PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT),
+        PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT),
+        PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT),
+        PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT),
+        PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT),
+        PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT),
+        PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT),
+
+        /* PTY GPIO */
+        PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT),
+        PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT),
+        PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT),
+        PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT),
+        PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT),
+        PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT),
+        PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT),
+        PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT),
+
+        /* PTZ GPIO */
+        PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT),
+        PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT),
+        PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT),
+        PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT),
+        PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT),
+        PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT),
+        PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT),
+        PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT),
+
+        /* PTA FN */
+        PINMUX_DATA(BS_MARK, PTA7_FN),
+        PINMUX_DATA(RDWR_MARK, PTA6_FN),
+        PINMUX_DATA(WE1_MARK, PTA5_FN),
+        PINMUX_DATA(RDY_MARK, PTA4_FN),
+        PINMUX_DATA(ET0_MDC_MARK, PTA3_FN),
+        PINMUX_DATA(ET0_MDIO_MARK, PTA2_FN),
+        PINMUX_DATA(ET1_MDC_MARK, PTA1_FN),
+        PINMUX_DATA(ET1_MDIO_MARK, PTA0_FN),
+
+        /* PTB FN */
+        PINMUX_DATA(IRQ15_MARK, PS0_15_FN1, PTB7_FN),
+        PINMUX_DATA(ON_NRE_MARK, PS0_15_FN2, PTB7_FN),
+        PINMUX_DATA(IRQ14_MARK, PS0_14_FN1, PTB6_FN),
+        PINMUX_DATA(ON_NWE_MARK, PS0_14_FN2, PTB6_FN),
+        PINMUX_DATA(IRQ13_MARK, PS0_13_FN1, PTB5_FN),
+        PINMUX_DATA(ON_NWP_MARK, PS0_13_FN2, PTB5_FN),
+        PINMUX_DATA(IRQ12_MARK, PS0_12_FN1, PTB4_FN),
+        PINMUX_DATA(ON_NCE0_MARK, PS0_12_FN2, PTB4_FN),
+        PINMUX_DATA(IRQ11_MARK, PS0_11_FN1, PTB3_FN),
+        PINMUX_DATA(ON_R_B0_MARK, PS0_11_FN2, PTB3_FN),
+        PINMUX_DATA(IRQ10_MARK, PS0_10_FN1, PTB2_FN),
+        PINMUX_DATA(ON_ALE_MARK, PS0_10_FN2, PTB2_FN),
+        PINMUX_DATA(IRQ9_MARK, PS0_9_FN1, PTB1_FN),
+        PINMUX_DATA(ON_CLE_MARK, PS0_9_FN2, PTB1_FN),
+        PINMUX_DATA(IRQ8_MARK, PS0_8_FN1, PTB0_FN),
+        PINMUX_DATA(TCLK_MARK, PS0_8_FN2, PTB0_FN),
+
+        /* PTC FN */
+        PINMUX_DATA(IRQ7_MARK, PS0_7_FN1, PTC7_FN),
+        PINMUX_DATA(PWMU0_MARK, PS0_7_FN2, PTC7_FN),
+        PINMUX_DATA(IRQ6_MARK, PS0_6_FN1, PTC6_FN),
+        PINMUX_DATA(PWMU1_MARK, PS0_6_FN2, PTC6_FN),
+        PINMUX_DATA(IRQ5_MARK, PS0_5_FN1, PTC5_FN),
+        PINMUX_DATA(PWMU2_MARK, PS0_5_FN2, PTC5_FN),
+        PINMUX_DATA(IRQ4_MARK, PS0_4_FN1, PTC5_FN),
+        PINMUX_DATA(PWMU3_MARK, PS0_4_FN2, PTC4_FN),
+        PINMUX_DATA(IRQ3_MARK, PS0_3_FN1, PTC3_FN),
+        PINMUX_DATA(PWMU4_MARK, PS0_3_FN2, PTC3_FN),
+        PINMUX_DATA(IRQ2_MARK, PS0_2_FN1, PTC2_FN),
+        PINMUX_DATA(PWMU5_MARK, PS0_2_FN2, PTC2_FN),
+        PINMUX_DATA(IRQ1_MARK, PTC1_FN),
+        PINMUX_DATA(IRQ0_MARK, PTC0_FN),
+
+        /* PTD FN */
+        PINMUX_DATA(SP0_MOSI_MARK, PTD7_FN),
+        PINMUX_DATA(SP0_MISO_MARK, PTD6_FN),
+        PINMUX_DATA(SP0_SCK_MARK, PTD5_FN),
+        PINMUX_DATA(SP0_SCK_FB_MARK, PTD4_FN),
+        PINMUX_DATA(SP0_SS0_MARK, PTD3_FN),
+        PINMUX_DATA(SP0_SS1_MARK, PS1_10_FN1, PTD2_FN),
+        PINMUX_DATA(DREQ0_MARK, PS1_10_FN2, PTD2_FN),
+        PINMUX_DATA(SP0_SS2_MARK, PS1_9_FN1, PTD1_FN),
+        PINMUX_DATA(DACK0_MARK, PS1_9_FN2, PTD1_FN),
+        PINMUX_DATA(SP0_SS3_MARK, PS1_8_FN1, PTD0_FN),
+        PINMUX_DATA(TEND0_MARK, PS1_8_FN2, PTD0_FN),
+
+        /* PTE FN */
+        PINMUX_DATA(RMII0_CRS_DV_MARK, PTE7_FN),
+        PINMUX_DATA(RMII0_TXD1_MARK, PTE6_FN),
+        PINMUX_DATA(RMII0_TXD0_MARK, PTE5_FN),
+        PINMUX_DATA(RMII0_TXEN_MARK, PTE4_FN),
+        PINMUX_DATA(RMII0_REFCLK_MARK, PTE3_FN),
+        PINMUX_DATA(RMII0_RXD1_MARK, PTE2_FN),
+        PINMUX_DATA(RMII0_RXD0_MARK, PTE1_FN),
+        PINMUX_DATA(RMII0_RX_ER_MARK, PTE0_FN),
+
+        /* PTF FN */
+        PINMUX_DATA(RMII1_CRS_DV_MARK, PTF7_FN),
+        PINMUX_DATA(RMII1_TXD1_MARK, PTF6_FN),
+        PINMUX_DATA(RMII1_TXD0_MARK, PTF5_FN),
+        PINMUX_DATA(RMII1_TXEN_MARK, PTF4_FN),
+        PINMUX_DATA(RMII1_REFCLK_MARK, PTF3_FN),
+        PINMUX_DATA(RMII1_RXD1_MARK, PS1_2_FN1, PTF2_FN),
+        PINMUX_DATA(RAC_RI_MARK, PS1_2_FN2, PTF2_FN),
+        PINMUX_DATA(RMII1_RXD0_MARK, PTF1_FN),
+        PINMUX_DATA(RMII1_RX_ER_MARK, PTF0_FN),
+
+        /* PTG FN */
+        PINMUX_DATA(BOOTFMS_MARK, PTG7_FN),
+        PINMUX_DATA(BOOTWP_MARK, PTG6_FN),
+        PINMUX_DATA(A25_MARK, PS2_13_FN1, PTG5_FN),
+        PINMUX_DATA(MMCCLK_MARK, PS2_13_FN2, PTG5_FN),
+        PINMUX_DATA(A24_MARK, PS2_12_FN1, PTG4_FN),
+        PINMUX_DATA(MMCCMD_MARK, PS2_12_FN2, PTG4_FN),
+        PINMUX_DATA(SERIRQ_MARK, PTG3_FN),
+        PINMUX_DATA(WDTOVF_MARK, PTG2_FN),
+        PINMUX_DATA(LPCPD_MARK, PTG1_FN),
+        PINMUX_DATA(LDRQ_MARK, PTG0_FN),
+
+        /* PTH FN */
+        PINMUX_DATA(SP1_MOSI_MARK, PS2_7_FN1, PTH7_FN),
+        PINMUX_DATA(TEND1_MARK, PS2_7_FN2, PTH7_FN),
+        PINMUX_DATA(SP1_MISO_MARK, PS2_6_FN1, PTH6_FN),
+        PINMUX_DATA(DREQ1_MARK, PS2_6_FN2, PTH6_FN),
+        PINMUX_DATA(SP1_SCK_MARK, PS2_5_FN1, PTH5_FN),
+        PINMUX_DATA(DACK1_MARK, PS2_5_FN2, PTH5_FN),
+        PINMUX_DATA(SP1_SCK_FB_MARK, PS2_4_FN1, PTH4_FN),
+        PINMUX_DATA(ADTRG1_MARK, PS2_4_FN2, PTH4_FN),
+        PINMUX_DATA(SP1_SS0_MARK, PTH3_FN),
+        PINMUX_DATA(SP1_SS1_MARK, PS2_2_FN1, PTH2_FN),
+        PINMUX_DATA(ADTRG0_MARK, PS2_2_FN2, PTH2_FN),
+        PINMUX_DATA(WP_MARK, PTH1_FN),
+        PINMUX_DATA(FMS0_MARK, PTH0_FN),
+
+        /* PTI FN */
+        PINMUX_DATA(D15_MARK, PS3_15_FN1, PTI7_FN),
+        PINMUX_DATA(SD_WP_MARK, PS3_15_FN2, PTI7_FN),
+        PINMUX_DATA(D14_MARK, PS3_14_FN1, PTI6_FN),
+        PINMUX_DATA(SD_CD_MARK, PS3_14_FN2, PTI6_FN),
+        PINMUX_DATA(D13_MARK, PS3_13_FN1, PTI5_FN),
+        PINMUX_DATA(SD_CLK_MARK, PS3_13_FN2, PTI5_FN),
+        PINMUX_DATA(D12_MARK, PS3_12_FN1, PTI4_FN),
+        PINMUX_DATA(SD_CMD_MARK, PS3_12_FN2, PTI4_FN),
+        PINMUX_DATA(D11_MARK, PS3_11_FN1, PTI3_FN),
+        PINMUX_DATA(SD_D3_MARK, PS3_11_FN2, PTI3_FN),
+        PINMUX_DATA(D10_MARK, PS3_10_FN1, PTI2_FN),
+        PINMUX_DATA(SD_D2_MARK, PS3_10_FN2, PTI2_FN),
+        PINMUX_DATA(D9_MARK, PS3_9_FN1, PTI1_FN),
+        PINMUX_DATA(SD_D1_MARK, PS3_9_FN2, PTI1_FN),
+        PINMUX_DATA(D8_MARK, PS3_8_FN1, PTI0_FN),
+        PINMUX_DATA(SD_D0_MARK, PS3_8_FN2, PTI0_FN),
+
+        /* PTJ FN */
+        PINMUX_DATA(RTS3_MARK, PTJ6_FN),
+        PINMUX_DATA(CTS3_MARK, PTJ5_FN),
+        PINMUX_DATA(TXD3_MARK, PTJ4_FN),
+        PINMUX_DATA(RXD3_MARK, PTJ3_FN),
+        PINMUX_DATA(RTS4_MARK, PTJ2_FN),
+        PINMUX_DATA(RXD4_MARK, PTJ1_FN),
+        PINMUX_DATA(TXD4_MARK, PTJ0_FN),
+
+        /* PTK FN */
+        PINMUX_DATA(COM2_TXD_MARK, PS3_7_FN1, PTK7_FN),
+        PINMUX_DATA(SCK2_MARK, PS3_7_FN2, PTK7_FN),
+        PINMUX_DATA(COM2_RXD_MARK, PTK6_FN),
+        PINMUX_DATA(COM2_RTS_MARK, PTK5_FN),
+        PINMUX_DATA(COM2_CTS_MARK, PTK4_FN),
+        PINMUX_DATA(COM2_DTR_MARK, PTK3_FN),
+        PINMUX_DATA(COM2_DSR_MARK, PS3_2_FN1, PTK2_FN),
+        PINMUX_DATA(SCK4_MARK, PS3_2_FN2, PTK2_FN),
+        PINMUX_DATA(COM2_DCD_MARK, PS3_1_FN1, PTK1_FN),
+        PINMUX_DATA(SCK3_MARK, PS3_1_FN2, PTK1_FN),
+        PINMUX_DATA(CLKOUT_MARK, PTK0_FN),
+
+        /* PTL FN */
+        PINMUX_DATA(RAC_RXD_MARK, PS4_14_FN1, PTL6_FN),
+        PINMUX_DATA(RXD2_MARK, PS4_14_FN2, PTL6_FN),
+        PINMUX_DATA(RAC_RTS_MARK, PS4_13_FN1, PTL5_FN),
+        PINMUX_DATA(CS5_MARK, PS4_13_FN2, PTL5_FN),
+        PINMUX_DATA(RAC_CTS_MARK, PS4_12_FN1, PTL4_FN),
+        PINMUX_DATA(CS6_MARK, PS4_12_FN2, PTL4_FN),
+        PINMUX_DATA(RAC_DTR_MARK, PTL3_FN),
+        PINMUX_DATA(RAC_DSR_MARK, PS4_10_FN1, PTL2_FN),
+        PINMUX_DATA(AUDSYNC_MARK, PS4_10_FN2, PTL2_FN),
+        PINMUX_DATA(RAC_DCD_MARK, PS4_9_FN1, PTL1_FN),
+        PINMUX_DATA(AUDCK_MARK, PS4_9_FN2, PTL1_FN),
+        PINMUX_DATA(RAC_TXD_MARK, PS4_8_FN1, PTL0_FN),
+        PINMUX_DATA(TXD2_MARK, PS4_8_FN1, PTL0_FN),
+
+        /* PTM FN */
+        PINMUX_DATA(CS4_MARK, PTM7_FN),
+        PINMUX_DATA(RD_MARK, PTM6_FN),
+        PINMUX_DATA(WE0_MARK, PTM7_FN),
+        PINMUX_DATA(CS0_MARK, PTM4_FN),
+        PINMUX_DATA(SDA6_MARK, PTM3_FN),
+        PINMUX_DATA(SCL6_MARK, PTM2_FN),
+        PINMUX_DATA(SDA7_MARK, PTM1_FN),
+        PINMUX_DATA(SCL7_MARK, PTM0_FN),
+
+        /* PTN FN */
+        PINMUX_DATA(VBUS_EN_MARK, PTN6_FN),
+        PINMUX_DATA(VBUS_OC_MARK, PTN5_FN),
+        PINMUX_DATA(JMCTCK_MARK, PS4_4_FN1, PTN4_FN),
+        PINMUX_DATA(SGPIO1_CLK_MARK, PS4_4_FN2, PTN4_FN),
+        PINMUX_DATA(JMCTMS_MARK, PS4_3_FN1, PTN5_FN),
+        PINMUX_DATA(SGPIO1_LOAD_MARK, PS4_3_FN2, PTN5_FN),
+        PINMUX_DATA(JMCTDO_MARK, PS4_2_FN1, PTN2_FN),
+        PINMUX_DATA(SGPIO1_DO_MARK, PS4_2_FN2, PTN2_FN),
+        PINMUX_DATA(JMCTDI_MARK, PS4_1_FN1, PTN1_FN),
+        PINMUX_DATA(SGPIO1_DI_MARK, PS4_1_FN2, PTN1_FN),
+        PINMUX_DATA(JMCTRST_MARK, PS4_0_FN1, PTN0_FN),
+        PINMUX_DATA(SUB_CLKIN_MARK, PS4_0_FN2, PTN0_FN),
+
+        /* PTO FN */
+        PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN),
+        PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN),
+        PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN),
+        PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN),
+        PINMUX_DATA(SGPIO2_CLK_MARK, PS5_11_FN1, PTO3_FN),
+        PINMUX_DATA(COM1_TXD_MARK, PS5_11_FN2, PTO3_FN),
+        PINMUX_DATA(SGPIO2_LOAD_MARK, PS5_10_FN1, PTO2_FN),
+        PINMUX_DATA(COM1_RXD_MARK, PS5_10_FN2, PTO2_FN),
+        PINMUX_DATA(SGPIO2_DI_MARK, PS5_9_FN1, PTO1_FN),
+        PINMUX_DATA(COM1_RTS_MARK, PS5_9_FN2, PTO1_FN),
+        PINMUX_DATA(SGPIO2_DO_MARK, PS5_8_FN1, PTO0_FN),
+        PINMUX_DATA(COM1_CTS_MARK, PS5_8_FN2, PTO0_FN),
+
+        /* PTP FN */
+
+        /* PTQ FN */
+        PINMUX_DATA(LAD3_MARK, PTQ6_FN),
+        PINMUX_DATA(LAD2_MARK, PTQ5_FN),
+        PINMUX_DATA(LAD1_MARK, PTQ4_FN),
+        PINMUX_DATA(LAD0_MARK, PTQ3_FN),
+        PINMUX_DATA(LFRAME_MARK, PTQ2_FN),
+        PINMUX_DATA(LRESET_MARK, PTQ1_FN),
+        PINMUX_DATA(LCLK_MARK, PTQ0_FN),
+
+        /* PTR FN */
+        PINMUX_DATA(SDA8_MARK, PTR7_FN),        /* DDC3? */
+        PINMUX_DATA(SCL8_MARK, PTR6_FN),        /* DDC2? */
+        PINMUX_DATA(SDA2_MARK, PTR5_FN),
+        PINMUX_DATA(SCL2_MARK, PTR4_FN),
+        PINMUX_DATA(SDA1_MARK, PTR3_FN),
+        PINMUX_DATA(SCL1_MARK, PTR2_FN),
+        PINMUX_DATA(SDA0_MARK, PTR1_FN),
+        PINMUX_DATA(SCL0_MARK, PTR0_FN),
+
+        /* PTS FN */
+        PINMUX_DATA(SDA9_MARK, PTS7_FN),        /* DDC1? */
+        PINMUX_DATA(SCL9_MARK, PTS6_FN),        /* DDC0? */
+        PINMUX_DATA(SDA5_MARK, PTS5_FN),
+        PINMUX_DATA(SCL5_MARK, PTS4_FN),
+        PINMUX_DATA(SDA4_MARK, PTS3_FN),
+        PINMUX_DATA(SCL4_MARK, PTS2_FN),
+        PINMUX_DATA(SDA3_MARK, PTS1_FN),
+        PINMUX_DATA(SCL3_MARK, PTS0_FN),
+
+        /* PTT FN */
+        PINMUX_DATA(PWMX7_MARK, PS5_7_FN1, PTT7_FN),
+        PINMUX_DATA(AUDATA3_MARK, PS5_7_FN2, PTT7_FN),
+        PINMUX_DATA(PWMX6_MARK, PS5_6_FN1, PTT6_FN),
+        PINMUX_DATA(AUDATA2_MARK, PS5_6_FN2, PTT6_FN),
+        PINMUX_DATA(PWMX5_MARK, PS5_5_FN1, PTT5_FN),
+        PINMUX_DATA(AUDATA1_MARK, PS5_5_FN2, PTT5_FN),
+        PINMUX_DATA(PWMX4_MARK, PS5_4_FN1, PTT4_FN),
+        PINMUX_DATA(AUDATA0_MARK, PS5_4_FN2, PTT4_FN),
+        PINMUX_DATA(PWMX3_MARK, PS5_3_FN1, PTT3_FN),
+        PINMUX_DATA(STATUS1_MARK, PS5_3_FN2, PTT3_FN),
+        PINMUX_DATA(PWMX2_MARK, PS5_2_FN1, PTT2_FN),
+        PINMUX_DATA(STATUS0_MARK, PS5_2_FN2, PTT2_FN),
+        PINMUX_DATA(PWMX1_MARK, PTT1_FN),
+        PINMUX_DATA(PWMX0_MARK, PTT0_FN),
+
+        /* PTU FN */
+        PINMUX_DATA(LGPIO7_MARK, PS6_15_FN1, PTU7_FN),
+        PINMUX_DATA(APMONCTL_O_MARK, PS6_15_FN2, PTU7_FN),
+        PINMUX_DATA(LGPIO6_MARK, PS6_14_FN1, PTU6_FN),
+        PINMUX_DATA(APMPWBTOUT_O_MARK, PS6_14_FN2, PTU6_FN),
+        PINMUX_DATA(LGPIO5_MARK, PS6_13_FN1, PTU5_FN),
+        PINMUX_DATA(APMSCI_O_MARK, PS6_13_FN2, PTU5_FN),
+        PINMUX_DATA(LGPIO4_MARK, PS6_12_FN1, PTU4_FN),
+        PINMUX_DATA(APMVDDON_MARK, PS6_12_FN2, PTU4_FN),
+        PINMUX_DATA(LGPIO3_MARK, PS6_11_FN1, PTU3_FN),
+        PINMUX_DATA(APMSLPBTN_MARK, PS6_11_FN2, PTU3_FN),
+        PINMUX_DATA(LGPIO2_MARK, PS6_10_FN1, PTU2_FN),
+        PINMUX_DATA(APMPWRBTN_MARK, PS6_10_FN2, PTU2_FN),
+        PINMUX_DATA(LGPIO1_MARK, PS6_9_FN1, PTU1_FN),
+        PINMUX_DATA(APMS5N_MARK, PS6_9_FN2, PTU1_FN),
+        PINMUX_DATA(LGPIO0_MARK, PS6_8_FN1, PTU0_FN),
+        PINMUX_DATA(APMS3N_MARK, PS6_8_FN2, PTU0_FN),
+
+        /* PTV FN */
+        PINMUX_DATA(A23_MARK, PS6_7_FN1, PTV7_FN),
+        PINMUX_DATA(COM2_RI_MARK, PS6_7_FN2, PTV7_FN),
+        PINMUX_DATA(A22_MARK, PS6_6_FN1, PTV6_FN),
+        PINMUX_DATA(R_SPI_MOSI_MARK, PS6_6_FN2, PTV6_FN),
+        PINMUX_DATA(A21_MARK, PS6_5_FN1, PTV5_FN),
+        PINMUX_DATA(R_SPI_MISO_MARK, PS6_5_FN2, PTV5_FN),
+        PINMUX_DATA(A20_MARK, PS6_4_FN1, PTV4_FN),
+        PINMUX_DATA(R_SPI_RSPCK_MARK, PS6_4_FN2, PTV4_FN),
+        PINMUX_DATA(A19_MARK, PS6_3_FN1, PTV3_FN),
+        PINMUX_DATA(R_SPI_SSL0_MARK, PS6_3_FN2, PTV3_FN),
+        PINMUX_DATA(A18_MARK, PS6_2_FN1, PTV2_FN),
+        PINMUX_DATA(R_SPI_SSL1_MARK, PS6_2_FN2, PTV2_FN),
+        PINMUX_DATA(A17_MARK, PS6_1_FN1, PTV1_FN),
+        PINMUX_DATA(EVENT7_MARK, PS6_1_FN2, PTV1_FN),
+        PINMUX_DATA(A16_MARK, PS6_0_FN1, PTV0_FN),
+        PINMUX_DATA(EVENT6_MARK, PS6_0_FN1, PTV0_FN),
+
+        /* PTW FN */
+        PINMUX_DATA(A15_MARK, PS7_15_FN1, PTW7_FN),
+        PINMUX_DATA(EVENT5_MARK, PS7_15_FN2, PTW7_FN),
+        PINMUX_DATA(A14_MARK, PS7_14_FN1, PTW6_FN),
+        PINMUX_DATA(EVENT4_MARK, PS7_14_FN2, PTW6_FN),
+        PINMUX_DATA(A13_MARK, PS7_13_FN1, PTW5_FN),
+        PINMUX_DATA(EVENT3_MARK, PS7_13_FN2, PTW5_FN),
+        PINMUX_DATA(A12_MARK, PS7_12_FN1, PTW4_FN),
+        PINMUX_DATA(EVENT2_MARK, PS7_12_FN2, PTW4_FN),
+        PINMUX_DATA(A11_MARK, PS7_11_FN1, PTW3_FN),
+        PINMUX_DATA(EVENT1_MARK, PS7_11_FN2, PTW3_FN),
+        PINMUX_DATA(A10_MARK, PS7_10_FN1, PTW2_FN),
+        PINMUX_DATA(EVENT0_MARK, PS7_10_FN2, PTW2_FN),
+        PINMUX_DATA(A9_MARK, PS7_9_FN1, PTW1_FN),
+        PINMUX_DATA(CTS4_MARK, PS7_9_FN2, PTW1_FN),
+        PINMUX_DATA(A8_MARK, PS7_8_FN1, PTW0_FN),
+        PINMUX_DATA(CTS2_MARK, PS7_8_FN2, PTW0_FN),
+
+        /* PTX FN */
+        PINMUX_DATA(A7_MARK, PS7_7_FN1, PTX7_FN),
+        PINMUX_DATA(RTS2_MARK, PS7_7_FN2, PTX7_FN),
+        PINMUX_DATA(A6_MARK, PS7_6_FN1, PTX6_FN),
+        PINMUX_DATA(SIM_D_MARK, PS7_6_FN2, PTX6_FN),
+        PINMUX_DATA(A5_MARK, PS7_5_FN1, PTX5_FN),
+        PINMUX_DATA(SIM_CLK_MARK, PS7_5_FN2, PTX5_FN),
+        PINMUX_DATA(A4_MARK, PS7_4_FN1, PTX4_FN),
+        PINMUX_DATA(SIM_RST_MARK, PS7_4_FN2, PTX4_FN),
+        PINMUX_DATA(A3_MARK, PTX3_FN),
+        PINMUX_DATA(A2_MARK, PTX2_FN),
+        PINMUX_DATA(A1_MARK, PTX1_FN),
+        PINMUX_DATA(A0_MARK, PTX0_FN),
+
+        /* PTY FN */
+        PINMUX_DATA(D7_MARK, PTY7_FN),
+        PINMUX_DATA(D6_MARK, PTY6_FN),
+        PINMUX_DATA(D5_MARK, PTY5_FN),
+        PINMUX_DATA(D4_MARK, PTY4_FN),
+        PINMUX_DATA(D3_MARK, PTY3_FN),
+        PINMUX_DATA(D2_MARK, PTY2_FN),
+        PINMUX_DATA(D1_MARK, PTY1_FN),
+        PINMUX_DATA(D0_MARK, PTY0_FN),
+
+        /* PTZ FN */
+        PINMUX_DATA(MMCDAT7_MARK, PS8_15_FN1, PTZ7_FN),
+        PINMUX_DATA(ON_DQ7_MARK, PS8_15_FN2, PTZ7_FN),
+        PINMUX_DATA(MMCDAT6_MARK, PS8_14_FN1, PTZ6_FN),
+        PINMUX_DATA(ON_DQ6_MARK, PS8_14_FN2, PTZ6_FN),
+        PINMUX_DATA(MMCDAT5_MARK, PS8_13_FN1, PTZ5_FN),
+        PINMUX_DATA(ON_DQ5_MARK, PS8_13_FN2, PTZ5_FN),
+        PINMUX_DATA(MMCDAT4_MARK, PS8_12_FN1, PTZ4_FN),
+        PINMUX_DATA(ON_DQ4_MARK, PS8_12_FN2, PTZ4_FN),
+        PINMUX_DATA(MMCDAT3_MARK, PS8_11_FN1, PTZ3_FN),
+        PINMUX_DATA(ON_DQ3_MARK, PS8_11_FN2, PTZ3_FN),
+        PINMUX_DATA(MMCDAT2_MARK, PS8_10_FN1, PTZ2_FN),
+        PINMUX_DATA(ON_DQ2_MARK, PS8_10_FN2, PTZ2_FN),
+        PINMUX_DATA(MMCDAT1_MARK, PS8_9_FN1, PTZ1_FN),
+        PINMUX_DATA(ON_DQ1_MARK, PS8_9_FN2, PTZ1_FN),
+        PINMUX_DATA(MMCDAT0_MARK, PS8_8_FN1, PTZ0_FN),
+        PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+        /* PTA */
+        PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
+        PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
+        PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
+        PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
+        PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
+        PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
+        PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
+        PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
+
+        /* PTB */
+        PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
+        PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
+        PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
+        PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
+        PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
+        PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
+        PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
+        PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
+
+        /* PTC */
+        PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
+        PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
+        PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
+        PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
+        PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
+        PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
+        PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
+        PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
+
+        /* PTD */
+        PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
+        PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
+        PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
+        PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
+        PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
+        PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
+        PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
+        PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
+
+        /* PTE */
+        PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
+        PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
+        PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
+        PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
+        PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
+        PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
+        PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
+        PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
+
+        /* PTF */
+        PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
+        PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
+        PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
+        PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
+        PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
+        PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
+        PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
+        PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
+
+        /* PTG */
+        PINMUX_GPIO(GPIO_PTG7, PTG7_DATA),
+        PINMUX_GPIO(GPIO_PTG6, PTG6_DATA),
+        PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
+        PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
+        PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
+        PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
+        PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
+        PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
+
+        /* PTH */
+        PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
+        PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
+        PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
+        PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
+        PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
+        PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
+        PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
+        PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
+
+        /* PTI */
+        PINMUX_GPIO(GPIO_PTI7, PTI7_DATA),
+        PINMUX_GPIO(GPIO_PTI6, PTI6_DATA),
+        PINMUX_GPIO(GPIO_PTI5, PTI5_DATA),
+        PINMUX_GPIO(GPIO_PTI4, PTI4_DATA),
+        PINMUX_GPIO(GPIO_PTI3, PTI3_DATA),
+        PINMUX_GPIO(GPIO_PTI2, PTI2_DATA),
+        PINMUX_GPIO(GPIO_PTI1, PTI1_DATA),
+        PINMUX_GPIO(GPIO_PTI0, PTI0_DATA),
+
+        /* PTJ */
+        PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
+        PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
+        PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA),
+        PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
+        PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
+        PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
+        PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
+
+        /* PTK */
+        PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
+        PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
+        PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
+        PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
+        PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
+        PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
+        PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
+        PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
+
+        /* PTL */
+        PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
+        PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
+        PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
+        PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
+        PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
+        PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
+        PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
+
+        /* PTM */
+        PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
+        PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
+        PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
+        PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
+        PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
+        PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
+        PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
+        PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
+
+        /* PTN */
+        PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
+        PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
+        PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
+        PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
+        PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
+        PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
+        PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
+
+        /* PTO */
+        PINMUX_GPIO(GPIO_PTO7, PTO7_DATA),
+        PINMUX_GPIO(GPIO_PTO6, PTO6_DATA),
+        PINMUX_GPIO(GPIO_PTO5, PTO5_DATA),
+        PINMUX_GPIO(GPIO_PTO4, PTO4_DATA),
+        PINMUX_GPIO(GPIO_PTO3, PTO3_DATA),
+        PINMUX_GPIO(GPIO_PTO2, PTO2_DATA),
+        PINMUX_GPIO(GPIO_PTO1, PTO1_DATA),
+        PINMUX_GPIO(GPIO_PTO0, PTO0_DATA),
+
+        /* PTP */
+        PINMUX_GPIO(GPIO_PTP7, PTP7_DATA),
+        PINMUX_GPIO(GPIO_PTP6, PTP6_DATA),
+        PINMUX_GPIO(GPIO_PTP5, PTP5_DATA),
+        PINMUX_GPIO(GPIO_PTP4, PTP4_DATA),
+        PINMUX_GPIO(GPIO_PTP3, PTP3_DATA),
+        PINMUX_GPIO(GPIO_PTP2, PTP2_DATA),
+        PINMUX_GPIO(GPIO_PTP1, PTP1_DATA),
+        PINMUX_GPIO(GPIO_PTP0, PTP0_DATA),
+
+        /* PTQ */
+        PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
+        PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
+        PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
+        PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
+        PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
+        PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
+        PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
+
+        /* PTR */
+        PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
+        PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
+        PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
+        PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
+        PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
+        PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
+        PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
+        PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
+
+        /* PTS */
+        PINMUX_GPIO(GPIO_PTS7, PTS7_DATA),
+        PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
+        PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
+        PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
+        PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
+        PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
+        PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
+        PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
+
+        /* PTT */
+        PINMUX_GPIO(GPIO_PTT7, PTT7_DATA),
+        PINMUX_GPIO(GPIO_PTT6, PTT6_DATA),
+        PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
+        PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
+        PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
+        PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
+        PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
+        PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
+
+        /* PTU */
+        PINMUX_GPIO(GPIO_PTU7, PTU7_DATA),
+        PINMUX_GPIO(GPIO_PTU6, PTU6_DATA),
+        PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
+        PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
+        PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
+        PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
+        PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
+        PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
+
+        /* PTV */
+        PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
+        PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
+        PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
+        PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
+        PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
+        PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
+        PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
+        PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
+
+        /* PTW */
+        PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
+        PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
+        PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
+        PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
+        PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
+        PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
+        PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
+        PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
+
+        /* PTX */
+        PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
+        PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
+        PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
+        PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
+        PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
+        PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
+        PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
+        PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
+
+        /* PTY */
+        PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
+        PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
+        PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
+        PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
+        PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
+        PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
+        PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
+        PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
+
+        /* PTZ */
+        PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
+        PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
+        PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
+        PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
+        PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
+        PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
+        PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
+        PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
+
+        /* PTA (mobule: LBSC, RGMII) */
+        PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
+        PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
+        PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK),
+        PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK),
+        PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK),
+        PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDC_MARK),
+        PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK),
+        PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDC_MARK),
+
+        /* PTB (mobule: INTC, ONFI, TMU) */
+        PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
+
+        /* PTC (mobule: IRQ, PWMU) */
+        PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK),
+
+        /* PTD (mobule: SPI0, DMAC) */
+        PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
+        PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
+
+        /* PTE (mobule: RMII) */
+        PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK),
+
+        /* PTF (mobule: RMII, SerMux) */
+        PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK),
+
+        /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
+        PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK),
+        PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK),
+        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
+        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
+        PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK),
+        PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
+        PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK),
+        PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK),
+
+        /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
+        PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK),
+        PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK),
+        PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK),
+        PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK),
+        PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_WP, WP_MARK),
+        PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK),
+        PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
+        PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK),
+        PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK),
+
+        /* PTI (mobule: LBSC, SDHI) */
+        PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
+        PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
+        PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
+        PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
+        PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
+        PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
+        PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
+        PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK),
+
+        /* PTJ (mobule: SCIF234, SERMUX) */
+        PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
+        PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
+
+        /* PTK (mobule: SERMUX, LBSC, SCIF) */
+        PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_CTS, COM2_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK),
+        PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
+
+        /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
+        PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
+
+        /* PTM (mobule: LBSC, IIC) */
+        PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
+        PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
+        PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK),
+        PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK),
+
+        /* PTN (mobule: USB, JMC, SGPIO, WDT) */
+        PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK),
+        PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK),
+        PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK),
+
+        /* PTO (mobule: SGPIO, SerMux) */
+        PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK),
+        PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK),
+
+        /* PTP (mobule: EVC, ADC) */
+
+        /* PTQ (mobule: LPC) */
+        PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK),
+        PINMUX_GPIO(GPIO_FN_LAD2, LAD2_MARK),
+        PINMUX_GPIO(GPIO_FN_LAD1, LAD1_MARK),
+        PINMUX_GPIO(GPIO_FN_LAD0, LAD0_MARK),
+        PINMUX_GPIO(GPIO_FN_LFRAME, LFRAME_MARK),
+        PINMUX_GPIO(GPIO_FN_LRESET, LRESET_MARK),
+        PINMUX_GPIO(GPIO_FN_LCLK, LCLK_MARK),
+
+        /* PTR (mobule: GRA, IIC) */
+        PINMUX_GPIO(GPIO_FN_DDC3, DDC3_MARK),
+        PINMUX_GPIO(GPIO_FN_DDC2, DDC2_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA8, SDA8_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL8, SCL8_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
+
+        /* PTS (mobule: GRA, IIC) */
+        PINMUX_GPIO(GPIO_FN_DDC1, DDC1_MARK),
+        PINMUX_GPIO(GPIO_FN_DDC0, DDC0_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA9, SDA9_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL9, SCL9_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA5, SDA5_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL5, SCL5_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA4, SDA4_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL4, SCL4_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
+
+        /* PTT (mobule: PWMX, AUD) */
+        PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
+
+        /* PTU (mobule: LPC, APM) */
+        PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK),
+        PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK),
+        PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK),
+        PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK),
+        PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK),
+        PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK),
+        PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK),
+        PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK),
+        PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK),
+
+        /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
+        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
+        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
+        PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
+        PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
+        PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
+        PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
+        PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
+        PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK),
+        PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK),
+        PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK),
+        PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK),
+        PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK),
+        PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK),
+        PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK),
+        PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK),
+        PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK),
+
+        /* PTW (mobule: LBSC, EVC, SCIF) */
+        PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
+        PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
+        PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
+        PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
+        PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
+        PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
+        PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
+        PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
+        PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK),
+        PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK),
+        PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK),
+
+        /* PTX (mobule: LBSC) */
+        PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
+        PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
+        PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
+        PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
+        PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
+        PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
+        PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
+        PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
+        PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK),
+        PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
+        PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
+
+        /* PTY (mobule: LBSC) */
+        PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
+        PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
+        PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
+        PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
+        PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
+        PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
+        PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
+        PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
+
+        /* PTZ (mobule: eMMC, ONFI) */
+        PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK),
+ };
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
+                PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU,
+                PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU,
+                PTA5_FN, PTA5_OUT, PTA5_IN, PTA5_IN_PU,
+                PTA4_FN, PTA4_OUT, PTA4_IN, PTA4_IN_PU,
+                PTA3_FN, PTA3_OUT, PTA3_IN, PTA3_IN_PU,
+                PTA2_FN, PTA2_OUT, PTA2_IN, PTA2_IN_PU,
+                PTA1_FN, PTA1_OUT, PTA1_IN, PTA1_IN_PU,
+                PTA0_FN, PTA0_OUT, PTA0_IN, PTA0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) {
+                PTB7_FN, PTB7_OUT, PTB7_IN, 0,
+                PTB6_FN, PTB6_OUT, PTB6_IN, 0,
+                PTB5_FN, PTB5_OUT, PTB5_IN, 0,
+                PTB4_FN, PTB4_OUT, PTB4_IN, 0,
+                PTB3_FN, PTB3_OUT, PTB3_IN, 0,
+                PTB2_FN, PTB2_OUT, PTB2_IN, 0,
+                PTB1_FN, PTB1_OUT, PTB1_IN, 0,
+                PTB0_FN, PTB0_OUT, PTB0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PCCR", 0xffec0004, 16, 2) {
+                PTC7_FN, PTC7_OUT, PTC7_IN, 0,
+                PTC6_FN, PTC6_OUT, PTC6_IN, 0,
+                PTC5_FN, PTC5_OUT, PTC5_IN, 0,
+                PTC4_FN, PTC4_OUT, PTC4_IN, 0,
+                PTC3_FN, PTC3_OUT, PTC3_IN, 0,
+                PTC2_FN, PTC2_OUT, PTC2_IN, 0,
+                PTC1_FN, PTC1_OUT, PTC1_IN, 0,
+                PTC0_FN, PTC0_OUT, PTC0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) {
+                PTD7_FN, PTD7_OUT, PTD7_IN, PTD7_IN_PU,
+                PTD6_FN, PTD6_OUT, PTD6_IN, PTD6_IN_PU,
+                PTD5_FN, PTD5_OUT, PTD5_IN, PTD5_IN_PU,
+                PTD4_FN, PTD4_OUT, PTD4_IN, PTD4_IN_PU,
+                PTD3_FN, PTD3_OUT, PTD3_IN, PTD3_IN_PU,
+                PTD2_FN, PTD2_OUT, PTD2_IN, PTD2_IN_PU,
+                PTD1_FN, PTD1_OUT, PTD1_IN, PTD1_IN_PU,
+                PTD0_FN, PTD0_OUT, PTD0_IN, PTD0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) {
+                PTE7_FN, PTE7_OUT, PTE7_IN, PTE7_IN_PU,
+                PTE6_FN, PTE6_OUT, PTE6_IN, PTE6_IN_PU,
+                PTE5_FN, PTE5_OUT, PTE5_IN, PTE5_IN_PU,
+                PTE4_FN, PTE4_OUT, PTE4_IN, PTE4_IN_PU,
+                PTE3_FN, PTE3_OUT, PTE3_IN, PTE3_IN_PU,
+                PTE2_FN, PTE2_OUT, PTE2_IN, PTE2_IN_PU,
+                PTE1_FN, PTE1_OUT, PTE1_IN, PTE1_IN_PU,
+                PTE0_FN, PTE0_OUT, PTE0_IN, PTE0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) {
+                PTF7_FN, PTF7_OUT, PTF7_IN, PTF7_IN_PU,
+                PTF6_FN, PTF6_OUT, PTF6_IN, PTF6_IN_PU,
+                PTF5_FN, PTF5_OUT, PTF5_IN, PTF5_IN_PU,
+                PTF4_FN, PTF4_OUT, PTF4_IN, PTF4_IN_PU,
+                PTF3_FN, PTF3_OUT, PTF3_IN, PTF3_IN_PU,
+                PTF2_FN, PTF2_OUT, PTF2_IN, PTF2_IN_PU,
+                PTF1_FN, PTF1_OUT, PTF1_IN, PTF1_IN_PU,
+                PTF0_FN, PTF0_OUT, PTF0_IN, PTF0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) {
+                PTG7_FN, PTG7_OUT, PTG7_IN, PTG7_IN_PU ,
+                PTG6_FN, PTG6_OUT, PTG6_IN, PTG6_IN_PU ,
+                PTG5_FN, PTG5_OUT, PTG5_IN, 0,
+                PTG4_FN, PTG4_OUT, PTG4_IN, PTG4_IN_PU ,
+                PTG3_FN, PTG3_OUT, PTG3_IN, 0,
+                PTG2_FN, PTG2_OUT, PTG2_IN, 0,
+                PTG1_FN, PTG1_OUT, PTG1_IN, 0,
+                PTG0_FN, PTG0_OUT, PTG0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) {
+                PTH7_FN, PTH7_OUT, PTH7_IN, PTH7_IN_PU,
+                PTH6_FN, PTH6_OUT, PTH6_IN, PTH6_IN_PU,
+                PTH5_FN, PTH5_OUT, PTH5_IN, PTH5_IN_PU,
+                PTH4_FN, PTH4_OUT, PTH4_IN, PTH4_IN_PU,
+                PTH3_FN, PTH3_OUT, PTH3_IN, PTH3_IN_PU,
+                PTH2_FN, PTH2_OUT, PTH2_IN, PTH2_IN_PU,
+                PTH1_FN, PTH1_OUT, PTH1_IN, PTH1_IN_PU,
+                PTH0_FN, PTH0_OUT, PTH0_IN, PTH0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) {
+                PTI7_FN, PTI7_OUT, PTI7_IN, PTI7_IN_PU,
+                PTI6_FN, PTI6_OUT, PTI6_IN, PTI6_IN_PU,
+                PTI5_FN, PTI5_OUT, PTI5_IN, 0,
+                PTI4_FN, PTI4_OUT, PTI4_IN, PTI4_IN_PU,
+                PTI3_FN, PTI3_OUT, PTI3_IN, PTI3_IN_PU,
+                PTI2_FN, PTI2_OUT, PTI2_IN, PTI2_IN_PU,
+                PTI1_FN, PTI1_OUT, PTI1_IN, PTI1_IN_PU,
+                PTI0_FN, PTI0_OUT, PTI0_IN, PTI0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) {
+                0, 0, 0, 0,     /* reserved: always set 1 */
+                PTJ6_FN, PTJ6_OUT, PTJ6_IN, PTJ6_IN_PU,
+                PTJ5_FN, PTJ5_OUT, PTJ5_IN, PTJ5_IN_PU,
+                PTJ4_FN, PTJ4_OUT, PTJ4_IN, PTJ4_IN_PU,
+                PTJ3_FN, PTJ3_OUT, PTJ3_IN, PTJ3_IN_PU,
+                PTJ2_FN, PTJ2_OUT, PTJ2_IN, PTJ2_IN_PU,
+                PTJ1_FN, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU,
+                PTJ0_FN, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) {
+                PTK7_FN, PTK7_OUT, PTK7_IN, PTK7_IN_PU,
+                PTK6_FN, PTK6_OUT, PTK6_IN, PTK6_IN_PU,
+                PTK5_FN, PTK5_OUT, PTK5_IN, PTK5_IN_PU,
+                PTK4_FN, PTK4_OUT, PTK4_IN, PTK4_IN_PU,
+                PTK3_FN, PTK3_OUT, PTK3_IN, PTK3_IN_PU,
+                PTK2_FN, PTK2_OUT, PTK2_IN, PTK2_IN_PU,
+                PTK1_FN, PTK1_OUT, PTK1_IN, PTK1_IN_PU,
+                PTK0_FN, PTK0_OUT, PTK0_IN, PTK0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) {
+                0, 0, 0, 0,     /* reserved: always set 1 */
+                PTL6_FN, PTL6_OUT, PTL6_IN, PTL6_IN_PU,
+                PTL5_FN, PTL5_OUT, PTL5_IN, PTL5_IN_PU,
+                PTL4_FN, PTL4_OUT, PTL4_IN, PTL4_IN_PU,
+                PTL3_FN, PTL3_OUT, PTL3_IN, PTL3_IN_PU,
+                PTL2_FN, PTL2_OUT, PTL2_IN, PTL2_IN_PU,
+                PTL1_FN, PTL1_OUT, PTL1_IN, PTL1_IN_PU,
+                PTL0_FN, PTL0_OUT, PTL0_IN, PTL0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) {
+                PTM7_FN, PTM7_OUT, PTM7_IN, PTM7_IN_PU,
+                PTM6_FN, PTM6_OUT, PTM6_IN, PTM6_IN_PU,
+                PTM5_FN, PTM5_OUT, PTM5_IN, PTM5_IN_PU,
+                PTM4_FN, PTM4_OUT, PTM4_IN, PTM4_IN_PU,
+                PTM3_FN, PTM3_OUT, PTM3_IN, 0,
+                PTM2_FN, PTM2_OUT, PTM2_IN, 0,
+                PTM1_FN, PTM1_OUT, PTM1_IN, 0,
+                PTM0_FN, PTM0_OUT, PTM0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) {
+                0, 0, 0, 0,     /* reserved: always set 1 */
+                PTN6_FN, PTN6_OUT, PTN6_IN, 0,
+                PTN5_FN, PTN5_OUT, PTN5_IN, 0,
+                PTN4_FN, PTN4_OUT, PTN4_IN, PTN4_IN_PU,
+                PTN3_FN, PTN3_OUT, PTN3_IN, PTN3_IN_PU,
+                PTN2_FN, PTN2_OUT, PTN2_IN, PTN2_IN_PU,
+                PTN1_FN, PTN1_OUT, PTN1_IN, PTN1_IN_PU,
+                PTN0_FN, PTN0_OUT, PTN0_IN, PTN0_IN_PU }
+        },
+        { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) {
+                PTO7_FN, PTO7_OUT, PTO7_IN, PTO7_IN_PU,
+                PTO6_FN, PTO6_OUT, PTO6_IN, PTO6_IN_PU,
+                PTO5_FN, PTO5_OUT, PTO5_IN, PTO5_IN_PU,
+                PTO4_FN, PTO4_OUT, PTO4_IN, PTO4_IN_PU,
+                PTO3_FN, PTO3_OUT, PTO3_IN, PTO3_IN_PU,
+                PTO2_FN, PTO2_OUT, PTO2_IN, PTO2_IN_PU,
+                PTO1_FN, PTO1_OUT, PTO1_IN, PTO1_IN_PU,
+                PTO0_FN, PTO0_OUT, PTO0_IN, PTO0_IN_PU }
+        },
+#if 0   /* FIXME: Remove it? */
+        { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) {
+                0, 0, 0, 0,     /* reserved: always set 1 */
+                PTP6_FN, PTP6_OUT, PTP6_IN, 0,
+                PTP5_FN, PTP5_OUT, PTP5_IN, 0,
+                PTP4_FN, PTP4_OUT, PTP4_IN, 0,
+                PTP3_FN, PTP3_OUT, PTP3_IN, 0,
+                PTP2_FN, PTP2_OUT, PTP2_IN, 0,
+                PTP1_FN, PTP1_OUT, PTP1_IN, 0,
+                PTP0_FN, PTP0_OUT, PTP0_IN, 0 }
+        },
+#endif
+        { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) {
+                0, 0, 0, 0,     /* reserved: always set 1 */
+                PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0,
+                PTQ5_FN, PTQ5_OUT, PTQ5_IN, 0,
+                PTQ4_FN, PTQ4_OUT, PTQ4_IN, 0,
+                PTQ3_FN, PTQ3_OUT, PTQ3_IN, 0,
+                PTQ2_FN, PTQ2_OUT, PTQ2_IN, 0,
+                PTQ1_FN, PTQ1_OUT, PTQ1_IN, 0,
+                PTQ0_FN, PTQ0_OUT, PTQ0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PRCR", 0xffec0022, 16, 2) {
+                PTR7_FN, PTR7_OUT, PTR7_IN, 0,
+                PTR6_FN, PTR6_OUT, PTR6_IN, 0,
+                PTR5_FN, PTR5_OUT, PTR5_IN, 0,
+                PTR4_FN, PTR4_OUT, PTR4_IN, 0,
+                PTR3_FN, PTR3_OUT, PTR3_IN, 0,
+                PTR2_FN, PTR2_OUT, PTR2_IN, 0,
+                PTR1_FN, PTR1_OUT, PTR1_IN, 0,
+                PTR0_FN, PTR0_OUT, PTR0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PSCR", 0xffec0024, 16, 2) {
+                PTS7_FN, PTS7_OUT, PTS7_IN, 0,
+                PTS6_FN, PTS6_OUT, PTS6_IN, 0,
+                PTS5_FN, PTS5_OUT, PTS5_IN, 0,
+                PTS4_FN, PTS4_OUT, PTS4_IN, 0,
+                PTS3_FN, PTS3_OUT, PTS3_IN, 0,
+                PTS2_FN, PTS2_OUT, PTS2_IN, 0,
+                PTS1_FN, PTS1_OUT, PTS1_IN, 0,
+                PTS0_FN, PTS0_OUT, PTS0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) {
+                PTT7_FN, PTT7_OUT, PTT7_IN, PTO7_IN_PU,
+                PTT6_FN, PTT6_OUT, PTT6_IN, PTO6_IN_PU,
+                PTT5_FN, PTT5_OUT, PTT5_IN, PTO5_IN_PU,
+                PTT4_FN, PTT4_OUT, PTT4_IN, PTO4_IN_PU,
+                PTT3_FN, PTT3_OUT, PTT3_IN, PTO3_IN_PU,
+                PTT2_FN, PTT2_OUT, PTT2_IN, PTO2_IN_PU,
+                PTT1_FN, PTT1_OUT, PTT1_IN, PTO1_IN_PU,
+                PTT0_FN, PTT0_OUT, PTT0_IN, PTO0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) {
+                PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU,
+                PTU6_FN, PTU6_OUT, PTU6_IN, PTU6_IN_PU,
+                PTU5_FN, PTU5_OUT, PTU5_IN, PTU5_IN_PU,
+                PTU4_FN, PTU4_OUT, PTU4_IN, PTU4_IN_PU,
+                PTU3_FN, PTU3_OUT, PTU3_IN, PTU3_IN_PU,
+                PTU2_FN, PTU2_OUT, PTU2_IN, PTU2_IN_PU,
+                PTU1_FN, PTU1_OUT, PTU1_IN, PTU1_IN_PU,
+                PTU0_FN, PTU0_OUT, PTU0_IN, PTU0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2) {
+                PTV7_FN, PTV7_OUT, PTV7_IN, PTV7_IN_PU,
+                PTV6_FN, PTV6_OUT, PTV6_IN, PTV6_IN_PU,
+                PTV5_FN, PTV5_OUT, PTV5_IN, PTV5_IN_PU,
+                PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU,
+                PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU,
+                PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU,
+                PTV1_FN, PTV1_OUT, PTV1_IN, 0,
+                PTV0_FN, PTV0_OUT, PTV0_IN, 0 }
+        },
+        { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) {
+                PTW7_FN, PTW7_OUT, PTW7_IN, 0,
+                PTW6_FN, PTW6_OUT, PTW6_IN, 0,
+                PTW5_FN, PTW5_OUT, PTW5_IN, 0,
+                PTW4_FN, PTW4_OUT, PTW4_IN, 0,
+                PTW3_FN, PTW3_OUT, PTW3_IN, 0,
+                PTW2_FN, PTW2_OUT, PTW2_IN, 0,
+                PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU,
+                PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2) {
+                PTX7_FN, PTX7_OUT, PTX7_IN, PTX7_IN_PU,
+                PTX6_FN, PTX6_OUT, PTX6_IN, PTX6_IN_PU,
+                PTX5_FN, PTX5_OUT, PTX5_IN, PTX5_IN_PU,
+                PTX4_FN, PTX4_OUT, PTX4_IN, PTX4_IN_PU,
+                PTX3_FN, PTX3_OUT, PTX3_IN, PTX3_IN_PU,
+                PTX2_FN, PTX2_OUT, PTX2_IN, PTX2_IN_PU,
+                PTX1_FN, PTX1_OUT, PTX1_IN, PTX1_IN_PU,
+                PTX0_FN, PTX0_OUT, PTX0_IN, PTX0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2) {
+                PTY7_FN, PTY7_OUT, PTY7_IN, PTY7_IN_PU,
+                PTY6_FN, PTY6_OUT, PTY6_IN, PTY6_IN_PU,
+                PTY5_FN, PTY5_OUT, PTY5_IN, PTY5_IN_PU,
+                PTY4_FN, PTY4_OUT, PTY4_IN, PTY4_IN_PU,
+                PTY3_FN, PTY3_OUT, PTY3_IN, PTY3_IN_PU,
+                PTY2_FN, PTY2_OUT, PTY2_IN, PTY2_IN_PU,
+                PTY1_FN, PTY1_OUT, PTY1_IN, PTY1_IN_PU,
+                PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU }
+        },
+        { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) {
+                PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0,
+                PTZ6_FN, PTZ6_OUT, PTZ6_IN, 0,
+                PTZ5_FN, PTZ5_OUT, PTZ5_IN, 0,
+                PTZ4_FN, PTZ4_OUT, PTZ4_IN, 0,
+                PTZ3_FN, PTZ3_OUT, PTZ3_IN, 0,
+                PTZ2_FN, PTZ2_OUT, PTZ2_IN, 0,
+                PTZ1_FN, PTZ1_OUT, PTZ1_IN, 0,
+                PTZ0_FN, PTZ0_OUT, PTZ0_IN, 0 }
+        },
+
+        { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) {
+                PS0_15_FN1, PS0_15_FN2,
+                PS0_14_FN1, PS0_14_FN2,
+                PS0_13_FN1, PS0_13_FN2,
+                PS0_12_FN1, PS0_12_FN2,
+                PS0_11_FN1, PS0_11_FN2,
+                PS0_10_FN1, PS0_10_FN2,
+                PS0_9_FN1, PS0_9_FN2,
+                PS0_8_FN1, PS0_8_FN2,
+                PS0_7_FN1, PS0_7_FN2,
+                PS0_6_FN1, PS0_6_FN2,
+                PS0_5_FN1, PS0_5_FN2,
+                PS0_4_FN1, PS0_4_FN2,
+                PS0_3_FN1, PS0_3_FN2,
+                PS0_2_FN1, PS0_2_FN2,
+                0, 0,
+                0, 0, }
+        },
+        { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PS1_10_FN1, PS1_10_FN2,
+                PS1_9_FN1, PS1_9_FN2,
+                PS1_8_FN1, PS1_8_FN2,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PS1_2_FN1, PS1_2_FN2,
+                0, 0,
+                0, 0, }
+        },
+        { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) {
+                0, 0,
+                0, 0,
+                PS2_13_FN1, PS2_13_FN2,
+                PS2_12_FN1, PS2_12_FN2,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PS2_7_FN1, PS2_7_FN2,
+                PS2_6_FN1, PS2_6_FN2,
+                PS2_5_FN1, PS2_5_FN2,
+                PS2_4_FN1, PS2_4_FN2,
+                0, 0,
+                PS2_2_FN1, PS2_2_FN2,
+                0, 0,
+                0, 0, }
+        },
+        { PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1) {
+                PS3_15_FN1, PS3_15_FN2,
+                PS3_14_FN1, PS3_14_FN2,
+                PS3_13_FN1, PS3_13_FN2,
+                PS3_12_FN1, PS3_12_FN2,
+                PS3_11_FN1, PS3_11_FN2,
+                PS3_10_FN1, PS3_10_FN2,
+                PS3_9_FN1, PS3_9_FN2,
+                PS3_8_FN1, PS3_8_FN2,
+                PS3_7_FN1, PS3_7_FN2,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PS3_2_FN1, PS3_2_FN2,
+                PS3_1_FN1, PS3_1_FN2,
+                0, 0, }
+        },
+
+        { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) {
+                0, 0,
+                PS4_14_FN1, PS4_14_FN2,
+                PS4_13_FN1, PS4_13_FN2,
+                PS4_12_FN1, PS4_12_FN2,
+                0, 0,
+                PS4_10_FN1, PS4_10_FN2,
+                PS4_9_FN1, PS4_9_FN2,
+                PS4_8_FN1, PS4_8_FN2,
+                0, 0,
+                0, 0,
+                0, 0,
+                PS4_4_FN1, PS4_4_FN2,
+                PS4_3_FN1, PS4_3_FN2,
+                PS4_2_FN1, PS4_2_FN2,
+                PS4_1_FN1, PS4_1_FN2,
+                PS4_0_FN1, PS4_0_FN2, }
+        },
+        { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                PS5_11_FN1, PS5_11_FN2,
+                PS5_10_FN1, PS5_10_FN2,
+                PS5_9_FN1, PS5_9_FN2,
+                PS5_8_FN1, PS5_8_FN2,
+                PS5_7_FN1, PS5_7_FN2,
+                PS5_6_FN1, PS5_6_FN2,
+                PS5_5_FN1, PS5_5_FN2,
+                PS5_4_FN1, PS5_4_FN2,
+                PS5_3_FN1, PS5_3_FN2,
+                PS5_2_FN1, PS5_2_FN2,
+                0, 0,
+                0, 0, }
+        },
+        { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) {
+                PS6_15_FN1, PS6_15_FN2,
+                PS6_14_FN1, PS6_14_FN2,
+                PS6_13_FN1, PS6_13_FN2,
+                PS6_12_FN1, PS6_12_FN2,
+                PS6_11_FN1, PS6_11_FN2,
+                PS6_10_FN1, PS6_10_FN2,
+                PS6_9_FN1, PS6_9_FN2,
+                PS6_8_FN1, PS6_8_FN2,
+                PS6_7_FN1, PS6_7_FN2,
+                PS6_6_FN1, PS6_6_FN2,
+                PS6_5_FN1, PS6_5_FN2,
+                PS6_4_FN1, PS6_4_FN2,
+                PS6_3_FN1, PS6_3_FN2,
+                PS6_2_FN1, PS6_2_FN2,
+                PS6_1_FN1, PS6_1_FN2,
+                PS6_0_FN1, PS6_0_FN2, }
+        },
+        { PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1) {
+                PS7_15_FN1, PS7_15_FN2,
+                PS7_14_FN1, PS7_14_FN2,
+                PS7_13_FN1, PS7_13_FN2,
+                PS7_12_FN1, PS7_12_FN2,
+                PS7_11_FN1, PS7_11_FN2,
+                PS7_10_FN1, PS7_10_FN2,
+                PS7_9_FN1, PS7_9_FN2,
+                PS7_8_FN1, PS7_8_FN2,
+                PS7_7_FN1, PS7_7_FN2,
+                PS7_6_FN1, PS7_6_FN2,
+                PS7_5_FN1, PS7_5_FN2,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0, }
+        },
+        { PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1) {
+                PS8_15_FN1, PS8_15_FN2,
+                PS8_14_FN1, PS8_14_FN2,
+                PS8_13_FN1, PS8_13_FN2,
+                PS8_12_FN1, PS8_12_FN2,
+                PS8_11_FN1, PS8_11_FN2,
+                PS8_10_FN1, PS8_10_FN2,
+                PS8_9_FN1, PS8_9_FN2,
+                PS8_8_FN1, PS8_8_FN2,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0, }
+        },
+        {}
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PADR", 0xffec0034, 8) {
+                PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
+                PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
+        },
+        { PINMUX_DATA_REG("PBDR", 0xffec0036, 8) {
+                PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
+                PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
+        },
+        { PINMUX_DATA_REG("PCDR", 0xffec0038, 8) {
+                PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
+                PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
+        },
+        { PINMUX_DATA_REG("PDDR", 0xffec003a, 8) {
+                PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
+                PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
+        },
+        { PINMUX_DATA_REG("PEDR", 0xffec003c, 8) {
+                PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
+                PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
+        },
+        { PINMUX_DATA_REG("PFDR", 0xffec003e, 8) {
+                PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
+                PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
+        },
+        { PINMUX_DATA_REG("PGDR", 0xffec0040, 8) {
+                PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
+                PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
+        },
+        { PINMUX_DATA_REG("PHDR", 0xffec0042, 8) {
+                PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
+                PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
+        },
+        { PINMUX_DATA_REG("PIDR", 0xffec0044, 8) {
+                PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
+                PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA }
+        },
+        { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) {
+                0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
+                PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
+        },
+        { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) {
+                PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
+                PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
+        },
+        { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) {
+                0, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+                PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
+        },
+        { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) {
+                PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+                PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
+        },
+        { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) {
+                0, PTN6_DATA, PTN5_DATA, PTN4_DATA,
+                PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
+        },
+        { PINMUX_DATA_REG("PODR", 0xffec0050, 8) {
+                PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
+                PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA }
+        },
+        { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) {
+                PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
+                PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
+        },
+        { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) {
+                0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
+                PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
+        },
+        { PINMUX_DATA_REG("PRDR", 0xffec0056, 8) {
+                PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
+                PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
+        },
+        { PINMUX_DATA_REG("PSDR", 0xffec0058, 8) {
+                PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
+                PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
+        },
+        { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) {
+                PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
+                PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
+        },
+        { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) {
+                PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
+                PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
+        },
+        { PINMUX_DATA_REG("PVDR", 0xffec005e, 8) {
+                PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
+                PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
+        },
+        { PINMUX_DATA_REG("PWDR", 0xffec0060, 8) {
+                PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
+                PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
+        },
+        { PINMUX_DATA_REG("PXDR", 0xffec0062, 8) {
+                PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
+                PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
+        },
+        { PINMUX_DATA_REG("PYDR", 0xffec0064, 8) {
+                PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
+                PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
+        },
+        { PINMUX_DATA_REG("PZDR", 0xffec0066, 8) {
+                PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
+                PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
+        },
+        { },
+};
+
+static struct pinmux_info sh7757_pinmux_info = {
+        .name = "sh7757_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PTA0,
+        .last_gpio = GPIO_FN_ON_DQ0,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+static int __init plat_pinmux_setup(void)
+{
+        return register_pinmux(&sh7757_pinmux_info);
+}
+arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
new file mode 100644
index 000000000000..aaa5338abbff
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
@@ -0,0 +1,587 @@
+/*
+ * SH-X3 prototype CPU pinmux
+ *
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <cpu/shx3.h>
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
+        PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
+        PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
+        PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
+        PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
+        PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
+        PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
+        PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
+        PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
+        PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
+        PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
+        PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
+        PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
+        PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
+
+        PH5_DATA, PH4_DATA,
+        PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PA7_IN, PA6_IN, PA5_IN, PA4_IN,
+        PA3_IN, PA2_IN, PA1_IN, PA0_IN,
+        PB7_IN, PB6_IN, PB5_IN, PB4_IN,
+        PB3_IN, PB2_IN, PB1_IN, PB0_IN,
+        PC7_IN, PC6_IN, PC5_IN, PC4_IN,
+        PC3_IN, PC2_IN, PC1_IN, PC0_IN,
+        PD7_IN, PD6_IN, PD5_IN, PD4_IN,
+        PD3_IN, PD2_IN, PD1_IN, PD0_IN,
+        PE7_IN, PE6_IN, PE5_IN, PE4_IN,
+        PE3_IN, PE2_IN, PE1_IN, PE0_IN,
+        PF7_IN, PF6_IN, PF5_IN, PF4_IN,
+        PF3_IN, PF2_IN, PF1_IN, PF0_IN,
+        PG7_IN, PG6_IN, PG5_IN, PG4_IN,
+        PG3_IN, PG2_IN, PG1_IN, PG0_IN,
+
+        PH5_IN, PH4_IN,
+        PH3_IN, PH2_IN, PH1_IN, PH0_IN,
+        PINMUX_INPUT_END,
+
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
+        PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
+        PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
+        PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
+        PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
+        PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
+        PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
+        PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
+        PE7_IN_PU, PE6_IN_PU, PE5_IN_PU, PE4_IN_PU,
+        PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU,
+        PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
+        PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
+        PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU,
+        PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU,
+
+        PH5_IN_PU, PH4_IN_PU,
+        PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
+        PINMUX_INPUT_PULLUP_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
+        PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
+        PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
+        PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
+        PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
+        PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
+        PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
+        PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
+        PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
+        PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
+        PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
+        PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
+        PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
+        PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
+
+        PH5_OUT, PH4_OUT,
+        PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PA7_FN, PA6_FN, PA5_FN, PA4_FN,
+        PA3_FN, PA2_FN, PA1_FN, PA0_FN,
+        PB7_FN, PB6_FN, PB5_FN, PB4_FN,
+        PB3_FN, PB2_FN, PB1_FN, PB0_FN,
+        PC7_FN, PC6_FN, PC5_FN, PC4_FN,
+        PC3_FN, PC2_FN, PC1_FN, PC0_FN,
+        PD7_FN, PD6_FN, PD5_FN, PD4_FN,
+        PD3_FN, PD2_FN, PD1_FN, PD0_FN,
+        PE7_FN, PE6_FN, PE5_FN, PE4_FN,
+        PE3_FN, PE2_FN, PE1_FN, PE0_FN,
+        PF7_FN, PF6_FN, PF5_FN, PF4_FN,
+        PF3_FN, PF2_FN, PF1_FN, PF0_FN,
+        PG7_FN, PG6_FN, PG5_FN, PG4_FN,
+        PG3_FN, PG2_FN, PG1_FN, PG0_FN,
+
+        PH5_FN, PH4_FN,
+        PH3_FN, PH2_FN, PH1_FN, PH0_FN,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+
+        D31_MARK, D30_MARK, D29_MARK, D28_MARK, D27_MARK, D26_MARK,
+        D25_MARK, D24_MARK, D23_MARK, D22_MARK, D21_MARK, D20_MARK,
+        D19_MARK, D18_MARK, D17_MARK, D16_MARK,
+
+        BACK_MARK, BREQ_MARK,
+        WE3_MARK, WE2_MARK,
+        CS6_MARK, CS5_MARK, CS4_MARK,
+        CLKOUTENB_MARK,
+
+        DACK3_MARK, DACK2_MARK, DACK1_MARK, DACK0_MARK,
+        DREQ3_MARK, DREQ2_MARK, DREQ1_MARK, DREQ0_MARK,
+
+        IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
+
+        DRAK3_MARK, DRAK2_MARK, DRAK1_MARK, DRAK0_MARK,
+
+        SCK3_MARK, SCK2_MARK, SCK1_MARK, SCK0_MARK,
+        IRL3_MARK, IRL2_MARK, IRL1_MARK, IRL0_MARK,
+        TXD3_MARK, TXD2_MARK, TXD1_MARK, TXD0_MARK,
+        RXD3_MARK, RXD2_MARK, RXD1_MARK, RXD0_MARK,
+
+        CE2B_MARK, CE2A_MARK, IOIS16_MARK,
+        STATUS1_MARK, STATUS0_MARK,
+
+        IRQOUT_MARK,
+
+        PINMUX_MARK_END,
+};
+
+static pinmux_enum_t shx3_pinmux_data[] = {
+
+        /* PA GPIO */
+        PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
+        PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
+        PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
+        PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
+        PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
+        PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
+        PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
+        PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
+
+        /* PB GPIO */
+        PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
+        PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
+        PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
+        PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
+        PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
+        PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
+        PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
+        PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
+
+        /* PC GPIO */
+        PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
+        PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
+        PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
+        PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
+        PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
+        PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
+        PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
+        PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
+
+        /* PD GPIO */
+        PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
+        PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
+        PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
+        PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
+        PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
+        PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
+        PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
+        PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
+
+        /* PE GPIO */
+        PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
+        PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
+        PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU),
+        PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU),
+        PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU),
+        PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU),
+        PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU),
+        PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU),
+
+        /* PF GPIO */
+        PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
+        PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
+        PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
+        PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
+        PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
+        PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
+        PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
+        PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
+
+        /* PG GPIO */
+        PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
+        PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
+        PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
+        PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU),
+        PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU),
+        PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU),
+        PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU),
+        PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU),
+
+        /* PH GPIO */
+        PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
+        PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
+        PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
+        PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
+        PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
+        PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
+
+        /* PA FN */
+        PINMUX_DATA(D31_MARK, PA7_FN),
+        PINMUX_DATA(D30_MARK, PA6_FN),
+        PINMUX_DATA(D29_MARK, PA5_FN),
+        PINMUX_DATA(D28_MARK, PA4_FN),
+        PINMUX_DATA(D27_MARK, PA3_FN),
+        PINMUX_DATA(D26_MARK, PA2_FN),
+        PINMUX_DATA(D25_MARK, PA1_FN),
+        PINMUX_DATA(D24_MARK, PA0_FN),
+
+        /* PB FN */
+        PINMUX_DATA(D23_MARK, PB7_FN),
+        PINMUX_DATA(D22_MARK, PB6_FN),
+        PINMUX_DATA(D21_MARK, PB5_FN),
+        PINMUX_DATA(D20_MARK, PB4_FN),
+        PINMUX_DATA(D19_MARK, PB3_FN),
+        PINMUX_DATA(D18_MARK, PB2_FN),
+        PINMUX_DATA(D17_MARK, PB1_FN),
+        PINMUX_DATA(D16_MARK, PB0_FN),
+
+        /* PC FN */
+        PINMUX_DATA(BACK_MARK,          PC7_FN),
+        PINMUX_DATA(BREQ_MARK,          PC6_FN),
+        PINMUX_DATA(WE3_MARK,           PC5_FN),
+        PINMUX_DATA(WE2_MARK,           PC4_FN),
+        PINMUX_DATA(CS6_MARK,           PC3_FN),
+        PINMUX_DATA(CS5_MARK,           PC2_FN),
+        PINMUX_DATA(CS4_MARK,           PC1_FN),
+        PINMUX_DATA(CLKOUTENB_MARK,     PC0_FN),
+
+        /* PD FN */
+        PINMUX_DATA(DACK3_MARK, PD7_FN),
+        PINMUX_DATA(DACK2_MARK, PD6_FN),
+        PINMUX_DATA(DACK1_MARK, PD5_FN),
+        PINMUX_DATA(DACK0_MARK, PD4_FN),
+        PINMUX_DATA(DREQ3_MARK, PD3_FN),
+        PINMUX_DATA(DREQ2_MARK, PD2_FN),
+        PINMUX_DATA(DREQ1_MARK, PD1_FN),
+        PINMUX_DATA(DREQ0_MARK, PD0_FN),
+
+        /* PE FN */
+        PINMUX_DATA(IRQ3_MARK,  PE7_FN),
+        PINMUX_DATA(IRQ2_MARK,  PE6_FN),
+        PINMUX_DATA(IRQ1_MARK,  PE5_FN),
+        PINMUX_DATA(IRQ0_MARK,  PE4_FN),
+        PINMUX_DATA(DRAK3_MARK, PE3_FN),
+        PINMUX_DATA(DRAK2_MARK, PE2_FN),
+        PINMUX_DATA(DRAK1_MARK, PE1_FN),
+        PINMUX_DATA(DRAK0_MARK, PE0_FN),
+
+        /* PF FN */
+        PINMUX_DATA(SCK3_MARK, PF7_FN),
+        PINMUX_DATA(SCK2_MARK, PF6_FN),
+        PINMUX_DATA(SCK1_MARK, PF5_FN),
+        PINMUX_DATA(SCK0_MARK, PF4_FN),
+        PINMUX_DATA(IRL3_MARK, PF3_FN),
+        PINMUX_DATA(IRL2_MARK, PF2_FN),
+        PINMUX_DATA(IRL1_MARK, PF1_FN),
+        PINMUX_DATA(IRL0_MARK, PF0_FN),
+
+        /* PG FN */
+        PINMUX_DATA(TXD3_MARK, PG7_FN),
+        PINMUX_DATA(TXD2_MARK, PG6_FN),
+        PINMUX_DATA(TXD1_MARK, PG5_FN),
+        PINMUX_DATA(TXD0_MARK, PG4_FN),
+        PINMUX_DATA(RXD3_MARK, PG3_FN),
+        PINMUX_DATA(RXD2_MARK, PG2_FN),
+        PINMUX_DATA(RXD1_MARK, PG1_FN),
+        PINMUX_DATA(RXD0_MARK, PG0_FN),
+
+        /* PH FN */
+        PINMUX_DATA(CE2B_MARK,          PH5_FN),
+        PINMUX_DATA(CE2A_MARK,          PH4_FN),
+        PINMUX_DATA(IOIS16_MARK,        PH3_FN),
+        PINMUX_DATA(STATUS1_MARK,       PH2_FN),
+        PINMUX_DATA(STATUS0_MARK,       PH1_FN),
+        PINMUX_DATA(IRQOUT_MARK,        PH0_FN),
+};
+
+static struct pinmux_gpio shx3_pinmux_gpios[] = {
+        /* PA */
+        PINMUX_GPIO(GPIO_PA7, PA7_DATA),
+        PINMUX_GPIO(GPIO_PA6, PA6_DATA),
+        PINMUX_GPIO(GPIO_PA5, PA5_DATA),
+        PINMUX_GPIO(GPIO_PA4, PA4_DATA),
+        PINMUX_GPIO(GPIO_PA3, PA3_DATA),
+        PINMUX_GPIO(GPIO_PA2, PA2_DATA),
+        PINMUX_GPIO(GPIO_PA1, PA1_DATA),
+        PINMUX_GPIO(GPIO_PA0, PA0_DATA),
+
+        /* PB */
+        PINMUX_GPIO(GPIO_PB7, PB7_DATA),
+        PINMUX_GPIO(GPIO_PB6, PB6_DATA),
+        PINMUX_GPIO(GPIO_PB5, PB5_DATA),
+        PINMUX_GPIO(GPIO_PB4, PB4_DATA),
+        PINMUX_GPIO(GPIO_PB3, PB3_DATA),
+        PINMUX_GPIO(GPIO_PB2, PB2_DATA),
+        PINMUX_GPIO(GPIO_PB1, PB1_DATA),
+        PINMUX_GPIO(GPIO_PB0, PB0_DATA),
+
+        /* PC */
+        PINMUX_GPIO(GPIO_PC7, PC7_DATA),
+        PINMUX_GPIO(GPIO_PC6, PC6_DATA),
+        PINMUX_GPIO(GPIO_PC5, PC5_DATA),
+        PINMUX_GPIO(GPIO_PC4, PC4_DATA),
+        PINMUX_GPIO(GPIO_PC3, PC3_DATA),
+        PINMUX_GPIO(GPIO_PC2, PC2_DATA),
+        PINMUX_GPIO(GPIO_PC1, PC1_DATA),
+        PINMUX_GPIO(GPIO_PC0, PC0_DATA),
+
+        /* PD */
+        PINMUX_GPIO(GPIO_PD7, PD7_DATA),
+        PINMUX_GPIO(GPIO_PD6, PD6_DATA),
+        PINMUX_GPIO(GPIO_PD5, PD5_DATA),
+        PINMUX_GPIO(GPIO_PD4, PD4_DATA),
+        PINMUX_GPIO(GPIO_PD3, PD3_DATA),
+        PINMUX_GPIO(GPIO_PD2, PD2_DATA),
+        PINMUX_GPIO(GPIO_PD1, PD1_DATA),
+        PINMUX_GPIO(GPIO_PD0, PD0_DATA),
+
+        /* PE */
+        PINMUX_GPIO(GPIO_PE7, PE7_DATA),
+        PINMUX_GPIO(GPIO_PE6, PE6_DATA),
+        PINMUX_GPIO(GPIO_PE5, PE5_DATA),
+        PINMUX_GPIO(GPIO_PE4, PE4_DATA),
+        PINMUX_GPIO(GPIO_PE3, PE3_DATA),
+        PINMUX_GPIO(GPIO_PE2, PE2_DATA),
+        PINMUX_GPIO(GPIO_PE1, PE1_DATA),
+        PINMUX_GPIO(GPIO_PE0, PE0_DATA),
+
+        /* PF */
+        PINMUX_GPIO(GPIO_PF7, PF7_DATA),
+        PINMUX_GPIO(GPIO_PF6, PF6_DATA),
+        PINMUX_GPIO(GPIO_PF5, PF5_DATA),
+        PINMUX_GPIO(GPIO_PF4, PF4_DATA),
+        PINMUX_GPIO(GPIO_PF3, PF3_DATA),
+        PINMUX_GPIO(GPIO_PF2, PF2_DATA),
+        PINMUX_GPIO(GPIO_PF1, PF1_DATA),
+        PINMUX_GPIO(GPIO_PF0, PF0_DATA),
+
+        /* PG */
+        PINMUX_GPIO(GPIO_PG7, PG7_DATA),
+        PINMUX_GPIO(GPIO_PG6, PG6_DATA),
+        PINMUX_GPIO(GPIO_PG5, PG5_DATA),
+        PINMUX_GPIO(GPIO_PG4, PG4_DATA),
+        PINMUX_GPIO(GPIO_PG3, PG3_DATA),
+        PINMUX_GPIO(GPIO_PG2, PG2_DATA),
+        PINMUX_GPIO(GPIO_PG1, PG1_DATA),
+        PINMUX_GPIO(GPIO_PG0, PG0_DATA),
+
+        /* PH */
+        PINMUX_GPIO(GPIO_PH5, PH5_DATA),
+        PINMUX_GPIO(GPIO_PH4, PH4_DATA),
+        PINMUX_GPIO(GPIO_PH3, PH3_DATA),
+        PINMUX_GPIO(GPIO_PH2, PH2_DATA),
+        PINMUX_GPIO(GPIO_PH1, PH1_DATA),
+        PINMUX_GPIO(GPIO_PH0, PH0_DATA),
+
+        /* FN */
+        PINMUX_GPIO(GPIO_FN_D31,        D31_MARK),
+        PINMUX_GPIO(GPIO_FN_D30,        D30_MARK),
+        PINMUX_GPIO(GPIO_FN_D29,        D29_MARK),
+        PINMUX_GPIO(GPIO_FN_D28,        D28_MARK),
+        PINMUX_GPIO(GPIO_FN_D27,        D27_MARK),
+        PINMUX_GPIO(GPIO_FN_D26,        D26_MARK),
+        PINMUX_GPIO(GPIO_FN_D25,        D25_MARK),
+        PINMUX_GPIO(GPIO_FN_D24,        D24_MARK),
+        PINMUX_GPIO(GPIO_FN_D23,        D23_MARK),
+        PINMUX_GPIO(GPIO_FN_D22,        D22_MARK),
+        PINMUX_GPIO(GPIO_FN_D21,        D21_MARK),
+        PINMUX_GPIO(GPIO_FN_D20,        D20_MARK),
+        PINMUX_GPIO(GPIO_FN_D19,        D19_MARK),
+        PINMUX_GPIO(GPIO_FN_D18,        D18_MARK),
+        PINMUX_GPIO(GPIO_FN_D17,        D17_MARK),
+        PINMUX_GPIO(GPIO_FN_D16,        D16_MARK),
+        PINMUX_GPIO(GPIO_FN_BACK,       BACK_MARK),
+        PINMUX_GPIO(GPIO_FN_BREQ,       BREQ_MARK),
+        PINMUX_GPIO(GPIO_FN_WE3,        WE3_MARK),
+        PINMUX_GPIO(GPIO_FN_WE2,        WE2_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6,        CS6_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5,        CS5_MARK),
+        PINMUX_GPIO(GPIO_FN_CS4,        CS4_MARK),
+        PINMUX_GPIO(GPIO_FN_CLKOUTENB,  CLKOUTENB_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK3,      DACK3_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK2,      DACK2_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK1,      DACK1_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK0,      DACK0_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ3,      DREQ3_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ2,      DREQ2_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ1,      DREQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ0,      DREQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ3,       IRQ3_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ2,       IRQ2_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ1,       IRQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ0,       IRQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_DRAK3,      DRAK3_MARK),
+        PINMUX_GPIO(GPIO_FN_DRAK2,      DRAK2_MARK),
+        PINMUX_GPIO(GPIO_FN_DRAK1,      DRAK1_MARK),
+        PINMUX_GPIO(GPIO_FN_DRAK0,      DRAK0_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK3,       SCK3_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK2,       SCK2_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK1,       SCK1_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK0,       SCK0_MARK),
+        PINMUX_GPIO(GPIO_FN_IRL3,       IRL3_MARK),
+        PINMUX_GPIO(GPIO_FN_IRL2,       IRL2_MARK),
+        PINMUX_GPIO(GPIO_FN_IRL1,       IRL1_MARK),
+        PINMUX_GPIO(GPIO_FN_IRL0,       IRL0_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD3,       TXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD2,       TXD2_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD1,       TXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD0,       TXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD3,       RXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD2,       RXD2_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD1,       RXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD0,       RXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_CE2B,       CE2B_MARK),
+        PINMUX_GPIO(GPIO_FN_CE2A,       CE2A_MARK),
+        PINMUX_GPIO(GPIO_FN_IOIS16,     IOIS16_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS1,    STATUS1_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS0,    STATUS0_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQOUT,     IRQOUT_MARK),
+};
+
+static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
+                PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
+                PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
+                PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
+                PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
+                PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
+                PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
+                PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
+                PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU,
+                PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
+                PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
+                PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
+                PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
+                PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
+                PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
+                PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
+                PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU, },
+        },
+        { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) {
+                PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
+                PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
+                PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
+                PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
+                PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
+                PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
+                PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
+                PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU,
+                PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
+                PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
+                PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
+                PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
+                PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
+                PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
+                PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
+                PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU, },
+        },
+        { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) {
+                PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
+                PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
+                PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU,
+                PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU,
+                PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU,
+                PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU,
+                PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU,
+                PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU,
+                PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
+                PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
+                PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
+                PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
+                PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
+                PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
+                PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
+                PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU, },
+        },
+        { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) {
+                PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
+                PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
+                PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
+                PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU,
+                PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU,
+                PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU,
+                PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU,
+                PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
+                PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
+                PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
+                PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
+                PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
+                PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU, },
+        },
+        { },
+};
+
+static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
+                PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
+                PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, },
+        },
+        { PINMUX_DATA_REG("PCDDR", 0xffc70014, 32) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
+                PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
+                PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, },
+        },
+        { PINMUX_DATA_REG("PEFDR", 0xffc70018, 32) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
+                PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
+                PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, },
+        },
+        { PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
+                PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, PH5_DATA, PH4_DATA,
+                PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, },
+        },
+        { },
+};
+
+static struct pinmux_info shx3_pinmux_info = {
+        .name           = "shx3_pfc",
+        .reserved_id    = PINMUX_RESERVED,
+        .data           = { PINMUX_DATA_BEGIN,     PINMUX_DATA_END },
+        .input          = { PINMUX_INPUT_BEGIN,    PINMUX_INPUT_END },
+        .input_pu       = { PINMUX_INPUT_PULLUP_BEGIN,
+                            PINMUX_INPUT_PULLUP_END },
+        .output         = { PINMUX_OUTPUT_BEGIN,   PINMUX_OUTPUT_END },
+        .mark           = { PINMUX_MARK_BEGIN,     PINMUX_MARK_END },
+        .function       = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+        .first_gpio     = GPIO_PA7,
+        .last_gpio      = GPIO_FN_IRQOUT,
+        .gpios          = shx3_pinmux_gpios,
+        .gpio_data      = shx3_pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
+        .cfg_regs       = shx3_pinmux_config_regs,
+        .data_regs      = shx3_pinmux_data_regs,
+};
+
+static int __init shx3_pinmux_setup(void)
+{
+        return register_pinmux(&shx3_pinmux_info);
+}
+arch_initcall(shx3_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index fbae06b1c98d..0d1be5d1fb86 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -15,6 +15,75 @@
 #include <linux/sh_timer.h>
 #include <asm/clock.h>
 
+/* Serial */
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 80, 80, 80, 80 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffe10000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 81, 81, 81, 81 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffe20000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 82, 82, 82, 82 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xffe30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 83, 83, 83, 83 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
 static struct resource iic0_resources[] = {
         [0] = {
                 .name   = "IIC0",
@@ -142,17 +211,14 @@ static struct platform_device jpu_device = {
 };
 
 static struct sh_timer_config cmt_platform_data = {
-        .name = "CMT",
         .channel_offset = 0x60,
         .timer_bit = 5,
-        .clk = "cmt0",
         .clockevent_rating = 125,
         .clocksource_rating = 200,
 };
 
 static struct resource cmt_resources[] = {
         [0] = {
-                .name   = "CMT",
                 .start  = 0x044a0060,
                 .end    = 0x044a006b,
                 .flags  = IORESOURCE_MEM,
@@ -174,16 +240,13 @@ static struct platform_device cmt_device = {
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "tmu0",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -205,16 +268,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "tmu0",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -236,15 +296,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "tmu0",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002b,
                 .flags  = IORESOURCE_MEM,
@@ -265,60 +322,17 @@ static struct platform_device tmu2_device = {
         .num_resources  = ARRAY_SIZE(tmu2_resources),
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 80, 80, 80, 80 },
-                .clk            = "scif0",
-        }, {
-                .mapbase        = 0xffe10000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 81, 81, 81, 81 },
-                .clk            = "scif1",
-        }, {
-                .mapbase        = 0xffe20000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 82, 82, 82, 82 },
-                .clk            = "scif2",
-        }, {
-                .mapbase        = 0xffe30000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 83, 83, 83, 83 },
-                .clk            = "scif3",
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = sci_platform_data,
-        },
-};
-
 static struct platform_device *sh7343_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
         &iic0_device,
         &iic1_device,
-        &sci_device,
         &vpu_device,
         &veu_device,
         &jpu_device,
@@ -333,9 +347,13 @@ static int __init sh7343_devices_setup(void)
         return platform_add_devices(sh7343_devices,
                                     ARRAY_SIZE(sh7343_devices));
 }
-__initcall(sh7343_devices_setup);
+arch_initcall(sh7343_devices_setup);
 
 static struct platform_device *sh7343_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index d4ee429032b1..f96b7eeb21eb 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -18,6 +18,23 @@
 #include <linux/usb/r8a66597.h>
 #include <asm/clock.h>
 
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 80, 80, 80, 80 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
 static struct resource iic_resources[] = {
         [0] = {
                 .name   = "IIC",
@@ -40,7 +57,7 @@ static struct platform_device iic_device = {
 };
 
 static struct r8a66597_platdata r8a66597_data = {
-        /* This set zero to all members */
+        .on_chip = 1,
 };
 
 static struct resource usb_host_resources[] = {
@@ -153,17 +170,14 @@ static struct platform_device veu1_device = {
 };
 
 static struct sh_timer_config cmt_platform_data = {
-        .name = "CMT",
         .channel_offset = 0x60,
         .timer_bit = 5,
-        .clk = "cmt0",
         .clockevent_rating = 125,
         .clocksource_rating = 200,
 };
 
 static struct resource cmt_resources[] = {
         [0] = {
-                .name   = "CMT",
                 .start  = 0x044a0060,
                 .end    = 0x044a006b,
                 .flags  = IORESOURCE_MEM,
@@ -185,16 +199,13 @@ static struct platform_device cmt_device = {
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "tmu0",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -216,16 +227,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "tmu0",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -247,15 +255,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "tmu0",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002b,
                 .flags  = IORESOURCE_MEM,
@@ -276,35 +281,13 @@ static struct platform_device tmu2_device = {
         .num_resources  = ARRAY_SIZE(tmu2_resources),
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 80, 80, 80, 80 },
-                .clk            = "scif0",
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = sci_platform_data,
-        },
-};
-
 static struct platform_device *sh7366_devices[] __initdata = {
+        &scif0_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
         &iic_device,
-        &sci_device,
         &usb_host_device,
         &vpu_device,
         &veu0_device,
@@ -320,9 +303,10 @@ static int __init sh7366_devices_setup(void)
         return platform_add_devices(sh7366_devices,
                                     ARRAY_SIZE(sh7366_devices));
 }
-__initcall(sh7366_devices_setup);
+arch_initcall(sh7366_devices_setup);
 
 static struct platform_device *sh7366_early_devices[] __initdata = {
+        &scif0_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index f7b0551bf104..73737d00e2e7 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -7,15 +7,227 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  */
-#include <linux/platform_device.h>
 #include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/platform_device.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
-#include <linux/mm.h>
-#include <linux/uio_driver.h>
 #include <linux/sh_timer.h>
+#include <linux/uio_driver.h>
+#include <linux/usb/m66592.h>
+
 #include <asm/clock.h>
 #include <asm/mmzone.h>
+#include <asm/siu.h>
+
+#include <cpu/dma-register.h>
+#include <cpu/sh7722.h>
+
+static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF0_TX,
+                .addr           = 0xffe0000c,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x21,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF0_RX,
+                .addr           = 0xffe00014,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x22,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF1_TX,
+                .addr           = 0xffe1000c,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x25,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF1_RX,
+                .addr           = 0xffe10014,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x26,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF2_TX,
+                .addr           = 0xffe2000c,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x29,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF2_RX,
+                .addr           = 0xffe20014,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2a,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SIUA_TX,
+                .addr           = 0xa454c098,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xb1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SIUA_RX,
+                .addr           = 0xa454c090,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xb2,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SIUB_TX,
+                .addr           = 0xa454c09c,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xb5,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SIUB_RX,
+                .addr           = 0xa454c094,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xb6,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI0_TX,
+                .addr           = 0x04ce0030,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI0_RX,
+                .addr           = 0x04ce0030,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc2,
+        },
+};
+
+static const struct sh_dmae_channel sh7722_dmae_channels[] = {
+        {
+                .offset = 0,
+                .dmars = 0,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x10,
+                .dmars = 0,
+                .dmars_bit = 8,
+        }, {
+                .offset = 0x20,
+                .dmars = 4,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x30,
+                .dmars = 4,
+                .dmars_bit = 8,
+        }, {
+                .offset = 0x50,
+                .dmars = 8,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x60,
+                .dmars = 8,
+                .dmars_bit = 8,
+        }
+};
+
+static const unsigned int ts_shift[] = TS_SHIFT;
+
+static struct sh_dmae_pdata dma_platform_data = {
+        .slave          = sh7722_dmae_slaves,
+        .slave_num      = ARRAY_SIZE(sh7722_dmae_slaves),
+        .channel        = sh7722_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh7722_dmae_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+static struct resource sh7722_dmae_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xfe008020,
+                .end    = 0xfe00808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* DMARSx */
+                .start  = 0xfe009000,
+                .end    = 0xfe00900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMA error IRQ */
+                .start  = 78,
+                .end    = 78,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 0-3 */
+                .start  = 48,
+                .end    = 51,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 4-5 */
+                .start  = 76,
+                .end    = 77,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device dma_device = {
+        .name           = "sh-dma-engine",
+        .id             = -1,
+        .resource       = sh7722_dmae_resources,
+        .num_resources  = ARRAY_SIZE(sh7722_dmae_resources),
+        .dev            = {
+                .platform_data  = &dma_platform_data,
+        },
+        .archdata = {
+                .hwblk_id = HWBLK_DMAC,
+        },
+};
+
+/* Serial */
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 80, 80, 80, 80 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffe10000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 81, 81, 81, 81 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffe20000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 82, 82, 82, 82 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
 
 static struct resource rtc_resources[] = {
         [0] = {
@@ -45,11 +257,18 @@ static struct platform_device rtc_device = {
         .id             = -1,
         .num_resources  = ARRAY_SIZE(rtc_resources),
         .resource       = rtc_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_RTC,
+        },
+};
+
+static struct m66592_platdata usbf_platdata = {
+        .on_chip = 1,
 };
 
 static struct resource usbf_resources[] = {
         [0] = {
-                .name   = "m66592_udc",
+                .name   = "USBF",
                 .start  = 0x04480000,
                 .end    = 0x044800FF,
                 .flags  = IORESOURCE_MEM,
@@ -67,9 +286,13 @@ static struct platform_device usbf_device = {
         .dev = {
                 .dma_mask               = NULL,
                 .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &usbf_platdata,
         },
         .num_resources  = ARRAY_SIZE(usbf_resources),
         .resource       = usbf_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_USBF,
+        },
 };
 
 static struct resource iic_resources[] = {
@@ -91,6 +314,9 @@ static struct platform_device iic_device = {
         .id             = 0, /* "i2c0" clock */
         .num_resources  = ARRAY_SIZE(iic_resources),
         .resource       = iic_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_IIC,
+        },
 };
 
 static struct uio_info vpu_platform_data = {
@@ -119,6 +345,9 @@ static struct platform_device vpu_device = {
         },
         .resource       = vpu_resources,
         .num_resources  = ARRAY_SIZE(vpu_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VPU,
+        },
 };
 
 static struct uio_info veu_platform_data = {
@@ -147,6 +376,9 @@ static struct platform_device veu_device = {
         },
         .resource       = veu_resources,
         .num_resources  = ARRAY_SIZE(veu_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VEU,
+        },
 };
 
 static struct uio_info jpu_platform_data = {
@@ -175,20 +407,20 @@ static struct platform_device jpu_device = {
         },
         .resource       = jpu_resources,
         .num_resources  = ARRAY_SIZE(jpu_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_JPU,
+        },
 };
 
 static struct sh_timer_config cmt_platform_data = {
-        .name = "CMT",
         .channel_offset = 0x60,
         .timer_bit = 5,
-        .clk = "cmt0",
         .clockevent_rating = 125,
         .clocksource_rating = 125,
 };
 
 static struct resource cmt_resources[] = {
         [0] = {
-                .name   = "CMT",
                 .start  = 0x044a0060,
                 .end    = 0x044a006b,
                 .flags  = IORESOURCE_MEM,
@@ -207,19 +439,19 @@ static struct platform_device cmt_device = {
         },
         .resource       = cmt_resources,
         .num_resources  = ARRAY_SIZE(cmt_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_CMT,
+        },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "tmu0",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -238,19 +470,19 @@ static struct platform_device tmu0_device = {
         },
         .resource       = tmu0_resources,
         .num_resources  = ARRAY_SIZE(tmu0_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU,
+        },
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "tmu0",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -269,18 +501,18 @@ static struct platform_device tmu1_device = {
         },
         .resource       = tmu1_resources,
         .num_resources  = ARRAY_SIZE(tmu1_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU,
+        },
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "tmu0",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002b,
                 .flags  = IORESOURCE_MEM,
@@ -299,47 +531,48 @@ static struct platform_device tmu2_device = {
         },
         .resource       = tmu2_resources,
         .num_resources  = ARRAY_SIZE(tmu2_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU,
+        },
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 80, 80, 80, 80 },
-                .clk            = "scif0",
-        }, {
-                .mapbase        = 0xffe10000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 81, 81, 81, 81 },
-                .clk            = "scif1",
-        }, {
-                .mapbase        = 0xffe20000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 82, 82, 82, 82 },
-                .clk            = "scif2",
-        }, {
-                .flags = 0,
-        }
+static struct siu_platform siu_platform_data = {
+        .dma_dev        = &dma_device.dev,
+        .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
+        .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
+        .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
+        .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
 };
 
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
+static struct resource siu_resources[] = {
+        [0] = {
+                .start  = 0xa4540000,
+                .end    = 0xa454c10f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 108,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device siu_device = {
+        .name           = "siu-pcm-audio",
         .id             = -1,
-        .dev            = {
-                .platform_data  = sci_platform_data,
+        .dev = {
+                .platform_data  = &siu_platform_data,
+        },
+        .resource       = siu_resources,
+        .num_resources  = ARRAY_SIZE(siu_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_SIU,
         },
 };
 
 static struct platform_device *sh7722_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
@@ -347,10 +580,11 @@ static struct platform_device *sh7722_devices[] __initdata = {
         &rtc_device,
         &usbf_device,
         &iic_device,
-        &sci_device,
         &vpu_device,
         &veu_device,
         &jpu_device,
+        &siu_device,
+        &dma_device,
 };
 
 static int __init sh7722_devices_setup(void)
@@ -362,9 +596,12 @@ static int __init sh7722_devices_setup(void)
         return platform_add_devices(sh7722_devices,
                                     ARRAY_SIZE(sh7722_devices));
 }
-__initcall(sh7722_devices_setup);
+arch_initcall(sh7722_devices_setup);
 
 static struct platform_device *sh7722_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
@@ -379,6 +616,8 @@ void __init plat_early_device_setup(void)
 
 enum {
         UNUSED=0,
+        ENABLED,
+        DISABLED,
 
         /* interrupt sources */
         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -394,7 +633,6 @@ enum {
         SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
-        SDHI0, SDHI1, SDHI2, SDHI3,
         CMT, TSIF, SIU, TWODG,
         TMU0, TMU1, TMU2,
         IRDA, JPU, LCDC,
@@ -427,8 +665,8 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
-        INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
-        INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
+        INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
+        INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
         INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
@@ -446,7 +684,6 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
-        INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
 };
 
 static struct intc_mask_reg mask_registers[] __initdata = {
@@ -468,7 +705,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
+          { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -506,9 +743,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
-                             mask_registers, prio_registers, sense_registers,
-                             ack_registers);
+static struct intc_desc intc_desc __initdata = {
+        .name = "sh7722",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(vectors, groups, mask_registers,
+                           prio_registers, sense_registers, ack_registers),
+};
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index bb4837b9dcf4..264983ddc8da 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -18,6 +18,110 @@
 #include <linux/io.h>
 #include <asm/clock.h>
 #include <asm/mmzone.h>
+#include <cpu/sh7723.h>
+
+/* Serial */
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 80, 80, 80, 80 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffe10000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 81, 81, 81, 81 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffe20000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 82, 82, 82, 82 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xa4e30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_3,
+        .type           = PORT_SCIFA,
+        .irqs           = { 56, 56, 56, 56 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xa4e40000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_3,
+        .type           = PORT_SCIFA,
+        .irqs           = { 88, 88, 88, 88 },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xa4e50000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_3,
+        .type           = PORT_SCIFA,
+        .irqs           = { 109, 109, 109, 109 },
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
 
 static struct uio_info vpu_platform_data = {
         .name = "VPU5",
@@ -45,6 +149,9 @@ static struct platform_device vpu_device = {
         },
         .resource       = vpu_resources,
         .num_resources  = ARRAY_SIZE(vpu_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VPU,
+        },
 };
 
 static struct uio_info veu0_platform_data = {
@@ -73,6 +180,9 @@ static struct platform_device veu0_device = {
         },
         .resource       = veu0_resources,
         .num_resources  = ARRAY_SIZE(veu0_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VEU2H0,
+        },
 };
 
 static struct uio_info veu1_platform_data = {
@@ -101,20 +211,20 @@ static struct platform_device veu1_device = {
         },
         .resource       = veu1_resources,
         .num_resources  = ARRAY_SIZE(veu1_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VEU2H1,
+        },
 };
 
 static struct sh_timer_config cmt_platform_data = {
-        .name = "CMT",
         .channel_offset = 0x60,
         .timer_bit = 5,
-        .clk = "cmt0",
         .clockevent_rating = 125,
         .clocksource_rating = 125,
 };
 
 static struct resource cmt_resources[] = {
         [0] = {
-                .name   = "CMT",
                 .start  = 0x044a0060,
                 .end    = 0x044a006b,
                 .flags  = IORESOURCE_MEM,
@@ -133,19 +243,19 @@ static struct platform_device cmt_device = {
         },
         .resource       = cmt_resources,
         .num_resources  = ARRAY_SIZE(cmt_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_CMT,
+        },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "tmu0",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -164,19 +274,19 @@ static struct platform_device tmu0_device = {
         },
         .resource       = tmu0_resources,
         .num_resources  = ARRAY_SIZE(tmu0_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU0,
+        },
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "tmu0",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -195,18 +305,18 @@ static struct platform_device tmu1_device = {
         },
         .resource       = tmu1_resources,
         .num_resources  = ARRAY_SIZE(tmu1_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU0,
+        },
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "tmu0",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002b,
                 .flags  = IORESOURCE_MEM,
@@ -225,18 +335,18 @@ static struct platform_device tmu2_device = {
         },
         .resource       = tmu2_resources,
         .num_resources  = ARRAY_SIZE(tmu2_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU0,
+        },
 };
 
 static struct sh_timer_config tmu3_platform_data = {
-        .name = "TMU3",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "tmu1",
 };
 
 static struct resource tmu3_resources[] = {
         [0] = {
-                .name   = "TMU3",
                 .start  = 0xffd90008,
                 .end    = 0xffd90013,
                 .flags  = IORESOURCE_MEM,
@@ -255,18 +365,18 @@ static struct platform_device tmu3_device = {
         },
         .resource       = tmu3_resources,
         .num_resources  = ARRAY_SIZE(tmu3_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU1,
+        },
 };
 
 static struct sh_timer_config tmu4_platform_data = {
-        .name = "TMU4",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "tmu1",
 };
 
 static struct resource tmu4_resources[] = {
         [0] = {
-                .name   = "TMU4",
                 .start  = 0xffd90014,
                 .end    = 0xffd9001f,
                 .flags  = IORESOURCE_MEM,
@@ -285,18 +395,18 @@ static struct platform_device tmu4_device = {
         },
         .resource       = tmu4_resources,
         .num_resources  = ARRAY_SIZE(tmu4_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU1,
+        },
 };
 
 static struct sh_timer_config tmu5_platform_data = {
-        .name = "TMU5",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "tmu1",
 };
 
 static struct resource tmu5_resources[] = {
         [0] = {
-                .name   = "TMU5",
                 .start  = 0xffd90020,
                 .end    = 0xffd9002b,
                 .flags  = IORESOURCE_MEM,
@@ -315,67 +425,8 @@ static struct platform_device tmu5_device = {
         },
         .resource       = tmu5_resources,
         .num_resources  = ARRAY_SIZE(tmu5_resources),
-};
-
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 80, 80, 80, 80 },
-                .clk            = "scif0",
-        },{
-                .mapbase        = 0xffe10000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 81, 81, 81, 81 },
-                .clk            = "scif1",
-        },{
-                .mapbase        = 0xffe20000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 82, 82, 82, 82 },
-                .clk            = "scif2",
-        },{
-                .mapbase        = 0xa4e30000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_3,
-                .type           = PORT_SCIFA,
-                .irqs           = { 56, 56, 56, 56 },
-                .clk            = "scif3",
-        },{
-                .mapbase        = 0xa4e40000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_3,
-                .type           = PORT_SCIFA,
-                .irqs           = { 88, 88, 88, 88 },
-                .clk            = "scif4",
-        },{
-                .mapbase        = 0xa4e50000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_3,
-                .type           = PORT_SCIFA,
-                .irqs           = { 109, 109, 109, 109 },
-                .clk            = "scif5",
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = sci_platform_data,
+        .archdata = {
+                .hwblk_id = HWBLK_TMU1,
         },
 };
 
@@ -407,10 +458,13 @@ static struct platform_device rtc_device = {
         .id             = -1,
         .num_resources  = ARRAY_SIZE(rtc_resources),
         .resource       = rtc_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_RTC,
+        },
 };
 
 static struct r8a66597_platdata r8a66597_data = {
-        /* This set zero to all members */
+        .on_chip = 1,
 };
 
 static struct resource sh7723_usb_host_resources[] = {
@@ -436,6 +490,9 @@ static struct platform_device sh7723_usb_host_device = {
         },
         .num_resources  = ARRAY_SIZE(sh7723_usb_host_resources),
         .resource       = sh7723_usb_host_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_USB,
+        },
 };
 
 static struct resource iic_resources[] = {
@@ -457,9 +514,18 @@ static struct platform_device iic_device = {
         .id             = 0, /* "i2c0" clock */
         .num_resources  = ARRAY_SIZE(iic_resources),
         .resource       = iic_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_IIC,
+        },
 };
 
 static struct platform_device *sh7723_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
@@ -467,7 +533,6 @@ static struct platform_device *sh7723_devices[] __initdata = {
         &tmu3_device,
         &tmu4_device,
         &tmu5_device,
-        &sci_device,
         &rtc_device,
         &iic_device,
         &sh7723_usb_host_device,
@@ -485,9 +550,15 @@ static int __init sh7723_devices_setup(void)
         return platform_add_devices(sh7723_devices,
                                     ARRAY_SIZE(sh7723_devices));
 }
-__initcall(sh7723_devices_setup);
+arch_initcall(sh7723_devices_setup);
 
 static struct platform_device *sh7723_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
@@ -506,14 +577,17 @@ void __init plat_early_device_setup(void)
 #define RAMCR_CACHE_L2FC        0x0002
 #define RAMCR_CACHE_L2E         0x0001
 #define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
-void __uses_jump_to_uncached l2_cache_init(void)
+
+void l2_cache_init(void)
 {
         /* Enable L2 cache */
-        ctrl_outl(L2_CACHE_ENABLE, RAMCR);
+        __raw_writel(L2_CACHE_ENABLE, RAMCR);
 }
 
 enum {
         UNUSED=0,
+        ENABLED,
+        DISABLED,
 
         /* interrupt sources */
         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -536,7 +610,6 @@ enum {
         SCIFA_SCIFA1,
         FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
         I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
-        SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
         CMT_CMTI,
         TSIF_TSIFI,
         SIU_SIUI,
@@ -544,7 +617,6 @@ enum {
         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
         IRDA_IRDAI,
         ATAPI_ATAPII,
-        SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
         VEU2H1_VEU2HI,
         LCDC_LCDCI,
         TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
@@ -615,9 +687,9 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(I2C_WAITI,0xE40),
         INTC_VECT(I2C_DTEI,0xE60),
 
-        INTC_VECT(SDHI0_SDHII0,0xE80),
-        INTC_VECT(SDHI0_SDHII1,0xEA0),
-        INTC_VECT(SDHI0_SDHII2,0xEC0),
+        INTC_VECT(SDHI0, 0xE80),
+        INTC_VECT(SDHI0, 0xEA0),
+        INTC_VECT(SDHI0, 0xEC0),
 
         INTC_VECT(CMT_CMTI,0xF00),
         INTC_VECT(TSIF_TSIFI,0xF20),
@@ -631,9 +703,9 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(IRDA_IRDAI,0x480),
         INTC_VECT(ATAPI_ATAPII,0x4A0),
 
-        INTC_VECT(SDHI1_SDHII0,0x4E0),
-        INTC_VECT(SDHI1_SDHII1,0x500),
-        INTC_VECT(SDHI1_SDHII2,0x520),
+        INTC_VECT(SDHI1, 0x4E0),
+        INTC_VECT(SDHI1, 0x500),
+        INTC_VECT(SDHI1, 0x520),
 
         INTC_VECT(VEU2H1_VEU2HI,0x560),
         INTC_VECT(LCDC_LCDCI,0x580),
@@ -652,15 +724,14 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
         INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
         INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
-        INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
         INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
         INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
-        INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
 };
 
 static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
-          { 0,  TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
+          { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
+            0, DISABLED, ENABLED, ENABLED } },
         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
           { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
@@ -677,7 +748,8 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
+          { 0, DISABLED, ENABLED, ENABLED,
+            0, 0, SCIFA_SCIFA2, SIU_SIUI } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -717,9 +789,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups,
-                             mask_registers, prio_registers, sense_registers,
-                             ack_registers);
+static struct intc_desc intc_desc __initdata = {
+        .name = "sh7723",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(vectors, groups, mask_registers,
+                           prio_registers, sense_registers, ack_registers),
+};
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index c934b78e5658..4a8b751c5f17 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -18,71 +18,341 @@
 #include <linux/mm.h>
 #include <linux/serial_sci.h>
 #include <linux/uio_driver.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
 #include <linux/io.h>
+#include <linux/notifier.h>
+
+#include <asm/suspend.h>
 #include <asm/clock.h>
 #include <asm/mmzone.h>
 
-/* Serial */
-static struct plat_sci_port sci_platform_data[] = {
+#include <cpu/dma-register.h>
+#include <cpu/sh7724.h>
+
+/* DMA */
+static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
         {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 80, 80, 80, 80 },
-                .clk            = "scif0",
+                .slave_id       = SHDMA_SLAVE_SCIF0_TX,
+                .addr           = 0xffe0000c,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x21,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF0_RX,
+                .addr           = 0xffe00014,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x22,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF1_TX,
+                .addr           = 0xffe1000c,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x25,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF1_RX,
+                .addr           = 0xffe10014,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x26,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF2_TX,
+                .addr           = 0xffe2000c,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x29,
         }, {
-                .mapbase        = 0xffe10000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 81, 81, 81, 81 },
-                .clk            = "scif1",
+                .slave_id       = SHDMA_SLAVE_SCIF2_RX,
+                .addr           = 0xffe20014,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2a,
         }, {
-                .mapbase        = 0xffe20000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 82, 82, 82, 82 },
-                .clk            = "scif2",
+                .slave_id       = SHDMA_SLAVE_SCIF3_TX,
+                .addr           = 0xa4e30020,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2d,
         }, {
-                .mapbase        = 0xa4e30000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_3,
-                .type           = PORT_SCIFA,
-                .irqs           = { 56, 56, 56, 56 },
-                .clk            = "scif3",
+                .slave_id       = SHDMA_SLAVE_SCIF3_RX,
+                .addr           = 0xa4e30024,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2e,
         }, {
-                .mapbase        = 0xa4e40000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_3,
-                .type           = PORT_SCIFA,
-                .irqs           = { 88, 88, 88, 88 },
-                .clk            = "scif4",
+                .slave_id       = SHDMA_SLAVE_SCIF4_TX,
+                .addr           = 0xa4e40020,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x31,
         }, {
-                .mapbase        = 0xa4e50000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_3,
-                .type           = PORT_SCIFA,
-                .irqs           = { 109, 109, 109, 109 },
-                .clk            = "scif5",
+                .slave_id       = SHDMA_SLAVE_SCIF4_RX,
+                .addr           = 0xa4e40024,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x32,
         }, {
-                .flags = 0,
+                .slave_id       = SHDMA_SLAVE_SCIF5_TX,
+                .addr           = 0xa4e50020,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x35,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF5_RX,
+                .addr           = 0xa4e50024,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x36,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI0_TX,
+                .addr           = 0x04ce0030,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI0_RX,
+                .addr           = 0x04ce0030,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc2,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI1_TX,
+                .addr           = 0x04cf0030,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc9,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI1_RX,
+                .addr           = 0x04cf0030,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xca,
+        },
+};
+
+static const struct sh_dmae_channel sh7724_dmae_channels[] = {
+        {
+                .offset = 0,
+                .dmars = 0,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x10,
+                .dmars = 0,
+                .dmars_bit = 8,
+        }, {
+                .offset = 0x20,
+                .dmars = 4,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x30,
+                .dmars = 4,
+                .dmars_bit = 8,
+        }, {
+                .offset = 0x50,
+                .dmars = 8,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x60,
+                .dmars = 8,
+                .dmars_bit = 8,
         }
 };
 
-static struct platform_device sci_device = {
+static const unsigned int ts_shift[] = TS_SHIFT;
+
+static struct sh_dmae_pdata dma_platform_data = {
+        .slave          = sh7724_dmae_slaves,
+        .slave_num      = ARRAY_SIZE(sh7724_dmae_slaves),
+        .channel        = sh7724_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh7724_dmae_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+/* Resource order important! */
+static struct resource sh7724_dmae0_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xfe008020,
+                .end    = 0xfe00808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMARSx */
+                .start  = 0xfe009000,
+                .end    = 0xfe00900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMA error IRQ */
+                .start  = 78,
+                .end    = 78,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 0-3 */
+                .start  = 48,
+                .end    = 51,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 4-5 */
+                .start  = 76,
+                .end    = 77,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+/* Resource order important! */
+static struct resource sh7724_dmae1_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xfdc08020,
+                .end    = 0xfdc0808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMARSx */
+                .start  = 0xfdc09000,
+                .end    = 0xfdc0900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMA error IRQ */
+                .start  = 74,
+                .end    = 74,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 0-3 */
+                .start  = 40,
+                .end    = 43,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 4-5 */
+                .start  = 72,
+                .end    = 73,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dma0_device = {
+        .name           = "sh-dma-engine",
+        .id             = 0,
+        .resource       = sh7724_dmae0_resources,
+        .num_resources  = ARRAY_SIZE(sh7724_dmae0_resources),
+        .dev            = {
+                .platform_data  = &dma_platform_data,
+        },
+        .archdata = {
+                .hwblk_id = HWBLK_DMAC0,
+        },
+};
+
+static struct platform_device dma1_device = {
+        .name           = "sh-dma-engine",
+        .id             = 1,
+        .resource       = sh7724_dmae1_resources,
+        .num_resources  = ARRAY_SIZE(sh7724_dmae1_resources),
+        .dev            = {
+                .platform_data  = &dma_platform_data,
+        },
+        .archdata = {
+                .hwblk_id = HWBLK_DMAC1,
+        },
+};
+
+/* Serial */
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 80, 80, 80, 80 },
+};
+
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffe10000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 81, 81, 81, 81 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffe20000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 82, 82, 82, 82 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xa4e30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_3,
+        .type           = PORT_SCIFA,
+        .irqs           = { 56, 56, 56, 56 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xa4e40000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_3,
+        .type           = PORT_SCIFA,
+        .irqs           = { 88, 88, 88, 88 },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xa4e50000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_3,
+        .type           = PORT_SCIFA,
+        .irqs           = { 109, 109, 109, 109 },
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
         },
 };
 
@@ -115,6 +385,9 @@ static struct platform_device rtc_device = {
         .id             = -1,
         .num_resources  = ARRAY_SIZE(rtc_resources),
         .resource       = rtc_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_RTC,
+        },
 };
 
 /* I2C0 */
@@ -137,6 +410,9 @@ static struct platform_device iic0_device = {
         .id             = 0, /* "i2c0" clock */
         .num_resources  = ARRAY_SIZE(iic0_resources),
         .resource       = iic0_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_IIC0,
+        },
 };
 
 /* I2C1 */
@@ -159,6 +435,9 @@ static struct platform_device iic1_device = {
         .id             = 1, /* "i2c1" clock */
         .num_resources  = ARRAY_SIZE(iic1_resources),
         .resource       = iic1_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_IIC1,
+        },
 };
 
 /* VPU */
@@ -188,6 +467,9 @@ static struct platform_device vpu_device = {
         },
         .resource       = vpu_resources,
         .num_resources  = ARRAY_SIZE(vpu_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VPU,
+        },
 };
 
 /* VEU0 */
@@ -201,7 +483,7 @@ static struct resource veu0_resources[] = {
         [0] = {
                 .name   = "VEU3F0",
                 .start  = 0xfe920000,
-                .end    = 0xfe9200cb - 1,
+                .end    = 0xfe9200cb,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -217,6 +499,9 @@ static struct platform_device veu0_device = {
         },
         .resource       = veu0_resources,
         .num_resources  = ARRAY_SIZE(veu0_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VEU0,
+        },
 };
 
 /* VEU1 */
@@ -230,7 +515,7 @@ static struct resource veu1_resources[] = {
         [0] = {
                 .name   = "VEU3F1",
                 .start  = 0xfe924000,
-                .end    = 0xfe9240cb - 1,
+                .end    = 0xfe9240cb,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -246,20 +531,84 @@ static struct platform_device veu1_device = {
         },
         .resource       = veu1_resources,
         .num_resources  = ARRAY_SIZE(veu1_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_VEU1,
+        },
+};
+
+/* BEU0 */
+static struct uio_info beu0_platform_data = {
+        .name = "BEU0",
+        .version = "0",
+        .irq = evt2irq(0x8A0),
+};
+
+static struct resource beu0_resources[] = {
+        [0] = {
+                .name   = "BEU0",
+                .start  = 0xfe930000,
+                .end    = 0xfe933400,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device beu0_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 6,
+        .dev = {
+                .platform_data  = &beu0_platform_data,
+        },
+        .resource       = beu0_resources,
+        .num_resources  = ARRAY_SIZE(beu0_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_BEU0,
+        },
+};
+
+/* BEU1 */
+static struct uio_info beu1_platform_data = {
+        .name = "BEU1",
+        .version = "0",
+        .irq = evt2irq(0xA00),
+};
+
+static struct resource beu1_resources[] = {
+        [0] = {
+                .name   = "BEU1",
+                .start  = 0xfe940000,
+                .end    = 0xfe943400,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device beu1_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 7,
+        .dev = {
+                .platform_data  = &beu1_platform_data,
+        },
+        .resource       = beu1_resources,
+        .num_resources  = ARRAY_SIZE(beu1_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_BEU1,
+        },
 };
 
 static struct sh_timer_config cmt_platform_data = {
-        .name = "CMT",
         .channel_offset = 0x60,
         .timer_bit = 5,
-        .clk = "cmt0",
         .clockevent_rating = 125,
         .clocksource_rating = 200,
 };
 
 static struct resource cmt_resources[] = {
         [0] = {
-                .name   = "CMT",
                 .start  = 0x044a0060,
                 .end    = 0x044a006b,
                 .flags  = IORESOURCE_MEM,
@@ -278,19 +627,19 @@ static struct platform_device cmt_device = {
         },
         .resource       = cmt_resources,
         .num_resources  = ARRAY_SIZE(cmt_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_CMT,
+        },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "tmu0",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -309,19 +658,19 @@ static struct platform_device tmu0_device = {
         },
         .resource       = tmu0_resources,
         .num_resources  = ARRAY_SIZE(tmu0_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU0,
+        },
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "tmu0",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -340,18 +689,18 @@ static struct platform_device tmu1_device = {
         },
         .resource       = tmu1_resources,
         .num_resources  = ARRAY_SIZE(tmu1_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU0,
+        },
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "tmu0",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002b,
                 .flags  = IORESOURCE_MEM,
@@ -370,19 +719,19 @@ static struct platform_device tmu2_device = {
         },
         .resource       = tmu2_resources,
         .num_resources  = ARRAY_SIZE(tmu2_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU0,
+        },
 };
 
 
 static struct sh_timer_config tmu3_platform_data = {
-        .name = "TMU3",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "tmu1",
 };
 
 static struct resource tmu3_resources[] = {
         [0] = {
-                .name   = "TMU3",
                 .start  = 0xffd90008,
                 .end    = 0xffd90013,
                 .flags  = IORESOURCE_MEM,
@@ -401,18 +750,18 @@ static struct platform_device tmu3_device = {
         },
         .resource       = tmu3_resources,
         .num_resources  = ARRAY_SIZE(tmu3_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU1,
+        },
 };
 
 static struct sh_timer_config tmu4_platform_data = {
-        .name = "TMU4",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "tmu1",
 };
 
 static struct resource tmu4_resources[] = {
         [0] = {
-                .name   = "TMU4",
                 .start  = 0xffd90014,
                 .end    = 0xffd9001f,
                 .flags  = IORESOURCE_MEM,
@@ -431,18 +780,18 @@ static struct platform_device tmu4_device = {
         },
         .resource       = tmu4_resources,
         .num_resources  = ARRAY_SIZE(tmu4_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU1,
+        },
 };
 
 static struct sh_timer_config tmu5_platform_data = {
-        .name = "TMU5",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "tmu1",
 };
 
 static struct resource tmu5_resources[] = {
         [0] = {
-                .name   = "TMU5",
                 .start  = 0xffd90020,
                 .end    = 0xffd9002b,
                 .flags  = IORESOURCE_MEM,
@@ -461,6 +810,9 @@ static struct platform_device tmu5_device = {
         },
         .resource       = tmu5_resources,
         .num_resources  = ARRAY_SIZE(tmu5_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_TMU1,
+        },
 };
 
 /* JPU */
@@ -490,9 +842,82 @@ static struct platform_device jpu_device = {
         },
         .resource       = jpu_resources,
         .num_resources  = ARRAY_SIZE(jpu_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_JPU,
+        },
+};
+
+/* SPU2DSP0 */
+static struct uio_info spu0_platform_data = {
+        .name = "SPU2DSP0",
+        .version = "0",
+        .irq = 86,
+};
+
+static struct resource spu0_resources[] = {
+        [0] = {
+                .name   = "SPU2DSP0",
+                .start  = 0xFE200000,
+                .end    = 0xFE2FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device spu0_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &spu0_platform_data,
+        },
+        .resource       = spu0_resources,
+        .num_resources  = ARRAY_SIZE(spu0_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_SPU,
+        },
+};
+
+/* SPU2DSP1 */
+static struct uio_info spu1_platform_data = {
+        .name = "SPU2DSP1",
+        .version = "0",
+        .irq = 87,
+};
+
+static struct resource spu1_resources[] = {
+        [0] = {
+                .name   = "SPU2DSP1",
+                .start  = 0xFE300000,
+                .end    = 0xFE3FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device spu1_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 5,
+        .dev = {
+                .platform_data  = &spu1_platform_data,
+        },
+        .resource       = spu1_resources,
+        .num_resources  = ARRAY_SIZE(spu1_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_SPU,
+        },
 };
 
 static struct platform_device *sh7724_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
@@ -500,14 +925,19 @@ static struct platform_device *sh7724_devices[] __initdata = {
         &tmu3_device,
         &tmu4_device,
         &tmu5_device,
-        &sci_device,
+        &dma0_device,
+        &dma1_device,
         &rtc_device,
         &iic0_device,
         &iic1_device,
         &vpu_device,
         &veu0_device,
         &veu1_device,
+        &beu0_device,
+        &beu1_device,
         &jpu_device,
+        &spu0_device,
+        &spu1_device,
 };
 
 static int __init sh7724_devices_setup(void)
@@ -516,13 +946,21 @@ static int __init sh7724_devices_setup(void)
         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
         platform_resource_setup_memory(&jpu_device,  "jpu",  2 << 20);
+        platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
+        platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
 
         return platform_add_devices(sh7724_devices,
                                     ARRAY_SIZE(sh7724_devices));
 }
-device_initcall(sh7724_devices_setup);
+arch_initcall(sh7724_devices_setup);
 
 static struct platform_device *sh7724_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &cmt_device,
         &tmu0_device,
         &tmu1_device,
@@ -541,14 +979,17 @@ void __init plat_early_device_setup(void)
 #define RAMCR_CACHE_L2FC        0x0002
 #define RAMCR_CACHE_L2E         0x0001
 #define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
-void __uses_jump_to_uncached l2_cache_init(void)
+
+void l2_cache_init(void)
 {
         /* Enable L2 cache */
-        ctrl_outl(L2_CACHE_ENABLE, RAMCR);
+        __raw_writel(L2_CACHE_ENABLE, RAMCR);
 }
 
 enum {
         UNUSED = 0,
+        ENABLED,
+        DISABLED,
 
         /* interrupt sources */
         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -577,14 +1018,12 @@ enum {
         ETHI,
         I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
         I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
-        SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3,
         CMT,
         TSIF,
         FSI,
         SCIFA5,
         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
         IRDA,
-        SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
         JPU,
         _2DDMAC,
         MMC_MMC2I, MMC_MMC3I,
@@ -666,10 +1105,10 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(I2C0_WAITI, 0xE40),
         INTC_VECT(I2C0_DTEI, 0xE60),
 
-        INTC_VECT(SDHI0_SDHII0, 0xE80),
-        INTC_VECT(SDHI0_SDHII1, 0xEA0),
-        INTC_VECT(SDHI0_SDHII2, 0xEC0),
-        INTC_VECT(SDHI0_SDHII3, 0xEE0),
+        INTC_VECT(SDHI0, 0xE80),
+        INTC_VECT(SDHI0, 0xEA0),
+        INTC_VECT(SDHI0, 0xEC0),
+        INTC_VECT(SDHI0, 0xEE0),
 
         INTC_VECT(CMT,    0xF00),
         INTC_VECT(TSIF,   0xF20),
@@ -682,9 +1121,9 @@ static struct intc_vect vectors[] __initdata = {
 
         INTC_VECT(IRDA,    0x480),
 
-        INTC_VECT(SDHI1_SDHII0, 0x4E0),
-        INTC_VECT(SDHI1_SDHII1, 0x500),
-        INTC_VECT(SDHI1_SDHII2, 0x520),
+        INTC_VECT(SDHI1, 0x4E0),
+        INTC_VECT(SDHI1, 0x500),
+        INTC_VECT(SDHI1, 0x520),
 
         INTC_VECT(JPU, 0x560),
         INTC_VECT(_2DDMAC, 0x4A0),
@@ -710,8 +1149,6 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
         INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
         INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
-        INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3),
-        INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
         INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
         INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
 };
@@ -719,7 +1156,7 @@ static struct intc_group groups[] __initdata = {
 static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
           { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
-            0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
+            0, DISABLED, ENABLED, ENABLED } },
         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
           { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
             DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
@@ -741,7 +1178,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
             I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
+          { DISABLED, DISABLED, ENABLED, ENABLED,
             0, 0, SCIFA5, FSI } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
@@ -788,11 +1225,205 @@ static struct intc_mask_reg ack_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
-                             mask_registers, prio_registers, sense_registers,
-                             ack_registers);
+static struct intc_desc intc_desc __initdata = {
+        .name = "sh7724",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(vectors, groups, mask_registers,
+                           prio_registers, sense_registers, ack_registers),
+};
 
 void __init plat_irq_setup(void)
 {
         register_intc_controller(&intc_desc);
 }
+
+static struct {
+        /* BSC */
+        unsigned long mmselr;
+        unsigned long cs0bcr;
+        unsigned long cs4bcr;
+        unsigned long cs5abcr;
+        unsigned long cs5bbcr;
+        unsigned long cs6abcr;
+        unsigned long cs6bbcr;
+        unsigned long cs4wcr;
+        unsigned long cs5awcr;
+        unsigned long cs5bwcr;
+        unsigned long cs6awcr;
+        unsigned long cs6bwcr;
+        /* INTC */
+        unsigned short ipra;
+        unsigned short iprb;
+        unsigned short iprc;
+        unsigned short iprd;
+        unsigned short ipre;
+        unsigned short iprf;
+        unsigned short iprg;
+        unsigned short iprh;
+        unsigned short ipri;
+        unsigned short iprj;
+        unsigned short iprk;
+        unsigned short iprl;
+        unsigned char imr0;
+        unsigned char imr1;
+        unsigned char imr2;
+        unsigned char imr3;
+        unsigned char imr4;
+        unsigned char imr5;
+        unsigned char imr6;
+        unsigned char imr7;
+        unsigned char imr8;
+        unsigned char imr9;
+        unsigned char imr10;
+        unsigned char imr11;
+        unsigned char imr12;
+        /* RWDT */
+        unsigned short rwtcnt;
+        unsigned short rwtcsr;
+        /* CPG */
+        unsigned long irdaclk;
+        unsigned long spuclk;
+} sh7724_rstandby_state;
+
+static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
+                                          unsigned long flags, void *unused)
+{
+        if (!(flags & SUSP_SH_RSTANDBY))
+                return NOTIFY_DONE;
+
+        /* BCR */
+        sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
+        sh7724_rstandby_state.mmselr |= 0xa5a50000;
+        sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
+        sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
+        sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
+        sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
+        sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
+        sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
+        sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
+        sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
+        sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
+        sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
+        sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
+
+        /* INTC */
+        sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
+        sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
+        sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
+        sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
+        sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
+        sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
+        sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
+        sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
+        sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
+        sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
+        sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
+        sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
+        sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
+        sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
+        sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
+        sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
+        sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
+        sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
+        sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
+        sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
+        sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
+        sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
+        sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
+        sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
+        sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
+
+        /* RWDT */
+        sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
+        sh7724_rstandby_state.rwtcnt |= 0x5a00;
+        sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
+        sh7724_rstandby_state.rwtcsr |= 0xa500;
+        __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
+
+        /* CPG */
+        sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
+        sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
+
+        return NOTIFY_DONE;
+}
+
+static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
+                                           unsigned long flags, void *unused)
+{
+        if (!(flags & SUSP_SH_RSTANDBY))
+                return NOTIFY_DONE;
+
+        /* BCR */
+        __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
+        __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
+        __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
+        __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
+        __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
+        __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
+        __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
+        __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
+        __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
+        __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
+        __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
+        __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
+
+        /* INTC */
+        __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
+        __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
+        __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
+        __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
+        __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
+        __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
+        __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
+        __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
+        __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
+        __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
+        __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
+        __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
+        __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
+        __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
+        __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
+        __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
+        __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
+        __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
+        __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
+        __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
+        __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
+        __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
+        __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
+        __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
+        __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
+
+        /* RWDT */
+        __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
+        __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
+
+        /* CPG */
+        __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
+        __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
+
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block sh7724_pre_sleep_notifier = {
+        .notifier_call = sh7724_pre_sleep_notifier_call,
+        .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
+};
+
+static struct notifier_block sh7724_post_sleep_notifier = {
+        .notifier_call = sh7724_post_sleep_notifier_call,
+        .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
+};
+
+static int __init sh7724_sleep_setup(void)
+{
+        atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
+                                       &sh7724_pre_sleep_notifier);
+
+        atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
+                                       &sh7724_post_sleep_notifier);
+        return 0;
+}
+arch_initcall(sh7724_sleep_setup);
+
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
new file mode 100644
index 000000000000..9c1de2633ac3
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -0,0 +1,623 @@
+/*
+ * SH7757 Setup
+ *
+ * Copyright (C) 2009  Renesas Solutions Corp.
+ *
+ *  based on setup-sh7785.c : Copyright (C) 2007  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/serial_sci.h>
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/sh_timer.h>
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xfe4b0000,           /* SCIF2 */
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 40, 40, 40 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xfe4c0000,           /* SCIF3 */
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 76, 76, 76, 76 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xfe4d0000,           /* SCIF4 */
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 104, 104, 104, 104 },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct sh_timer_config tmu0_platform_data = {
+        .channel_offset = 0x04,
+        .timer_bit = 0,
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu0_resources[] = {
+        [0] = {
+                .start  = 0xfe430008,
+                .end    = 0xfe430013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 28,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu0_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu0_platform_data,
+        },
+        .resource       = tmu0_resources,
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
+};
+
+static struct sh_timer_config tmu1_platform_data = {
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu1_resources[] = {
+        [0] = {
+                .start  = 0xfe430014,
+                .end    = 0xfe43001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 29,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu1_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu1_platform_data,
+        },
+        .resource       = tmu1_resources,
+        .num_resources  = ARRAY_SIZE(tmu1_resources),
+};
+
+static struct platform_device *sh7757_devices[] __initdata = {
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &tmu0_device,
+        &tmu1_device,
+};
+
+static int __init sh7757_devices_setup(void)
+{
+        return platform_add_devices(sh7757_devices,
+                                    ARRAY_SIZE(sh7757_devices));
+}
+arch_initcall(sh7757_devices_setup);
+
+static struct platform_device *sh7757_early_devices[] __initdata = {
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &tmu0_device,
+        &tmu1_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7757_early_devices,
+                                   ARRAY_SIZE(sh7757_early_devices));
+}
+
+enum {
+        UNUSED = 0,
+
+        /* interrupt sources */
+
+        IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
+        IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
+        IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
+        IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
+
+        IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
+        IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
+        IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
+        IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
+        IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+
+        SDHI, DVC,
+        IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
+        TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
+        HUDI,
+        ARC4,
+        DMAC0_5, DMAC6_7, DMAC8_11,
+        SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
+        USB0, USB1,
+        JMC,
+        SPI0, SPI1,
+        TMR01, TMR23, TMR45,
+        FRT,
+        LPC, LPC5, LPC6, LPC7, LPC8,
+        PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
+        ETHERC,
+        ADC0, ADC1,
+        SIM,
+        IIC0_0, IIC0_1, IIC0_2, IIC0_3,
+        IIC1_0, IIC1_1, IIC1_2, IIC1_3,
+        IIC2_0, IIC2_1, IIC2_2, IIC2_3,
+        IIC3_0, IIC3_1, IIC3_2, IIC3_3,
+        IIC4_0, IIC4_1, IIC4_2, IIC4_3,
+        IIC5_0, IIC5_1, IIC5_2, IIC5_3,
+        IIC6_0, IIC6_1, IIC6_2, IIC6_3,
+        IIC7_0, IIC7_1, IIC7_2, IIC7_3,
+        IIC8_0, IIC8_1, IIC8_2, IIC8_3,
+        IIC9_0, IIC9_1, IIC9_2, IIC9_3,
+        ONFICTL,
+        MMC1, MMC2,
+        ECCU,
+        PCIC,
+        G200,
+        RSPI,
+        SGPIO,
+        DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
+        DMINT20, DMINT21, DMINT22, DMINT23,
+        DDRECC,
+        TSIP,
+        PCIE_BRIDGE,
+        WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
+        GETHER0, GETHER1, GETHER2,
+        PBIA, PBIB, PBIC,
+        DMAE2, DMAE3,
+        SERMUX2, SERMUX3,
+
+        /* interrupt groups */
+
+        TMU012, TMU345,
+};
+
+static struct intc_vect vectors[] __initdata = {
+        INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
+        INTC_VECT(SDHI, 0x4c0),
+        INTC_VECT(DVC, 0x4e0),
+        INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
+        INTC_VECT(IRQ10, 0x540),
+        INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
+        INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
+        INTC_VECT(HUDI, 0x600),
+        INTC_VECT(ARC4, 0x620),
+        INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
+        INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
+        INTC_VECT(DMAC0_5, 0x6c0),
+        INTC_VECT(IRQ11, 0x6e0),
+        INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
+        INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
+        INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
+        INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
+        INTC_VECT(USB0, 0x840),
+        INTC_VECT(IRQ12, 0x880),
+        INTC_VECT(JMC, 0x8a0),
+        INTC_VECT(SPI1, 0x8c0),
+        INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
+        INTC_VECT(USB1, 0x920),
+        INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
+        INTC_VECT(TMR45, 0xa40),
+        INTC_VECT(FRT, 0xa80),
+        INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
+        INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
+        INTC_VECT(LPC, 0xb20),
+        INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
+        INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
+        INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
+        INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
+        INTC_VECT(PECI2, 0xc40),
+        INTC_VECT(IRQ15, 0xc60),
+        INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
+        INTC_VECT(SPI0, 0xcc0),
+        INTC_VECT(ADC1, 0xce0),
+        INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
+        INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
+        INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
+        INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
+        INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
+        INTC_VECT(TMU5, 0xe40),
+        INTC_VECT(ADC0, 0xe60),
+        INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
+        INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
+        INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
+        INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
+        INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
+        INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
+        INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
+        INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
+        INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
+        INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
+        INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
+        INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
+        INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
+        INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
+        INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
+        INTC_VECT(IIC6_2, 0x1920),
+        INTC_VECT(ONFICTL, 0x1960),
+        INTC_VECT(IIC6_3, 0x1980),
+        INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
+        INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
+        INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
+        INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
+        INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
+        INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
+        INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
+        INTC_VECT(ECCU, 0x1cc0),
+        INTC_VECT(PCIC, 0x1ce0),
+        INTC_VECT(G200, 0x1d00),
+        INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
+        INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
+        INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
+        INTC_VECT(PECI5, 0x1f00),
+        INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
+        INTC_VECT(SGPIO, 0x1fc0),
+        INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
+        INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
+        INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
+        INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
+        INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
+        INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
+        INTC_VECT(DDRECC, 0x2620),
+        INTC_VECT(TSIP, 0x2640),
+        INTC_VECT(PCIE_BRIDGE, 0x27c0),
+        INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
+        INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
+        INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
+        INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
+        INTC_VECT(WDT8B, 0x2900),
+        INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
+        INTC_VECT(GETHER2, 0x29a0),
+        INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
+        INTC_VECT(PBIC, 0x2a40),
+        INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
+        INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
+        INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
+        INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
+};
+
+static struct intc_group groups[] __initdata = {
+        INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
+        INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
+};
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+        { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+
+        { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
+          { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
+            IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
+            IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
+            IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
+            IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
+            IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
+            IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
+            IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
+
+        { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
+          { 0, 0, 0, 0, 0, 0, 0, 0,
+            0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
+            TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
+            HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
+             } },
+
+        { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
+          { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
+            IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
+            ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
+            ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
+             } },
+
+        { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
+          { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
+            0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
+            IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
+            IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
+             } },
+
+        { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
+          { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
+            IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
+            PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
+            IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
+             } },
+
+        { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
+          { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
+            0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
+            PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
+            DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
+             } },
+
+        { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
+          { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
+            DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
+            0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
+            DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
+             } },
+};
+
+#define INTPRI          0xffd00010
+#define INT2PRI0        0xffd40000
+#define INT2PRI1        0xffd40004
+#define INT2PRI2        0xffd40008
+#define INT2PRI3        0xffd4000c
+#define INT2PRI4        0xffd40010
+#define INT2PRI5        0xffd40014
+#define INT2PRI6        0xffd40018
+#define INT2PRI7        0xffd4001c
+#define INT2PRI8        0xffd400a0
+#define INT2PRI9        0xffd400a4
+#define INT2PRI10       0xffd400a8
+#define INT2PRI11       0xffd400ac
+#define INT2PRI12       0xffd400b0
+#define INT2PRI13       0xffd400b4
+#define INT2PRI14       0xffd400b8
+#define INT2PRI15       0xffd400bc
+#define INT2PRI16       0xffd10000
+#define INT2PRI17       0xffd10004
+#define INT2PRI18       0xffd10008
+#define INT2PRI19       0xffd1000c
+#define INT2PRI20       0xffd10010
+#define INT2PRI21       0xffd10014
+#define INT2PRI22       0xffd10018
+#define INT2PRI23       0xffd1001c
+#define INT2PRI24       0xffd100a0
+#define INT2PRI25       0xffd100a4
+#define INT2PRI26       0xffd100a8
+#define INT2PRI27       0xffd100ac
+#define INT2PRI28       0xffd100b0
+#define INT2PRI29       0xffd100b4
+#define INT2PRI30       0xffd100b8
+#define INT2PRI31       0xffd100bc
+#define INT2PRI32       0xffd20000
+#define INT2PRI33       0xffd20004
+#define INT2PRI34       0xffd20008
+#define INT2PRI35       0xffd2000c
+#define INT2PRI36       0xffd20010
+#define INT2PRI37       0xffd20014
+#define INT2PRI38       0xffd20018
+#define INT2PRI39       0xffd2001c
+#define INT2PRI40       0xffd200a0
+#define INT2PRI41       0xffd200a4
+#define INT2PRI42       0xffd200a8
+#define INT2PRI43       0xffd200ac
+#define INT2PRI44       0xffd200b0
+#define INT2PRI45       0xffd200b4
+#define INT2PRI46       0xffd200b8
+#define INT2PRI47       0xffd200bc
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+        { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
+                              IRQ4, IRQ5, IRQ6, IRQ7 } },
+
+        { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
+        { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
+        { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
+        { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
+        { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
+        { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
+        { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
+        { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
+        { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
+        { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
+        { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
+        { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
+        { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
+        { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
+
+        { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
+        { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
+        { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
+        { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
+        { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
+        { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
+        { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
+        { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
+        { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
+        { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
+        { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
+        { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
+        { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
+        { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
+        { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
+        { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
+        { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
+        { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
+        { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
+        { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
+        { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
+        { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
+        { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
+        { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
+        { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
+        { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
+        { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
+        { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
+        { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
+        { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
+        { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
+        { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
+};
+
+static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
+        { 0xffd100f8, 32, 2, /* ICR2 */   { IRQ15, IRQ14, IRQ13, IRQ12,
+                                            IRQ11, IRQ10, IRQ9, IRQ8 } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
+                         mask_registers, prio_registers,
+                         sense_registers_irq8to15);
+
+/* Support for external interrupt pins in IRQ mode */
+static struct intc_vect vectors_irq0123[] __initdata = {
+        INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
+        INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
+};
+
+static struct intc_vect vectors_irq4567[] __initdata = {
+        INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
+        INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
+};
+
+static struct intc_sense_reg sense_registers[] __initdata = {
+        { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
+                                            IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_mask_reg ack_registers[] __initdata = {
+        { 0xffd00024, 0, 32, /* INTREQ */
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
+                             vectors_irq0123, NULL, mask_registers,
+                             prio_registers, sense_registers, ack_registers);
+
+static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
+                             vectors_irq4567, NULL, mask_registers,
+                             prio_registers, sense_registers, ack_registers);
+
+/* External interrupt pins in IRL mode */
+static struct intc_vect vectors_irl0123[] __initdata = {
+        INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
+        INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
+        INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
+        INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
+        INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
+        INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
+        INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
+        INTC_VECT(IRL0_HHHL, 0x3c0),
+};
+
+static struct intc_vect vectors_irl4567[] __initdata = {
+        INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
+        INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
+        INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
+        INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
+        INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
+        INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
+        INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
+        INTC_VECT(IRL4_HHHL, 0xcc0),
+};
+
+static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
+                         NULL, mask_registers, NULL, NULL);
+
+static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
+                         NULL, mask_registers, NULL, NULL);
+
+#define INTC_ICR0       0xffd00000
+#define INTC_INTMSK0    0xffd00044
+#define INTC_INTMSK1    0xffd00048
+#define INTC_INTMSK2    0xffd40080
+#define INTC_INTMSKCLR1 0xffd00068
+#define INTC_INTMSKCLR2 0xffd40084
+
+void __init plat_irq_setup(void)
+{
+        /* disable IRQ3-0 + IRQ7-4 */
+        __raw_writel(0xff000000, INTC_INTMSK0);
+
+        /* disable IRL3-0 + IRL7-4 */
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
+
+        /* select IRL mode for IRL3-0 + IRL7-4 */
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+
+        /* disable holding function, ie enable "SH-4 Mode" */
+        __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+
+        register_intc_controller(&intc_desc);
+}
+
+void __init plat_irq_setup_pins(int mode)
+{
+        switch (mode) {
+        case IRQ_MODE_IRQ7654:
+                /* select IRQ mode for IRL7-4 */
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
+                register_intc_controller(&intc_desc_irq4567);
+                break;
+        case IRQ_MODE_IRQ3210:
+                /* select IRQ mode for IRL3-0 */
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
+                register_intc_controller(&intc_desc_irq0123);
+                break;
+        case IRQ_MODE_IRL7654:
+                /* enable IRL7-4 but don't provide any masking */
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
+                break;
+        case IRQ_MODE_IRL3210:
+                /* enable IRL0-3 but don't provide any masking */
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
+                break;
+        case IRQ_MODE_IRL7654_MASK:
+                /* enable IRL7-4 and mask using cpu intc controller */
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                register_intc_controller(&intc_desc_irl4567);
+                break;
+        case IRQ_MODE_IRL3210_MASK:
+                /* enable IRL0-3 and mask using cpu intc controller */
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                register_intc_controller(&intc_desc_irl0123);
+                break;
+        default:
+                BUG();
+        }
+}
+
+void __init plat_mem_setup(void)
+{
+}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index ab02771ee888..593eca6509b5 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -16,6 +16,57 @@
 #include <linux/io.h>
 #include <linux/serial_sci.h>
 
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 40, 40, 40 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffe08000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 76, 76, 76, 76 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffe10000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 104, 104, 104, 104 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
 static struct resource rtc_resources[] = {
         [0] = {
                 .start  = 0xffe80000,
@@ -36,41 +87,6 @@ static struct platform_device rtc_device = {
         .resource       = rtc_resources,
 };
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 40, 40, 40 },
-        }, {
-                .mapbase        = 0xffe08000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 76, 76, 76, 76 },
-        }, {
-                .mapbase        = 0xffe10000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 104, 104, 104, 104 },
-        }, {
-                .flags = 0,
-        }
-};
-
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = sci_platform_data,
-        },
-};
-
 static struct resource usb_ohci_resources[] = {
         [0] = {
                 .start  = 0xffec8000,
@@ -121,16 +137,13 @@ static struct platform_device usbf_device = {
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -152,16 +165,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -183,15 +193,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002f,
                 .flags  = IORESOURCE_MEM,
@@ -213,15 +220,12 @@ static struct platform_device tmu2_device = {
 };
 
 static struct sh_timer_config tmu3_platform_data = {
-        .name = "TMU3",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu3_resources[] = {
         [0] = {
-                .name   = "TMU3",
                 .start  = 0xffd88008,
                 .end    = 0xffd88013,
                 .flags  = IORESOURCE_MEM,
@@ -243,15 +247,12 @@ static struct platform_device tmu3_device = {
 };
 
 static struct sh_timer_config tmu4_platform_data = {
-        .name = "TMU4",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu4_resources[] = {
         [0] = {
-                .name   = "TMU4",
                 .start  = 0xffd88014,
                 .end    = 0xffd8801f,
                 .flags  = IORESOURCE_MEM,
@@ -273,15 +274,12 @@ static struct platform_device tmu4_device = {
 };
 
 static struct sh_timer_config tmu5_platform_data = {
-        .name = "TMU5",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu5_resources[] = {
         [0] = {
-                .name   = "TMU5",
                 .start  = 0xffd88020,
                 .end    = 0xffd8802b,
                 .flags  = IORESOURCE_MEM,
@@ -303,6 +301,9 @@ static struct platform_device tmu5_device = {
 };
 
 static struct platform_device *sh7763_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -310,7 +311,6 @@ static struct platform_device *sh7763_devices[] __initdata = {
         &tmu4_device,
         &tmu5_device,
         &rtc_device,
-        &sci_device,
         &usb_ohci_device,
         &usbf_device,
 };
@@ -320,9 +320,12 @@ static int __init sh7763_devices_setup(void)
         return platform_add_devices(sh7763_devices,
                                     ARRAY_SIZE(sh7763_devices));
 }
-__initcall(sh7763_devices_setup);
+arch_initcall(sh7763_devices_setup);
 
 static struct platform_device *sh7763_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -523,11 +526,11 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ7-0 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         register_intc_controller(&intc_desc);
 }
@@ -537,27 +540,27 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ:
                 /* select IRQ mode for IRL3-0 + IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
                 register_intc_controller(&intc_irq_desc);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl7654_desc);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl3210_desc);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 746f4fb9ccf0..2c6aa22cf5f6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -14,101 +14,184 @@
 #include <linux/sh_timer.h>
 #include <linux/io.h>
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xff923000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 61, 61, 61, 61 },
-        }, {
-                .mapbase        = 0xff924000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 62, 62, 62, 62 },
-        }, {
-                .mapbase        = 0xff925000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 63, 63, 63, 63 },
-        }, {
-                .mapbase        = 0xff926000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 64, 64, 64, 64 },
-        }, {
-                .mapbase        = 0xff927000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 65, 65, 65, 65 },
-        }, {
-                .mapbase        = 0xff928000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 66, 66, 66, 66 },
-        }, {
-                .mapbase        = 0xff929000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 67, 67, 67, 67 },
-        }, {
-                .mapbase        = 0xff92a000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 68, 68, 68, 68 },
-        }, {
-                .mapbase        = 0xff92b000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 69, 69, 69, 69 },
-        }, {
-                .mapbase        = 0xff92c000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 70, 70, 70, 70 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xff923000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 61, 61, 61, 61 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xff924000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 62, 62, 62, 62 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xff925000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 63, 63, 63, 63 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xff926000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 64, 64, 64, 64 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xff927000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 65, 65, 65, 65 },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xff928000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 66, 66, 66, 66 },
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
+static struct plat_sci_port scif6_platform_data = {
+        .mapbase        = 0xff929000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 67, 67, 67, 67 },
+};
+
+static struct platform_device scif6_device = {
+        .name           = "sh-sci",
+        .id             = 6,
+        .dev            = {
+                .platform_data  = &scif6_platform_data,
+        },
+};
+
+static struct plat_sci_port scif7_platform_data = {
+        .mapbase        = 0xff92a000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 68, 68, 68, 68 },
+};
+
+static struct platform_device scif7_device = {
+        .name           = "sh-sci",
+        .id             = 7,
+        .dev            = {
+                .platform_data  = &scif7_platform_data,
+        },
+};
+
+static struct plat_sci_port scif8_platform_data = {
+        .mapbase        = 0xff92b000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 69, 69, 69, 69 },
+};
+
+static struct platform_device scif8_device = {
+        .name           = "sh-sci",
+        .id             = 8,
+        .dev            = {
+                .platform_data  = &scif8_platform_data,
+        },
+};
+
+static struct plat_sci_port scif9_platform_data = {
+        .mapbase        = 0xff92c000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 70, 70, 70, 70 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif9_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 9,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif9_platform_data,
         },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -130,16 +213,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -161,15 +241,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002f,
                 .flags  = IORESOURCE_MEM,
@@ -191,15 +268,12 @@ static struct platform_device tmu2_device = {
 };
 
 static struct sh_timer_config tmu3_platform_data = {
-        .name = "TMU3",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu3_resources[] = {
         [0] = {
-                .name   = "TMU3",
                 .start  = 0xffd81008,
                 .end    = 0xffd81013,
                 .flags  = IORESOURCE_MEM,
@@ -221,15 +295,12 @@ static struct platform_device tmu3_device = {
 };
 
 static struct sh_timer_config tmu4_platform_data = {
-        .name = "TMU4",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu4_resources[] = {
         [0] = {
-                .name   = "TMU4",
                 .start  = 0xffd81014,
                 .end    = 0xffd8101f,
                 .flags  = IORESOURCE_MEM,
@@ -251,15 +322,12 @@ static struct platform_device tmu4_device = {
 };
 
 static struct sh_timer_config tmu5_platform_data = {
-        .name = "TMU5",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu5_resources[] = {
         [0] = {
-                .name   = "TMU5",
                 .start  = 0xffd81020,
                 .end    = 0xffd8102f,
                 .flags  = IORESOURCE_MEM,
@@ -281,15 +349,12 @@ static struct platform_device tmu5_device = {
 };
 
 static struct sh_timer_config tmu6_platform_data = {
-        .name = "TMU6",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu6_resources[] = {
         [0] = {
-                .name   = "TMU6",
                 .start  = 0xffd82008,
                 .end    = 0xffd82013,
                 .flags  = IORESOURCE_MEM,
@@ -311,15 +376,12 @@ static struct platform_device tmu6_device = {
 };
 
 static struct sh_timer_config tmu7_platform_data = {
-        .name = "TMU7",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu7_resources[] = {
         [0] = {
-                .name   = "TMU7",
                 .start  = 0xffd82014,
                 .end    = 0xffd8201f,
                 .flags  = IORESOURCE_MEM,
@@ -341,15 +403,12 @@ static struct platform_device tmu7_device = {
 };
 
 static struct sh_timer_config tmu8_platform_data = {
-        .name = "TMU8",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu8_resources[] = {
         [0] = {
-                .name   = "TMU8",
                 .start  = 0xffd82020,
                 .end    = 0xffd8202b,
                 .flags  = IORESOURCE_MEM,
@@ -371,6 +430,16 @@ static struct platform_device tmu8_device = {
 };
 
 static struct platform_device *sh7770_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &scif7_device,
+        &scif8_device,
+        &scif9_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -380,7 +449,6 @@ static struct platform_device *sh7770_devices[] __initdata = {
         &tmu6_device,
         &tmu7_device,
         &tmu8_device,
-        &sci_device,
 };
 
 static int __init sh7770_devices_setup(void)
@@ -388,9 +456,19 @@ static int __init sh7770_devices_setup(void)
         return platform_add_devices(sh7770_devices,
                                     ARRAY_SIZE(sh7770_devices));
 }
-__initcall(sh7770_devices_setup);
+arch_initcall(sh7770_devices_setup);
 
 static struct platform_device *sh7770_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &scif7_device,
+        &scif8_device,
+        &scif9_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -609,17 +687,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ7-0 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         /* disable holding function, ie enable "SH-4 Mode" */
-        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -629,27 +707,27 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ:
                 /* select IRQ mode for IRL3-0 + IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
                 register_intc_controller(&intc_irq_desc);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl7654_desc);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl3210_desc);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index bcd411eb9cb0..08add7fa6849 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -12,19 +12,53 @@
 #include <linux/serial.h>
 #include <linux/io.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
 
+#include <cpu/dma-register.h>
+
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffe00000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 40, 40, 40 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffe10000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 76, 76, 76, 76 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -46,16 +80,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -77,15 +108,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002f,
                 .flags  = IORESOURCE_MEM,
@@ -107,15 +135,12 @@ static struct platform_device tmu2_device = {
 };
 
 static struct sh_timer_config tmu3_platform_data = {
-        .name = "TMU3",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu3_resources[] = {
         [0] = {
-                .name   = "TMU3",
                 .start  = 0xffdc0008,
                 .end    = 0xffdc0013,
                 .flags  = IORESOURCE_MEM,
@@ -137,15 +162,12 @@ static struct platform_device tmu3_device = {
 };
 
 static struct sh_timer_config tmu4_platform_data = {
-        .name = "TMU4",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu4_resources[] = {
         [0] = {
-                .name   = "TMU4",
                 .start  = 0xffdc0014,
                 .end    = 0xffdc001f,
                 .flags  = IORESOURCE_MEM,
@@ -167,15 +189,12 @@ static struct platform_device tmu4_device = {
 };
 
 static struct sh_timer_config tmu5_platform_data = {
-        .name = "TMU5",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu5_resources[] = {
         [0] = {
-                .name   = "TMU5",
                 .start  = 0xffdc0020,
                 .end    = 0xffdc002b,
                 .flags  = IORESOURCE_MEM,
@@ -216,35 +235,137 @@ static struct platform_device rtc_device = {
         .resource       = rtc_resources,
 };
 
-static struct plat_sci_port sci_platform_data[] = {
+/* DMA */
+static const struct sh_dmae_channel sh7780_dmae0_channels[] = {
         {
-                .mapbase        = 0xffe00000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 40, 40, 40 },
+                .offset = 0,
+                .dmars = 0,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x10,
+                .dmars = 0,
+                .dmars_bit = 8,
+        }, {
+                .offset = 0x20,
+                .dmars = 4,
+                .dmars_bit = 0,
         }, {
-                .mapbase        = 0xffe10000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 76, 76, 76, 76 },
+                .offset = 0x30,
+                .dmars = 4,
+                .dmars_bit = 8,
         }, {
-                .flags = 0,
+                .offset = 0x50,
+                .dmars = 8,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x60,
+                .dmars = 8,
+                .dmars_bit = 8,
         }
 };
 
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
+static const struct sh_dmae_channel sh7780_dmae1_channels[] = {
+        {
+                .offset = 0,
+        }, {
+                .offset = 0x10,
+        }, {
+                .offset = 0x20,
+        }, {
+                .offset = 0x30,
+        }, {
+                .offset = 0x50,
+        }, {
+                .offset = 0x60,
+        }
+};
+
+static const unsigned int ts_shift[] = TS_SHIFT;
+
+static struct sh_dmae_pdata dma0_platform_data = {
+        .channel        = sh7780_dmae0_channels,
+        .channel_num    = ARRAY_SIZE(sh7780_dmae0_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+static struct sh_dmae_pdata dma1_platform_data = {
+        .channel        = sh7780_dmae1_channels,
+        .channel_num    = ARRAY_SIZE(sh7780_dmae1_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+static struct resource sh7780_dmae0_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xfc808020,
+                .end    = 0xfc80808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* DMARSx */
+                .start  = 0xfc809000,
+                .end    = 0xfc80900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
+                .start  = 34,
+                .end    = 34,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+};
+
+static struct resource sh7780_dmae1_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xfc818020,
+                .end    = 0xfc81808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        /* DMAC1 has no DMARS */
+        {
+                /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
+                .start  = 46,
+                .end    = 46,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+};
+
+static struct platform_device dma0_device = {
+        .name           = "sh-dma-engine",
+        .id             = 0,
+        .resource       = sh7780_dmae0_resources,
+        .num_resources  = ARRAY_SIZE(sh7780_dmae0_resources),
+        .dev            = {
+                .platform_data  = &dma0_platform_data,
+        },
+};
+
+static struct platform_device dma1_device = {
+        .name           = "sh-dma-engine",
+        .id             = 1,
+        .resource       = sh7780_dmae1_resources,
+        .num_resources  = ARRAY_SIZE(sh7780_dmae1_resources),
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &dma1_platform_data,
         },
 };
 
 static struct platform_device *sh7780_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -252,7 +373,8 @@ static struct platform_device *sh7780_devices[] __initdata = {
         &tmu4_device,
         &tmu5_device,
         &rtc_device,
-        &sci_device,
+        &dma0_device,
+        &dma1_device,
 };
 
 static int __init sh7780_devices_setup(void)
@@ -260,9 +382,11 @@ static int __init sh7780_devices_setup(void)
         return platform_add_devices(sh7780_devices,
                                     ARRAY_SIZE(sh7780_devices));
 }
-__initcall(sh7780_devices_setup);
+arch_initcall(sh7780_devices_setup);
 
 static struct platform_device *sh7780_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -273,6 +397,13 @@ static struct platform_device *sh7780_early_devices[] __initdata = {
 
 void __init plat_early_device_setup(void)
 {
+        if (mach_is_sh2007()) {
+                scif0_platform_data.scscr &= ~SCSCR_CKE1;
+                scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
+                scif1_platform_data.scscr &= ~SCSCR_CKE1;
+                scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
+        }
+
         early_platform_add_devices(sh7780_early_devices,
                                    ARRAY_SIZE(sh7780_early_devices));
 }
@@ -443,17 +574,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ7-0 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         /* disable holding function, ie enable "SH-4 Mode" */
-        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -463,27 +594,27 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ:
                 /* select IRQ mode for IRL3-0 + IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
                 register_intc_controller(&intc_irq_desc);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl7654_desc);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl3210_desc);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 3ae2e2071009..18d8fc136fb2 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -13,20 +13,123 @@
 #include <linux/serial_sci.h>
 #include <linux/io.h>
 #include <linux/mm.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
+
 #include <asm/mmzone.h>
 
+#include <cpu/dma-register.h>
+
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffea0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 40, 40, 40 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffeb0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 44, 44, 44, 44 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffec0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 60, 60, 60, 60 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xffed0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 61, 61, 61, 61 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xffee0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 62, 62, 62, 62 },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xffef0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 63, 63, 63, 63 },
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "tmu012_fck",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -48,16 +151,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "tmu012_fck",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -79,15 +179,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "tmu012_fck",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002f,
                 .flags  = IORESOURCE_MEM,
@@ -109,15 +206,12 @@ static struct platform_device tmu2_device = {
 };
 
 static struct sh_timer_config tmu3_platform_data = {
-        .name = "TMU3",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "tmu345_fck",
 };
 
 static struct resource tmu3_resources[] = {
         [0] = {
-                .name   = "TMU3",
                 .start  = 0xffdc0008,
                 .end    = 0xffdc0013,
                 .flags  = IORESOURCE_MEM,
@@ -139,15 +233,12 @@ static struct platform_device tmu3_device = {
 };
 
 static struct sh_timer_config tmu4_platform_data = {
-        .name = "TMU4",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "tmu345_fck",
 };
 
 static struct resource tmu4_resources[] = {
         [0] = {
-                .name   = "TMU4",
                 .start  = 0xffdc0014,
                 .end    = 0xffdc001f,
                 .flags  = IORESOURCE_MEM,
@@ -169,15 +260,12 @@ static struct platform_device tmu4_device = {
 };
 
 static struct sh_timer_config tmu5_platform_data = {
-        .name = "TMU5",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "tmu345_fck",
 };
 
 static struct resource tmu5_resources[] = {
         [0] = {
-                .name   = "TMU5",
                 .start  = 0xffdc0020,
                 .end    = 0xffdc002b,
                 .flags  = IORESOURCE_MEM,
@@ -198,76 +286,149 @@ static struct platform_device tmu5_device = {
         .num_resources  = ARRAY_SIZE(tmu5_resources),
 };
 
-static struct plat_sci_port sci_platform_data[] = {
+/* DMA */
+static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
         {
-                .mapbase        = 0xffea0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 40, 40, 40 },
-                .clk            = "scif_fck",
+                .offset = 0,
+                .dmars = 0,
+                .dmars_bit = 0,
         }, {
-                .mapbase        = 0xffeb0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 44, 44, 44, 44 },
-                .clk            = "scif_fck",
+                .offset = 0x10,
+                .dmars = 0,
+                .dmars_bit = 8,
         }, {
-                .mapbase        = 0xffec0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 60, 60, 60, 60 },
-                .clk            = "scif_fck",
+                .offset = 0x20,
+                .dmars = 4,
+                .dmars_bit = 0,
         }, {
-                .mapbase        = 0xffed0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 61, 61, 61, 61 },
-                .clk            = "scif_fck",
+                .offset = 0x30,
+                .dmars = 4,
+                .dmars_bit = 8,
         }, {
-                .mapbase        = 0xffee0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 62, 62, 62, 62 },
-                .clk            = "scif_fck",
+                .offset = 0x50,
+                .dmars = 8,
+                .dmars_bit = 0,
         }, {
-                .mapbase        = 0xffef0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 63, 63, 63, 63 },
-                .clk            = "scif_fck",
+                .offset = 0x60,
+                .dmars = 8,
+                .dmars_bit = 8,
+        }
+};
+
+static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
+        {
+                .offset = 0,
         }, {
-                .flags = 0,
+                .offset = 0x10,
+        }, {
+                .offset = 0x20,
+        }, {
+                .offset = 0x30,
+        }, {
+                .offset = 0x50,
+        }, {
+                .offset = 0x60,
         }
 };
 
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
+static const unsigned int ts_shift[] = TS_SHIFT;
+
+static struct sh_dmae_pdata dma0_platform_data = {
+        .channel        = sh7785_dmae0_channels,
+        .channel_num    = ARRAY_SIZE(sh7785_dmae0_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+static struct sh_dmae_pdata dma1_platform_data = {
+        .channel        = sh7785_dmae1_channels,
+        .channel_num    = ARRAY_SIZE(sh7785_dmae1_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+static struct resource sh7785_dmae0_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xfc808020,
+                .end    = 0xfc80808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* DMARSx */
+                .start  = 0xfc809000,
+                .end    = 0xfc80900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
+                .start  = 33,
+                .end    = 33,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+};
+
+static struct resource sh7785_dmae1_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xfcc08020,
+                .end    = 0xfcc0808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        /* DMAC1 has no DMARS */
+        {
+                /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
+                .start  = 52,
+                .end    = 52,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+};
+
+static struct platform_device dma0_device = {
+        .name           = "sh-dma-engine",
+        .id             = 0,
+        .resource       = sh7785_dmae0_resources,
+        .num_resources  = ARRAY_SIZE(sh7785_dmae0_resources),
+        .dev            = {
+                .platform_data  = &dma0_platform_data,
+        },
+};
+
+static struct platform_device dma1_device = {
+        .name           = "sh-dma-engine",
+        .id             = 1,
+        .resource       = sh7785_dmae1_resources,
+        .num_resources  = ARRAY_SIZE(sh7785_dmae1_resources),
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &dma1_platform_data,
         },
 };
 
 static struct platform_device *sh7785_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
         &tmu3_device,
         &tmu4_device,
         &tmu5_device,
-        &sci_device,
+        &dma0_device,
+        &dma1_device,
 };
 
 static int __init sh7785_devices_setup(void)
@@ -275,9 +436,15 @@ static int __init sh7785_devices_setup(void)
         return platform_add_devices(sh7785_devices,
                                     ARRAY_SIZE(sh7785_devices));
 }
-__initcall(sh7785_devices_setup);
+arch_initcall(sh7785_devices_setup);
 
 static struct platform_device *sh7785_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -482,17 +649,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ3-0 + IRQ7-4 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         /* disable holding function, ie enable "SH-4 Mode" */
-        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -502,32 +669,32 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ7654:
                 /* select IRQ mode for IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq4567);
                 break;
         case IRQ_MODE_IRQ3210:
                 /* select IRQ mode for IRL3-0 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq0123);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl4567);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl0123);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 8b7ea4bd965d..1656b8c91faf 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -1,7 +1,7 @@
 /*
  * SH7786 Setup
  *
- * Copyright (C) 2009  Renesas Solutions Corp.
+ * Copyright (C) 2009 - 2010  Renesas Solutions Corp.
  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  * Paul Mundt <paul.mundt@renesas.com>
  *
@@ -21,79 +21,124 @@
 #include <linux/mm.h>
 #include <linux/dma-mapping.h>
 #include <linux/sh_timer.h>
+#include <linux/sh_dma.h>
+#include <linux/sh_intc.h>
+#include <cpu/dma-register.h>
 #include <asm/mmzone.h>
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffea0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 41, 43, 42 },
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffea0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 41, 43, 42 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
         },
-        /*
-         * The rest of these all have multiplexed IRQs
-         */
-        {
-                .mapbase        = 0xffeb0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 44, 44, 44, 44 },
-        }, {
-                .mapbase        = 0xffec0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 50, 50, 50, 50 },
-        }, {
-                .mapbase        = 0xffed0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 51, 51, 51, 51 },
-        }, {
-                .mapbase        = 0xffee0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 52, 52, 52, 52 },
-        }, {
-                .mapbase        = 0xffef0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 53, 53, 53, 53 },
-        }, {
-                .flags = 0,
-        }
 };
 
-static struct platform_device sci_device = {
+/*
+ * The rest of these all have multiplexed IRQs
+ */
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffeb0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 44, 44, 44, 44 },
+};
+
+static struct platform_device scif1_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffec0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 50, 50, 50, 50 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xffed0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 51, 51, 51, 51 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xffee0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 52, 52, 52, 52 },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xffef0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 53, 53, 53, 53 },
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
         },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -115,16 +160,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -146,15 +188,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002f,
                 .flags  = IORESOURCE_MEM,
@@ -176,15 +215,12 @@ static struct platform_device tmu2_device = {
 };
 
 static struct sh_timer_config tmu3_platform_data = {
-        .name = "TMU3",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu3_resources[] = {
         [0] = {
-                .name   = "TMU3",
                 .start  = 0xffda0008,
                 .end    = 0xffda0013,
                 .flags  = IORESOURCE_MEM,
@@ -206,15 +242,12 @@ static struct platform_device tmu3_device = {
 };
 
 static struct sh_timer_config tmu4_platform_data = {
-        .name = "TMU4",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu4_resources[] = {
         [0] = {
-                .name   = "TMU4",
                 .start  = 0xffda0014,
                 .end    = 0xffda001f,
                 .flags  = IORESOURCE_MEM,
@@ -236,15 +269,12 @@ static struct platform_device tmu4_device = {
 };
 
 static struct sh_timer_config tmu5_platform_data = {
-        .name = "TMU5",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu5_resources[] = {
         [0] = {
-                .name   = "TMU5",
                 .start  = 0xffda0020,
                 .end    = 0xffda002b,
                 .flags  = IORESOURCE_MEM,
@@ -266,15 +296,12 @@ static struct platform_device tmu5_device = {
 };
 
 static struct sh_timer_config tmu6_platform_data = {
-        .name = "TMU6",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu6_resources[] = {
         [0] = {
-                .name   = "TMU6",
                 .start  = 0xffdc0008,
                 .end    = 0xffdc0013,
                 .flags  = IORESOURCE_MEM,
@@ -296,15 +323,12 @@ static struct platform_device tmu6_device = {
 };
 
 static struct sh_timer_config tmu7_platform_data = {
-        .name = "TMU7",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu7_resources[] = {
         [0] = {
-                .name   = "TMU7",
                 .start  = 0xffdc0014,
                 .end    = 0xffdc001f,
                 .flags  = IORESOURCE_MEM,
@@ -326,15 +350,12 @@ static struct platform_device tmu7_device = {
 };
 
 static struct sh_timer_config tmu8_platform_data = {
-        .name = "TMU8",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu8_resources[] = {
         [0] = {
-                .name   = "TMU8",
                 .start  = 0xffdc0020,
                 .end    = 0xffdc002b,
                 .flags  = IORESOURCE_MEM,
@@ -356,15 +377,12 @@ static struct platform_device tmu8_device = {
 };
 
 static struct sh_timer_config tmu9_platform_data = {
-        .name = "TMU9",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu9_resources[] = {
         [0] = {
-                .name   = "TMU9",
                 .start  = 0xffde0008,
                 .end    = 0xffde0013,
                 .flags  = IORESOURCE_MEM,
@@ -386,15 +404,12 @@ static struct platform_device tmu9_device = {
 };
 
 static struct sh_timer_config tmu10_platform_data = {
-        .name = "TMU10",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu10_resources[] = {
         [0] = {
-                .name   = "TMU10",
                 .start  = 0xffde0014,
                 .end    = 0xffde001f,
                 .flags  = IORESOURCE_MEM,
@@ -416,15 +431,12 @@ static struct platform_device tmu10_device = {
 };
 
 static struct sh_timer_config tmu11_platform_data = {
-        .name = "TMU11",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu11_resources[] = {
         [0] = {
-                .name   = "TMU11",
                 .start  = 0xffde0020,
                 .end    = 0xffde002b,
                 .flags  = IORESOURCE_MEM,
@@ -445,10 +457,114 @@ static struct platform_device tmu11_device = {
         .num_resources  = ARRAY_SIZE(tmu11_resources),
 };
 
+static const struct sh_dmae_channel dmac0_channels[] = {
+        {
+                .offset = 0,
+                .dmars = 0,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x10,
+                .dmars = 0,
+                .dmars_bit = 8,
+        }, {
+                .offset = 0x20,
+                .dmars = 4,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x30,
+                .dmars = 4,
+                .dmars_bit = 8,
+        }, {
+                .offset = 0x50,
+                .dmars = 8,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x60,
+                .dmars = 8,
+                .dmars_bit = 8,
+        }
+};
+
+static const unsigned int ts_shift[] = TS_SHIFT;
+
+static struct sh_dmae_pdata dma0_platform_data = {
+        .channel        = dmac0_channels,
+        .channel_num    = ARRAY_SIZE(dmac0_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+/* Resource order important! */
+static struct resource dmac0_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xfe008020,
+                .end    = 0xfe00808f,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                /* DMARSx */
+                .start  = 0xfe009000,
+                .end    = 0xfe00900b,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                /* DMA error IRQ */
+                .start  = evt2irq(0x5c0),
+                .end    = evt2irq(0x5c0),
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                /* IRQ for channels 0-5 */
+                .start  = evt2irq(0x500),
+                .end    = evt2irq(0x5a0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dma0_device = {
+        .name           = "sh-dma-engine",
+        .id             = 0,
+        .resource       = dmac0_resources,
+        .num_resources  = ARRAY_SIZE(dmac0_resources),
+        .dev            = {
+                .platform_data  = &dma0_platform_data,
+        },
+};
+
+#define USB_EHCI_START 0xffe70000
+#define USB_OHCI_START 0xffe70400
+
+static struct resource usb_ehci_resources[] = {
+        [0] = {
+                .start  = USB_EHCI_START,
+                .end    = USB_EHCI_START + 0x3ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 77,
+                .end    = 77,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usb_ehci_device = {
+        .name           = "sh_ehci",
+        .id             = -1,
+        .dev = {
+                .dma_mask               = &usb_ehci_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(usb_ehci_resources),
+        .resource       = usb_ehci_resources,
+};
+
 static struct resource usb_ohci_resources[] = {
         [0] = {
-                .start  = 0xffe70400,
-                .end    = 0xffe704ff,
+                .start  = USB_OHCI_START,
+                .end    = USB_OHCI_START + 0x3ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -458,12 +574,11 @@ static struct resource usb_ohci_resources[] = {
         },
 };
 
-static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
 static struct platform_device usb_ohci_device = {
         .name           = "sh_ohci",
         .id             = -1,
         .dev = {
-                .dma_mask               = &usb_ohci_dma_mask,
+                .dma_mask               = &usb_ohci_device.dev.coherent_dma_mask,
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
@@ -471,6 +586,12 @@ static struct platform_device usb_ohci_device = {
 };
 
 static struct platform_device *sh7786_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -486,11 +607,11 @@ static struct platform_device *sh7786_early_devices[] __initdata = {
 };
 
 static struct platform_device *sh7786_devices[] __initdata = {
-        &sci_device,
+        &dma0_device,
+        &usb_ehci_device,
         &usb_ohci_device,
 };
 
-
 /*
  * Please call this function if your platform board
  * use external clock for USB
@@ -498,6 +619,7 @@ static struct platform_device *sh7786_devices[] __initdata = {
 #define USBCTL0         0xffe70858
 #define CLOCK_MODE_MASK 0xffffff7f
 #define EXT_CLOCK_MODE  0x00000080
+
 void __init sh7786_usb_use_exclock(void)
 {
         u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
@@ -515,6 +637,7 @@ void __init sh7786_usb_use_exclock(void)
 #define PLL_ENB         0x00000002
 #define PHY_RST         0x00000004
 #define ACT_PLL_STATUS  0xc0000000
+
 static void __init sh7786_usb_setup(void)
 {
         int i = 1000000;
@@ -545,33 +668,10 @@ static void __init sh7786_usb_setup(void)
         }
 }
 
-static int __init sh7786_devices_setup(void)
-{
-        int ret;
-
-        sh7786_usb_setup();
-
-        ret = platform_add_devices(sh7786_early_devices,
-                                   ARRAY_SIZE(sh7786_early_devices));
-        if (unlikely(ret != 0))
-                return ret;
-
-        return platform_add_devices(sh7786_devices,
-                                    ARRAY_SIZE(sh7786_devices));
-}
-device_initcall(sh7786_devices_setup);
-
-void __init plat_early_device_setup(void)
-{
-        early_platform_add_devices(sh7786_early_devices,
-                                   ARRAY_SIZE(sh7786_early_devices));
-}
-
 enum {
         UNUSED = 0,
 
         /* interrupt sources */
-
         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
@@ -609,9 +709,12 @@ enum {
         Thermal,
         INTICI0, INTICI1, INTICI2, INTICI3,
         INTICI4, INTICI5, INTICI6, INTICI7,
+
+        /* Muxed sub-events */
+        TXI1, BRI1, RXI1, ERI1,
 };
 
-static struct intc_vect vectors[] __initdata = {
+static struct intc_vect sh7786_vectors[] __initdata = {
         INTC_VECT(WDT, 0x3e0),
         INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
         INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
@@ -670,9 +773,17 @@ static struct intc_vect vectors[] __initdata = {
 #define INTMSK2         0xfe410068
 #define INTMSKCLR2      0xfe41006c
 
-static struct intc_mask_reg mask_registers[] __initdata = {
+#define INTDISTCR0      0xfe4100b0
+#define INTDISTCR1      0xfe4100b4
+#define INT2DISTCR0     0xfe410900
+#define INT2DISTCR1     0xfe410904
+#define INT2DISTCR2     0xfe410908
+#define INT2DISTCR3     0xfe41090c
+
+static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
         { CnINTMSK0, CnINTMSKCLR0, 32,
-          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+          { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
+            INTC_SMP_BALANCING(INTDISTCR0) },
         { INTMSK2, INTMSKCLR2, 32,
           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
@@ -684,7 +795,8 @@ static struct intc_mask_reg mask_registers[] __initdata = {
             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
         { CnINT2MSKR0, CnINT2MSKCR0 , 32,
           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
+            0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
+            INTC_SMP_BALANCING(INT2DISTCR0) },
         { CnINT2MSKR1, CnINT2MSKCR1, 32,
           { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
             DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
@@ -693,14 +805,14 @@ static struct intc_mask_reg mask_registers[] __initdata = {
             HPB_0, HPB_1, HPB_2,
             SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
             SCIF1,
-            TMU2, TMU3, 0, } },
+            TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
         { CnINT2MSKR2, CnINT2MSKCR2, 32,
           { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
             Eth_0, Eth_1,
             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
             PCIeC0_0, PCIeC0_1, PCIeC0_2,
             PCIeC1_0, PCIeC1_1, PCIeC1_2,
-            USB, 0, 0 } },
+            USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
         { CnINT2MSKR3, CnINT2MSKCR3, 32,
           { 0, 0, 0, 0, 0, 0,
             I2C0, I2C1,
@@ -709,10 +821,10 @@ static struct intc_mask_reg mask_registers[] __initdata = {
             HAC0, HAC1,
             FLCTL, 0,
             HSPI, GPIO0, GPIO1, Thermal,
-            0, 0, 0, 0, 0, 0, 0, 0 } },
+            0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
 };
 
-static struct intc_prio_reg prio_registers[] __initdata = {
+static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
         { 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
         { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
@@ -756,11 +868,27 @@ static struct intc_prio_reg prio_registers[] __initdata = {
             INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
 };
 
-static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
-                         mask_registers, prio_registers, NULL);
+static struct intc_subgroup sh7786_subgroups[] __initdata = {
+        { 0xfe410c20, 32, SCIF1,
+          { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+            0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
+};
 
-/* Support for external interrupt pins in IRQ mode */
+static struct intc_desc sh7786_intc_desc __initdata = {
+        .name           = "sh7786",
+        .hw             = {
+                .vectors        = sh7786_vectors,
+                .nr_vectors     = ARRAY_SIZE(sh7786_vectors),
+                .mask_regs      = sh7786_mask_registers,
+                .nr_mask_regs   = ARRAY_SIZE(sh7786_mask_registers),
+                .subgroups      = sh7786_subgroups,
+                .nr_subgroups   = ARRAY_SIZE(sh7786_subgroups),
+                .prio_regs      = sh7786_prio_registers,
+                .nr_prio_regs   = ARRAY_SIZE(sh7786_prio_registers),
+        },
+};
 
+/* Support for external interrupt pins in IRQ mode */
 static struct intc_vect vectors_irq0123[] __initdata = {
         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
@@ -771,23 +899,25 @@ static struct intc_vect vectors_irq4567[] __initdata = {
         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
 };
 
-static struct intc_sense_reg sense_registers[] __initdata = {
+static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static struct intc_mask_reg ack_registers[] __initdata = {
+static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
         { 0xfe410024, 0, 32, /* INTREQ */
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
-                             vectors_irq0123, NULL, mask_registers,
-                             prio_registers, sense_registers, ack_registers);
+                             vectors_irq0123, NULL, sh7786_mask_registers,
+                             sh7786_prio_registers, sh7786_sense_registers,
+                             sh7786_ack_registers);
 
 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
-                             vectors_irq4567, NULL, mask_registers,
-                             prio_registers, sense_registers, ack_registers);
+                             vectors_irq4567, NULL, sh7786_mask_registers,
+                             sh7786_prio_registers, sh7786_sense_registers,
+                             sh7786_ack_registers);
 
 /* External interrupt pins in IRL mode */
 
@@ -814,10 +944,10 @@ static struct intc_vect vectors_irl4567[] __initdata = {
 };
 
 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
-                         NULL, mask_registers, NULL, NULL);
+                         NULL, sh7786_mask_registers, NULL, NULL);
 
 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
-                         NULL, mask_registers, NULL, NULL);
+                         NULL, sh7786_mask_registers, NULL, NULL);
 
 #define INTC_ICR0       0xfe410000
 #define INTC_INTMSK0    CnINTMSK0
@@ -829,16 +959,16 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ3-0 + IRQ7-4 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
-        register_intc_controller(&intc_desc);
+        register_intc_controller(&sh7786_intc_desc);
 }
 
 void __init plat_irq_setup_pins(int mode)
@@ -846,32 +976,32 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ7654:
                 /* select IRQ mode for IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq4567);
                 break;
         case IRQ_MODE_IRQ3210:
                 /* select IRQ mode for IRL3-0 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq0123);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl4567);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl0123);
                 break;
         default:
@@ -882,3 +1012,39 @@ void __init plat_irq_setup_pins(int mode)
 void __init plat_mem_setup(void)
 {
 }
+
+static int __init sh7786_devices_setup(void)
+{
+        int ret, irq;
+
+        sh7786_usb_setup();
+
+        /*
+         * De-mux SCIF1 IRQs if possible
+         */
+        irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
+        if (irq > 0) {
+                scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq;
+                scif1_platform_data.irqs[SCIx_ERI_IRQ] =
+                        intc_irq_lookup(sh7786_intc_desc.name, ERI1);
+                scif1_platform_data.irqs[SCIx_BRI_IRQ] =
+                        intc_irq_lookup(sh7786_intc_desc.name, BRI1);
+                scif1_platform_data.irqs[SCIx_RXI_IRQ] =
+                        intc_irq_lookup(sh7786_intc_desc.name, RXI1);
+        }
+
+        ret = platform_add_devices(sh7786_early_devices,
+                                   ARRAY_SIZE(sh7786_early_devices));
+        if (unlikely(ret != 0))
+                return ret;
+
+        return platform_add_devices(sh7786_devices,
+                                    ARRAY_SIZE(sh7786_devices));
+}
+arch_initcall(sh7786_devices_setup);
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7786_early_devices,
+                                   ARRAY_SIZE(sh7786_early_devices));
+}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 4a26cc304139..bb208806dc1a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -1,7 +1,7 @@
 /*
  * SH-X3 Prototype Setup
  *
- *  Copyright (C) 2007 - 2009  Paul Mundt
+ *  Copyright (C) 2007 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -12,62 +12,79 @@
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 #include <linux/sh_timer.h>
+#include <cpu/shx3.h>
 #include <asm/mmzone.h>
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffc30000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 41, 43, 42 },
-        }, {
-                .mapbase        = 0xffc40000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 44, 45, 47, 46 },
-        }, {
-                .mapbase        = 0xffc50000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 48, 49, 51, 50 },
-        }, {
-                .mapbase        = 0xffc60000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 52, 53, 55, 54 },
-        }, {
-                .flags = 0,
-        }
+/*
+ * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
+ * INTEVT values overlap with the FPU EXPEVT ones, requiring special
+ * demuxing in the exception dispatch path.
+ *
+ * As this overlap is something that never should have made it in to
+ * silicon in the first place, we just refuse to deal with the port at
+ * all rather than adding infrastructure to hack around it.
+ */
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffc30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 41, 43, 42 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffc40000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 44, 45, 47, 46 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffc60000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 52, 53, 55, 54 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif2_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 2,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffc10008,
                 .end    = 0xffc10013,
                 .flags  = IORESOURCE_MEM,
@@ -89,16 +106,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffc10014,
                 .end    = 0xffc1001f,
                 .flags  = IORESOURCE_MEM,
@@ -120,15 +134,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffc10020,
                 .end    = 0xffc1002f,
                 .flags  = IORESOURCE_MEM,
@@ -150,15 +161,12 @@ static struct platform_device tmu2_device = {
 };
 
 static struct sh_timer_config tmu3_platform_data = {
-        .name = "TMU3",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu3_resources[] = {
         [0] = {
-                .name   = "TMU3",
                 .start  = 0xffc20008,
                 .end    = 0xffc20013,
                 .flags  = IORESOURCE_MEM,
@@ -180,15 +188,12 @@ static struct platform_device tmu3_device = {
 };
 
 static struct sh_timer_config tmu4_platform_data = {
-        .name = "TMU4",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu4_resources[] = {
         [0] = {
-                .name   = "TMU4",
                 .start  = 0xffc20014,
                 .end    = 0xffc2001f,
                 .flags  = IORESOURCE_MEM,
@@ -210,15 +215,12 @@ static struct platform_device tmu4_device = {
 };
 
 static struct sh_timer_config tmu5_platform_data = {
-        .name = "TMU5",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu5_resources[] = {
         [0] = {
-                .name   = "TMU5",
                 .start  = 0xffc20020,
                 .end    = 0xffc2002b,
                 .flags  = IORESOURCE_MEM,
@@ -240,6 +242,9 @@ static struct platform_device tmu5_device = {
 };
 
 static struct platform_device *shx3_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -248,23 +253,12 @@ static struct platform_device *shx3_early_devices[] __initdata = {
         &tmu5_device,
 };
 
-static struct platform_device *shx3_devices[] __initdata = {
-        &sci_device,
-};
-
 static int __init shx3_devices_setup(void)
 {
-        int ret;
-
-        ret = platform_add_devices(shx3_early_devices,
+        return platform_add_devices(shx3_early_devices,
                                    ARRAY_SIZE(shx3_early_devices));
-        if (unlikely(ret != 0))
-                return ret;
-
-        return platform_add_devices(shx3_devices,
-                                    ARRAY_SIZE(shx3_devices));
 }
-__initcall(shx3_devices_setup);
+arch_initcall(shx3_devices_setup);
 
 void __init plat_early_device_setup(void)
 {
@@ -295,10 +289,7 @@ enum {
         DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
         DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
         IIC, VIN0, VIN1, VCORE0, ATAPI,
-        DTU0_TEND, DTU0_AE, DTU0_TMISS,
-        DTU1_TEND, DTU1_AE, DTU1_TMISS,
-        DTU2_TEND, DTU2_AE, DTU2_TMISS,
-        DTU3_TEND, DTU3_AE, DTU3_TMISS,
+        DTU0, DTU1, DTU2, DTU3,
         FE0, FE1,
         GPIO0, GPIO1, GPIO2, GPIO3,
         PAM, IRM,
@@ -307,7 +298,7 @@ enum {
 
         /* interrupt groups */
         IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
-        DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3,
+        DMAC0, DMAC1,
 };
 
 static struct intc_vect vectors[] __initdata = {
@@ -324,8 +315,6 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
         INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
         INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
-        INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820),
-        INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860),
         INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
         INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
         INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
@@ -340,14 +329,14 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(IIC, 0xae0),
         INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
         INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
-        INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20),
-        INTC_VECT(DTU0_TMISS, 0xc40),
-        INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80),
-        INTC_VECT(DTU1_TMISS, 0xca0),
-        INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0),
-        INTC_VECT(DTU2_TMISS, 0xd00),
-        INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40),
-        INTC_VECT(DTU3_TMISS, 0xd60),
+        INTC_VECT(DTU0, 0xc00), INTC_VECT(DTU0, 0xc20),
+        INTC_VECT(DTU0, 0xc40),
+        INTC_VECT(DTU1, 0xc60), INTC_VECT(DTU1, 0xc80),
+        INTC_VECT(DTU1, 0xca0),
+        INTC_VECT(DTU2, 0xcc0), INTC_VECT(DTU2, 0xce0),
+        INTC_VECT(DTU2, 0xd00),
+        INTC_VECT(DTU3, 0xd20), INTC_VECT(DTU3, 0xd40),
+        INTC_VECT(DTU3, 0xd60),
         INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
         INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
         INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
@@ -366,18 +355,17 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
         INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
         INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
-        INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
         INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI),
         INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
                    DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
         INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
                    DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
-        INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS),
-        INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS),
-        INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS),
-        INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
 };
 
+#define INT2DISTCR0     0xfe4108a0
+#define INT2DISTCR1     0xfe4108a4
+#define INT2DISTCR2     0xfe4108a8
+
 static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
           { IRQ0, IRQ1, IRQ2, IRQ3 } },
@@ -387,20 +375,23 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
             DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
             0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
-            0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } },
+            0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, },
+            INTC_SMP_BALANCING(INT2DISTCR0) },
         { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
           { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
             PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
             PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
             DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
             DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
-            DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } },
+            DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 },
+            INTC_SMP_BALANCING(INT2DISTCR1) },
         { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
             SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
             SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
             SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
-            SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
+            SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI },
+            INTC_SMP_BALANCING(INT2DISTCR2) },
 };
 
 static struct intc_prio_reg prio_registers[] __initdata = {
@@ -457,11 +448,33 @@ static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
 
 void __init plat_irq_setup_pins(int mode)
 {
+        int ret = 0;
+
         switch (mode) {
         case IRQ_MODE_IRQ:
+                ret |= gpio_request(GPIO_FN_IRQ3, intc_desc_irq.name);
+                ret |= gpio_request(GPIO_FN_IRQ2, intc_desc_irq.name);
+                ret |= gpio_request(GPIO_FN_IRQ1, intc_desc_irq.name);
+                ret |= gpio_request(GPIO_FN_IRQ0, intc_desc_irq.name);
+
+                if (unlikely(ret)) {
+                        pr_err("Failed to set IRQ mode\n");
+                        return;
+                }
+
                 register_intc_controller(&intc_desc_irq);
                 break;
         case IRQ_MODE_IRL3210:
+                ret |= gpio_request(GPIO_FN_IRL3, intc_desc_irl.name);
+                ret |= gpio_request(GPIO_FN_IRL2, intc_desc_irl.name);
+                ret |= gpio_request(GPIO_FN_IRL1, intc_desc_irl.name);
+                ret |= gpio_request(GPIO_FN_IRL0, intc_desc_irl.name);
+
+                if (unlikely(ret)) {
+                        pr_err("Failed to set IRL mode\n");
+                        return;
+                }
+
                 register_intc_controller(&intc_desc_irl);
                 break;
         default:
@@ -471,6 +484,9 @@ void __init plat_irq_setup_pins(int mode)
 
 void __init plat_irq_setup(void)
 {
+        reserve_intc_vectors(vectors_irq, ARRAY_SIZE(vectors_irq));
+        reserve_intc_vectors(vectors_irl, ARRAY_SIZE(vectors_irl));
+
         register_intc_controller(&intc_desc);
 }
 
diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
index 2b6b0d50c576..de865cac02ee 100644
--- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
@@ -1,7 +1,7 @@
 /*
  * SH-X3 SMP
  *
- *  Copyright (C) 2007 - 2008  Paul Mundt
+ *  Copyright (C) 2007 - 2010  Paul Mundt
  *  Copyright (C) 2007  Magnus Damm
  *
  * This file is subject to the terms and conditions of the GNU General Public
@@ -9,10 +9,23 @@
  * for more details.
  */
 #include <linux/init.h>
+#include <linux/kernel.h>
 #include <linux/cpumask.h>
 #include <linux/smp.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/cpu.h>
+#include <asm/sections.h>
+
+#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
+#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
+
+#define STBCR_MSTP      0x00000001
+#define STBCR_RESET     0x00000002
+#define STBCR_SLEEP     0x00000004
+#define STBCR_LTSLP     0x80000000
 
 static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
 {
@@ -21,22 +34,25 @@ static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
         unsigned int offs = 4 * cpu;
         unsigned int x;
 
-        x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
+        x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
         x &= (1 << (message << 2));
-        ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
+        __raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
 
         smp_message_recv(message);
 
         return IRQ_HANDLED;
 }
 
-void __init plat_smp_setup(void)
+static void shx3_smp_setup(void)
 {
         unsigned int cpu = 0;
         int i, num;
 
         init_cpu_possible(cpumask_of(cpu));
 
+        /* Enable light sleep for the boot CPU */
+        __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu));
+
         __cpu_number_map[0] = 0;
         __cpu_logical_map[0] = 0;
 
@@ -53,50 +69,98 @@ void __init plat_smp_setup(void)
         printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
 }
 
-void __init plat_prepare_cpus(unsigned int max_cpus)
+static void shx3_prepare_cpus(unsigned int max_cpus)
 {
         int i;
 
+        local_timer_setup(0);
+
         BUILD_BUG_ON(SMP_MSG_NR >= 8);
 
         for (i = 0; i < SMP_MSG_NR; i++)
-                request_irq(104 + i, ipi_interrupt_handler, IRQF_DISABLED,
-                            "IPI", (void *)(long)i);
-}
-
-#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
-#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
+                request_irq(104 + i, ipi_interrupt_handler,
+                            IRQF_DISABLED | IRQF_PERCPU, "IPI", (void *)(long)i);
 
-#define STBCR_MSTP      0x00000001
-#define STBCR_RESET     0x00000002
-#define STBCR_LTSLP     0x80000000
-
-#define STBCR_AP_VAL    (STBCR_RESET | STBCR_LTSLP)
+        for (i = 0; i < max_cpus; i++)
+                set_cpu_present(i, true);
+}
 
-void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
+static void shx3_start_cpu(unsigned int cpu, unsigned long entry_point)
 {
-        ctrl_outl(entry_point, RESET_REG(cpu));
+        if (__in_29bit_mode())
+                __raw_writel(entry_point, RESET_REG(cpu));
+        else
+                __raw_writel(virt_to_phys(entry_point), RESET_REG(cpu));
 
-        if (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
-                ctrl_outl(STBCR_MSTP, STBCR_REG(cpu));
+        if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
+                __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
 
-        while (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
+        while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
                 cpu_relax();
 
         /* Start up secondary processor by sending a reset */
-        ctrl_outl(STBCR_AP_VAL, STBCR_REG(cpu));
+        __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu));
 }
 
-int plat_smp_processor_id(void)
+static unsigned int shx3_smp_processor_id(void)
 {
-        return ctrl_inl(0xff000048); /* CPIDR */
+        return __raw_readl(0xff000048); /* CPIDR */
 }
 
-void plat_send_ipi(unsigned int cpu, unsigned int message)
+static void shx3_send_ipi(unsigned int cpu, unsigned int message)
 {
         unsigned long addr = 0xfe410070 + (cpu * 4);
 
         BUG_ON(cpu >= 4);
 
-        ctrl_outl(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
+        __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
+}
+
+static void shx3_update_boot_vector(unsigned int cpu)
+{
+        __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
+        while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
+                cpu_relax();
+        __raw_writel(STBCR_RESET, STBCR_REG(cpu));
+}
+
+static int __cpuinit
+shx3_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
+{
+        unsigned int cpu = (unsigned int)hcpu;
+
+        switch (action) {
+        case CPU_UP_PREPARE:
+                shx3_update_boot_vector(cpu);
+                break;
+        case CPU_ONLINE:
+                pr_info("CPU %u is now online\n", cpu);
+                break;
+        case CPU_DEAD:
+                break;
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata shx3_cpu_notifier = {
+        .notifier_call          = shx3_cpu_callback,
+};
+
+static int __cpuinit register_shx3_cpu_notifier(void)
+{
+        register_hotcpu_notifier(&shx3_cpu_notifier);
+        return 0;
 }
+late_initcall(register_shx3_cpu_notifier);
+
+struct plat_smp_ops shx3_smp_ops = {
+        .smp_setup              = shx3_smp_setup,
+        .prepare_cpus           = shx3_prepare_cpus,
+        .start_cpu              = shx3_start_cpu,
+        .smp_processor_id       = shx3_smp_processor_id,
+        .send_ipi               = shx3_send_ipi,
+        .cpu_die                = native_cpu_die,
+        .cpu_disable            = native_cpu_disable,
+        .play_dead              = native_play_dead,
+};
diff --git a/arch/sh/kernel/cpu/sh4a/ubc.c b/arch/sh/kernel/cpu/sh4a/ubc.c
new file mode 100644
index 000000000000..efb2745bcb36
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/ubc.c
@@ -0,0 +1,133 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/ubc.c
+ *
+ * On-chip UBC support for SH-4A CPUs.
+ *
+ * Copyright (C) 2009 - 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <asm/hw_breakpoint.h>
+
+#define UBC_CBR(idx)    (0xff200000 + (0x20 * idx))
+#define UBC_CRR(idx)    (0xff200004 + (0x20 * idx))
+#define UBC_CAR(idx)    (0xff200008 + (0x20 * idx))
+#define UBC_CAMR(idx)   (0xff20000c + (0x20 * idx))
+
+#define UBC_CCMFR       0xff200600
+#define UBC_CBCR        0xff200620
+
+/* CRR */
+#define UBC_CRR_PCB     (1 << 1)
+#define UBC_CRR_BIE     (1 << 0)
+
+/* CBR */
+#define UBC_CBR_CE      (1 << 0)
+
+static struct sh_ubc sh4a_ubc;
+
+static void sh4a_ubc_enable(struct arch_hw_breakpoint *info, int idx)
+{
+        __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx));
+        __raw_writel(info->address, UBC_CAR(idx));
+}
+
+static void sh4a_ubc_disable(struct arch_hw_breakpoint *info, int idx)
+{
+        __raw_writel(0, UBC_CBR(idx));
+        __raw_writel(0, UBC_CAR(idx));
+}
+
+static void sh4a_ubc_enable_all(unsigned long mask)
+{
+        int i;
+
+        for (i = 0; i < sh4a_ubc.num_events; i++)
+                if (mask & (1 << i))
+                        __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE,
+                                     UBC_CBR(i));
+}
+
+static void sh4a_ubc_disable_all(void)
+{
+        int i;
+
+        for (i = 0; i < sh4a_ubc.num_events; i++)
+                __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE,
+                             UBC_CBR(i));
+}
+
+static unsigned long sh4a_ubc_active_mask(void)
+{
+        unsigned long active = 0;
+        int i;
+
+        for (i = 0; i < sh4a_ubc.num_events; i++)
+                if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE)
+                        active |= (1 << i);
+
+        return active;
+}
+
+static unsigned long sh4a_ubc_triggered_mask(void)
+{
+        return __raw_readl(UBC_CCMFR);
+}
+
+static void sh4a_ubc_clear_triggered_mask(unsigned long mask)
+{
+        __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR);
+}
+
+static struct sh_ubc sh4a_ubc = {
+        .name                   = "SH-4A",
+        .num_events             = 2,
+        .trap_nr                = 0x1e0,
+        .enable                 = sh4a_ubc_enable,
+        .disable                = sh4a_ubc_disable,
+        .enable_all             = sh4a_ubc_enable_all,
+        .disable_all            = sh4a_ubc_disable_all,
+        .active_mask            = sh4a_ubc_active_mask,
+        .triggered_mask         = sh4a_ubc_triggered_mask,
+        .clear_triggered_mask   = sh4a_ubc_clear_triggered_mask,
+};
+
+static int __init sh4a_ubc_init(void)
+{
+        struct clk *ubc_iclk = clk_get(NULL, "ubc0");
+        int i;
+
+        /*
+         * The UBC MSTP bit is optional, as not all platforms will have
+         * it. Just ignore it if we can't find it.
+         */
+        if (IS_ERR(ubc_iclk))
+                ubc_iclk = NULL;
+
+        clk_enable(ubc_iclk);
+
+        __raw_writel(0, UBC_CBCR);
+
+        for (i = 0; i < sh4a_ubc.num_events; i++) {
+                __raw_writel(0, UBC_CAMR(i));
+                __raw_writel(0, UBC_CBR(i));
+
+                __raw_writel(UBC_CRR_BIE | UBC_CRR_PCB, UBC_CRR(i));
+
+                /* dummy read for write posting */
+                (void)__raw_readl(UBC_CRR(i));
+        }
+
+        clk_disable(ubc_iclk);
+
+        sh4a_ubc.clk = ubc_iclk;
+
+        return register_sh_ubc(&sh4a_ubc);
+}
+arch_initcall(sh4a_ubc_init);
diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c
index 7f864ebc51d3..9cfc19b8dbe4 100644
--- a/arch/sh/kernel/cpu/sh5/clock-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c
@@ -24,7 +24,7 @@ static unsigned long cprc_base;
 
 static void master_clk_init(struct clk *clk)
 {
-        int idx = (ctrl_inl(cprc_base + 0x00) >> 6) & 0x0007;
+        int idx = (__raw_readl(cprc_base + 0x00) >> 6) & 0x0007;
         clk->rate *= ifc_table[idx];
 }
 
@@ -34,7 +34,7 @@ static struct clk_ops sh5_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007;
+        int idx = (__raw_readw(cprc_base) >> 12) & 0x0007;
         return clk->parent->rate / ifc_table[idx];
 }
 
@@ -44,7 +44,7 @@ static struct clk_ops sh5_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007;
+        int idx = (__raw_readw(cprc_base) >> 3) & 0x0007;
         return clk->parent->rate / ifc_table[idx];
 }
 
@@ -54,7 +54,7 @@ static struct clk_ops sh5_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(cprc_base) & 0x0007);
+        int idx = (__raw_readw(cprc_base) & 0x0007);
         return clk->parent->rate / ifc_table[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh5/entry.S b/arch/sh/kernel/cpu/sh5/entry.S
index b0aacf675258..6b80295dd7a4 100644
--- a/arch/sh/kernel/cpu/sh5/entry.S
+++ b/arch/sh/kernel/cpu/sh5/entry.S
@@ -187,7 +187,7 @@ trap_jtable:
         .rept 6
                 .long do_exception_error        /* 0x880 - 0x920 */
         .endr
-        .long   do_software_break_point /* 0x940 */
+        .long   breakpoint_trap_handler /* 0x940 */
         .long   do_exception_error              /* 0x960 */
         .long   do_single_step          /* 0x980 */
 
@@ -933,7 +933,7 @@ ret_with_reschedule:
 
         pta     restore_all, tr1
 
-        movi    (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), r8
+        movi    _TIF_SIGPENDING, r8
         and     r8, r7, r8
         pta     work_notifysig, tr0
         bne     r8, ZERO, tr0
@@ -1124,7 +1124,7 @@ fpu_error_or_IRQA:
         pta     its_IRQ, tr0
         beqi/l  r4, EVENT_INTERRUPT, tr0
 #ifdef CONFIG_SH_FPU
-        movi    do_fpu_state_restore, r6
+        movi    fpu_state_restore_trap_handler, r6
 #else
         movi    do_exception_error, r6
 #endif
@@ -1135,7 +1135,7 @@ fpu_error_or_IRQB:
         pta     its_IRQ, tr0
         beqi/l  r4, EVENT_INTERRUPT, tr0
 #ifdef CONFIG_SH_FPU
-        movi    do_fpu_state_restore, r6
+        movi    fpu_state_restore_trap_handler, r6
 #else
         movi    do_exception_error, r6
 #endif
diff --git a/arch/sh/kernel/cpu/sh5/fpu.c b/arch/sh/kernel/cpu/sh5/fpu.c
index dd4f51ffb50e..4b3bb35e99f3 100644
--- a/arch/sh/kernel/cpu/sh5/fpu.c
+++ b/arch/sh/kernel/cpu/sh5/fpu.c
@@ -15,26 +15,8 @@
 #include <linux/sched.h>
 #include <linux/signal.h>
 #include <asm/processor.h>
-#include <asm/user.h>
-#include <asm/io.h>
-#include <asm/fpu.h>
 
-/*
- * Initially load the FPU with signalling NANS.  This bit pattern
- * has the property that no matter whether considered as single or as
- * double precision, it still represents a signalling NAN.
- */
-#define sNAN64          0xFFFFFFFFFFFFFFFFULL
-#define sNAN32          0xFFFFFFFFUL
-
-static union sh_fpu_union init_fpuregs = {
-        .hard = {
-                .fp_regs = { [0 ... 63] = sNAN32 },
-                .fpscr = FPSCR_INIT
-        }
-};
-
-void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
+void save_fpu(struct task_struct *tsk)
 {
         asm volatile("fst.p     %0, (0*8), fp0\n\t"
                      "fst.p     %0, (1*8), fp2\n\t"
@@ -72,12 +54,11 @@ void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
                      "fgetscr   fr63\n\t"
                      "fst.s     %0, (32*8), fr63\n\t"
                 : /* no output */
-                : "r" (&tsk->thread.fpu.hard)
+                : "r" (&tsk->thread.xstate->hardfpu)
                 : "memory");
 }
 
-static inline void
-fpload(struct sh_fpu_hard_struct *fpregs)
+void restore_fpu(struct task_struct *tsk)
 {
         asm volatile("fld.p     %0, (0*8), fp0\n\t"
                      "fld.p     %0, (1*8), fp2\n\t"
@@ -116,16 +97,11 @@ fpload(struct sh_fpu_hard_struct *fpregs)
 
                      "fld.p     %0, (31*8), fp62\n\t"
                 : /* no output */
-                : "r" (fpregs) );
-}
-
-void fpinit(struct sh_fpu_hard_struct *fpregs)
-{
-        *fpregs = init_fpuregs.hard;
+                : "r" (&tsk->thread.xstate->hardfpu)
+                : "memory");
 }
 
-asmlinkage void
-do_fpu_error(unsigned long ex, struct pt_regs *regs)
+asmlinkage void do_fpu_error(unsigned long ex, struct pt_regs *regs)
 {
         struct task_struct *tsk = current;
 
@@ -133,35 +109,6 @@ do_fpu_error(unsigned long ex, struct pt_regs *regs)
 
         tsk->thread.trap_no = 11;
         tsk->thread.error_code = 0;
-        force_sig(SIGFPE, tsk);
-}
-
-
-asmlinkage void
-do_fpu_state_restore(unsigned long ex, struct pt_regs *regs)
-{
-        void die(const char *str, struct pt_regs *regs, long err);
-
-        if (! user_mode(regs))
-                die("FPU used in kernel", regs, ex);
 
-        regs->sr &= ~SR_FD;
-
-        if (last_task_used_math == current)
-                return;
-
-        enable_fpu();
-        if (last_task_used_math != NULL)
-                /* Other processes fpu state, save away */
-                save_fpu(last_task_used_math, regs);
-
-        last_task_used_math = current;
-        if (used_math()) {
-                fpload(&current->thread.fpu.hard);
-        } else {
-                /* First time FPU user.  */
-                fpload(&init_fpuregs.hard);
-                set_used_math();
-        }
-        disable_fpu();
+        force_sig(SIGFPE, tsk);
 }
diff --git a/arch/sh/kernel/cpu/sh5/probe.c b/arch/sh/kernel/cpu/sh5/probe.c
index 92ad844b5c12..9e882409e4e9 100644
--- a/arch/sh/kernel/cpu/sh5/probe.c
+++ b/arch/sh/kernel/cpu/sh5/probe.c
@@ -17,7 +17,7 @@
 #include <asm/cache.h>
 #include <asm/tlb.h>
 
-int __init detect_cpu_and_cache_system(void)
+void __cpuinit cpu_probe(void)
 {
         unsigned long long cir;
 
@@ -34,6 +34,8 @@ int __init detect_cpu_and_cache_system(void)
                 /* CPU.VCR aliased at CIR address on SH5-101 */
                 boot_cpu_data.type = CPU_SH5_101;
 
+        boot_cpu_data.family = CPU_FAMILY_SH5;
+
         /*
          * First, setup some sane values for the I-cache.
          */
@@ -70,6 +72,4 @@ int __init detect_cpu_and_cache_system(void)
 
         /* Setup some I/D TLB defaults */
         sh64_tlb_init();
-
-        return 0;
 }
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index 72aa86ec7446..18419f1de963 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -16,24 +16,20 @@
 #include <linux/sh_timer.h>
 #include <asm/addrspace.h>
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = PHYS_PERIPHERAL_BLOCK + 0x01030000,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 39, 40, 42, 0 },
-        }, {
-                .flags = 0,
-        }
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = PHYS_PERIPHERAL_BLOCK + 0x01030000,
+        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 39, 40, 42, 0 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif0_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 0,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif0_platform_data,
         },
 };
 
@@ -74,16 +70,13 @@ static struct platform_device rtc_device = {
 #define TMU2_BASE       (TMU_BASE + 0x8 + (0xc * 0x2))
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = TMU0_BASE,
                 .end    = TMU0_BASE + 0xc - 1,
                 .flags  = IORESOURCE_MEM,
@@ -105,16 +98,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = TMU1_BASE,
                 .end    = TMU1_BASE + 0xc - 1,
                 .flags  = IORESOURCE_MEM,
@@ -136,15 +126,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = TMU2_BASE,
                 .end    = TMU2_BASE + 0xc - 1,
                 .flags  = IORESOURCE_MEM,
@@ -166,13 +153,13 @@ static struct platform_device tmu2_device = {
 };
 
 static struct platform_device *sh5_early_devices[] __initdata = {
+        &scif0_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
 };
 
 static struct platform_device *sh5_devices[] __initdata = {
-        &sci_device,
         &rtc_device,
 };
 
@@ -188,7 +175,7 @@ static int __init sh5_devices_setup(void)
         return platform_add_devices(sh5_devices,
                                     ARRAY_SIZE(sh5_devices));
 }
-__initcall(sh5_devices_setup);
+arch_initcall(sh5_devices_setup);
 
 void __init plat_early_device_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/shmobile/Makefile b/arch/sh/kernel/cpu/shmobile/Makefile
index 08bfa7c7db29..a39f88ea1a85 100644
--- a/arch/sh/kernel/cpu/shmobile/Makefile
+++ b/arch/sh/kernel/cpu/shmobile/Makefile
@@ -4,3 +4,5 @@
 
 # Power Management & Sleep mode
 obj-$(CONFIG_PM)        += pm.o sleep.o
+obj-$(CONFIG_CPU_IDLE)  += cpuidle.o
+obj-$(CONFIG_PM_RUNTIME)        += pm_runtime.o
diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
new file mode 100644
index 000000000000..83972aa319c2
--- /dev/null
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -0,0 +1,119 @@
+/*
+ * arch/sh/kernel/cpu/shmobile/cpuidle.c
+ *
+ * Cpuidle support code for SuperH Mobile
+ *
+ *  Copyright (C) 2009 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/suspend.h>
+#include <linux/cpuidle.h>
+#include <asm/suspend.h>
+#include <asm/uaccess.h>
+#include <asm/hwblk.h>
+
+static unsigned long cpuidle_mode[] = {
+        SUSP_SH_SLEEP, /* regular sleep mode */
+        SUSP_SH_SLEEP | SUSP_SH_SF, /* sleep mode + self refresh */
+        SUSP_SH_STANDBY | SUSP_SH_SF, /* software standby mode + self refresh */
+};
+
+static int cpuidle_sleep_enter(struct cpuidle_device *dev,
+                               struct cpuidle_state *state)
+{
+        unsigned long allowed_mode = arch_hwblk_sleep_mode();
+        ktime_t before, after;
+        int requested_state = state - &dev->states[0];
+        int allowed_state;
+        int k;
+
+        /* convert allowed mode to allowed state */
+        for (k = ARRAY_SIZE(cpuidle_mode) - 1; k > 0; k--)
+                if (cpuidle_mode[k] == allowed_mode)
+                        break;
+
+        allowed_state = k;
+
+        /* take the following into account for sleep mode selection:
+         * - allowed_state: best mode allowed by hardware (clock deps)
+         * - requested_state: best mode allowed by software (latencies)
+         */
+        k = min_t(int, allowed_state, requested_state);
+
+        dev->last_state = &dev->states[k];
+        before = ktime_get();
+        sh_mobile_call_standby(cpuidle_mode[k]);
+        after = ktime_get();
+        return ktime_to_ns(ktime_sub(after, before)) >> 10;
+}
+
+static struct cpuidle_device cpuidle_dev;
+static struct cpuidle_driver cpuidle_driver = {
+        .name =         "sh_idle",
+        .owner =        THIS_MODULE,
+};
+
+void sh_mobile_setup_cpuidle(void)
+{
+        struct cpuidle_device *dev = &cpuidle_dev;
+        struct cpuidle_state *state;
+        int i;
+
+        cpuidle_register_driver(&cpuidle_driver);
+
+        for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
+                dev->states[i].name[0] = '\0';
+                dev->states[i].desc[0] = '\0';
+        }
+
+        i = CPUIDLE_DRIVER_STATE_START;
+
+        state = &dev->states[i++];
+        snprintf(state->name, CPUIDLE_NAME_LEN, "C0");
+        strncpy(state->desc, "SuperH Sleep Mode", CPUIDLE_DESC_LEN);
+        state->exit_latency = 1;
+        state->target_residency = 1 * 2;
+        state->power_usage = 3;
+        state->flags = 0;
+        state->flags |= CPUIDLE_FLAG_SHALLOW;
+        state->flags |= CPUIDLE_FLAG_TIME_VALID;
+        state->enter = cpuidle_sleep_enter;
+
+        dev->safe_state = state;
+
+        if (sh_mobile_sleep_supported & SUSP_SH_SF) {
+                state = &dev->states[i++];
+                snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
+                strncpy(state->desc, "SuperH Sleep Mode [SF]",
+                        CPUIDLE_DESC_LEN);
+                state->exit_latency = 100;
+                state->target_residency = 1 * 2;
+                state->power_usage = 1;
+                state->flags = 0;
+                state->flags |= CPUIDLE_FLAG_TIME_VALID;
+                state->enter = cpuidle_sleep_enter;
+        }
+
+        if (sh_mobile_sleep_supported & SUSP_SH_STANDBY) {
+                state = &dev->states[i++];
+                snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
+                strncpy(state->desc, "SuperH Mobile Standby Mode [SF]",
+                        CPUIDLE_DESC_LEN);
+                state->exit_latency = 2300;
+                state->target_residency = 1 * 2;
+                state->power_usage = 1;
+                state->flags = 0;
+                state->flags |= CPUIDLE_FLAG_TIME_VALID;
+                state->enter = cpuidle_sleep_enter;
+        }
+
+        dev->state_count = i;
+
+        cpuidle_register_device(dev);
+}
diff --git a/arch/sh/kernel/cpu/shmobile/pm.c b/arch/sh/kernel/cpu/shmobile/pm.c
index 8c067adf6830..e55968712706 100644
--- a/arch/sh/kernel/cpu/shmobile/pm.c
+++ b/arch/sh/kernel/cpu/shmobile/pm.c
@@ -1,5 +1,5 @@
 /*
- * arch/sh/kernel/cpu/sh4a/pm-sh_mobile.c
+ * arch/sh/kernel/cpu/shmobile/pm.c
  *
  * Power management support code for SuperH Mobile
  *
@@ -15,6 +15,13 @@
 #include <linux/suspend.h>
 #include <asm/suspend.h>
 #include <asm/uaccess.h>
+#include <asm/cacheflush.h>
+
+/*
+ * Notifier lists for pre/post sleep notification
+ */
+ATOMIC_NOTIFIER_HEAD(sh_mobile_pre_sleep_notifier_list);
+ATOMIC_NOTIFIER_HEAD(sh_mobile_post_sleep_notifier_list);
 
 /*
  * Sleep modes available on SuperH Mobile:
@@ -26,50 +33,106 @@
 #define SUSP_MODE_SLEEP         (SUSP_SH_SLEEP)
 #define SUSP_MODE_SLEEP_SF      (SUSP_SH_SLEEP | SUSP_SH_SF)
 #define SUSP_MODE_STANDBY_SF    (SUSP_SH_STANDBY | SUSP_SH_SF)
+#define SUSP_MODE_RSTANDBY_SF \
+        (SUSP_SH_RSTANDBY | SUSP_SH_MMU | SUSP_SH_REGS | SUSP_SH_SF)
+ /*
+  * U-standby mode is unsupported since it needs bootloader hacks
+  */
 
-/*
- * The following modes are not there yet:
- *
- * R-standby mode is unsupported, but will be added in the future
- * U-standby mode is low priority since it needs bootloader hacks
- *
- * All modes should be tied in with cpuidle. But before that can
- * happen we need to keep track of enabled hardware blocks so we
- * can avoid entering sleep modes that stop clocks to hardware
- * blocks that are in use even though the cpu core is idle.
- */
-
-extern const unsigned char sh_mobile_standby[];
-extern const unsigned int sh_mobile_standby_size;
+#ifdef CONFIG_CPU_SUBTYPE_SH7724
+#define RAM_BASE 0xfd800000 /* RSMEM */
+#else
+#define RAM_BASE 0xe5200000 /* ILRAM */
+#endif
 
-static void sh_mobile_call_standby(unsigned long mode)
+void sh_mobile_call_standby(unsigned long mode)
 {
-        extern void *vbr_base;
-        void *onchip_mem = (void *)0xe5200000; /* ILRAM */
-        void (*standby_onchip_mem)(unsigned long) = onchip_mem;
-
-        /* Note: Wake up from sleep may generate exceptions!
-         * Setup VBR to point to on-chip ram if self-refresh is
-         * going to be used.
-         */
-        if (mode & SUSP_SH_SF)
-                asm volatile("ldc %0, vbr" : : "r" (onchip_mem) : "memory");
-
-        /* Copy the assembly snippet to the otherwise ununsed ILRAM */
-        memcpy(onchip_mem, sh_mobile_standby, sh_mobile_standby_size);
-        wmb();
-        ctrl_barrier();
+        void *onchip_mem = (void *)RAM_BASE;
+        struct sh_sleep_data *sdp = onchip_mem;
+        void (*standby_onchip_mem)(unsigned long, unsigned long);
+
+        /* code located directly after data structure */
+        standby_onchip_mem = (void *)(sdp + 1);
+
+        atomic_notifier_call_chain(&sh_mobile_pre_sleep_notifier_list,
+                                   mode, NULL);
+
+        /* flush the caches if MMU flag is set */
+        if (mode & SUSP_SH_MMU)
+                flush_cache_all();
 
         /* Let assembly snippet in on-chip memory handle the rest */
-        standby_onchip_mem(mode);
+        standby_onchip_mem(mode, RAM_BASE);
+
+        atomic_notifier_call_chain(&sh_mobile_post_sleep_notifier_list,
+                                   mode, NULL);
+}
+
+extern char sh_mobile_sleep_enter_start;
+extern char sh_mobile_sleep_enter_end;
+
+extern char sh_mobile_sleep_resume_start;
+extern char sh_mobile_sleep_resume_end;
+
+unsigned long sh_mobile_sleep_supported = SUSP_SH_SLEEP;
+
+void sh_mobile_register_self_refresh(unsigned long flags,
+                                     void *pre_start, void *pre_end,
+                                     void *post_start, void *post_end)
+{
+        void *onchip_mem = (void *)RAM_BASE;
+        void *vp;
+        struct sh_sleep_data *sdp;
+        int n;
 
-        /* Put VBR back in System RAM again */
-        if (mode & SUSP_SH_SF)
-                asm volatile("ldc %0, vbr" : : "r" (&vbr_base) : "memory");
+        /* part 0: data area */
+        sdp = onchip_mem;
+        sdp->addr.stbcr = 0xa4150020; /* STBCR */
+        sdp->addr.bar = 0xa4150040; /* BAR */
+        sdp->addr.pteh = 0xff000000; /* PTEH */
+        sdp->addr.ptel = 0xff000004; /* PTEL */
+        sdp->addr.ttb = 0xff000008; /* TTB */
+        sdp->addr.tea = 0xff00000c; /* TEA */
+        sdp->addr.mmucr = 0xff000010; /* MMUCR */
+        sdp->addr.ptea = 0xff000034; /* PTEA */
+        sdp->addr.pascr = 0xff000070; /* PASCR */
+        sdp->addr.irmcr = 0xff000078; /* IRMCR */
+        sdp->addr.ccr = 0xff00001c; /* CCR */
+        sdp->addr.ramcr = 0xff000074; /* RAMCR */
+        vp = sdp + 1;
+
+        /* part 1: common code to enter sleep mode */
+        n = &sh_mobile_sleep_enter_end - &sh_mobile_sleep_enter_start;
+        memcpy(vp, &sh_mobile_sleep_enter_start, n);
+        vp += roundup(n, 4);
+
+        /* part 2: board specific code to enter self-refresh mode */
+        n = pre_end - pre_start;
+        memcpy(vp, pre_start, n);
+        sdp->sf_pre = (unsigned long)vp;
+        vp += roundup(n, 4);
+
+        /* part 3: board specific code to resume from self-refresh mode */
+        n = post_end - post_start;
+        memcpy(vp, post_start, n);
+        sdp->sf_post = (unsigned long)vp;
+        vp += roundup(n, 4);
+
+        /* part 4: common code to resume from sleep mode */
+        WARN_ON(vp > (onchip_mem + 0x600));
+        vp = onchip_mem + 0x600; /* located at interrupt vector */
+        n = &sh_mobile_sleep_resume_end - &sh_mobile_sleep_resume_start;
+        memcpy(vp, &sh_mobile_sleep_resume_start, n);
+        sdp->resume = (unsigned long)vp;
+
+        sh_mobile_sleep_supported |= flags;
 }
 
 static int sh_pm_enter(suspend_state_t state)
 {
+        if (!(sh_mobile_sleep_supported & SUSP_MODE_STANDBY_SF))
+                return -ENXIO;
+
         local_irq_disable();
         set_bl_bit();
         sh_mobile_call_standby(SUSP_MODE_STANDBY_SF);
@@ -86,6 +149,7 @@ static struct platform_suspend_ops sh_pm_ops = {
 static int __init sh_pm_init(void)
 {
         suspend_set_ops(&sh_pm_ops);
+        sh_mobile_setup_cpuidle();
         return 0;
 }
 
diff --git a/arch/sh/kernel/cpu/shmobile/pm_runtime.c b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
new file mode 100644
index 000000000000..6dcb8166a64d
--- /dev/null
+++ b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
@@ -0,0 +1,308 @@
+/*
+ * arch/sh/kernel/cpu/shmobile/pm_runtime.c
+ *
+ * Runtime PM support code for SuperH Mobile
+ *
+ *  Copyright (C) 2009 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <asm/hwblk.h>
+
+static DEFINE_SPINLOCK(hwblk_lock);
+static LIST_HEAD(hwblk_idle_list);
+static struct work_struct hwblk_work;
+
+extern struct hwblk_info *hwblk_info;
+
+static void platform_pm_runtime_not_idle(struct platform_device *pdev)
+{
+        unsigned long flags;
+
+        /* remove device from idle list */
+        spin_lock_irqsave(&hwblk_lock, flags);
+        if (test_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags)) {
+                list_del(&pdev->archdata.entry);
+                __clear_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags);
+        }
+        spin_unlock_irqrestore(&hwblk_lock, flags);
+}
+
+static int __platform_pm_runtime_resume(struct platform_device *pdev)
+{
+        struct device *d = &pdev->dev;
+        struct pdev_archdata *ad = &pdev->archdata;
+        int hwblk = ad->hwblk_id;
+        int ret = -ENOSYS;
+
+        dev_dbg(d, "__platform_pm_runtime_resume() [%d]\n", hwblk);
+
+        if (d->driver) {
+                hwblk_enable(hwblk_info, hwblk);
+                ret = 0;
+
+                if (test_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags)) {
+                        if (d->driver->pm && d->driver->pm->runtime_resume)
+                                ret = d->driver->pm->runtime_resume(d);
+
+                        if (!ret)
+                                clear_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
+                        else
+                                hwblk_disable(hwblk_info, hwblk);
+                }
+        }
+
+        dev_dbg(d, "__platform_pm_runtime_resume() [%d] - returns %d\n",
+                hwblk, ret);
+
+        return ret;
+}
+
+static int __platform_pm_runtime_suspend(struct platform_device *pdev)
+{
+        struct device *d = &pdev->dev;
+        struct pdev_archdata *ad = &pdev->archdata;
+        int hwblk = ad->hwblk_id;
+        int ret = -ENOSYS;
+
+        dev_dbg(d, "__platform_pm_runtime_suspend() [%d]\n", hwblk);
+
+        if (d->driver) {
+                BUG_ON(!test_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags));
+                ret = 0;
+
+                if (d->driver->pm && d->driver->pm->runtime_suspend) {
+                        hwblk_enable(hwblk_info, hwblk);
+                        ret = d->driver->pm->runtime_suspend(d);
+                        hwblk_disable(hwblk_info, hwblk);
+                }
+
+                if (!ret) {
+                        set_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
+                        platform_pm_runtime_not_idle(pdev);
+                        hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE);
+                }
+        }
+
+        dev_dbg(d, "__platform_pm_runtime_suspend() [%d] - returns %d\n",
+                hwblk, ret);
+
+        return ret;
+}
+
+static void platform_pm_runtime_work(struct work_struct *work)
+{
+        struct platform_device *pdev;
+        unsigned long flags;
+        int ret;
+
+        /* go through the idle list and suspend one device at a time */
+        do {
+                spin_lock_irqsave(&hwblk_lock, flags);
+                if (list_empty(&hwblk_idle_list))
+                        pdev = NULL;
+                else
+                        pdev = list_first_entry(&hwblk_idle_list,
+                                                struct platform_device,
+                                                archdata.entry);
+                spin_unlock_irqrestore(&hwblk_lock, flags);
+
+                if (pdev) {
+                        mutex_lock(&pdev->archdata.mutex);
+                        ret = __platform_pm_runtime_suspend(pdev);
+
+                        /* at this point the platform device may be:
+                         * suspended: ret = 0, FLAG_SUSP set, clock stopped
+                         * failed: ret < 0, FLAG_IDLE set, clock stopped
+                         */
+                        mutex_unlock(&pdev->archdata.mutex);
+                } else {
+                        ret = -ENODEV;
+                }
+        } while (!ret);
+}
+
+/* this function gets called from cpuidle context when all devices in the
+ * main power domain are unused but some are counted as idle, ie the hwblk
+ * counter values are (HWBLK_CNT_USAGE == 0) && (HWBLK_CNT_IDLE != 0)
+ */
+void platform_pm_runtime_suspend_idle(void)
+{
+        queue_work(pm_wq, &hwblk_work);
+}
+
+int platform_pm_runtime_suspend(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct pdev_archdata *ad = &pdev->archdata;
+        unsigned long flags;
+        int hwblk = ad->hwblk_id;
+        int ret = 0;
+
+        dev_dbg(dev, "platform_pm_runtime_suspend() [%d]\n", hwblk);
+
+        /* ignore off-chip platform devices */
+        if (!hwblk)
+                goto out;
+
+        /* interrupt context not allowed */
+        might_sleep();
+
+        /* catch misconfigured drivers not starting with resume */
+        if (test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags)) {
+                ret = -EINVAL;
+                goto out;
+        }
+
+        /* serialize */
+        mutex_lock(&ad->mutex);
+
+        /* disable clock */
+        hwblk_disable(hwblk_info, hwblk);
+
+        /* put device on idle list */
+        spin_lock_irqsave(&hwblk_lock, flags);
+        list_add_tail(&pdev->archdata.entry, &hwblk_idle_list);
+        __set_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags);
+        spin_unlock_irqrestore(&hwblk_lock, flags);
+
+        /* increase idle count */
+        hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_IDLE);
+
+        /* at this point the platform device is:
+         * idle: ret = 0, FLAG_IDLE set, clock stopped
+         */
+        mutex_unlock(&ad->mutex);
+
+out:
+        dev_dbg(dev, "platform_pm_runtime_suspend() [%d] returns %d\n",
+                hwblk, ret);
+
+        return ret;
+}
+
+int platform_pm_runtime_resume(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct pdev_archdata *ad = &pdev->archdata;
+        int hwblk = ad->hwblk_id;
+        int ret = 0;
+
+        dev_dbg(dev, "platform_pm_runtime_resume() [%d]\n", hwblk);
+
+        /* ignore off-chip platform devices */
+        if (!hwblk)
+                goto out;
+
+        /* interrupt context not allowed */
+        might_sleep();
+
+        /* serialize */
+        mutex_lock(&ad->mutex);
+
+        /* make sure device is removed from idle list */
+        platform_pm_runtime_not_idle(pdev);
+
+        /* decrease idle count */
+        if (!test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags) &&
+            !test_bit(PDEV_ARCHDATA_FLAG_SUSP, &pdev->archdata.flags))
+                hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE);
+
+        /* resume the device if needed */
+        ret = __platform_pm_runtime_resume(pdev);
+
+        /* the driver has been initialized now, so clear the init flag */
+        clear_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
+
+        /* at this point the platform device may be:
+         * resumed: ret = 0, flags = 0, clock started
+         * failed: ret < 0, FLAG_SUSP set, clock stopped
+         */
+        mutex_unlock(&ad->mutex);
+out:
+        dev_dbg(dev, "platform_pm_runtime_resume() [%d] returns %d\n",
+                hwblk, ret);
+
+        return ret;
+}
+
+int platform_pm_runtime_idle(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        int hwblk = pdev->archdata.hwblk_id;
+        int ret = 0;
+
+        dev_dbg(dev, "platform_pm_runtime_idle() [%d]\n", hwblk);
+
+        /* ignore off-chip platform devices */
+        if (!hwblk)
+                goto out;
+
+        /* interrupt context not allowed, use pm_runtime_put()! */
+        might_sleep();
+
+        /* suspend synchronously to disable clocks immediately */
+        ret = pm_runtime_suspend(dev);
+out:
+        dev_dbg(dev, "platform_pm_runtime_idle() [%d] done!\n", hwblk);
+        return ret;
+}
+
+static int platform_bus_notify(struct notifier_block *nb,
+                               unsigned long action, void *data)
+{
+        struct device *dev = data;
+        struct platform_device *pdev = to_platform_device(dev);
+        int hwblk = pdev->archdata.hwblk_id;
+
+        /* ignore off-chip platform devices */
+        if (!hwblk)
+                return 0;
+
+        switch (action) {
+        case BUS_NOTIFY_ADD_DEVICE:
+                INIT_LIST_HEAD(&pdev->archdata.entry);
+                mutex_init(&pdev->archdata.mutex);
+                /* platform devices without drivers should be disabled */
+                hwblk_enable(hwblk_info, hwblk);
+                hwblk_disable(hwblk_info, hwblk);
+                /* make sure driver re-inits itself once */
+                __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
+                break;
+        /* TODO: add BUS_NOTIFY_BIND_DRIVER and increase idle count */
+        case BUS_NOTIFY_BOUND_DRIVER:
+                /* keep track of number of devices in use per hwblk */
+                hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_DEVICES);
+                break;
+        case BUS_NOTIFY_UNBOUND_DRIVER:
+                /* keep track of number of devices in use per hwblk */
+                hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_DEVICES);
+                /* make sure driver re-inits itself once */
+                __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
+                break;
+        case BUS_NOTIFY_DEL_DEVICE:
+                break;
+        }
+        return 0;
+}
+
+static struct notifier_block platform_bus_notifier = {
+        .notifier_call = platform_bus_notify
+};
+
+static int __init sh_pm_runtime_init(void)
+{
+        INIT_WORK(&hwblk_work, platform_pm_runtime_work);
+
+        bus_register_notifier(&platform_bus_type, &platform_bus_notifier);
+        return 0;
+}
+core_initcall(sh_pm_runtime_init);
diff --git a/arch/sh/kernel/cpu/shmobile/sleep.S b/arch/sh/kernel/cpu/shmobile/sleep.S
index 5d888ef53d82..e6aac65f5750 100644
--- a/arch/sh/kernel/cpu/shmobile/sleep.S
+++ b/arch/sh/kernel/cpu/shmobile/sleep.S
@@ -16,35 +16,147 @@
 #include <asm/asm-offsets.h>
 #include <asm/suspend.h>
 
-/* manage self-refresh and enter standby mode.
+/*
+ * Kernel mode register usage, see entry.S:
+ *      k0      scratch
+ *      k1      scratch
+ */
+#define k0      r0
+#define k1      r1
+
+/* manage self-refresh and enter standby mode. must be self-contained.
  * this code will be copied to on-chip memory and executed from there.
  */
+        .balign 4
+ENTRY(sh_mobile_sleep_enter_start)
+
+        /* save mode flags */
+        mov.l   r4, @(SH_SLEEP_MODE, r5)
+
+        /* save original vbr */
+        stc     vbr, r0
+        mov.l   r0, @(SH_SLEEP_VBR, r5)
+
+        /* point vbr to our on-chip memory page */
+        ldc     r5, vbr
+
+        /* save return address */
+        sts     pr, r0
+        mov.l   r0, @(SH_SLEEP_SPC, r5)
+
+        /* save sr */
+        stc     sr, r0
+        mov.l   r0, @(SH_SLEEP_SR, r5)
+
+        /* save general purpose registers to stack if needed */
+        mov.l   @(SH_SLEEP_MODE, r5), r0
+        tst     #SUSP_SH_REGS, r0
+        bt      skip_regs_save
+
+        sts.l   pr, @-r15
+        mov.l   r14, @-r15
+        mov.l   r13, @-r15
+        mov.l   r12, @-r15
+        mov.l   r11, @-r15
+        mov.l   r10, @-r15
+        mov.l   r9, @-r15
+        mov.l   r8, @-r15
+
+        /* make sure bank0 is selected, save low registers */
+        mov.l   rb_bit, r9
+        not     r9, r9
+        bsr     set_sr
+         mov    #0, r10
+
+        bsr     save_low_regs
+         nop
+
+        /* switch to bank 1, save low registers */
+        mov.l   rb_bit, r10
+        bsr     set_sr
+         mov    #-1, r9
+
+        bsr     save_low_regs
+         nop
+
+        /* switch back to bank 0 */
+        mov.l   rb_bit, r9
+        not     r9, r9
+        bsr     set_sr
+         mov    #0, r10
+
+skip_regs_save:
+
+        /* save sp, also set to internal ram */
+        mov.l   r15, @(SH_SLEEP_SP, r5)
+        mov     r5, r15
+
+        /* save stbcr */
+        bsr     save_register
+         mov    #SH_SLEEP_REG_STBCR, r0
+
+        /* save mmu and cache context if needed */
+        mov.l   @(SH_SLEEP_MODE, r5), r0
+        tst     #SUSP_SH_MMU, r0
+        bt      skip_mmu_save_disable
+
+        /* save mmu state */
+        bsr     save_register
+         mov    #SH_SLEEP_REG_PTEH, r0
+
+        bsr     save_register
+         mov    #SH_SLEEP_REG_PTEL, r0
+
+        bsr     save_register
+         mov    #SH_SLEEP_REG_TTB, r0
+
+        bsr     save_register
+         mov    #SH_SLEEP_REG_TEA, r0
 
-        .balign         4096,0,4096
-ENTRY(sh_mobile_standby)
-        mov     r4, r0
+        bsr     save_register
+         mov    #SH_SLEEP_REG_MMUCR, r0
 
+        bsr     save_register
+         mov    #SH_SLEEP_REG_PTEA, r0
+
+        bsr     save_register
+         mov    #SH_SLEEP_REG_PASCR, r0
+
+        bsr     save_register
+         mov    #SH_SLEEP_REG_IRMCR, r0
+
+        /* invalidate TLBs and disable the MMU */
+        bsr     get_register
+         mov    #SH_SLEEP_REG_MMUCR, r0
+        mov     #4, r1
+        mov.l   r1, @r0
+        icbi    @r0
+
+        /* save cache registers and disable caches */
+        bsr     save_register
+         mov    #SH_SLEEP_REG_CCR, r0
+
+        bsr     save_register
+         mov    #SH_SLEEP_REG_RAMCR, r0
+
+        bsr     get_register
+         mov    #SH_SLEEP_REG_CCR, r0
+        mov     #0, r1
+        mov.l   r1, @r0
+        icbi    @r0
+
+skip_mmu_save_disable:
+        /* call self-refresh entering code if needed */
+        mov.l   @(SH_SLEEP_MODE, r5), r0
         tst     #SUSP_SH_SF, r0
         bt      skip_set_sf
 
-        /* SDRAM: disable power down and put in self-refresh mode */
-        mov.l   1f, r4
-        mov.l   2f, r1
-        mov.l   @r4, r2
-        or      r1, r2
-        mov.l   3f, r3
-        and     r3, r2
-        mov.l   r2, @r4
+        mov.l   @(SH_SLEEP_SF_PRE, r5), r0
+        jsr     @r0
+         nop
 
 skip_set_sf:
-        tst     #SUSP_SH_SLEEP, r0
-        bt      test_standby
-
-        /* set mode to "sleep mode" */
-        bra     do_sleep
-         mov    #0x00, r1
-
-test_standby:
+        mov.l   @(SH_SLEEP_MODE, r5), r0
         tst     #SUSP_SH_STANDBY, r0
         bt      test_rstandby
 
@@ -56,70 +168,238 @@ test_rstandby:
         tst     #SUSP_SH_RSTANDBY, r0
         bt      test_ustandby
 
+        /* setup BAR register */
+        bsr     get_register
+         mov    #SH_SLEEP_REG_BAR, r0
+        mov.l   @(SH_SLEEP_RESUME, r5), r1
+        mov.l   r1, @r0
+
         /* set mode to "r-standby mode" */
         bra     do_sleep
          mov    #0x20, r1
 
 test_ustandby:
         tst     #SUSP_SH_USTANDBY, r0
-        bt      done_sleep
+        bt      force_sleep
 
         /* set mode to "u-standby mode" */
-        mov     #0x10, r1
+        bra     do_sleep
+         mov    #0x10, r1
+
+force_sleep:
 
-        /* fall-through */
+        /* set mode to "sleep mode" */
+        mov     #0x00, r1
 
 do_sleep:
         /* setup and enter selected standby mode */
-        mov.l   5f, r4
-        mov.l   r1, @r4
+        bsr     get_register
+         mov    #SH_SLEEP_REG_STBCR, r0
+        mov.l   r1, @r0
+again:
         sleep
+        bra     again
+         nop
 
-done_sleep:
-        /* reset standby mode to sleep mode */
-        mov.l   5f, r4
-        mov     #0x00, r1
-        mov.l   r1, @r4
+save_register:
+        add     #SH_SLEEP_BASE_ADDR, r0
+        mov.l   @(r0, r5), r1
+        add     #-SH_SLEEP_BASE_ADDR, r0
+        mov.l   @r1, r1
+        add     #SH_SLEEP_BASE_DATA, r0
+        mov.l   r1, @(r0, r5)
+        add     #-SH_SLEEP_BASE_DATA, r0
+        rts
+         nop
+
+get_register:
+        add     #SH_SLEEP_BASE_ADDR, r0
+        mov.l   @(r0, r5), r0
+        rts
+         nop
 
+set_sr:
+        stc     sr, r8
+        and     r9, r8
+        or      r10, r8
+        ldc     r8, sr
+        rts
+         nop
+
+save_low_regs:
+        mov.l   r7, @-r15
+        mov.l   r6, @-r15
+        mov.l   r5, @-r15
+        mov.l   r4, @-r15
+        mov.l   r3, @-r15
+        mov.l   r2, @-r15
+        mov.l   r1, @-r15
+        rts
+         mov.l  r0, @-r15
+
+        .balign 4
+rb_bit: .long   0x20000000 ! RB=1
+
+ENTRY(sh_mobile_sleep_enter_end)
+
+        .balign 4
+ENTRY(sh_mobile_sleep_resume_start)
+
+        /* figure out start address */
+        bsr     0f
+         nop
+0:
+        sts     pr, k1
+        mov.l   1f, k0
+        and     k0, k1
+
+        /* store pointer to data area in VBR */
+        ldc     k1, vbr
+
+        /* setup sr with saved sr */
+        mov.l   @(SH_SLEEP_SR, k1), k0
+        ldc     k0, sr
+
+        /* now: user register set! */
+        stc     vbr, r5
+
+        /* setup spc with return address to c code */
+        mov.l   @(SH_SLEEP_SPC, r5), r0
+        ldc     r0, spc
+
+        /* restore vbr */
+        mov.l   @(SH_SLEEP_VBR, r5), r0
+        ldc     r0, vbr
+
+        /* setup ssr with saved sr */
+        mov.l   @(SH_SLEEP_SR, r5), r0
+        ldc     r0, ssr
+
+        /* restore sp */
+        mov.l   @(SH_SLEEP_SP, r5), r15
+
+        /* restore sleep mode register */
+        bsr     restore_register
+         mov    #SH_SLEEP_REG_STBCR, r0
+
+        /* call self-refresh resume code if needed */
+        mov.l   @(SH_SLEEP_MODE, r5), r0
         tst     #SUSP_SH_SF, r0
         bt      skip_restore_sf
 
-        /* SDRAM: set auto-refresh mode */
-        mov.l   1f, r4
-        mov.l   @r4, r2
-        mov.l   4f, r3
-        and     r3, r2
-        mov.l   r2, @r4
-        mov.l   6f, r4
-        mov.l   7f, r1
-        mov.l   8f, r2
-        mov.l   @r4, r3
-        mov     #-1, r4
-        add     r4, r3
-        or      r2, r3
-        mov.l   r3, @r1
+        mov.l   @(SH_SLEEP_SF_POST, r5), r0
+        jsr     @r0
+         nop
+
 skip_restore_sf:
-        rts
+        /* restore mmu and cache state if needed */
+        mov.l   @(SH_SLEEP_MODE, r5), r0
+        tst     #SUSP_SH_MMU, r0
+        bt      skip_restore_mmu
+
+        /* restore mmu state */
+        bsr     restore_register
+         mov    #SH_SLEEP_REG_PTEH, r0
+
+        bsr     restore_register
+         mov    #SH_SLEEP_REG_PTEL, r0
+
+        bsr     restore_register
+         mov    #SH_SLEEP_REG_TTB, r0
+
+        bsr     restore_register
+         mov    #SH_SLEEP_REG_TEA, r0
+
+        bsr     restore_register
+         mov    #SH_SLEEP_REG_PTEA, r0
+
+        bsr     restore_register
+         mov    #SH_SLEEP_REG_PASCR, r0
+
+        bsr     restore_register
+         mov    #SH_SLEEP_REG_IRMCR, r0
+
+        bsr     restore_register
+         mov    #SH_SLEEP_REG_MMUCR, r0
+        icbi    @r0
+
+        /* restore cache settings */
+        bsr     restore_register
+         mov    #SH_SLEEP_REG_RAMCR, r0
+        icbi    @r0
+
+        bsr     restore_register
+         mov    #SH_SLEEP_REG_CCR, r0
+        icbi    @r0
+
+skip_restore_mmu:
+
+        /* restore general purpose registers if needed */
+        mov.l   @(SH_SLEEP_MODE, r5), r0
+        tst     #SUSP_SH_REGS, r0
+        bt      skip_restore_regs
+
+        /* switch to bank 1, restore low registers */
+        mov.l   _rb_bit, r10
+        bsr     _set_sr
+         mov    #-1, r9
+
+        bsr     restore_low_regs
          nop
 
-        .balign 4
-1:      .long   0xfe400008 /* SDCR0 */
-2:      .long   0x00000400
-3:      .long   0xffff7fff
-4:      .long   0xfffffbff
-5:      .long   0xa4150020 /* STBCR */
-6:      .long   0xfe40001c /* RTCOR */
-7:      .long   0xfe400018 /* RTCNT */
-8:      .long   0xa55a0000
-
-/* interrupt vector @ 0x600 */
-        .balign         0x400,0,0x400
-        .long   0xdeadbeef
-        .balign         0x200,0,0x200
-        /* sh7722 will end up here in sleep mode */
+        /* switch to bank0, restore low registers */
+        mov.l   _rb_bit, r9
+        not     r9, r9
+        bsr     _set_sr
+         mov    #0, r10
+
+        bsr     restore_low_regs
+         nop
+
+        /* restore the rest of the registers */
+        mov.l   @r15+, r8
+        mov.l   @r15+, r9
+        mov.l   @r15+, r10
+        mov.l   @r15+, r11
+        mov.l   @r15+, r12
+        mov.l   @r15+, r13
+        mov.l   @r15+, r14
+        lds.l   @r15+, pr
+
+skip_restore_regs:
         rte
          nop
-sh_mobile_standby_end:
 
-ENTRY(sh_mobile_standby_size)
-        .long sh_mobile_standby_end - sh_mobile_standby
+restore_register:
+        add     #SH_SLEEP_BASE_DATA, r0
+        mov.l   @(r0, r5), r1
+        add     #-SH_SLEEP_BASE_DATA, r0
+        add     #SH_SLEEP_BASE_ADDR, r0
+        mov.l   @(r0, r5), r0
+        mov.l   r1, @r0
+        rts
+         nop
+
+_set_sr:
+        stc     sr, r8
+        and     r9, r8
+        or      r10, r8
+        ldc     r8, sr
+        rts
+         nop
+
+restore_low_regs:
+        mov.l   @r15+, r0
+        mov.l   @r15+, r1
+        mov.l   @r15+, r2
+        mov.l   @r15+, r3
+        mov.l   @r15+, r4
+        mov.l   @r15+, r5
+        mov.l   @r15+, r6
+        rts
+         mov.l  @r15+, r7
+
+        .balign 4
+_rb_bit:        .long   0x20000000 ! RB=1
+1:      .long   ~0x7ff
+ENTRY(sh_mobile_sleep_resume_end)
diff --git a/arch/sh/kernel/cpu/ubc.S b/arch/sh/kernel/cpu/ubc.S
deleted file mode 100644
index 81923079fa12..000000000000
--- a/arch/sh/kernel/cpu/ubc.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * arch/sh/kernel/cpu/ubc.S
- *
- * Set of management routines for the User Break Controller (UBC)
- *
- * Copyright (C) 2002 Paul Mundt
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/linkage.h>
-#include <asm/ubc.h>
-
-#define STBCR2          0xffc00010
-
-ENTRY(ubc_sleep)
-        mov     #0, r0
-
-        mov.l   1f, r1          ! Zero out UBC_BBRA ..
-        mov.w   r0, @r1
-
-        mov.l   2f, r1          ! .. same for BBRB ..
-        mov.w   r0, @r1
-
-        mov.l   3f, r1          ! .. and again for BRCR.
-        mov.w   r0, @r1
-
-        mov.w   @r1, r0         ! Dummy read BRCR
-
-        mov.l   4f, r1          ! Set MSTP5 in STBCR2
-        mov.b   @r1, r0
-        or      #0x01, r0
-        mov.b   r0, @r1
-
-        mov.b   @r1, r0         ! Two dummy reads ..
-        mov.b   @r1, r0
-
-        rts
-        nop
-
-ENTRY(ubc_wakeup)
-        mov.l   4f, r1          ! Clear MSTP5
-        mov.b   @r1, r0
-        and     #0xfe, r0
-        mov.b   r0, @r1
-
-        mov.b   @r1, r0         ! Two more dummy reads ..
-        mov.b   @r1, r0
-
-        rts
-        nop
-
-1:      .long   UBC_BBRA
-2:      .long   UBC_BBRB
-3:      .long   UBC_BRCR
-4:      .long   STBCR2
-