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authorPaul Mundt <lethal@linux-sh.org>2011-01-13 01:06:28 -0500
committerPaul Mundt <lethal@linux-sh.org>2011-01-13 01:06:28 -0500
commitf43dc23d5ea91fca257be02138a255f02d98e806 (patch)
treeb29722f6e965316e90ac97abf79923ced250dc21 /arch/sh/kernel/cpu/sh5
parentf8e53553f452dcbf67cb89c8cba63a1cd6eb4cc0 (diff)
parent4162cf64973df51fc885825bc9ca4d055891c49f (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into common/serial-rework
Conflicts: arch/sh/kernel/cpu/sh2/setup-sh7619.c arch/sh/kernel/cpu/sh2a/setup-mxg.c arch/sh/kernel/cpu/sh2a/setup-sh7201.c arch/sh/kernel/cpu/sh2a/setup-sh7203.c arch/sh/kernel/cpu/sh2a/setup-sh7206.c arch/sh/kernel/cpu/sh3/setup-sh7705.c arch/sh/kernel/cpu/sh3/setup-sh770x.c arch/sh/kernel/cpu/sh3/setup-sh7710.c arch/sh/kernel/cpu/sh3/setup-sh7720.c arch/sh/kernel/cpu/sh4/setup-sh4-202.c arch/sh/kernel/cpu/sh4/setup-sh7750.c arch/sh/kernel/cpu/sh4/setup-sh7760.c arch/sh/kernel/cpu/sh4a/setup-sh7343.c arch/sh/kernel/cpu/sh4a/setup-sh7366.c arch/sh/kernel/cpu/sh4a/setup-sh7722.c arch/sh/kernel/cpu/sh4a/setup-sh7723.c arch/sh/kernel/cpu/sh4a/setup-sh7724.c arch/sh/kernel/cpu/sh4a/setup-sh7763.c arch/sh/kernel/cpu/sh4a/setup-sh7770.c arch/sh/kernel/cpu/sh4a/setup-sh7780.c arch/sh/kernel/cpu/sh4a/setup-sh7785.c arch/sh/kernel/cpu/sh4a/setup-sh7786.c arch/sh/kernel/cpu/sh4a/setup-shx3.c arch/sh/kernel/cpu/sh5/setup-sh5.c drivers/serial/sh-sci.c drivers/serial/sh-sci.h include/linux/serial_sci.h
Diffstat (limited to 'arch/sh/kernel/cpu/sh5')
-rw-r--r--arch/sh/kernel/cpu/sh5/clock-sh5.c8
-rw-r--r--arch/sh/kernel/cpu/sh5/entry.S8
-rw-r--r--arch/sh/kernel/cpu/sh5/fpu.c67
-rw-r--r--arch/sh/kernel/cpu/sh5/probe.c6
-rw-r--r--arch/sh/kernel/cpu/sh5/setup-sh5.c37
5 files changed, 30 insertions, 96 deletions
diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c
index 7f864ebc51d3..9cfc19b8dbe4 100644
--- a/arch/sh/kernel/cpu/sh5/clock-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c
@@ -24,7 +24,7 @@ static unsigned long cprc_base;
24 24
25static void master_clk_init(struct clk *clk) 25static void master_clk_init(struct clk *clk)
26{ 26{
27 int idx = (ctrl_inl(cprc_base + 0x00) >> 6) & 0x0007; 27 int idx = (__raw_readl(cprc_base + 0x00) >> 6) & 0x0007;
28 clk->rate *= ifc_table[idx]; 28 clk->rate *= ifc_table[idx];
29} 29}
30 30
@@ -34,7 +34,7 @@ static struct clk_ops sh5_master_clk_ops = {
34 34
35static unsigned long module_clk_recalc(struct clk *clk) 35static unsigned long module_clk_recalc(struct clk *clk)
36{ 36{
37 int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007; 37 int idx = (__raw_readw(cprc_base) >> 12) & 0x0007;
38 return clk->parent->rate / ifc_table[idx]; 38 return clk->parent->rate / ifc_table[idx];
39} 39}
40 40
@@ -44,7 +44,7 @@ static struct clk_ops sh5_module_clk_ops = {
44 44
45static unsigned long bus_clk_recalc(struct clk *clk) 45static unsigned long bus_clk_recalc(struct clk *clk)
46{ 46{
47 int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007; 47 int idx = (__raw_readw(cprc_base) >> 3) & 0x0007;
48 return clk->parent->rate / ifc_table[idx]; 48 return clk->parent->rate / ifc_table[idx];
49} 49}
50 50
@@ -54,7 +54,7 @@ static struct clk_ops sh5_bus_clk_ops = {
54 54
55static unsigned long cpu_clk_recalc(struct clk *clk) 55static unsigned long cpu_clk_recalc(struct clk *clk)
56{ 56{
57 int idx = (ctrl_inw(cprc_base) & 0x0007); 57 int idx = (__raw_readw(cprc_base) & 0x0007);
58 return clk->parent->rate / ifc_table[idx]; 58 return clk->parent->rate / ifc_table[idx];
59} 59}
60 60
diff --git a/arch/sh/kernel/cpu/sh5/entry.S b/arch/sh/kernel/cpu/sh5/entry.S
index b0aacf675258..6b80295dd7a4 100644
--- a/arch/sh/kernel/cpu/sh5/entry.S
+++ b/arch/sh/kernel/cpu/sh5/entry.S
@@ -187,7 +187,7 @@ trap_jtable:
187 .rept 6 187 .rept 6
188 .long do_exception_error /* 0x880 - 0x920 */ 188 .long do_exception_error /* 0x880 - 0x920 */
189 .endr 189 .endr
190 .long do_software_break_point /* 0x940 */ 190 .long breakpoint_trap_handler /* 0x940 */
191 .long do_exception_error /* 0x960 */ 191 .long do_exception_error /* 0x960 */
192 .long do_single_step /* 0x980 */ 192 .long do_single_step /* 0x980 */
193 193
@@ -933,7 +933,7 @@ ret_with_reschedule:
933 933
934 pta restore_all, tr1 934 pta restore_all, tr1
935 935
936 movi (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), r8 936 movi _TIF_SIGPENDING, r8
937 and r8, r7, r8 937 and r8, r7, r8
938 pta work_notifysig, tr0 938 pta work_notifysig, tr0
939 bne r8, ZERO, tr0 939 bne r8, ZERO, tr0
@@ -1124,7 +1124,7 @@ fpu_error_or_IRQA:
1124 pta its_IRQ, tr0 1124 pta its_IRQ, tr0
1125 beqi/l r4, EVENT_INTERRUPT, tr0 1125 beqi/l r4, EVENT_INTERRUPT, tr0
1126#ifdef CONFIG_SH_FPU 1126#ifdef CONFIG_SH_FPU
1127 movi do_fpu_state_restore, r6 1127 movi fpu_state_restore_trap_handler, r6
1128#else 1128#else
1129 movi do_exception_error, r6 1129 movi do_exception_error, r6
1130#endif 1130#endif
@@ -1135,7 +1135,7 @@ fpu_error_or_IRQB:
1135 pta its_IRQ, tr0 1135 pta its_IRQ, tr0
1136 beqi/l r4, EVENT_INTERRUPT, tr0 1136 beqi/l r4, EVENT_INTERRUPT, tr0
1137#ifdef CONFIG_SH_FPU 1137#ifdef CONFIG_SH_FPU
1138 movi do_fpu_state_restore, r6 1138 movi fpu_state_restore_trap_handler, r6
1139#else 1139#else
1140 movi do_exception_error, r6 1140 movi do_exception_error, r6
1141#endif 1141#endif
diff --git a/arch/sh/kernel/cpu/sh5/fpu.c b/arch/sh/kernel/cpu/sh5/fpu.c
index dd4f51ffb50e..4b3bb35e99f3 100644
--- a/arch/sh/kernel/cpu/sh5/fpu.c
+++ b/arch/sh/kernel/cpu/sh5/fpu.c
@@ -15,26 +15,8 @@
15#include <linux/sched.h> 15#include <linux/sched.h>
16#include <linux/signal.h> 16#include <linux/signal.h>
17#include <asm/processor.h> 17#include <asm/processor.h>
18#include <asm/user.h>
19#include <asm/io.h>
20#include <asm/fpu.h>
21 18
22/* 19void save_fpu(struct task_struct *tsk)
23 * Initially load the FPU with signalling NANS. This bit pattern
24 * has the property that no matter whether considered as single or as
25 * double precision, it still represents a signalling NAN.
26 */
27#define sNAN64 0xFFFFFFFFFFFFFFFFULL
28#define sNAN32 0xFFFFFFFFUL
29
30static union sh_fpu_union init_fpuregs = {
31 .hard = {
32 .fp_regs = { [0 ... 63] = sNAN32 },
33 .fpscr = FPSCR_INIT
34 }
35};
36
37void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
38{ 20{
39 asm volatile("fst.p %0, (0*8), fp0\n\t" 21 asm volatile("fst.p %0, (0*8), fp0\n\t"
40 "fst.p %0, (1*8), fp2\n\t" 22 "fst.p %0, (1*8), fp2\n\t"
@@ -72,12 +54,11 @@ void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
72 "fgetscr fr63\n\t" 54 "fgetscr fr63\n\t"
73 "fst.s %0, (32*8), fr63\n\t" 55 "fst.s %0, (32*8), fr63\n\t"
74 : /* no output */ 56 : /* no output */
75 : "r" (&tsk->thread.fpu.hard) 57 : "r" (&tsk->thread.xstate->hardfpu)
76 : "memory"); 58 : "memory");
77} 59}
78 60
79static inline void 61void restore_fpu(struct task_struct *tsk)
80fpload(struct sh_fpu_hard_struct *fpregs)
81{ 62{
82 asm volatile("fld.p %0, (0*8), fp0\n\t" 63 asm volatile("fld.p %0, (0*8), fp0\n\t"
83 "fld.p %0, (1*8), fp2\n\t" 64 "fld.p %0, (1*8), fp2\n\t"
@@ -116,16 +97,11 @@ fpload(struct sh_fpu_hard_struct *fpregs)
116 97
117 "fld.p %0, (31*8), fp62\n\t" 98 "fld.p %0, (31*8), fp62\n\t"
118 : /* no output */ 99 : /* no output */
119 : "r" (fpregs) ); 100 : "r" (&tsk->thread.xstate->hardfpu)
120} 101 : "memory");
121
122void fpinit(struct sh_fpu_hard_struct *fpregs)
123{
124 *fpregs = init_fpuregs.hard;
125} 102}
126 103
127asmlinkage void 104asmlinkage void do_fpu_error(unsigned long ex, struct pt_regs *regs)
128do_fpu_error(unsigned long ex, struct pt_regs *regs)
129{ 105{
130 struct task_struct *tsk = current; 106 struct task_struct *tsk = current;
131 107
@@ -133,35 +109,6 @@ do_fpu_error(unsigned long ex, struct pt_regs *regs)
133 109
134 tsk->thread.trap_no = 11; 110 tsk->thread.trap_no = 11;
135 tsk->thread.error_code = 0; 111 tsk->thread.error_code = 0;
136 force_sig(SIGFPE, tsk);
137}
138
139
140asmlinkage void
141do_fpu_state_restore(unsigned long ex, struct pt_regs *regs)
142{
143 void die(const char *str, struct pt_regs *regs, long err);
144
145 if (! user_mode(regs))
146 die("FPU used in kernel", regs, ex);
147 112
148 regs->sr &= ~SR_FD; 113 force_sig(SIGFPE, tsk);
149
150 if (last_task_used_math == current)
151 return;
152
153 enable_fpu();
154 if (last_task_used_math != NULL)
155 /* Other processes fpu state, save away */
156 save_fpu(last_task_used_math, regs);
157
158 last_task_used_math = current;
159 if (used_math()) {
160 fpload(&current->thread.fpu.hard);
161 } else {
162 /* First time FPU user. */
163 fpload(&init_fpuregs.hard);
164 set_used_math();
165 }
166 disable_fpu();
167} 114}
diff --git a/arch/sh/kernel/cpu/sh5/probe.c b/arch/sh/kernel/cpu/sh5/probe.c
index 92ad844b5c12..9e882409e4e9 100644
--- a/arch/sh/kernel/cpu/sh5/probe.c
+++ b/arch/sh/kernel/cpu/sh5/probe.c
@@ -17,7 +17,7 @@
17#include <asm/cache.h> 17#include <asm/cache.h>
18#include <asm/tlb.h> 18#include <asm/tlb.h>
19 19
20int __init detect_cpu_and_cache_system(void) 20void __cpuinit cpu_probe(void)
21{ 21{
22 unsigned long long cir; 22 unsigned long long cir;
23 23
@@ -34,6 +34,8 @@ int __init detect_cpu_and_cache_system(void)
34 /* CPU.VCR aliased at CIR address on SH5-101 */ 34 /* CPU.VCR aliased at CIR address on SH5-101 */
35 boot_cpu_data.type = CPU_SH5_101; 35 boot_cpu_data.type = CPU_SH5_101;
36 36
37 boot_cpu_data.family = CPU_FAMILY_SH5;
38
37 /* 39 /*
38 * First, setup some sane values for the I-cache. 40 * First, setup some sane values for the I-cache.
39 */ 41 */
@@ -70,6 +72,4 @@ int __init detect_cpu_and_cache_system(void)
70 72
71 /* Setup some I/D TLB defaults */ 73 /* Setup some I/D TLB defaults */
72 sh64_tlb_init(); 74 sh64_tlb_init();
73
74 return 0;
75} 75}
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index 72aa86ec7446..18419f1de963 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -16,24 +16,20 @@
16#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17#include <asm/addrspace.h> 17#include <asm/addrspace.h>
18 18
19static struct plat_sci_port sci_platform_data[] = { 19static struct plat_sci_port scif0_platform_data = {
20 { 20 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000,
21 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000, 21 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
22 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 23 .scbrr_algo_id = SCBRR_ALGO_2,
24 .scbrr_algo_id = SCBRR_ALGO_2, 24 .type = PORT_SCIF,
25 .type = PORT_SCIF, 25 .irqs = { 39, 40, 42, 0 },
26 .irqs = { 39, 40, 42, 0 },
27 }, {
28 .flags = 0,
29 }
30}; 26};
31 27
32static struct platform_device sci_device = { 28static struct platform_device scif0_device = {
33 .name = "sh-sci", 29 .name = "sh-sci",
34 .id = -1, 30 .id = 0,
35 .dev = { 31 .dev = {
36 .platform_data = sci_platform_data, 32 .platform_data = &scif0_platform_data,
37 }, 33 },
38}; 34};
39 35
@@ -74,16 +70,13 @@ static struct platform_device rtc_device = {
74#define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2)) 70#define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2))
75 71
76static struct sh_timer_config tmu0_platform_data = { 72static struct sh_timer_config tmu0_platform_data = {
77 .name = "TMU0",
78 .channel_offset = 0x04, 73 .channel_offset = 0x04,
79 .timer_bit = 0, 74 .timer_bit = 0,
80 .clk = "peripheral_clk",
81 .clockevent_rating = 200, 75 .clockevent_rating = 200,
82}; 76};
83 77
84static struct resource tmu0_resources[] = { 78static struct resource tmu0_resources[] = {
85 [0] = { 79 [0] = {
86 .name = "TMU0",
87 .start = TMU0_BASE, 80 .start = TMU0_BASE,
88 .end = TMU0_BASE + 0xc - 1, 81 .end = TMU0_BASE + 0xc - 1,
89 .flags = IORESOURCE_MEM, 82 .flags = IORESOURCE_MEM,
@@ -105,16 +98,13 @@ static struct platform_device tmu0_device = {
105}; 98};
106 99
107static struct sh_timer_config tmu1_platform_data = { 100static struct sh_timer_config tmu1_platform_data = {
108 .name = "TMU1",
109 .channel_offset = 0x10, 101 .channel_offset = 0x10,
110 .timer_bit = 1, 102 .timer_bit = 1,
111 .clk = "peripheral_clk",
112 .clocksource_rating = 200, 103 .clocksource_rating = 200,
113}; 104};
114 105
115static struct resource tmu1_resources[] = { 106static struct resource tmu1_resources[] = {
116 [0] = { 107 [0] = {
117 .name = "TMU1",
118 .start = TMU1_BASE, 108 .start = TMU1_BASE,
119 .end = TMU1_BASE + 0xc - 1, 109 .end = TMU1_BASE + 0xc - 1,
120 .flags = IORESOURCE_MEM, 110 .flags = IORESOURCE_MEM,
@@ -136,15 +126,12 @@ static struct platform_device tmu1_device = {
136}; 126};
137 127
138static struct sh_timer_config tmu2_platform_data = { 128static struct sh_timer_config tmu2_platform_data = {
139 .name = "TMU2",
140 .channel_offset = 0x1c, 129 .channel_offset = 0x1c,
141 .timer_bit = 2, 130 .timer_bit = 2,
142 .clk = "peripheral_clk",
143}; 131};
144 132
145static struct resource tmu2_resources[] = { 133static struct resource tmu2_resources[] = {
146 [0] = { 134 [0] = {
147 .name = "TMU2",
148 .start = TMU2_BASE, 135 .start = TMU2_BASE,
149 .end = TMU2_BASE + 0xc - 1, 136 .end = TMU2_BASE + 0xc - 1,
150 .flags = IORESOURCE_MEM, 137 .flags = IORESOURCE_MEM,
@@ -166,13 +153,13 @@ static struct platform_device tmu2_device = {
166}; 153};
167 154
168static struct platform_device *sh5_early_devices[] __initdata = { 155static struct platform_device *sh5_early_devices[] __initdata = {
156 &scif0_device,
169 &tmu0_device, 157 &tmu0_device,
170 &tmu1_device, 158 &tmu1_device,
171 &tmu2_device, 159 &tmu2_device,
172}; 160};
173 161
174static struct platform_device *sh5_devices[] __initdata = { 162static struct platform_device *sh5_devices[] __initdata = {
175 &sci_device,
176 &rtc_device, 163 &rtc_device,
177}; 164};
178 165
@@ -188,7 +175,7 @@ static int __init sh5_devices_setup(void)
188 return platform_add_devices(sh5_devices, 175 return platform_add_devices(sh5_devices,
189 ARRAY_SIZE(sh5_devices)); 176 ARRAY_SIZE(sh5_devices));
190} 177}
191__initcall(sh5_devices_setup); 178arch_initcall(sh5_devices_setup);
192 179
193void __init plat_early_device_setup(void) 180void __init plat_early_device_setup(void)
194{ 181{