sh: intc - mark data structures as __initdata

With the intc core improved it is now possible to put the intc data
structures in the initdata section.

Version two of this patch puts the __initdata inside DECLARE_INTC_DESC()
and removes the __initdata included in the board specific r2d code.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

4 files changed, 36 insertions, 37 deletions

diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index ae63635cf1ef..55f66104431d 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -84,7 +84,7 @@ enum {
         SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
 };
 
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
@@ -117,7 +117,7 @@ static struct intc_vect vectors[] = {
         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 };
 
-static struct intc_group groups[] = {
+static struct intc_group groups[] __initdata = {
         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
@@ -130,7 +130,7 @@ static struct intc_group groups[] = {
         INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
 };
 
-static struct intc_prio priorities[] = {
+static struct intc_prio priorities[] __initdata = {
         INTC_PRIO(SCIF0, 3),
         INTC_PRIO(SCIF1, 3),
         INTC_PRIO(SCIF2, 3),
@@ -138,7 +138,7 @@ static struct intc_prio priorities[] = {
         INTC_PRIO(TMU1, 2),
 };
 
-static struct intc_mask_reg mask_registers[] = {
+static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
           { } },
         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
@@ -168,7 +168,7 @@ static struct intc_mask_reg mask_registers[] = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static struct intc_prio_reg prio_registers[] = {
+static struct intc_prio_reg prio_registers[] __initdata = {
         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
@@ -185,7 +185,7 @@ static struct intc_prio_reg prio_registers[] = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static struct intc_sense_reg sense_registers[] = {
+static struct intc_sense_reg sense_registers[] __initdata = {
         { 0xa414001c, 16, 2, /* ICR1 */
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index c9965c0dde6d..d84c4575fc0a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -114,7 +114,7 @@ enum {
         PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
 };
 
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
         INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
         INTC_VECT(RTC_CUI, 0x4c0),
         INTC_VECT(WDT, 0x560),
@@ -150,7 +150,7 @@ static struct intc_vect vectors[] = {
         INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
 };
 
-static struct intc_group groups[] = {
+static struct intc_group groups[] __initdata = {
         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
         INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
@@ -167,12 +167,12 @@ static struct intc_group groups[] = {
         INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
 };
 
-static struct intc_prio priorities[] = {
+static struct intc_prio priorities[] __initdata = {
         INTC_PRIO(SCIF0, 3),
         INTC_PRIO(SCIF1, 3),
 };
 
-static struct intc_mask_reg mask_registers[] = {
+static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
           { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
             SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
@@ -180,7 +180,7 @@ static struct intc_mask_reg mask_registers[] = {
             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 };
 
-static struct intc_prio_reg prio_registers[] = {
+static struct intc_prio_reg prio_registers[] __initdata = {
         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
                                                  TMU2, TMU2_TICPI } },
         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
@@ -199,24 +199,24 @@ static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities,
 
 /* Support for external interrupt pins in IRQ mode */
 
-static struct intc_vect irq_vectors[] = {
+static struct intc_vect irq_vectors[] __initdata = {
         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 };
 
-static struct intc_mask_reg irq_mask_registers[] = {
+static struct intc_mask_reg irq_mask_registers[] __initdata = {
         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static struct intc_prio_reg irq_prio_registers[] = {
+static struct intc_prio_reg irq_prio_registers[] __initdata = {
         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static struct intc_sense_reg irq_sense_registers[] = {
+static struct intc_sense_reg irq_sense_registers[] __initdata = {
         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
@@ -227,7 +227,7 @@ static DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors,
 
 /* External interrupt pins in IRL mode */
 
-static struct intc_vect irl_vectors[] = {
+static struct intc_vect irl_vectors[] __initdata = {
         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
@@ -238,7 +238,7 @@ static struct intc_vect irl_vectors[] = {
         INTC_VECT(IRL_HHHL, 0x3c0),
 };
 
-static struct intc_mask_reg irl3210_mask_registers[] = {
+static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
         { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
@@ -246,7 +246,7 @@ static struct intc_mask_reg irl3210_mask_registers[] = {
             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 };
 
-static struct intc_mask_reg irl7654_mask_registers[] = {
+static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
         { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index a33d6a54c03d..a595203f74c6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -117,7 +117,7 @@ enum {
         PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
 };
 
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
         INTC_VECT(WDT, 0x560),
         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
@@ -158,7 +158,7 @@ static struct intc_vect vectors[] = {
         INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
 };
 
-static struct intc_group groups[] = {
+static struct intc_group groups[] __initdata = {
         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
         INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
                    DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
@@ -175,7 +175,7 @@ static struct intc_group groups[] = {
         INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
 };
 
-static struct intc_prio priorities[] = {
+static struct intc_prio priorities[] __initdata = {
         INTC_PRIO(SCIF0, 3),
         INTC_PRIO(SCIF1, 3),
         INTC_PRIO(SCIF2, 3),
@@ -184,7 +184,7 @@ static struct intc_prio priorities[] = {
         INTC_PRIO(SCIF5, 3),
 };
 
-static struct intc_mask_reg mask_registers[] = {
+static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 
@@ -205,7 +205,7 @@ static struct intc_mask_reg mask_registers[] = {
             SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
 };
 
-static struct intc_prio_reg prio_registers[] = {
+static struct intc_prio_reg prio_registers[] __initdata = {
         { 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
@@ -227,20 +227,19 @@ static struct intc_prio_reg prio_registers[] = {
 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, priorities,
                          mask_registers, prio_registers, NULL);
 
-
 /* Support for external interrupt pins in IRQ mode */
 
-static struct intc_vect vectors_irq0123[] = {
+static struct intc_vect vectors_irq0123[] __initdata = {
         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 };
 
-static struct intc_vect vectors_irq4567[] = {
+static struct intc_vect vectors_irq4567[] __initdata = {
         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 };
 
-static struct intc_sense_reg sense_registers[] = {
+static struct intc_sense_reg sense_registers[] __initdata = {
         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
@@ -255,7 +254,7 @@ static DECLARE_INTC_DESC(intc_desc_irq4567, "sh7785-irq4567", vectors_irq4567,
 
 /* External interrupt pins in IRL mode */
 
-static struct intc_vect vectors_irl0123[] = {
+static struct intc_vect vectors_irl0123[] __initdata = {
         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
@@ -266,7 +265,7 @@ static struct intc_vect vectors_irl0123[] = {
         INTC_VECT(IRL0_HHHL, 0x3c0),
 };
 
-static struct intc_vect vectors_irl4567[] = {
+static struct intc_vect vectors_irl4567[] __initdata = {
         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 3c8a2edff2c9..4cfd532086fa 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -97,7 +97,7 @@ enum {
         DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3,
 };
 
-static struct intc_vect vectors[] = {
+static struct intc_vect vectors[] __initdata = {
         INTC_VECT(HUDII, 0x3e0),
         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),
@@ -145,7 +145,7 @@ static struct intc_vect vectors[] = {
         INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
 };
 
-static struct intc_group groups[] = {
+static struct intc_group groups[] __initdata = {
         INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
                    IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
                    IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
@@ -165,14 +165,14 @@ static struct intc_group groups[] = {
         INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
 };
 
-static struct intc_prio priorities[] = {
+static struct intc_prio priorities[] __initdata = {
         INTC_PRIO(SCIF0, 3),
         INTC_PRIO(SCIF1, 3),
         INTC_PRIO(SCIF2, 3),
         INTC_PRIO(SCIF3, 3),
 };
 
-static struct intc_mask_reg mask_registers[] = {
+static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
           { IRQ0, IRQ1, IRQ2, IRQ3 } },
         { 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */
@@ -197,7 +197,7 @@ static struct intc_mask_reg mask_registers[] = {
             SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
 };
 
-static struct intc_prio_reg prio_registers[] = {
+static struct intc_prio_reg prio_registers[] __initdata = {
         { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
 
         { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
@@ -222,12 +222,12 @@ static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, priorities,
                          mask_registers, prio_registers, NULL);
 
 /* Support for external interrupt pins in IRQ mode */
-static struct intc_vect vectors_irq[] = {
+static struct intc_vect vectors_irq[] __initdata = {
         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 };
 
-static struct intc_sense_reg sense_registers[] = {
+static struct intc_sense_reg sense_registers[] __initdata = {
         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3 } },
 };
 
@@ -236,7 +236,7 @@ static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
                          sense_registers);
 
 /* External interrupt pins in IRL mode */
-static struct intc_vect vectors_irl[] = {
+static struct intc_vect vectors_irl[] __initdata = {
         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),