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authorPaul Mundt <lethal@linux-sh.org>2010-05-13 04:45:44 -0400
committerPaul Mundt <lethal@linux-sh.org>2010-05-13 04:45:44 -0400
commitc5eb5b372e7ea18a5eeb6b5192a6369967cb1afe (patch)
tree4e18e43ca25db9b8df6d332f9c2d3989288988a2 /arch/sh/kernel/cpu/sh4a
parent15f2a7967a46c7fab579ab88b9f1e0c7f78ac495 (diff)
parentf5ca6d4cbd49dbb6e179a71fa610eb321a3e9951 (diff)
Merge branch 'sh/clkfwk'
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a')
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7343.c213
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c192
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c47
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c47
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c38
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c11
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7763.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7780.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7785.c149
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c181
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-shx3.c13
11 files changed, 627 insertions, 288 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index a066c438b404..71291ae201b9 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -37,8 +37,6 @@
37 37
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
39static struct clk r_clk = { 39static struct clk r_clk = {
40 .name = "rclk",
41 .id = -1,
42 .rate = 32768, 40 .rate = 32768,
43}; 41};
44 42
@@ -47,8 +45,6 @@ static struct clk r_clk = {
47 * from the platform code. 45 * from the platform code.
48 */ 46 */
49struct clk extal_clk = { 47struct clk extal_clk = {
50 .name = "extal",
51 .id = -1,
52 .rate = 33333333, 48 .rate = 33333333,
53}; 49};
54 50
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
70}; 66};
71 67
72static struct clk dll_clk = { 68static struct clk dll_clk = {
73 .name = "dll_clk",
74 .id = -1,
75 .ops = &dll_clk_ops, 69 .ops = &dll_clk_ops,
76 .parent = &r_clk, 70 .parent = &r_clk,
77 .flags = CLK_ENABLE_ON_INIT, 71 .flags = CLK_ENABLE_ON_INIT,
@@ -92,8 +86,6 @@ static struct clk_ops pll_clk_ops = {
92}; 86};
93 87
94static struct clk pll_clk = { 88static struct clk pll_clk = {
95 .name = "pll_clk",
96 .id = -1,
97 .ops = &pll_clk_ops, 89 .ops = &pll_clk_ops,
98 .flags = CLK_ENABLE_ON_INIT, 90 .flags = CLK_ENABLE_ON_INIT,
99}; 91};
@@ -122,18 +114,18 @@ static struct clk_div4_table div4_table = {
122enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 114enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
123 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; 115 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
124 116
125#define DIV4(_str, _reg, _bit, _mask, _flags) \ 117#define DIV4(_reg, _bit, _mask, _flags) \
126 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
127 119
128struct clk div4_clks[DIV4_NR] = { 120struct clk div4_clks[DIV4_NR] = {
129 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), 121 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
130 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 122 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
131 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 123 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
132 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 124 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
133 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 125 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
134 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 126 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
135 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 127 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
136 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 128 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
137}; 129};
138 130
139enum { DIV6_V, DIV6_NR }; 131enum { DIV6_V, DIV6_NR };
@@ -142,61 +134,148 @@ struct clk div6_clks[DIV6_NR] = {
142 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 134 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
143}; 135};
144 136
145#define MSTP(_str, _parent, _reg, _bit, _flags) \ 137#define MSTP(_parent, _reg, _bit, _flags) \
146 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 138 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
147 139
148static struct clk mstp_clks[] = { 140enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
149 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 141 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
150 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 142 MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
151 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 143 MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001,
152 MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 144 MSTP109, MSTP108, MSTP100,
153 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 145 MSTP225, MSTP224, MSTP218, MSTP217, MSTP216,
154 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), 146 MSTP214, MSTP213, MSTP212, MSTP211, MSTP208,
155 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), 147 MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
156 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), 148 MSTP_NR };
157 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 149
158 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 150static struct clk mstp_clks[MSTP_NR] = {
159 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 151 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
160 MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 152 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
161 MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0), 153 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
162 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 154 [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
163 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 155 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
164 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 156 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
165 SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0), 157 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
166 SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0), 158 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
167 SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0), 159 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
168 SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 4, 0), 160 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
169 MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0), 161 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
170 MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 162 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
171 MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 163 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
172 164 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
173 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 165 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
174 MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0), 166 [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
175 167 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
176 MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0), 168 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
177 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0), 169 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
178 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 170 [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
179 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), 171 [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
180 MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0), 172 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
181 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0), 173 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
182 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0), 174
183 MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0), 175 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
184 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 176 [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
185 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0), 177
186 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), 178 [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
187 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 179 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
188 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 180 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
189 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 181 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
190 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 182 [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
191 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 183 [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
192 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), 184 [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
185 [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
186 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
187 [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
188 [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
189 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
190 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
191 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
192 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
193 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
194 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
193}; 195};
194 196
195#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 197#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
196 198
197static struct clk_lookup lookups[] = { 199static struct clk_lookup lookups[] = {
200 /* main clocks */
201 CLKDEV_CON_ID("rclk", &r_clk),
202 CLKDEV_CON_ID("extal", &extal_clk),
203 CLKDEV_CON_ID("dll_clk", &dll_clk),
204 CLKDEV_CON_ID("pll_clk", &pll_clk),
205
206 /* DIV4 clocks */
207 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
208 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
209 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
210 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
211 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
212 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
213 CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
214 CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
215
198 /* DIV6 clocks */ 216 /* DIV6 clocks */
199 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 217 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
218
219 /* MSTP32 clocks */
220 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
221 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
222 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
223 CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
224 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
225 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
226 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
227 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
228 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
229 CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
230 CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
231 CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
232 CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
233 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
234 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
235 CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
236 {
237 /* SCIF0 */
238 .dev_id = "sh-sci.0",
239 .con_id = "sci_fck",
240 .clk = &mstp_clks[MSTP007],
241 }, {
242 /* SCIF1 */
243 .dev_id = "sh-sci.1",
244 .con_id = "sci_fck",
245 .clk = &mstp_clks[MSTP006],
246 }, {
247 /* SCIF2 */
248 .dev_id = "sh-sci.2",
249 .con_id = "sci_fck",
250 .clk = &mstp_clks[MSTP005],
251 }, {
252 /* SCIF3 */
253 .dev_id = "sh-sci.3",
254 .con_id = "sci_fck",
255 .clk = &mstp_clks[MSTP004],
256 },
257 CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]),
258 CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]),
259 CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]),
260 CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
261 CLKDEV_CON_ID("i2c1", &mstp_clks[MSTP108]),
262 CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]),
263 CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]),
264 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
265 CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
266 CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]),
267 CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]),
268 CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]),
269 CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]),
270 CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
271 CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]),
272 CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]),
273 CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
274 CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
275 CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
276 CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
277 CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
278 CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
200}; 279};
201 280
202int __init arch_clk_init(void) 281int __init arch_clk_init(void)
@@ -221,7 +300,7 @@ int __init arch_clk_init(void)
221 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 300 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
222 301
223 if (!ret) 302 if (!ret)
224 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 303 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
225 304
226 return ret; 305 return ret;
227} 306}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index 44cc5a0965d9..7ce5bbcd4084 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -37,8 +37,6 @@
37 37
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
39static struct clk r_clk = { 39static struct clk r_clk = {
40 .name = "rclk",
41 .id = -1,
42 .rate = 32768, 40 .rate = 32768,
43}; 41};
44 42
@@ -47,8 +45,6 @@ static struct clk r_clk = {
47 * from the platform code. 45 * from the platform code.
48 */ 46 */
49struct clk extal_clk = { 47struct clk extal_clk = {
50 .name = "extal",
51 .id = -1,
52 .rate = 33333333, 48 .rate = 33333333,
53}; 49};
54 50
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
70}; 66};
71 67
72static struct clk dll_clk = { 68static struct clk dll_clk = {
73 .name = "dll_clk",
74 .id = -1,
75 .ops = &dll_clk_ops, 69 .ops = &dll_clk_ops,
76 .parent = &r_clk, 70 .parent = &r_clk,
77 .flags = CLK_ENABLE_ON_INIT, 71 .flags = CLK_ENABLE_ON_INIT,
@@ -95,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
95}; 89};
96 90
97static struct clk pll_clk = { 91static struct clk pll_clk = {
98 .name = "pll_clk",
99 .id = -1,
100 .ops = &pll_clk_ops, 92 .ops = &pll_clk_ops,
101 .flags = CLK_ENABLE_ON_INIT, 93 .flags = CLK_ENABLE_ON_INIT,
102}; 94};
@@ -125,18 +117,18 @@ static struct clk_div4_table div4_table = {
125enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 117enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
126 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; 118 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
127 119
128#define DIV4(_str, _reg, _bit, _mask, _flags) \ 120#define DIV4(_reg, _bit, _mask, _flags) \
129 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
130 122
131struct clk div4_clks[DIV4_NR] = { 123struct clk div4_clks[DIV4_NR] = {
132 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), 124 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
133 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 125 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
134 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 126 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
135 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 127 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
136 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 128 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
137 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 129 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
138 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 130 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
139 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 131 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
140}; 132};
141 133
142enum { DIV6_V, DIV6_NR }; 134enum { DIV6_V, DIV6_NR };
@@ -145,58 +137,134 @@ struct clk div6_clks[DIV6_NR] = {
145 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 137 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
146}; 138};
147 139
148#define MSTP(_str, _parent, _reg, _bit, _flags) \ 140#define MSTP(_parent, _reg, _bit, _flags) \
149 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 141 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
150 142
151static struct clk mstp_clks[] = { 143enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
144 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
145 MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
146 MSTP007, MSTP006, MSTP005, MSTP002, MSTP001,
147 MSTP109, MSTP100,
148 MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217,
149 MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
150 MSTP_NR };
151
152static struct clk mstp_clks[MSTP_NR] = {
152 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ 153 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
153 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 154 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
154 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 155 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
155 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 156 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
156 MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 157 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
157 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 158 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
158 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), 159 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
159 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), 160 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
160 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), 161 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
161 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 162 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
162 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 163 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
163 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 164 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
164 MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 165 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
165 MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0), 166 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
166 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 167 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
167 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 168 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
168 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 169 [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
169 SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 7, 0), 170 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
170 SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 6, 0), 171 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
171 SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 5, 0), 172 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
172 MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 173 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
173 MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 174 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
174 175
175 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 176 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
176 177
177 MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0), 178 [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
178 MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0), 179 [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
179 MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0), 180 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
180 MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0), 181 [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
181 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0), 182 [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
182 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 183 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
183 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), 184 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
184 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 185 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
185 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0), 186 [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
186 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), 187 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
187 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 188 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
188 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 189 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
189 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 190 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
190 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 191 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
191 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 192 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
192 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
193}; 193};
194 194
195#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 195#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
196 196
197static struct clk_lookup lookups[] = { 197static struct clk_lookup lookups[] = {
198 /* main clocks */
199 CLKDEV_CON_ID("rclk", &r_clk),
200 CLKDEV_CON_ID("extal", &extal_clk),
201 CLKDEV_CON_ID("dll_clk", &dll_clk),
202 CLKDEV_CON_ID("pll_clk", &pll_clk),
203
204 /* DIV4 clocks */
205 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
206 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
207 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
208 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
209 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
210 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
211 CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
212 CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
213
198 /* DIV6 clocks */ 214 /* DIV6 clocks */
199 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 215 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
216
217 /* MSTP32 clocks */
218 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
219 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
220 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
221 CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
222 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
223 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
224 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
225 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
226 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
227 CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
228 CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
229 CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
230 CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
231 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
232 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
233 CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
234 {
235 /* SCIF0 */
236 .dev_id = "sh-sci.0",
237 .con_id = "sci_fck",
238 .clk = &mstp_clks[MSTP007],
239 }, {
240 /* SCIF1 */
241 .dev_id = "sh-sci.1",
242 .con_id = "sci_fck",
243 .clk = &mstp_clks[MSTP006],
244 }, {
245 /* SCIF2 */
246 .dev_id = "sh-sci.2",
247 .con_id = "sci_fck",
248 .clk = &mstp_clks[MSTP005],
249 },
250 CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]),
251 CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]),
252 CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
253 CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]),
254 CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]),
255 CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]),
256 CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]),
257 CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]),
258 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
259 CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
260 CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
261 CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]),
262 CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
263 CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
264 CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
265 CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
266 CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
267 CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
200}; 268};
201 269
202int __init arch_clk_init(void) 270int __init arch_clk_init(void)
@@ -221,7 +289,7 @@ int __init arch_clk_init(void)
221 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 289 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
222 290
223 if (!ret) 291 if (!ret)
224 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 292 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
225 293
226 return ret; 294 return ret;
227} 295}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 2798ceaa648f..2030f3d9fac7 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -37,8 +37,6 @@
37 37
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
39static struct clk r_clk = { 39static struct clk r_clk = {
40 .name = "rclk",
41 .id = -1,
42 .rate = 32768, 40 .rate = 32768,
43}; 41};
44 42
@@ -47,8 +45,6 @@ static struct clk r_clk = {
47 * from the platform code. 45 * from the platform code.
48 */ 46 */
49struct clk extal_clk = { 47struct clk extal_clk = {
50 .name = "extal",
51 .id = -1,
52 .rate = 33333333, 48 .rate = 33333333,
53}; 49};
54 50
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
70}; 66};
71 67
72static struct clk dll_clk = { 68static struct clk dll_clk = {
73 .name = "dll_clk",
74 .id = -1,
75 .ops = &dll_clk_ops, 69 .ops = &dll_clk_ops,
76 .parent = &r_clk, 70 .parent = &r_clk,
77 .flags = CLK_ENABLE_ON_INIT, 71 .flags = CLK_ENABLE_ON_INIT,
@@ -95,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
95}; 89};
96 90
97static struct clk pll_clk = { 91static struct clk pll_clk = {
98 .name = "pll_clk",
99 .id = -1,
100 .ops = &pll_clk_ops, 92 .ops = &pll_clk_ops,
101 .flags = CLK_ENABLE_ON_INIT, 93 .flags = CLK_ENABLE_ON_INIT,
102}; 94};
@@ -122,31 +114,31 @@ static struct clk_div4_table div4_table = {
122 .div_mult_table = &div4_div_mult_table, 114 .div_mult_table = &div4_div_mult_table,
123}; 115};
124 116
125#define DIV4(_str, _reg, _bit, _mask, _flags) \ 117#define DIV4(_reg, _bit, _mask, _flags) \
126 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
127 119
128enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; 120enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
129 121
130struct clk div4_clks[DIV4_NR] = { 122struct clk div4_clks[DIV4_NR] = {
131 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), 123 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
132 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 124 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
133 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 125 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
134 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 126 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
135 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 127 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
136 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 128 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
137}; 129};
138 130
139enum { DIV4_IRDA, DIV4_ENABLE_NR }; 131enum { DIV4_IRDA, DIV4_ENABLE_NR };
140 132
141struct clk div4_enable_clks[DIV4_ENABLE_NR] = { 133struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
142 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0), 134 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
143}; 135};
144 136
145enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; 137enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
146 138
147struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { 139struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
148 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 140 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
149 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 141 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
150}; 142};
151 143
152enum { DIV6_V, DIV6_NR }; 144enum { DIV6_V, DIV6_NR };
@@ -186,6 +178,23 @@ static struct clk mstp_clks[HWBLK_NR] = {
186#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 178#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
187 179
188static struct clk_lookup lookups[] = { 180static struct clk_lookup lookups[] = {
181 /* main clocks */
182 CLKDEV_CON_ID("rclk", &r_clk),
183 CLKDEV_CON_ID("extal", &extal_clk),
184 CLKDEV_CON_ID("dll_clk", &dll_clk),
185 CLKDEV_CON_ID("pll_clk", &pll_clk),
186
187 /* DIV4 clocks */
188 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
189 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
190 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
191 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
192 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
193 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
194 CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
195 CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
196 CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
197
189 /* DIV6 clocks */ 198 /* DIV6 clocks */
190 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 199 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
191 200
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 500715f78142..d3938f0d3702 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -38,8 +38,6 @@
38 38
39/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 39/* Fixed 32 KHz root clock for RTC and Power Management purposes */
40static struct clk r_clk = { 40static struct clk r_clk = {
41 .name = "rclk",
42 .id = -1,
43 .rate = 32768, 41 .rate = 32768,
44}; 42};
45 43
@@ -48,8 +46,6 @@ static struct clk r_clk = {
48 * from the platform code. 46 * from the platform code.
49 */ 47 */
50struct clk extal_clk = { 48struct clk extal_clk = {
51 .name = "extal",
52 .id = -1,
53 .rate = 33333333, 49 .rate = 33333333,
54}; 50};
55 51
@@ -71,8 +67,6 @@ static struct clk_ops dll_clk_ops = {
71}; 67};
72 68
73static struct clk dll_clk = { 69static struct clk dll_clk = {
74 .name = "dll_clk",
75 .id = -1,
76 .ops = &dll_clk_ops, 70 .ops = &dll_clk_ops,
77 .parent = &r_clk, 71 .parent = &r_clk,
78 .flags = CLK_ENABLE_ON_INIT, 72 .flags = CLK_ENABLE_ON_INIT,
@@ -96,8 +90,6 @@ static struct clk_ops pll_clk_ops = {
96}; 90};
97 91
98static struct clk pll_clk = { 92static struct clk pll_clk = {
99 .name = "pll_clk",
100 .id = -1,
101 .ops = &pll_clk_ops, 93 .ops = &pll_clk_ops,
102 .flags = CLK_ENABLE_ON_INIT, 94 .flags = CLK_ENABLE_ON_INIT,
103}; 95};
@@ -125,29 +117,29 @@ static struct clk_div4_table div4_table = {
125 117
126enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; 118enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
127 119
128#define DIV4(_str, _reg, _bit, _mask, _flags) \ 120#define DIV4(_reg, _bit, _mask, _flags) \
129 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
130 122
131struct clk div4_clks[DIV4_NR] = { 123struct clk div4_clks[DIV4_NR] = {
132 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), 124 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
133 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), 125 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
134 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), 126 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
135 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), 127 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
136 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), 128 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
137 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0), 129 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
138}; 130};
139 131
140enum { DIV4_IRDA, DIV4_ENABLE_NR }; 132enum { DIV4_IRDA, DIV4_ENABLE_NR };
141 133
142struct clk div4_enable_clks[DIV4_ENABLE_NR] = { 134struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
143 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0), 135 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
144}; 136};
145 137
146enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; 138enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
147 139
148struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { 140struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
149 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0), 141 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
150 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0), 142 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
151}; 143};
152enum { DIV6_V, DIV6_NR }; 144enum { DIV6_V, DIV6_NR };
153 145
@@ -211,6 +203,23 @@ static struct clk mstp_clks[] = {
211#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 203#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
212 204
213static struct clk_lookup lookups[] = { 205static struct clk_lookup lookups[] = {
206 /* main clocks */
207 CLKDEV_CON_ID("rclk", &r_clk),
208 CLKDEV_CON_ID("extal", &extal_clk),
209 CLKDEV_CON_ID("dll_clk", &dll_clk),
210 CLKDEV_CON_ID("pll_clk", &pll_clk),
211
212 /* DIV4 clocks */
213 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
214 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
215 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
216 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
217 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
218 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
219 CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
220 CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
221 CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
222
214 /* DIV6 clocks */ 223 /* DIV6 clocks */
215 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 224 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
216 225
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 2bbff53fcd87..2d9700c6b53a 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -41,8 +41,6 @@
41 41
42/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 42/* Fixed 32 KHz root clock for RTC and Power Management purposes */
43static struct clk r_clk = { 43static struct clk r_clk = {
44 .name = "rclk",
45 .id = -1,
46 .rate = 32768, 44 .rate = 32768,
47}; 45};
48 46
@@ -51,8 +49,6 @@ static struct clk r_clk = {
51 * from the platform code. 49 * from the platform code.
52 */ 50 */
53struct clk extal_clk = { 51struct clk extal_clk = {
54 .name = "extal",
55 .id = -1,
56 .rate = 33333333, 52 .rate = 33333333,
57}; 53};
58 54
@@ -76,8 +72,6 @@ static struct clk_ops fll_clk_ops = {
76}; 72};
77 73
78static struct clk fll_clk = { 74static struct clk fll_clk = {
79 .name = "fll_clk",
80 .id = -1,
81 .ops = &fll_clk_ops, 75 .ops = &fll_clk_ops,
82 .parent = &r_clk, 76 .parent = &r_clk,
83 .flags = CLK_ENABLE_ON_INIT, 77 .flags = CLK_ENABLE_ON_INIT,
@@ -98,8 +92,6 @@ static struct clk_ops pll_clk_ops = {
98}; 92};
99 93
100static struct clk pll_clk = { 94static struct clk pll_clk = {
101 .name = "pll_clk",
102 .id = -1,
103 .ops = &pll_clk_ops, 95 .ops = &pll_clk_ops,
104 .flags = CLK_ENABLE_ON_INIT, 96 .flags = CLK_ENABLE_ON_INIT,
105}; 97};
@@ -115,8 +107,6 @@ static struct clk_ops div3_clk_ops = {
115}; 107};
116 108
117static struct clk div3_clk = { 109static struct clk div3_clk = {
118 .name = "div3_clk",
119 .id = -1,
120 .ops = &div3_clk_ops, 110 .ops = &div3_clk_ops,
121 .parent = &pll_clk, 111 .parent = &pll_clk,
122}; 112};
@@ -153,15 +143,15 @@ static struct clk_div4_table div4_table = {
153 143
154enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; 144enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
155 145
156#define DIV4(_str, _reg, _bit, _mask, _flags) \ 146#define DIV4(_reg, _bit, _mask, _flags) \
157 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 147 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
158 148
159struct clk div4_clks[DIV4_NR] = { 149struct clk div4_clks[DIV4_NR] = {
160 [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), 150 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
161 [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), 151 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
162 [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), 152 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
163 [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0), 153 [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
164 [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), 154 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
165}; 155};
166 156
167enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR }; 157enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
@@ -234,6 +224,20 @@ static struct clk mstp_clks[HWBLK_NR] = {
234#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 224#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
235 225
236static struct clk_lookup lookups[] = { 226static struct clk_lookup lookups[] = {
227 /* main clocks */
228 CLKDEV_CON_ID("rclk", &r_clk),
229 CLKDEV_CON_ID("extal", &extal_clk),
230 CLKDEV_CON_ID("fll_clk", &fll_clk),
231 CLKDEV_CON_ID("pll_clk", &pll_clk),
232 CLKDEV_CON_ID("div3_clk", &div3_clk),
233
234 /* DIV4 clocks */
235 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
236 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
237 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
238 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
239 CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
240
237 /* DIV6 clocks */ 241 /* DIV6 clocks */
238 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 242 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
239 CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]), 243 CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index 86aae60677dc..0a752bd324ac 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/clkdev.h>
15#include <asm/clock.h> 16#include <asm/clock.h>
16#include <asm/freq.h> 17#include <asm/freq.h>
17 18
@@ -87,7 +88,6 @@ static struct clk_ops sh7757_shyway_clk_ops = {
87}; 88};
88 89
89static struct clk sh7757_shyway_clk = { 90static struct clk sh7757_shyway_clk = {
90 .name = "shyway_clk",
91 .flags = CLK_ENABLE_ON_INIT, 91 .flags = CLK_ENABLE_ON_INIT,
92 .ops = &sh7757_shyway_clk_ops, 92 .ops = &sh7757_shyway_clk_ops,
93}; 93};
@@ -100,6 +100,13 @@ static struct clk *sh7757_onchip_clocks[] = {
100 &sh7757_shyway_clk, 100 &sh7757_shyway_clk,
101}; 101};
102 102
103#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
104
105static struct clk_lookup lookups[] = {
106 /* main clocks */
107 CLKDEV_CON_ID("shyway_clk", &sh7757_shyway_clk),
108};
109
103static int __init sh7757_clk_init(void) 110static int __init sh7757_clk_init(void)
104{ 111{
105 struct clk *clk = clk_get(NULL, "master_clk"); 112 struct clk *clk = clk_get(NULL, "master_clk");
@@ -123,6 +130,8 @@ static int __init sh7757_clk_init(void)
123 130
124 clk_put(clk); 131 clk_put(clk);
125 132
133 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
134
126 return 0; 135 return 0;
127} 136}
128 137
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 9f401163e71e..1f1df48008cd 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -12,6 +12,8 @@
12 */ 12 */
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <asm/clkdev.h>
15#include <asm/clock.h> 17#include <asm/clock.h>
16#include <asm/freq.h> 18#include <asm/freq.h>
17#include <asm/io.h> 19#include <asm/io.h>
@@ -77,7 +79,6 @@ static struct clk_ops sh7763_shyway_clk_ops = {
77}; 79};
78 80
79static struct clk sh7763_shyway_clk = { 81static struct clk sh7763_shyway_clk = {
80 .name = "shyway_clk",
81 .flags = CLK_ENABLE_ON_INIT, 82 .flags = CLK_ENABLE_ON_INIT,
82 .ops = &sh7763_shyway_clk_ops, 83 .ops = &sh7763_shyway_clk_ops,
83}; 84};
@@ -90,6 +91,13 @@ static struct clk *sh7763_onchip_clocks[] = {
90 &sh7763_shyway_clk, 91 &sh7763_shyway_clk,
91}; 92};
92 93
94#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
95
96static struct clk_lookup lookups[] = {
97 /* main clocks */
98 CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk),
99};
100
93int __init arch_clk_init(void) 101int __init arch_clk_init(void)
94{ 102{
95 struct clk *clk; 103 struct clk *clk;
@@ -107,5 +115,7 @@ int __init arch_clk_init(void)
107 115
108 clk_put(clk); 116 clk_put(clk);
109 117
118 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
119
110 return ret; 120 return ret;
111} 121}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index 150963a6001e..62d706350060 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -11,6 +11,8 @@
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <asm/clkdev.h>
14#include <asm/clock.h> 16#include <asm/clock.h>
15#include <asm/freq.h> 17#include <asm/freq.h>
16#include <asm/io.h> 18#include <asm/io.h>
@@ -83,7 +85,6 @@ static struct clk_ops sh7780_shyway_clk_ops = {
83}; 85};
84 86
85static struct clk sh7780_shyway_clk = { 87static struct clk sh7780_shyway_clk = {
86 .name = "shyway_clk",
87 .flags = CLK_ENABLE_ON_INIT, 88 .flags = CLK_ENABLE_ON_INIT,
88 .ops = &sh7780_shyway_clk_ops, 89 .ops = &sh7780_shyway_clk_ops,
89}; 90};
@@ -96,6 +97,13 @@ static struct clk *sh7780_onchip_clocks[] = {
96 &sh7780_shyway_clk, 97 &sh7780_shyway_clk,
97}; 98};
98 99
100#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
101
102static struct clk_lookup lookups[] = {
103 /* main clocks */
104 CLKDEV_CON_ID("shyway_clk", &sh7780_shyway_clk),
105};
106
99int __init arch_clk_init(void) 107int __init arch_clk_init(void)
100{ 108{
101 struct clk *clk; 109 struct clk *clk;
@@ -113,5 +121,7 @@ int __init arch_clk_init(void)
113 121
114 clk_put(clk); 122 clk_put(clk);
115 123
124 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
125
116 return ret; 126 return ret;
117} 127}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 28de049a59b1..c3e458aaa2b7 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -24,8 +24,6 @@
24 * from the platform code. 24 * from the platform code.
25 */ 25 */
26static struct clk extal_clk = { 26static struct clk extal_clk = {
27 .name = "extal",
28 .id = -1,
29 .rate = 33333333, 27 .rate = 33333333,
30}; 28};
31 29
@@ -43,8 +41,6 @@ static struct clk_ops pll_clk_ops = {
43}; 41};
44 42
45static struct clk pll_clk = { 43static struct clk pll_clk = {
46 .name = "pll_clk",
47 .id = -1,
48 .ops = &pll_clk_ops, 44 .ops = &pll_clk_ops,
49 .parent = &extal_clk, 45 .parent = &extal_clk,
50 .flags = CLK_ENABLE_ON_INIT, 46 .flags = CLK_ENABLE_ON_INIT,
@@ -70,82 +66,149 @@ static struct clk_div4_table div4_table = {
70enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, 66enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
71 DIV4_DU, DIV4_P, DIV4_NR }; 67 DIV4_DU, DIV4_P, DIV4_NR };
72 68
73#define DIV4(_str, _bit, _mask, _flags) \ 69#define DIV4(_bit, _mask, _flags) \
74 SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) 70 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
75 71
76struct clk div4_clks[DIV4_NR] = { 72struct clk div4_clks[DIV4_NR] = {
77 [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0), 73 [DIV4_P] = DIV4(0, 0x0f80, 0),
78 [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0), 74 [DIV4_DU] = DIV4(4, 0x0ff0, 0),
79 [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0), 75 [DIV4_GA] = DIV4(8, 0x0030, 0),
80 [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT), 76 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
81 [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT), 77 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
82 [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT), 78 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
83 [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT), 79 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
84 [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT), 80 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
85}; 81};
86 82
87#define MSTPCR0 0xffc80030 83#define MSTPCR0 0xffc80030
88#define MSTPCR1 0xffc80034 84#define MSTPCR1 0xffc80034
89 85
90static struct clk mstp_clks[] = { 86enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
87 MSTP021, MSTP020, MSTP017, MSTP016,
88 MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002,
89 MSTP119, MSTP117, MSTP105, MSTP104, MSTP100,
90 MSTP_NR };
91
92static struct clk mstp_clks[MSTP_NR] = {
91 /* MSTPCR0 */ 93 /* MSTPCR0 */
92 SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), 94 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
93 SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), 95 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
94 SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), 96 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
95 SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), 97 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
96 SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), 98 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
97 SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), 99 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
98 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), 100 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
99 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), 101 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
100 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), 102 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
101 SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), 103 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
102 SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0), 104 [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
103 SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0), 105 [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
104 SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), 106 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
105 SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), 107 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
106 SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0), 108 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
107 SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), 109 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
108 110
109 /* MSTPCR1 */ 111 /* MSTPCR1 */
110 SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0), 112 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
111 SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0), 113 [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
112 SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), 114 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
113 SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), 115 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
114 SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0), 116 [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
115}; 117};
116 118
119#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
120
117static struct clk_lookup lookups[] = { 121static struct clk_lookup lookups[] = {
122 /* main clocks */
123 CLKDEV_CON_ID("extal", &extal_clk),
124 CLKDEV_CON_ID("pll_clk", &pll_clk),
125
126 /* DIV4 clocks */
127 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
128 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
129 CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]),
130 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
131 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
132 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
133 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
134 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
135
136 /* MSTP32 clocks */
137 {
138 /* SCIF5 */
139 .dev_id = "sh-sci.5",
140 .con_id = "sci_fck",
141 .clk = &mstp_clks[MSTP029],
142 }, {
143 /* SCIF4 */
144 .dev_id = "sh-sci.4",
145 .con_id = "sci_fck",
146 .clk = &mstp_clks[MSTP028],
147 }, {
148 /* SCIF3 */
149 .dev_id = "sh-sci.3",
150 .con_id = "sci_fck",
151 .clk = &mstp_clks[MSTP027],
152 }, {
153 /* SCIF2 */
154 .dev_id = "sh-sci.2",
155 .con_id = "sci_fck",
156 .clk = &mstp_clks[MSTP026],
157 }, {
158 /* SCIF1 */
159 .dev_id = "sh-sci.1",
160 .con_id = "sci_fck",
161 .clk = &mstp_clks[MSTP025],
162 }, {
163 /* SCIF0 */
164 .dev_id = "sh-sci.0",
165 .con_id = "sci_fck",
166 .clk = &mstp_clks[MSTP024],
167 },
168 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
169 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
170 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
171 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
172 CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]),
173 CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]),
118 { 174 {
119 /* TMU0 */ 175 /* TMU0 */
120 .dev_id = "sh_tmu.0", 176 .dev_id = "sh_tmu.0",
121 .con_id = "tmu_fck", 177 .con_id = "tmu_fck",
122 .clk = &mstp_clks[13], /* tmu012_fck */ 178 .clk = &mstp_clks[MSTP008],
123 }, { 179 }, {
124 /* TMU1 */ 180 /* TMU1 */
125 .dev_id = "sh_tmu.1", 181 .dev_id = "sh_tmu.1",
126 .con_id = "tmu_fck", 182 .con_id = "tmu_fck",
127 .clk = &mstp_clks[13], 183 .clk = &mstp_clks[MSTP008],
128 }, { 184 }, {
129 /* TMU2 */ 185 /* TMU2 */
130 .dev_id = "sh_tmu.2", 186 .dev_id = "sh_tmu.2",
131 .con_id = "tmu_fck", 187 .con_id = "tmu_fck",
132 .clk = &mstp_clks[13], 188 .clk = &mstp_clks[MSTP008],
133 }, { 189 }, {
134 /* TMU3 */ 190 /* TMU3 */
135 .dev_id = "sh_tmu.3", 191 .dev_id = "sh_tmu.3",
136 .con_id = "tmu_fck", 192 .con_id = "tmu_fck",
137 .clk = &mstp_clks[12], /* tmu345_fck */ 193 .clk = &mstp_clks[MSTP009],
138 }, { 194 }, {
139 /* TMU4 */ 195 /* TMU4 */
140 .dev_id = "sh_tmu.4", 196 .dev_id = "sh_tmu.4",
141 .con_id = "tmu_fck", 197 .con_id = "tmu_fck",
142 .clk = &mstp_clks[12], 198 .clk = &mstp_clks[MSTP009],
143 }, { 199 }, {
144 /* TMU5 */ 200 /* TMU5 */
145 .dev_id = "sh_tmu.5", 201 .dev_id = "sh_tmu.5",
146 .con_id = "tmu_fck", 202 .con_id = "tmu_fck",
147 .clk = &mstp_clks[12], 203 .clk = &mstp_clks[MSTP009],
148 }, 204 },
205 CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]),
206 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
207 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
208 CLKDEV_CON_ID("ubc_fck", &mstp_clks[MSTP117]),
209 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
210 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
211 CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]),
149}; 212};
150 213
151int __init arch_clk_init(void) 214int __init arch_clk_init(void)
@@ -161,7 +224,7 @@ int __init arch_clk_init(void)
161 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), 224 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
162 &div4_table); 225 &div4_table);
163 if (!ret) 226 if (!ret)
164 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 227 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
165 228
166 return ret; 229 return ret;
167} 230}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index c4a84bb2f3d9..105a6d41b569 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -23,8 +23,6 @@
23 * from the platform code. 23 * from the platform code.
24 */ 24 */
25static struct clk extal_clk = { 25static struct clk extal_clk = {
26 .name = "extal",
27 .id = -1,
28 .rate = 33333333, 26 .rate = 33333333,
29}; 27};
30 28
@@ -46,8 +44,6 @@ static struct clk_ops pll_clk_ops = {
46}; 44};
47 45
48static struct clk pll_clk = { 46static struct clk pll_clk = {
49 .name = "pll_clk",
50 .id = -1,
51 .ops = &pll_clk_ops, 47 .ops = &pll_clk_ops,
52 .parent = &extal_clk, 48 .parent = &extal_clk,
53 .flags = CLK_ENABLE_ON_INIT, 49 .flags = CLK_ENABLE_ON_INIT,
@@ -72,118 +68,191 @@ static struct clk_div4_table div4_table = {
72 68
73enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; 69enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
74 70
75#define DIV4(_str, _bit, _mask, _flags) \ 71#define DIV4(_bit, _mask, _flags) \
76 SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) 72 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
77 73
78struct clk div4_clks[DIV4_NR] = { 74struct clk div4_clks[DIV4_NR] = {
79 [DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0), 75 [DIV4_P] = DIV4(0, 0x0b40, 0),
80 [DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0), 76 [DIV4_DU] = DIV4(4, 0x0010, 0),
81 [DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT), 77 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
82 [DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT), 78 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
83 [DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT), 79 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
84 [DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT), 80 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
85}; 81};
86 82
87#define MSTPCR0 0xffc40030 83#define MSTPCR0 0xffc40030
88#define MSTPCR1 0xffc40034 84#define MSTPCR1 0xffc40034
89 85
90static struct clk mstp_clks[] = { 86enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
87 MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
88 MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
89 MSTP005, MSTP004, MSTP002,
90 MSTP112, MSTP110, MSTP109, MSTP108,
91 MSTP105, MSTP104, MSTP103, MSTP102,
92 MSTP_NR };
93
94static struct clk mstp_clks[MSTP_NR] = {
91 /* MSTPCR0 */ 95 /* MSTPCR0 */
92 SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), 96 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
93 SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), 97 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
94 SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), 98 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
95 SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), 99 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
96 SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), 100 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
97 SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), 101 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
98 SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0), 102 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
99 SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0), 103 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
100 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), 104 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
101 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), 105 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
102 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), 106 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
103 SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), 107 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
104 SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0), 108 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
105 SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0), 109 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
106 SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0), 110 [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
107 SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0), 111 [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
108 SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), 112 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
109 SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), 113 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
110 SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0), 114 [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
111 SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0), 115 [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
112 SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), 116 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
113 117
114 /* MSTPCR1 */ 118 /* MSTPCR1 */
115 SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0), 119 [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
116 SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0), 120 [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
117 SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0), 121 [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
118 SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0), 122 [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
119 SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), 123 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
120 SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), 124 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
121 SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0), 125 [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
122 SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0), 126 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
123}; 127};
124 128
129#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
130
125static struct clk_lookup lookups[] = { 131static struct clk_lookup lookups[] = {
132 /* main clocks */
133 CLKDEV_CON_ID("extal", &extal_clk),
134 CLKDEV_CON_ID("pll_clk", &pll_clk),
135
136 /* DIV4 clocks */
137 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
138 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
139 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
140 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
141 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
142 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
143
144 /* MSTP32 clocks */
145 {
146 /* SCIF5 */
147 .dev_id = "sh-sci.5",
148 .con_id = "sci_fck",
149 .clk = &mstp_clks[MSTP029],
150 }, {
151 /* SCIF4 */
152 .dev_id = "sh-sci.4",
153 .con_id = "sci_fck",
154 .clk = &mstp_clks[MSTP028],
155 }, {
156 /* SCIF3 */
157 .dev_id = "sh-sci.3",
158 .con_id = "sci_fck",
159 .clk = &mstp_clks[MSTP027],
160 }, {
161 /* SCIF2 */
162 .dev_id = "sh-sci.2",
163 .con_id = "sci_fck",
164 .clk = &mstp_clks[MSTP026],
165 }, {
166 /* SCIF1 */
167 .dev_id = "sh-sci.1",
168 .con_id = "sci_fck",
169 .clk = &mstp_clks[MSTP025],
170 }, {
171 /* SCIF0 */
172 .dev_id = "sh-sci.0",
173 .con_id = "sci_fck",
174 .clk = &mstp_clks[MSTP024],
175 },
176 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
177 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
178 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
179 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
180 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
181 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
182 CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
183 CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
126 { 184 {
127 /* TMU0 */ 185 /* TMU0 */
128 .dev_id = "sh_tmu.0", 186 .dev_id = "sh_tmu.0",
129 .con_id = "tmu_fck", 187 .con_id = "tmu_fck",
130 .clk = &mstp_clks[17], /* tmu012_fck */ 188 .clk = &mstp_clks[MSTP008],
131 }, { 189 }, {
132 /* TMU1 */ 190 /* TMU1 */
133 .dev_id = "sh_tmu.1", 191 .dev_id = "sh_tmu.1",
134 .con_id = "tmu_fck", 192 .con_id = "tmu_fck",
135 .clk = &mstp_clks[17], 193 .clk = &mstp_clks[MSTP008],
136 }, { 194 }, {
137 /* TMU2 */ 195 /* TMU2 */
138 .dev_id = "sh_tmu.2", 196 .dev_id = "sh_tmu.2",
139 .con_id = "tmu_fck", 197 .con_id = "tmu_fck",
140 .clk = &mstp_clks[17], 198 .clk = &mstp_clks[MSTP008],
141 }, { 199 }, {
142 /* TMU3 */ 200 /* TMU3 */
143 .dev_id = "sh_tmu.3", 201 .dev_id = "sh_tmu.3",
144 .con_id = "tmu_fck", 202 .con_id = "tmu_fck",
145 .clk = &mstp_clks[16], /* tmu345_fck */ 203 .clk = &mstp_clks[MSTP009],
146 }, { 204 }, {
147 /* TMU4 */ 205 /* TMU4 */
148 .dev_id = "sh_tmu.4", 206 .dev_id = "sh_tmu.4",
149 .con_id = "tmu_fck", 207 .con_id = "tmu_fck",
150 .clk = &mstp_clks[16], 208 .clk = &mstp_clks[MSTP009],
151 }, { 209 }, {
152 /* TMU5 */ 210 /* TMU5 */
153 .dev_id = "sh_tmu.5", 211 .dev_id = "sh_tmu.5",
154 .con_id = "tmu_fck", 212 .con_id = "tmu_fck",
155 .clk = &mstp_clks[16], 213 .clk = &mstp_clks[MSTP009],
156 }, { 214 }, {
157 /* TMU6 */ 215 /* TMU6 */
158 .dev_id = "sh_tmu.6", 216 .dev_id = "sh_tmu.6",
159 .con_id = "tmu_fck", 217 .con_id = "tmu_fck",
160 .clk = &mstp_clks[15], /* tmu678_fck */ 218 .clk = &mstp_clks[MSTP010],
161 }, { 219 }, {
162 /* TMU7 */ 220 /* TMU7 */
163 .dev_id = "sh_tmu.7", 221 .dev_id = "sh_tmu.7",
164 .con_id = "tmu_fck", 222 .con_id = "tmu_fck",
165 .clk = &mstp_clks[15], 223 .clk = &mstp_clks[MSTP010],
166 }, { 224 }, {
167 /* TMU8 */ 225 /* TMU8 */
168 .dev_id = "sh_tmu.8", 226 .dev_id = "sh_tmu.8",
169 .con_id = "tmu_fck", 227 .con_id = "tmu_fck",
170 .clk = &mstp_clks[15], 228 .clk = &mstp_clks[MSTP010],
171 }, { 229 }, {
172 /* TMU9 */ 230 /* TMU9 */
173 .dev_id = "sh_tmu.9", 231 .dev_id = "sh_tmu.9",
174 .con_id = "tmu_fck", 232 .con_id = "tmu_fck",
175 .clk = &mstp_clks[14], /* tmu9_11_fck */ 233 .clk = &mstp_clks[MSTP011],
176 }, { 234 }, {
177 /* TMU10 */ 235 /* TMU10 */
178 .dev_id = "sh_tmu.10", 236 .dev_id = "sh_tmu.10",
179 .con_id = "tmu_fck", 237 .con_id = "tmu_fck",
180 .clk = &mstp_clks[14], 238 .clk = &mstp_clks[MSTP011],
181 }, { 239 }, {
182 /* TMU11 */ 240 /* TMU11 */
183 .dev_id = "sh_tmu.11", 241 .dev_id = "sh_tmu.11",
184 .con_id = "tmu_fck", 242 .con_id = "tmu_fck",
185 .clk = &mstp_clks[14], 243 .clk = &mstp_clks[MSTP011],
186 } 244 },
245 CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
246 CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
247 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
248 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
249 CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
250 CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
251 CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
252 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
253 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
254 CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
255 CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
187}; 256};
188 257
189int __init arch_clk_init(void) 258int __init arch_clk_init(void)
@@ -199,7 +268,7 @@ int __init arch_clk_init(void)
199 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), 268 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
200 &div4_table); 269 &div4_table);
201 if (!ret) 270 if (!ret)
202 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 271 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
203 272
204 return ret; 273 return ret;
205} 274}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index e75c57bdfa5e..236a6282d778 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -13,9 +13,10 @@
13 */ 13 */
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/io.h>
17#include <asm/clkdev.h>
16#include <asm/clock.h> 18#include <asm/clock.h>
17#include <asm/freq.h> 19#include <asm/freq.h>
18#include <asm/io.h>
19 20
20static int ifc_divisors[] = { 1, 2, 4 ,6 }; 21static int ifc_divisors[] = { 1, 2, 4 ,6 };
21static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 }; 22static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
@@ -94,7 +95,6 @@ static struct clk_ops shx3_shyway_clk_ops = {
94}; 95};
95 96
96static struct clk shx3_shyway_clk = { 97static struct clk shx3_shyway_clk = {
97 .name = "shyway_clk",
98 .flags = CLK_ENABLE_ON_INIT, 98 .flags = CLK_ENABLE_ON_INIT,
99 .ops = &shx3_shyway_clk_ops, 99 .ops = &shx3_shyway_clk_ops,
100}; 100};
@@ -107,6 +107,13 @@ static struct clk *shx3_onchip_clocks[] = {
107 &shx3_shyway_clk, 107 &shx3_shyway_clk,
108}; 108};
109 109
110#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
111
112static struct clk_lookup lookups[] = {
113 /* main clocks */
114 CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk),
115};
116
110int __init arch_clk_init(void) 117int __init arch_clk_init(void)
111{ 118{
112 struct clk *clk; 119 struct clk *clk;
@@ -124,5 +131,7 @@ int __init arch_clk_init(void)
124 131
125 clk_put(clk); 132 clk_put(clk);
126 133
134 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
135
127 return ret; 136 return ret;
128} 137}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 11:28:16 -0500