aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/kernel/cpu/sh4a
diff options
context:
space:
mode:
authorPaul Mundt <lethal@linux-sh.org>2011-01-13 01:06:28 -0500
committerPaul Mundt <lethal@linux-sh.org>2011-01-13 01:06:28 -0500
commitf43dc23d5ea91fca257be02138a255f02d98e806 (patch)
treeb29722f6e965316e90ac97abf79923ced250dc21 /arch/sh/kernel/cpu/sh4a
parentf8e53553f452dcbf67cb89c8cba63a1cd6eb4cc0 (diff)
parent4162cf64973df51fc885825bc9ca4d055891c49f (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into common/serial-rework
Conflicts: arch/sh/kernel/cpu/sh2/setup-sh7619.c arch/sh/kernel/cpu/sh2a/setup-mxg.c arch/sh/kernel/cpu/sh2a/setup-sh7201.c arch/sh/kernel/cpu/sh2a/setup-sh7203.c arch/sh/kernel/cpu/sh2a/setup-sh7206.c arch/sh/kernel/cpu/sh3/setup-sh7705.c arch/sh/kernel/cpu/sh3/setup-sh770x.c arch/sh/kernel/cpu/sh3/setup-sh7710.c arch/sh/kernel/cpu/sh3/setup-sh7720.c arch/sh/kernel/cpu/sh4/setup-sh4-202.c arch/sh/kernel/cpu/sh4/setup-sh7750.c arch/sh/kernel/cpu/sh4/setup-sh7760.c arch/sh/kernel/cpu/sh4a/setup-sh7343.c arch/sh/kernel/cpu/sh4a/setup-sh7366.c arch/sh/kernel/cpu/sh4a/setup-sh7722.c arch/sh/kernel/cpu/sh4a/setup-sh7723.c arch/sh/kernel/cpu/sh4a/setup-sh7724.c arch/sh/kernel/cpu/sh4a/setup-sh7763.c arch/sh/kernel/cpu/sh4a/setup-sh7770.c arch/sh/kernel/cpu/sh4a/setup-sh7780.c arch/sh/kernel/cpu/sh4a/setup-sh7785.c arch/sh/kernel/cpu/sh4a/setup-sh7786.c arch/sh/kernel/cpu/sh4a/setup-shx3.c arch/sh/kernel/cpu/sh5/setup-sh5.c drivers/serial/sh-sci.c drivers/serial/sh-sci.h include/linux/serial_sci.h
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a')
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile22
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7343.c237
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c216
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c207
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c304
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c362
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c162
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7763.c20
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7770.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7780.c22
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7785.c182
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c314
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-shx3.c228
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c106
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c117
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c121
-rw-r--r--arch/sh/kernel/cpu/sh4a/intc-shx3.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/perf_event.c287
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c21
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c2287
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-shx3.c587
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c138
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c58
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c357
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c280
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c813
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c623
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c133
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c314
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c231
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c329
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c466
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c196
-rw-r--r--arch/sh/kernel/cpu/sh4a/smp-shx3.c116
-rw-r--r--arch/sh/kernel/cpu/sh4a/ubc.c133
35 files changed, 8490 insertions, 1541 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index ebdd391d5f42..cc122b1d3035 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -3,31 +3,33 @@
3# 3#
4 4
5# CPU subtype setup 5# CPU subtype setup
6obj-$(CONFIG_CPU_SUBTYPE_SH7757) += setup-sh7757.o
6obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o 7obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
7obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o 8obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
8obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o
15obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o 16obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
16obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o 17obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o
17 18
18# SMP setup 19# SMP setup
19smp-$(CONFIG_CPU_SHX3) := smp-shx3.o 20smp-$(CONFIG_CPU_SHX3) := smp-shx3.o
20 21
21# Primary on-chip clocks (common) 22# Primary on-chip clocks (common)
23clock-$(CONFIG_CPU_SUBTYPE_SH7757) := clock-sh7757.o
22clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o 24clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o
23clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o 25clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
24clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o 26clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
25clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o 27clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
26clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
27clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o 29clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
28clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o hwblk-sh7722.o
29clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o hwblk-sh7723.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o 32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o hwblk-sh7724.o
31clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o 33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o
32clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
33 35
@@ -35,9 +37,13 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
35pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o 37pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
36pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o 38pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
37pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o 39pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o
40pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o
38pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 41pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
39pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o 42pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
43pinmux-$(CONFIG_CPU_SUBTYPE_SHX3) := pinmux-shx3.o
40 44
41obj-y += $(clock-y) 45obj-y += $(clock-y)
42obj-$(CONFIG_SMP) += $(smp-y) 46obj-$(CONFIG_SMP) += $(smp-y)
43obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) 47obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y)
48obj-$(CONFIG_PERF_EVENTS) += perf_event.o
49obj-$(CONFIG_HAVE_HW_BREAKPOINT) += ubc.o
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 0ee3ee861252..93c646072c1b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clkdev.h>
24#include <asm/clock.h> 25#include <asm/clock.h>
25 26
26/* SH7343 registers */ 27/* SH7343 registers */
@@ -36,8 +37,6 @@
36 37
37/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
38static struct clk r_clk = { 39static struct clk r_clk = {
39 .name = "rclk",
40 .id = -1,
41 .rate = 32768, 40 .rate = 32768,
42}; 41};
43 42
@@ -46,8 +45,6 @@ static struct clk r_clk = {
46 * from the platform code. 45 * from the platform code.
47 */ 46 */
48struct clk extal_clk = { 47struct clk extal_clk = {
49 .name = "extal",
50 .id = -1,
51 .rate = 33333333, 48 .rate = 33333333,
52}; 49};
53 50
@@ -69,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
69}; 66};
70 67
71static struct clk dll_clk = { 68static struct clk dll_clk = {
72 .name = "dll_clk",
73 .id = -1,
74 .ops = &dll_clk_ops, 69 .ops = &dll_clk_ops,
75 .parent = &r_clk, 70 .parent = &r_clk,
76 .flags = CLK_ENABLE_ON_INIT, 71 .flags = CLK_ENABLE_ON_INIT,
@@ -91,8 +86,6 @@ static struct clk_ops pll_clk_ops = {
91}; 86};
92 87
93static struct clk pll_clk = { 88static struct clk pll_clk = {
94 .name = "pll_clk",
95 .id = -1,
96 .ops = &pll_clk_ops, 89 .ops = &pll_clk_ops,
97 .flags = CLK_ENABLE_ON_INIT, 90 .flags = CLK_ENABLE_ON_INIT,
98}; 91};
@@ -107,82 +100,182 @@ struct clk *main_clks[] = {
107static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 100static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
108static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 101static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
109 102
110static struct clk_div_mult_table div4_table = { 103static struct clk_div_mult_table div4_div_mult_table = {
111 .divisors = divisors, 104 .divisors = divisors,
112 .nr_divisors = ARRAY_SIZE(divisors), 105 .nr_divisors = ARRAY_SIZE(divisors),
113 .multipliers = multipliers, 106 .multipliers = multipliers,
114 .nr_multipliers = ARRAY_SIZE(multipliers), 107 .nr_multipliers = ARRAY_SIZE(multipliers),
115}; 108};
116 109
110static struct clk_div4_table div4_table = {
111 .div_mult_table = &div4_div_mult_table,
112};
113
117enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 114enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
118 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; 115 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
119 116
120#define DIV4(_str, _reg, _bit, _mask, _flags) \ 117#define DIV4(_reg, _bit, _mask, _flags) \
121 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
122 119
123struct clk div4_clks[DIV4_NR] = { 120struct clk div4_clks[DIV4_NR] = {
124 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), 121 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
125 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 122 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
126 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 123 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
127 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 124 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
128 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 125 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 126 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
130 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 127 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
131 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 128 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
132}; 129};
133 130
134struct clk div6_clks[] = { 131enum { DIV6_V, DIV6_NR };
135 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 132
133struct clk div6_clks[DIV6_NR] = {
134 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
135};
136
137#define MSTP(_parent, _reg, _bit, _flags) \
138 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
139
140enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
141 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
142 MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
143 MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001,
144 MSTP109, MSTP108, MSTP100,
145 MSTP225, MSTP224, MSTP218, MSTP217, MSTP216,
146 MSTP214, MSTP213, MSTP212, MSTP211, MSTP208,
147 MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
148 MSTP_NR };
149
150static struct clk mstp_clks[MSTP_NR] = {
151 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
152 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
153 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
154 [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
155 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
156 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
157 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
158 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
159 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
160 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
161 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
162 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
163 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
164 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
165 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
166 [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
167 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
168 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
169 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
170 [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
171 [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
172 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
173 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
174
175 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
176 [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
177
178 [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
179 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
180 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
181 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
182 [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
183 [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
184 [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
185 [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
186 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
187 [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
188 [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
189 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
190 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
191 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
192 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
193 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
194 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
136}; 195};
137 196
138#define MSTP(_str, _parent, _reg, _bit, _flags) \ 197#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
139 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 198
140 199static struct clk_lookup lookups[] = {
141static struct clk mstp_clks[] = { 200 /* main clocks */
142 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 201 CLKDEV_CON_ID("rclk", &r_clk),
143 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 202 CLKDEV_CON_ID("extal", &extal_clk),
144 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 203 CLKDEV_CON_ID("dll_clk", &dll_clk),
145 MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 204 CLKDEV_CON_ID("pll_clk", &pll_clk),
146 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 205
147 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), 206 /* DIV4 clocks */
148 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), 207 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
149 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), 208 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
150 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 209 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
151 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 210 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
152 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 211 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
153 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 212 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
154 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), 213 CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
155 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 214 CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
156 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 215
157 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 216 /* DIV6 clocks */
158 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), 217 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
159 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), 218
160 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), 219 /* MSTP32 clocks */
161 MSTP("scif3", &div4_clks[DIV4_P], MSTPCR0, 4, 0), 220 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
162 MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0), 221 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
163 MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 222 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
164 MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 223 CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
165 224 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
166 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 225 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
167 MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0), 226 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
168 227 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
169 MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0), 228 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
170 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0), 229 CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
171 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 230 CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
172 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), 231 CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
173 MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0), 232 CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
174 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0), 233 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
175 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0), 234 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
176 MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0), 235 CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
177 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 236 {
178 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0), 237 /* SCIF0 */
179 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), 238 .dev_id = "sh-sci.0",
180 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 239 .con_id = "sci_fck",
181 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 240 .clk = &mstp_clks[MSTP007],
182 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 241 }, {
183 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 242 /* SCIF1 */
184 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 243 .dev_id = "sh-sci.1",
185 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), 244 .con_id = "sci_fck",
245 .clk = &mstp_clks[MSTP006],
246 }, {
247 /* SCIF2 */
248 .dev_id = "sh-sci.2",
249 .con_id = "sci_fck",
250 .clk = &mstp_clks[MSTP005],
251 }, {
252 /* SCIF3 */
253 .dev_id = "sh-sci.3",
254 .con_id = "sci_fck",
255 .clk = &mstp_clks[MSTP004],
256 },
257 CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]),
258 CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]),
259 CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]),
260 CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
261 CLKDEV_CON_ID("i2c1", &mstp_clks[MSTP108]),
262 CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]),
263 CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]),
264 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
265 CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
266 CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]),
267 CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]),
268 CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]),
269 CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]),
270 CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
271 CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]),
272 CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]),
273 CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
274 CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
275 CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
276 CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
277 CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
278 CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
186}; 279};
187 280
188int __init arch_clk_init(void) 281int __init arch_clk_init(void)
@@ -198,14 +291,16 @@ int __init arch_clk_init(void)
198 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 291 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
199 ret = clk_register(main_clks[k]); 292 ret = clk_register(main_clks[k]);
200 293
294 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
295
201 if (!ret) 296 if (!ret)
202 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 297 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
203 298
204 if (!ret) 299 if (!ret)
205 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 300 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
206 301
207 if (!ret) 302 if (!ret)
208 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 303 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
209 304
210 return ret; 305 return ret;
211} 306}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index a95ebaba095c..049dc0628ccc 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clkdev.h>
24#include <asm/clock.h> 25#include <asm/clock.h>
25 26
26/* SH7366 registers */ 27/* SH7366 registers */
@@ -36,8 +37,6 @@
36 37
37/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
38static struct clk r_clk = { 39static struct clk r_clk = {
39 .name = "rclk",
40 .id = -1,
41 .rate = 32768, 40 .rate = 32768,
42}; 41};
43 42
@@ -46,8 +45,6 @@ static struct clk r_clk = {
46 * from the platform code. 45 * from the platform code.
47 */ 46 */
48struct clk extal_clk = { 47struct clk extal_clk = {
49 .name = "extal",
50 .id = -1,
51 .rate = 33333333, 48 .rate = 33333333,
52}; 49};
53 50
@@ -69,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
69}; 66};
70 67
71static struct clk dll_clk = { 68static struct clk dll_clk = {
72 .name = "dll_clk",
73 .id = -1,
74 .ops = &dll_clk_ops, 69 .ops = &dll_clk_ops,
75 .parent = &r_clk, 70 .parent = &r_clk,
76 .flags = CLK_ENABLE_ON_INIT, 71 .flags = CLK_ENABLE_ON_INIT,
@@ -94,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
94}; 89};
95 90
96static struct clk pll_clk = { 91static struct clk pll_clk = {
97 .name = "pll_clk",
98 .id = -1,
99 .ops = &pll_clk_ops, 92 .ops = &pll_clk_ops,
100 .flags = CLK_ENABLE_ON_INIT, 93 .flags = CLK_ENABLE_ON_INIT,
101}; 94};
@@ -110,79 +103,168 @@ struct clk *main_clks[] = {
110static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 103static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
111static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 104static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
112 105
113static struct clk_div_mult_table div4_table = { 106static struct clk_div_mult_table div4_div_mult_table = {
114 .divisors = divisors, 107 .divisors = divisors,
115 .nr_divisors = ARRAY_SIZE(divisors), 108 .nr_divisors = ARRAY_SIZE(divisors),
116 .multipliers = multipliers, 109 .multipliers = multipliers,
117 .nr_multipliers = ARRAY_SIZE(multipliers), 110 .nr_multipliers = ARRAY_SIZE(multipliers),
118}; 111};
119 112
113static struct clk_div4_table div4_table = {
114 .div_mult_table = &div4_div_mult_table,
115};
116
120enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 117enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
121 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; 118 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
122 119
123#define DIV4(_str, _reg, _bit, _mask, _flags) \ 120#define DIV4(_reg, _bit, _mask, _flags) \
124 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
125 122
126struct clk div4_clks[DIV4_NR] = { 123struct clk div4_clks[DIV4_NR] = {
127 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), 124 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
128 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 125 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 126 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
130 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 127 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
131 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 128 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
132 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 129 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
133 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 130 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
134 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 131 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
135}; 132};
136 133
137struct clk div6_clks[] = { 134enum { DIV6_V, DIV6_NR };
138 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 135
136struct clk div6_clks[DIV6_NR] = {
137 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
139}; 138};
140 139
141#define MSTP(_str, _parent, _reg, _bit, _flags) \ 140#define MSTP(_parent, _reg, _bit, _flags) \
142 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 141 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
142
143enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
144 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
145 MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
146 MSTP007, MSTP006, MSTP005, MSTP002, MSTP001,
147 MSTP109, MSTP100,
148 MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217,
149 MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
150 MSTP_NR };
143 151
144static struct clk mstp_clks[] = { 152static struct clk mstp_clks[MSTP_NR] = {
145 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ 153 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
146 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 154 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
147 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 155 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
148 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 156 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
149 MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 157 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
150 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 158 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
151 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), 159 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
152 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), 160 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
153 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), 161 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
154 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 162 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
155 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 163 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
156 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 164 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
157 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 165 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
158 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), 166 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
159 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 167 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
160 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 168 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
161 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 169 [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
162 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), 170 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
163 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), 171 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
164 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), 172 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
165 MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 173 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
166 MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 174 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
167 175
168 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 176 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
169 177
170 MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0), 178 [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
171 MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0), 179 [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
172 MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0), 180 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
173 MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0), 181 [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
174 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0), 182 [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
175 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 183 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
176 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), 184 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
177 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 185 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
178 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0), 186 [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
179 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), 187 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
180 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 188 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
181 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 189 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
182 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 190 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
183 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 191 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
184 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 192 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
185 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), 193};
194
195#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
196
197static struct clk_lookup lookups[] = {
198 /* main clocks */
199 CLKDEV_CON_ID("rclk", &r_clk),
200 CLKDEV_CON_ID("extal", &extal_clk),
201 CLKDEV_CON_ID("dll_clk", &dll_clk),
202 CLKDEV_CON_ID("pll_clk", &pll_clk),
203
204 /* DIV4 clocks */
205 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
206 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
207 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
208 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
209 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
210 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
211 CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
212 CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
213
214 /* DIV6 clocks */
215 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
216
217 /* MSTP32 clocks */
218 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
219 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
220 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
221 CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
222 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
223 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
224 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
225 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
226 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
227 CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
228 CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
229 CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
230 CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
231 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
232 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
233 CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
234 {
235 /* SCIF0 */
236 .dev_id = "sh-sci.0",
237 .con_id = "sci_fck",
238 .clk = &mstp_clks[MSTP007],
239 }, {
240 /* SCIF1 */
241 .dev_id = "sh-sci.1",
242 .con_id = "sci_fck",
243 .clk = &mstp_clks[MSTP006],
244 }, {
245 /* SCIF2 */
246 .dev_id = "sh-sci.2",
247 .con_id = "sci_fck",
248 .clk = &mstp_clks[MSTP005],
249 },
250 CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]),
251 CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]),
252 CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
253 CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]),
254 CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]),
255 CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]),
256 CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]),
257 CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]),
258 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
259 CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
260 CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
261 CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]),
262 CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
263 CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
264 CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
265 CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
266 CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
267 CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
186}; 268};
187 269
188int __init arch_clk_init(void) 270int __init arch_clk_init(void)
@@ -198,14 +280,16 @@ int __init arch_clk_init(void)
198 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 280 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
199 ret = clk_register(main_clks[k]); 281 ret = clk_register(main_clks[k]);
200 282
283 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
284
201 if (!ret) 285 if (!ret)
202 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 286 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
203 287
204 if (!ret) 288 if (!ret)
205 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 289 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
206 290
207 if (!ret) 291 if (!ret)
208 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 292 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
209 293
210 return ret; 294 return ret;
211} 295}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 40f859354f79..9d23a36f0647 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -21,7 +21,10 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clkdev.h>
24#include <asm/clock.h> 25#include <asm/clock.h>
26#include <asm/hwblk.h>
27#include <cpu/sh7722.h>
25 28
26/* SH7722 registers */ 29/* SH7722 registers */
27#define FRQCR 0xa4150000 30#define FRQCR 0xa4150000
@@ -30,15 +33,10 @@
30#define SCLKBCR 0xa415000c 33#define SCLKBCR 0xa415000c
31#define IRDACLKCR 0xa4150018 34#define IRDACLKCR 0xa4150018
32#define PLLCR 0xa4150024 35#define PLLCR 0xa4150024
33#define MSTPCR0 0xa4150030
34#define MSTPCR1 0xa4150034
35#define MSTPCR2 0xa4150038
36#define DLLFRQ 0xa4150050 36#define DLLFRQ 0xa4150050
37 37
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
39static struct clk r_clk = { 39static struct clk r_clk = {
40 .name = "rclk",
41 .id = -1,
42 .rate = 32768, 40 .rate = 32768,
43}; 41};
44 42
@@ -47,8 +45,6 @@ static struct clk r_clk = {
47 * from the platform code. 45 * from the platform code.
48 */ 46 */
49struct clk extal_clk = { 47struct clk extal_clk = {
50 .name = "extal",
51 .id = -1,
52 .rate = 33333333, 48 .rate = 33333333,
53}; 49};
54 50
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
70}; 66};
71 67
72static struct clk dll_clk = { 68static struct clk dll_clk = {
73 .name = "dll_clk",
74 .id = -1,
75 .ops = &dll_clk_ops, 69 .ops = &dll_clk_ops,
76 .parent = &r_clk, 70 .parent = &r_clk,
77 .flags = CLK_ENABLE_ON_INIT, 71 .flags = CLK_ENABLE_ON_INIT,
@@ -95,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
95}; 89};
96 90
97static struct clk pll_clk = { 91static struct clk pll_clk = {
98 .name = "pll_clk",
99 .id = -1,
100 .ops = &pll_clk_ops, 92 .ops = &pll_clk_ops,
101 .flags = CLK_ENABLE_ON_INIT, 93 .flags = CLK_ENABLE_ON_INIT,
102}; 94};
@@ -111,64 +103,153 @@ struct clk *main_clks[] = {
111static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 103static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
112static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 104static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
113 105
114static struct clk_div_mult_table div4_table = { 106static struct clk_div_mult_table div4_div_mult_table = {
115 .divisors = divisors, 107 .divisors = divisors,
116 .nr_divisors = ARRAY_SIZE(divisors), 108 .nr_divisors = ARRAY_SIZE(divisors),
117 .multipliers = multipliers, 109 .multipliers = multipliers,
118 .nr_multipliers = ARRAY_SIZE(multipliers), 110 .nr_multipliers = ARRAY_SIZE(multipliers),
119}; 111};
120 112
121enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 113static struct clk_div4_table div4_table = {
122 DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR }; 114 .div_mult_table = &div4_div_mult_table,
115};
116
117#define DIV4(_reg, _bit, _mask, _flags) \
118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
123 119
124#define DIV4(_str, _reg, _bit, _mask, _flags) \ 120enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
125 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
126 121
127struct clk div4_clks[DIV4_NR] = { 122struct clk div4_clks[DIV4_NR] = {
128 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), 123 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
129 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 124 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
130 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 125 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
131 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 126 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
132 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 127 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
133 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 128 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
134 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 129};
135 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 130
136 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0), 131enum { DIV4_IRDA, DIV4_ENABLE_NR };
132
133struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
134 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
135};
136
137enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
138
139struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
140 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
141 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
142};
143
144enum { DIV6_V, DIV6_NR };
145
146struct clk div6_clks[DIV6_NR] = {
147 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
137}; 148};
138 149
139struct clk div6_clks[] = { 150static struct clk mstp_clks[HWBLK_NR] = {
140 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 151 SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
152 SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
153 SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
154 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
155 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
156 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
157 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
158 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
159 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
160
161 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
162 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
163
164 SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
165 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
166 SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0),
167 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
168 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
169 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
170 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
171 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
172 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
173 SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0),
174 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
175 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
141}; 176};
142 177
143#define MSTP(_str, _parent, _reg, _bit, _flags) \ 178#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
144 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 179
145 180static struct clk_lookup lookups[] = {
146static struct clk mstp_clks[] = { 181 /* main clocks */
147 MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 182 CLKDEV_CON_ID("rclk", &r_clk),
148 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 183 CLKDEV_CON_ID("extal", &extal_clk),
149 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 184 CLKDEV_CON_ID("dll_clk", &dll_clk),
150 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), 185 CLKDEV_CON_ID("pll_clk", &pll_clk),
151 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 186
152 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 187 /* DIV4 clocks */
153 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), 188 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
154 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), 189 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
155 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), 190 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
156 191 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
157 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 192 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
158 MSTP("rtc0", &r_clk, MSTPCR1, 8, 0), 193 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
159 194 CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
160 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 195 CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
161 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0), 196 CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
162 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 197
163 MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 9, 0), 198 /* DIV6 clocks */
164 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0), 199 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
165 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 200
166 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), 201 /* MSTP clocks */
167 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 202 CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
168 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 203 CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
169 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 204 {
170 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 205 /* TMU0 */
171 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), 206 .dev_id = "sh_tmu.0",
207 .con_id = "tmu_fck",
208 .clk = &mstp_clks[HWBLK_TMU],
209 }, {
210 /* TMU1 */
211 .dev_id = "sh_tmu.1",
212 .con_id = "tmu_fck",
213 .clk = &mstp_clks[HWBLK_TMU],
214 }, {
215 /* TMU2 */
216 .dev_id = "sh_tmu.2",
217 .con_id = "tmu_fck",
218 .clk = &mstp_clks[HWBLK_TMU],
219 },
220 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
221 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
222 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
223 {
224 /* SCIF0 */
225 .dev_id = "sh-sci.0",
226 .con_id = "sci_fck",
227 .clk = &mstp_clks[HWBLK_SCIF0],
228 }, {
229 /* SCIF1 */
230 .dev_id = "sh-sci.1",
231 .con_id = "sci_fck",
232 .clk = &mstp_clks[HWBLK_SCIF1],
233 }, {
234 /* SCIF2 */
235 .dev_id = "sh-sci.2",
236 .con_id = "sci_fck",
237 .clk = &mstp_clks[HWBLK_SCIF2],
238 },
239 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
240 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
241 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
242 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
243 CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
244 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
245 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
246 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
247 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
248 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
249 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
250 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
251 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
252 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
172}; 253};
173 254
174int __init arch_clk_init(void) 255int __init arch_clk_init(void)
@@ -184,14 +265,24 @@ int __init arch_clk_init(void)
184 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 265 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
185 ret = clk_register(main_clks[k]); 266 ret = clk_register(main_clks[k]);
186 267
268 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
269
187 if (!ret) 270 if (!ret)
188 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 271 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
189 272
190 if (!ret) 273 if (!ret)
191 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 274 ret = sh_clk_div4_enable_register(div4_enable_clks,
275 DIV4_ENABLE_NR, &div4_table);
276
277 if (!ret)
278 ret = sh_clk_div4_reparent_register(div4_reparent_clks,
279 DIV4_REPARENT_NR, &div4_table);
280
281 if (!ret)
282 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
192 283
193 if (!ret) 284 if (!ret)
194 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 285 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
195 286
196 return ret; 287 return ret;
197} 288}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index e67c2678b8ae..55493cd5bd8f 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -21,7 +21,11 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/clkdev.h>
24#include <asm/clock.h> 26#include <asm/clock.h>
27#include <asm/hwblk.h>
28#include <cpu/sh7723.h>
25 29
26/* SH7723 registers */ 30/* SH7723 registers */
27#define FRQCR 0xa4150000 31#define FRQCR 0xa4150000
@@ -30,15 +34,10 @@
30#define SCLKBCR 0xa415000c 34#define SCLKBCR 0xa415000c
31#define IRDACLKCR 0xa4150018 35#define IRDACLKCR 0xa4150018
32#define PLLCR 0xa4150024 36#define PLLCR 0xa4150024
33#define MSTPCR0 0xa4150030
34#define MSTPCR1 0xa4150034
35#define MSTPCR2 0xa4150038
36#define DLLFRQ 0xa4150050 37#define DLLFRQ 0xa4150050
37 38
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 39/* Fixed 32 KHz root clock for RTC and Power Management purposes */
39static struct clk r_clk = { 40static struct clk r_clk = {
40 .name = "rclk",
41 .id = -1,
42 .rate = 32768, 41 .rate = 32768,
43}; 42};
44 43
@@ -47,8 +46,6 @@ static struct clk r_clk = {
47 * from the platform code. 46 * from the platform code.
48 */ 47 */
49struct clk extal_clk = { 48struct clk extal_clk = {
50 .name = "extal",
51 .id = -1,
52 .rate = 33333333, 49 .rate = 33333333,
53}; 50};
54 51
@@ -70,8 +67,6 @@ static struct clk_ops dll_clk_ops = {
70}; 67};
71 68
72static struct clk dll_clk = { 69static struct clk dll_clk = {
73 .name = "dll_clk",
74 .id = -1,
75 .ops = &dll_clk_ops, 70 .ops = &dll_clk_ops,
76 .parent = &r_clk, 71 .parent = &r_clk,
77 .flags = CLK_ENABLE_ON_INIT, 72 .flags = CLK_ENABLE_ON_INIT,
@@ -95,8 +90,6 @@ static struct clk_ops pll_clk_ops = {
95}; 90};
96 91
97static struct clk pll_clk = { 92static struct clk pll_clk = {
98 .name = "pll_clk",
99 .id = -1,
100 .ops = &pll_clk_ops, 93 .ops = &pll_clk_ops,
101 .flags = CLK_ENABLE_ON_INIT, 94 .flags = CLK_ENABLE_ON_INIT,
102}; 95};
@@ -111,89 +104,228 @@ struct clk *main_clks[] = {
111static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 104static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
112static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 105static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
113 106
114static struct clk_div_mult_table div4_table = { 107static struct clk_div_mult_table div4_div_mult_table = {
115 .divisors = divisors, 108 .divisors = divisors,
116 .nr_divisors = ARRAY_SIZE(divisors), 109 .nr_divisors = ARRAY_SIZE(divisors),
117 .multipliers = multipliers, 110 .multipliers = multipliers,
118 .nr_multipliers = ARRAY_SIZE(multipliers), 111 .nr_multipliers = ARRAY_SIZE(multipliers),
119}; 112};
120 113
121enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 114static struct clk_div4_table div4_table = {
122 DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR }; 115 .div_mult_table = &div4_div_mult_table,
116};
117
118enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
123 119
124#define DIV4(_str, _reg, _bit, _mask, _flags) \ 120#define DIV4(_reg, _bit, _mask, _flags) \
125 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
126 122
127struct clk div4_clks[DIV4_NR] = { 123struct clk div4_clks[DIV4_NR] = {
128 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), 124 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
129 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), 125 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
130 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), 126 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
131 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), 127 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
132 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), 128 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
133 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0), 129 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
134 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0), 130};
135 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0), 131
136 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0), 132enum { DIV4_IRDA, DIV4_ENABLE_NR };
133
134struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
135 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
137}; 136};
138 137
139struct clk div6_clks[] = { 138enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
140 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 139
140struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
141 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
142 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
141}; 143};
144enum { DIV6_V, DIV6_NR };
142 145
143#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \ 146struct clk div6_clks[DIV6_NR] = {
144 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT) 147 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
148};
145 149
146static struct clk mstp_clks[] = { 150static struct clk mstp_clks[] = {
147 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ 151 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
148 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0), 152 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
149 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0), 153 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
150 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0), 154 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
151 MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 28, 1, 1, 0), 155 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
152 MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0), 156 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
153 MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0), 157 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
154 MSTP("intc0", &div4_clks[DIV4_I], MSTPCR0, 22, 1, 1, 0), 158 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
155 MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1), 159 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
156 MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0), 160 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
157 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0), 161 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
158 MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0), 162 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
159 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0), 163 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
160 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0), 164 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
161 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0), 165 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
162 MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1), 166 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
163 MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 11, 0, 1, 0), 167 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
164 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0), 168 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
165 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0), 169 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
166 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0), 170 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
167 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0), 171 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
168 MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0), 172 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
169 MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0), 173 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
170 MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0), 174 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
171 MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0), 175 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
172 MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0), 176 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
173 MSTP("meram0", &div4_clks[DIV4_SH], MSTPCR0, 0, 1, 1, 0), 177 SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0),
174 178
175 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0), 179 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
176 MSTP("rtc0", &r_clk, MSTPCR1, 8, 0, 0, 0), 180 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
177 181
178 MSTP("atapi0", &div4_clks[DIV4_SH], MSTPCR2, 28, 0, 1, 0), 182 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0),
179 MSTP("adc0", &div4_clks[DIV4_P], MSTPCR2, 27, 0, 1, 0), 183 SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0),
180 MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0), 184 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
181 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0), 185 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
182 MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0), 186 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
183 MSTP("icb0", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1), 187 SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
184 MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0), 188 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
185 MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0), 189 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
186 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0, 0, 0), 190 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
187 MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 11, 0, 1, 0), 191 SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0),
188 MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 10, 0, 1, 1), 192 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
189 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0, 1, 0), 193 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
190 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1), 194 SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0),
191 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1), 195 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
192 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1), 196 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
193 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1), 197 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
194 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1), 198 SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0),
195 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1), 199 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
196 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1), 200 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
201};
202
203#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
204
205static struct clk_lookup lookups[] = {
206 /* main clocks */
207 CLKDEV_CON_ID("rclk", &r_clk),
208 CLKDEV_CON_ID("extal", &extal_clk),
209 CLKDEV_CON_ID("dll_clk", &dll_clk),
210 CLKDEV_CON_ID("pll_clk", &pll_clk),
211
212 /* DIV4 clocks */
213 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
214 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
215 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
216 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
217 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
218 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
219 CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
220 CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
221 CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
222
223 /* DIV6 clocks */
224 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
225
226 /* MSTP clocks */
227 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
228 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
229 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
230 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
231 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
232 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
233 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
234 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
235 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
236 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
237 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
238 {
239 /* TMU0 */
240 .dev_id = "sh_tmu.0",
241 .con_id = "tmu_fck",
242 .clk = &mstp_clks[HWBLK_TMU0],
243 }, {
244 /* TMU1 */
245 .dev_id = "sh_tmu.1",
246 .con_id = "tmu_fck",
247 .clk = &mstp_clks[HWBLK_TMU0],
248 }, {
249 /* TMU2 */
250 .dev_id = "sh_tmu.2",
251 .con_id = "tmu_fck",
252 .clk = &mstp_clks[HWBLK_TMU0],
253 },
254 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
255 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
256 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
257 {
258 /* TMU3 */
259 .dev_id = "sh_tmu.3",
260 .con_id = "tmu_fck",
261 .clk = &mstp_clks[HWBLK_TMU1],
262 }, {
263 /* TMU4 */
264 .dev_id = "sh_tmu.4",
265 .con_id = "tmu_fck",
266 .clk = &mstp_clks[HWBLK_TMU1],
267 }, {
268 /* TMU5 */
269 .dev_id = "sh_tmu.5",
270 .con_id = "tmu_fck",
271 .clk = &mstp_clks[HWBLK_TMU1],
272 },
273 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
274 {
275 /* SCIF0 */
276 .dev_id = "sh-sci.0",
277 .con_id = "sci_fck",
278 .clk = &mstp_clks[HWBLK_SCIF0],
279 }, {
280 /* SCIF1 */
281 .dev_id = "sh-sci.1",
282 .con_id = "sci_fck",
283 .clk = &mstp_clks[HWBLK_SCIF1],
284 }, {
285 /* SCIF2 */
286 .dev_id = "sh-sci.2",
287 .con_id = "sci_fck",
288 .clk = &mstp_clks[HWBLK_SCIF2],
289 }, {
290 /* SCIF3 */
291 .dev_id = "sh-sci.3",
292 .con_id = "sci_fck",
293 .clk = &mstp_clks[HWBLK_SCIF3],
294 }, {
295 /* SCIF4 */
296 .dev_id = "sh-sci.4",
297 .con_id = "sci_fck",
298 .clk = &mstp_clks[HWBLK_SCIF4],
299 }, {
300 /* SCIF5 */
301 .dev_id = "sh-sci.5",
302 .con_id = "sci_fck",
303 .clk = &mstp_clks[HWBLK_SCIF5],
304 },
305 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
306 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
307 CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
308 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
309 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
310 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
311 CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]),
312 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
313 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
314 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
315 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
316 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
317 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
318 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
319 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
320 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
321 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
322 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
323 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
324 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
325 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
326 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
327 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
328 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
197}; 329};
198 330
199int __init arch_clk_init(void) 331int __init arch_clk_init(void)
@@ -207,16 +339,26 @@ int __init arch_clk_init(void)
207 pll_clk.parent = &extal_clk; 339 pll_clk.parent = &extal_clk;
208 340
209 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 341 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
210 ret = clk_register(main_clks[k]); 342 ret |= clk_register(main_clks[k]);
343
344 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
211 345
212 if (!ret) 346 if (!ret)
213 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 347 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
214 348
215 if (!ret) 349 if (!ret)
216 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 350 ret = sh_clk_div4_enable_register(div4_enable_clks,
351 DIV4_ENABLE_NR, &div4_table);
352
353 if (!ret)
354 ret = sh_clk_div4_reparent_register(div4_reparent_clks,
355 DIV4_REPARENT_NR, &div4_table);
356
357 if (!ret)
358 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
217 359
218 if (!ret) 360 if (!ret)
219 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 361 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
220 362
221 return ret; 363 return ret;
222} 364}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 5d5c9b952883..d08fa953c88b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -21,7 +21,11 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/clkdev.h>
24#include <asm/clock.h> 26#include <asm/clock.h>
27#include <asm/hwblk.h>
28#include <cpu/sh7724.h>
25 29
26/* SH7724 registers */ 30/* SH7724 registers */
27#define FRQCRA 0xa4150000 31#define FRQCRA 0xa4150000
@@ -31,17 +35,12 @@
31#define FCLKBCR 0xa415000c 35#define FCLKBCR 0xa415000c
32#define IRDACLKCR 0xa4150018 36#define IRDACLKCR 0xa4150018
33#define PLLCR 0xa4150024 37#define PLLCR 0xa4150024
34#define MSTPCR0 0xa4150030
35#define MSTPCR1 0xa4150034
36#define MSTPCR2 0xa4150038
37#define SPUCLKCR 0xa415003c 38#define SPUCLKCR 0xa415003c
38#define FLLFRQ 0xa4150050 39#define FLLFRQ 0xa4150050
39#define LSTATS 0xa4150060 40#define LSTATS 0xa4150060
40 41
41/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 42/* Fixed 32 KHz root clock for RTC and Power Management purposes */
42static struct clk r_clk = { 43static struct clk r_clk = {
43 .name = "rclk",
44 .id = -1,
45 .rate = 32768, 44 .rate = 32768,
46}; 45};
47 46
@@ -49,9 +48,7 @@ static struct clk r_clk = {
49 * Default rate for the root input clock, reset this with clk_set_rate() 48 * Default rate for the root input clock, reset this with clk_set_rate()
50 * from the platform code. 49 * from the platform code.
51 */ 50 */
52struct clk extal_clk = { 51static struct clk extal_clk = {
53 .name = "extal",
54 .id = -1,
55 .rate = 33333333, 52 .rate = 33333333,
56}; 53};
57 54
@@ -75,8 +72,6 @@ static struct clk_ops fll_clk_ops = {
75}; 72};
76 73
77static struct clk fll_clk = { 74static struct clk fll_clk = {
78 .name = "fll_clk",
79 .id = -1,
80 .ops = &fll_clk_ops, 75 .ops = &fll_clk_ops,
81 .parent = &r_clk, 76 .parent = &r_clk,
82 .flags = CLK_ENABLE_ON_INIT, 77 .flags = CLK_ENABLE_ON_INIT,
@@ -97,8 +92,6 @@ static struct clk_ops pll_clk_ops = {
97}; 92};
98 93
99static struct clk pll_clk = { 94static struct clk pll_clk = {
100 .name = "pll_clk",
101 .id = -1,
102 .ops = &pll_clk_ops, 95 .ops = &pll_clk_ops,
103 .flags = CLK_ENABLE_ON_INIT, 96 .flags = CLK_ENABLE_ON_INIT,
104}; 97};
@@ -114,106 +107,282 @@ static struct clk_ops div3_clk_ops = {
114}; 107};
115 108
116static struct clk div3_clk = { 109static struct clk div3_clk = {
117 .name = "div3_clk",
118 .id = -1,
119 .ops = &div3_clk_ops, 110 .ops = &div3_clk_ops,
120 .parent = &pll_clk, 111 .parent = &pll_clk,
121}; 112};
122 113
123struct clk *main_clks[] = { 114/* External input clock (pin name: FSIMCKA/FSIMCKB ) */
115struct clk sh7724_fsimcka_clk = {
116};
117
118struct clk sh7724_fsimckb_clk = {
119};
120
121static struct clk *main_clks[] = {
124 &r_clk, 122 &r_clk,
125 &extal_clk, 123 &extal_clk,
126 &fll_clk, 124 &fll_clk,
127 &pll_clk, 125 &pll_clk,
128 &div3_clk, 126 &div3_clk,
127 &sh7724_fsimcka_clk,
128 &sh7724_fsimckb_clk,
129}; 129};
130 130
131static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; 131static void div4_kick(struct clk *clk)
132{
133 unsigned long value;
134
135 /* set KICK bit in FRQCRA to update hardware setting */
136 value = __raw_readl(FRQCRA);
137 value |= (1 << 31);
138 __raw_writel(value, FRQCRA);
139}
140
141static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
132 142
133static struct clk_div_mult_table div4_table = { 143static struct clk_div_mult_table div4_div_mult_table = {
134 .divisors = divisors, 144 .divisors = divisors,
135 .nr_divisors = ARRAY_SIZE(divisors), 145 .nr_divisors = ARRAY_SIZE(divisors),
136}; 146};
137 147
148static struct clk_div4_table div4_table = {
149 .div_mult_table = &div4_div_mult_table,
150 .kick = div4_kick,
151};
152
138enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; 153enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
139 154
140#define DIV4(_str, _reg, _bit, _mask, _flags) \ 155#define DIV4(_reg, _bit, _mask, _flags) \
141 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 156 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
142 157
143struct clk div4_clks[DIV4_NR] = { 158struct clk div4_clks[DIV4_NR] = {
144 [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), 159 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
145 [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), 160 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
146 [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), 161 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
147 [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0), 162 [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
148 [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0), 163 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
149}; 164};
150 165
151struct clk div6_clks[] = { 166enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR };
152 SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0), 167
153 SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0), 168static struct clk div6_clks[DIV6_NR] = {
154 SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0), 169 [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
155 SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0), 170 [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
156 SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0), 171 [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
157}; 172};
158 173
159#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \ 174enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR };
160 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT) 175
161 176/* Indices are important - they are the actual src selecting values */
162static struct clk mstp_clks[] = { 177static struct clk *fclkacr_parent[] = {
163 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0), 178 [0] = &div3_clk,
164 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0), 179 [1] = NULL,
165 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0), 180 [2] = &sh7724_fsimcka_clk,
166 MSTP("rs0", &div4_clks[DIV4_B], MSTPCR0, 28, 1, 1, 0), 181 [3] = NULL,
167 MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0), 182};
168 MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 26, 1, 1, 0), 183
169 MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0), 184static struct clk *fclkbcr_parent[] = {
170 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 1, 1, 0), 185 [0] = &div3_clk,
171 MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1), 186 [1] = NULL,
172 MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0), 187 [2] = &sh7724_fsimckb_clk,
173 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0), 188 [3] = NULL,
174 MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0), 189};
175 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0), 190
176 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0), 191static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
177 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0), 192 [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0,
178 MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1), 193 fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
179 MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0), 194 [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0,
180 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0), 195 fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
181 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0), 196};
182 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0), 197
183 MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0), 198static struct clk mstp_clks[HWBLK_NR] = {
184 MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0), 199 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
185 MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0), 200 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
186 MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0), 201 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
187 MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0), 202 SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
188 203 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
189 MSTP("keysc0", &r_clk, MSTPCR1, 12, 0, 0, 0), 204 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
190 MSTP("rtc0", &r_clk, MSTPCR1, 11, 0, 0, 0), 205 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
191 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0), 206 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT),
192 MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0, 1, 0), 207 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
193 208 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
194 MSTP("mmc0", &div4_clks[DIV4_B], MSTPCR2, 29, 0, 1, 0), 209 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
195 MSTP("eth0", &div4_clks[DIV4_B], MSTPCR2, 28, 0, 1, 0), 210 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
196 MSTP("atapi0", &div4_clks[DIV4_B], MSTPCR2, 26, 0, 1, 0), 211 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
197 MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0), 212 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
198 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0), 213 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
199 MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0), 214 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
200 MSTP("usb1", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1), 215 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
201 MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 20, 0, 1, 1), 216 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
202 MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 19, 0, 1, 1), 217 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
203 MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0), 218 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
204 MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0), 219 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
205 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 15, 1, 1, 1), 220 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
206 MSTP("ceu1", &div4_clks[DIV4_B], MSTPCR2, 13, 0, 1, 1), 221 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
207 MSTP("beu1", &div4_clks[DIV4_B], MSTPCR2, 12, 0, 1, 1), 222 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
208 MSTP("2ddmac0", &div4_clks[DIV4_SH], MSTPCR2, 10, 0, 1, 1), 223 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
209 MSTP("spu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0, 1, 0), 224
210 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1), 225 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
211 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1), 226 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
212 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1), 227 SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0),
213 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1), 228 SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0),
214 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1), 229
215 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1), 230 SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0),
216 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1), 231 SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0),
232 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0),
233 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
234 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
235 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
236 SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0),
237 SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0),
238 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
239 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
240 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
241 SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0),
242 SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0),
243 SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0),
244 SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0),
245 SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0),
246 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
247 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
248 SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0),
249 SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0),
250 SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0),
251 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
252 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
253};
254
255#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
256
257static struct clk_lookup lookups[] = {
258 /* main clocks */
259 CLKDEV_CON_ID("rclk", &r_clk),
260 CLKDEV_CON_ID("extal", &extal_clk),
261 CLKDEV_CON_ID("fll_clk", &fll_clk),
262 CLKDEV_CON_ID("pll_clk", &pll_clk),
263 CLKDEV_CON_ID("div3_clk", &div3_clk),
264
265 /* DIV4 clocks */
266 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
267 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
268 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
269 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
270 CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
271
272 /* DIV6 clocks */
273 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
274 CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]),
275 CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]),
276 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
277 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
278
279 /* MSTP clocks */
280 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
281 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
282 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
283 CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
284 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
285 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
286 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
287 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
288 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
289 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
290 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
291 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
292 {
293 /* TMU0 */
294 .dev_id = "sh_tmu.0",
295 .con_id = "tmu_fck",
296 .clk = &mstp_clks[HWBLK_TMU0],
297 }, {
298 /* TMU1 */
299 .dev_id = "sh_tmu.1",
300 .con_id = "tmu_fck",
301 .clk = &mstp_clks[HWBLK_TMU0],
302 }, {
303 /* TMU2 */
304 .dev_id = "sh_tmu.2",
305 .con_id = "tmu_fck",
306 .clk = &mstp_clks[HWBLK_TMU0],
307 }, {
308 /* TMU3 */
309 .dev_id = "sh_tmu.3",
310 .con_id = "tmu_fck",
311 .clk = &mstp_clks[HWBLK_TMU1],
312 },
313 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
314 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
315 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
316 {
317 /* TMU4 */
318 .dev_id = "sh_tmu.4",
319 .con_id = "tmu_fck",
320 .clk = &mstp_clks[HWBLK_TMU1],
321 }, {
322 /* TMU5 */
323 .dev_id = "sh_tmu.5",
324 .con_id = "tmu_fck",
325 .clk = &mstp_clks[HWBLK_TMU1],
326 }, {
327 /* SCIF0 */
328 .dev_id = "sh-sci.0",
329 .con_id = "sci_fck",
330 .clk = &mstp_clks[HWBLK_SCIF0],
331 }, {
332 /* SCIF1 */
333 .dev_id = "sh-sci.1",
334 .con_id = "sci_fck",
335 .clk = &mstp_clks[HWBLK_SCIF1],
336 }, {
337 /* SCIF2 */
338 .dev_id = "sh-sci.2",
339 .con_id = "sci_fck",
340 .clk = &mstp_clks[HWBLK_SCIF2],
341 }, {
342 /* SCIF3 */
343 .dev_id = "sh-sci.3",
344 .con_id = "sci_fck",
345 .clk = &mstp_clks[HWBLK_SCIF3],
346 }, {
347 /* SCIF4 */
348 .dev_id = "sh-sci.4",
349 .con_id = "sci_fck",
350 .clk = &mstp_clks[HWBLK_SCIF4],
351 }, {
352 /* SCIF5 */
353 .dev_id = "sh-sci.5",
354 .con_id = "sci_fck",
355 .clk = &mstp_clks[HWBLK_SCIF5],
356 },
357 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
358 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
359 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
360 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
361 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC0]),
362 CLKDEV_CON_ID("i2c1", &mstp_clks[HWBLK_IIC1]),
363 CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]),
364 CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]),
365 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
366 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
367 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
368 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
369 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
370 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
371 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
372 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
373 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
374 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
375 CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]),
376 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
377 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
378 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
379 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
380 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
381 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
382 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]),
383 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
384 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
385 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
217}; 386};
218 387
219int __init arch_clk_init(void) 388int __init arch_clk_init(void)
@@ -229,14 +398,19 @@ int __init arch_clk_init(void)
229 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 398 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
230 ret = clk_register(main_clks[k]); 399 ret = clk_register(main_clks[k]);
231 400
401 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
402
232 if (!ret) 403 if (!ret)
233 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 404 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
234 405
235 if (!ret) 406 if (!ret)
236 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 407 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
408
409 if (!ret)
410 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
237 411
238 if (!ret) 412 if (!ret)
239 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 413 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
240 414
241 return ret; 415 return ret;
242} 416}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
new file mode 100644
index 000000000000..e073e3eb4c3d
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -0,0 +1,162 @@
1/*
2 * arch/sh/kernel/cpu/sh4/clock-sh7757.c
3 *
4 * SH7757 support for the clock framework
5 *
6 * Copyright (C) 2009-2010 Renesas Solutions Corp.
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/clkdev.h>
16#include <asm/clock.h>
17#include <asm/freq.h>
18
19/*
20 * Default rate for the root input clock, reset this with clk_set_rate()
21 * from the platform code.
22 */
23static struct clk extal_clk = {
24 .rate = 48000000,
25};
26
27static unsigned long pll_recalc(struct clk *clk)
28{
29 int multiplier;
30
31 multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16;
32
33 return clk->parent->rate * multiplier;
34}
35
36static struct clk_ops pll_clk_ops = {
37 .recalc = pll_recalc,
38};
39
40static struct clk pll_clk = {
41 .ops = &pll_clk_ops,
42 .parent = &extal_clk,
43 .flags = CLK_ENABLE_ON_INIT,
44};
45
46static struct clk *clks[] = {
47 &extal_clk,
48 &pll_clk,
49};
50
51static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6,
52 1, 1, 1, 16, 1, 24, 1, 1 };
53
54static struct clk_div_mult_table div4_div_mult_table = {
55 .divisors = div2,
56 .nr_divisors = ARRAY_SIZE(div2),
57};
58
59static struct clk_div4_table div4_table = {
60 .div_mult_table = &div4_div_mult_table,
61};
62
63enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR };
64
65#define DIV4(_bit, _mask, _flags) \
66 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
67
68struct clk div4_clks[DIV4_NR] = {
69 /*
70 * P clock is always enable, because some P clock modules is used
71 * by Host PC.
72 */
73 [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
74 [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
75 [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
76};
77
78#define MSTPCR0 0xffc80030
79#define MSTPCR1 0xffc80034
80
81enum { MSTP004, MSTP000, MSTP114, MSTP113, MSTP112,
82 MSTP111, MSTP110, MSTP103, MSTP102,
83 MSTP_NR };
84
85static struct clk mstp_clks[MSTP_NR] = {
86 /* MSTPCR0 */
87 [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
88 [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
89
90 /* MSTPCR1 */
91 [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
92 [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
93 [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
94 [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
95 [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
96 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
97 [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
98};
99
100#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
101
102static struct clk_lookup lookups[] = {
103 /* main clocks */
104 CLKDEV_CON_ID("extal", &extal_clk),
105 CLKDEV_CON_ID("pll_clk", &pll_clk),
106
107 /* DIV4 clocks */
108 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
109 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
110 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
111
112 /* MSTP32 clocks */
113 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP004]),
114 CLKDEV_CON_ID("riic", &mstp_clks[MSTP000]),
115 {
116 /* TMU0 */
117 .dev_id = "sh_tmu.0",
118 .con_id = "tmu_fck",
119 .clk = &mstp_clks[MSTP113],
120 }, {
121 /* TMU1 */
122 .dev_id = "sh_tmu.1",
123 .con_id = "tmu_fck",
124 .clk = &mstp_clks[MSTP114],
125 },
126 {
127 /* SCIF4 (But, ID is 2) */
128 .dev_id = "sh-sci.2",
129 .con_id = "sci_fck",
130 .clk = &mstp_clks[MSTP112],
131 }, {
132 /* SCIF3 */
133 .dev_id = "sh-sci.1",
134 .con_id = "sci_fck",
135 .clk = &mstp_clks[MSTP111],
136 }, {
137 /* SCIF2 */
138 .dev_id = "sh-sci.0",
139 .con_id = "sci_fck",
140 .clk = &mstp_clks[MSTP110],
141 },
142 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]),
143};
144
145int __init arch_clk_init(void)
146{
147 int i, ret = 0;
148
149 for (i = 0; i < ARRAY_SIZE(clks); i++)
150 ret |= clk_register(clks[i]);
151 for (i = 0; i < ARRAY_SIZE(lookups); i++)
152 clkdev_add(&lookups[i]);
153
154 if (!ret)
155 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
156 &div4_table);
157 if (!ret)
158 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
159
160 return ret;
161}
162
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 370cd47642ef..599630fc4d3b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -12,6 +12,8 @@
12 */ 12 */
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/clkdev.h>
15#include <asm/clock.h> 17#include <asm/clock.h>
16#include <asm/freq.h> 18#include <asm/freq.h>
17#include <asm/io.h> 19#include <asm/io.h>
@@ -22,7 +24,7 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 };
22 24
23static void master_clk_init(struct clk *clk) 25static void master_clk_init(struct clk *clk)
24{ 26{
25 clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07]; 27 clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07];
26} 28}
27 29
28static struct clk_ops sh7763_master_clk_ops = { 30static struct clk_ops sh7763_master_clk_ops = {
@@ -31,7 +33,7 @@ static struct clk_ops sh7763_master_clk_ops = {
31 33
32static unsigned long module_clk_recalc(struct clk *clk) 34static unsigned long module_clk_recalc(struct clk *clk)
33{ 35{
34 int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07); 36 int idx = ((__raw_readl(FRQCR) >> 4) & 0x07);
35 return clk->parent->rate / p0fc_divisors[idx]; 37 return clk->parent->rate / p0fc_divisors[idx];
36} 38}
37 39
@@ -41,7 +43,7 @@ static struct clk_ops sh7763_module_clk_ops = {
41 43
42static unsigned long bus_clk_recalc(struct clk *clk) 44static unsigned long bus_clk_recalc(struct clk *clk)
43{ 45{
44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07); 46 int idx = ((__raw_readl(FRQCR) >> 16) & 0x07);
45 return clk->parent->rate / bfc_divisors[idx]; 47 return clk->parent->rate / bfc_divisors[idx];
46} 48}
47 49
@@ -68,7 +70,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
68 70
69static unsigned long shyway_clk_recalc(struct clk *clk) 71static unsigned long shyway_clk_recalc(struct clk *clk)
70{ 72{
71 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07); 73 int idx = ((__raw_readl(FRQCR) >> 20) & 0x07);
72 return clk->parent->rate / cfc_divisors[idx]; 74 return clk->parent->rate / cfc_divisors[idx];
73} 75}
74 76
@@ -77,7 +79,6 @@ static struct clk_ops sh7763_shyway_clk_ops = {
77}; 79};
78 80
79static struct clk sh7763_shyway_clk = { 81static struct clk sh7763_shyway_clk = {
80 .name = "shyway_clk",
81 .flags = CLK_ENABLE_ON_INIT, 82 .flags = CLK_ENABLE_ON_INIT,
82 .ops = &sh7763_shyway_clk_ops, 83 .ops = &sh7763_shyway_clk_ops,
83}; 84};
@@ -90,6 +91,13 @@ static struct clk *sh7763_onchip_clocks[] = {
90 &sh7763_shyway_clk, 91 &sh7763_shyway_clk,
91}; 92};
92 93
94#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
95
96static struct clk_lookup lookups[] = {
97 /* main clocks */
98 CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk),
99};
100
93int __init arch_clk_init(void) 101int __init arch_clk_init(void)
94{ 102{
95 struct clk *clk; 103 struct clk *clk;
@@ -107,5 +115,7 @@ int __init arch_clk_init(void)
107 115
108 clk_put(clk); 116 clk_put(clk);
109 117
118 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
119
110 return ret; 120 return ret;
111} 121}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
index e0b896769205..9e3354365d40 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
@@ -21,7 +21,7 @@ static int pfc_divisors[] = { 1, 8, 1,10,12,16, 1, 1 };
21 21
22static void master_clk_init(struct clk *clk) 22static void master_clk_init(struct clk *clk)
23{ 23{
24 clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> 28) & 0x000f]; 24 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f];
25} 25}
26 26
27static struct clk_ops sh7770_master_clk_ops = { 27static struct clk_ops sh7770_master_clk_ops = {
@@ -30,7 +30,7 @@ static struct clk_ops sh7770_master_clk_ops = {
30 30
31static unsigned long module_clk_recalc(struct clk *clk) 31static unsigned long module_clk_recalc(struct clk *clk)
32{ 32{
33 int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f); 33 int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f);
34 return clk->parent->rate / pfc_divisors[idx]; 34 return clk->parent->rate / pfc_divisors[idx];
35} 35}
36 36
@@ -40,7 +40,7 @@ static struct clk_ops sh7770_module_clk_ops = {
40 40
41static unsigned long bus_clk_recalc(struct clk *clk) 41static unsigned long bus_clk_recalc(struct clk *clk)
42{ 42{
43 int idx = (ctrl_inl(FRQCR) & 0x000f); 43 int idx = (__raw_readl(FRQCR) & 0x000f);
44 return clk->parent->rate / bfc_divisors[idx]; 44 return clk->parent->rate / bfc_divisors[idx];
45} 45}
46 46
@@ -50,7 +50,7 @@ static struct clk_ops sh7770_bus_clk_ops = {
50 50
51static unsigned long cpu_clk_recalc(struct clk *clk) 51static unsigned long cpu_clk_recalc(struct clk *clk)
52{ 52{
53 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f); 53 int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f);
54 return clk->parent->rate / ifc_divisors[idx]; 54 return clk->parent->rate / ifc_divisors[idx];
55} 55}
56 56
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index a249d823578e..8894926479a6 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -11,6 +11,8 @@
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/clkdev.h>
14#include <asm/clock.h> 16#include <asm/clock.h>
15#include <asm/freq.h> 17#include <asm/freq.h>
16#include <asm/io.h> 18#include <asm/io.h>
@@ -22,7 +24,7 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 6, 1, 1, 1 };
22 24
23static void master_clk_init(struct clk *clk) 25static void master_clk_init(struct clk *clk)
24{ 26{
25 clk->rate *= pfc_divisors[ctrl_inl(FRQCR) & 0x0003]; 27 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003];
26} 28}
27 29
28static struct clk_ops sh7780_master_clk_ops = { 30static struct clk_ops sh7780_master_clk_ops = {
@@ -31,7 +33,7 @@ static struct clk_ops sh7780_master_clk_ops = {
31 33
32static unsigned long module_clk_recalc(struct clk *clk) 34static unsigned long module_clk_recalc(struct clk *clk)
33{ 35{
34 int idx = (ctrl_inl(FRQCR) & 0x0003); 36 int idx = (__raw_readl(FRQCR) & 0x0003);
35 return clk->parent->rate / pfc_divisors[idx]; 37 return clk->parent->rate / pfc_divisors[idx];
36} 38}
37 39
@@ -41,7 +43,7 @@ static struct clk_ops sh7780_module_clk_ops = {
41 43
42static unsigned long bus_clk_recalc(struct clk *clk) 44static unsigned long bus_clk_recalc(struct clk *clk)
43{ 45{
44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007); 46 int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007);
45 return clk->parent->rate / bfc_divisors[idx]; 47 return clk->parent->rate / bfc_divisors[idx];
46} 48}
47 49
@@ -51,7 +53,7 @@ static struct clk_ops sh7780_bus_clk_ops = {
51 53
52static unsigned long cpu_clk_recalc(struct clk *clk) 54static unsigned long cpu_clk_recalc(struct clk *clk)
53{ 55{
54 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001); 56 int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001);
55 return clk->parent->rate / ifc_divisors[idx]; 57 return clk->parent->rate / ifc_divisors[idx];
56} 58}
57 59
@@ -74,7 +76,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
74 76
75static unsigned long shyway_clk_recalc(struct clk *clk) 77static unsigned long shyway_clk_recalc(struct clk *clk)
76{ 78{
77 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007); 79 int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007);
78 return clk->parent->rate / cfc_divisors[idx]; 80 return clk->parent->rate / cfc_divisors[idx];
79} 81}
80 82
@@ -83,7 +85,6 @@ static struct clk_ops sh7780_shyway_clk_ops = {
83}; 85};
84 86
85static struct clk sh7780_shyway_clk = { 87static struct clk sh7780_shyway_clk = {
86 .name = "shyway_clk",
87 .flags = CLK_ENABLE_ON_INIT, 88 .flags = CLK_ENABLE_ON_INIT,
88 .ops = &sh7780_shyway_clk_ops, 89 .ops = &sh7780_shyway_clk_ops,
89}; 90};
@@ -96,6 +97,13 @@ static struct clk *sh7780_onchip_clocks[] = {
96 &sh7780_shyway_clk, 97 &sh7780_shyway_clk,
97}; 98};
98 99
100#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
101
102static struct clk_lookup lookups[] = {
103 /* main clocks */
104 CLKDEV_CON_ID("shyway_clk", &sh7780_shyway_clk),
105};
106
99int __init arch_clk_init(void) 107int __init arch_clk_init(void)
100{ 108{
101 struct clk *clk; 109 struct clk *clk;
@@ -113,5 +121,7 @@ int __init arch_clk_init(void)
113 121
114 clk_put(clk); 122 clk_put(clk);
115 123
124 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
125
116 return ret; 126 return ret;
117} 127}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 73abfbf2f16d..2d960247f3eb 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * SH7785 support for the clock framework 4 * SH7785 support for the clock framework
5 * 5 *
6 * Copyright (C) 2007 - 2009 Paul Mundt 6 * Copyright (C) 2007 - 2010 Paul Mundt
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -14,6 +14,7 @@
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/cpufreq.h> 16#include <linux/cpufreq.h>
17#include <linux/clkdev.h>
17#include <asm/clock.h> 18#include <asm/clock.h>
18#include <asm/freq.h> 19#include <asm/freq.h>
19#include <cpu/sh7785.h> 20#include <cpu/sh7785.h>
@@ -23,8 +24,6 @@
23 * from the platform code. 24 * from the platform code.
24 */ 25 */
25static struct clk extal_clk = { 26static struct clk extal_clk = {
26 .name = "extal",
27 .id = -1,
28 .rate = 33333333, 27 .rate = 33333333,
29}; 28};
30 29
@@ -42,8 +41,6 @@ static struct clk_ops pll_clk_ops = {
42}; 41};
43 42
44static struct clk pll_clk = { 43static struct clk pll_clk = {
45 .name = "pll_clk",
46 .id = -1,
47 .ops = &pll_clk_ops, 44 .ops = &pll_clk_ops,
48 .parent = &extal_clk, 45 .parent = &extal_clk,
49 .flags = CLK_ENABLE_ON_INIT, 46 .flags = CLK_ENABLE_ON_INIT,
@@ -57,56 +54,161 @@ static struct clk *clks[] = {
57static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, 54static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
58 24, 32, 36, 48 }; 55 24, 32, 36, 48 };
59 56
60static struct clk_div_mult_table div4_table = { 57static struct clk_div_mult_table div4_div_mult_table = {
61 .divisors = div2, 58 .divisors = div2,
62 .nr_divisors = ARRAY_SIZE(div2), 59 .nr_divisors = ARRAY_SIZE(div2),
63}; 60};
64 61
62static struct clk_div4_table div4_table = {
63 .div_mult_table = &div4_div_mult_table,
64};
65
65enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, 66enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
66 DIV4_DU, DIV4_P, DIV4_NR }; 67 DIV4_DU, DIV4_P, DIV4_NR };
67 68
68#define DIV4(_str, _bit, _mask, _flags) \ 69#define DIV4(_bit, _mask, _flags) \
69 SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) 70 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
70 71
71struct clk div4_clks[DIV4_NR] = { 72struct clk div4_clks[DIV4_NR] = {
72 [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0), 73 [DIV4_P] = DIV4(0, 0x0f80, 0),
73 [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0), 74 [DIV4_DU] = DIV4(4, 0x0ff0, 0),
74 [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0), 75 [DIV4_GA] = DIV4(8, 0x0030, 0),
75 [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT), 76 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
76 [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT), 77 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
77 [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT), 78 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
78 [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT), 79 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
79 [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT), 80 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
80}; 81};
81 82
82#define MSTPCR0 0xffc80030 83#define MSTPCR0 0xffc80030
83#define MSTPCR1 0xffc80034 84#define MSTPCR1 0xffc80034
84 85
85static struct clk mstp_clks[] = { 86enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
87 MSTP021, MSTP020, MSTP017, MSTP016,
88 MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002,
89 MSTP119, MSTP117, MSTP105, MSTP104, MSTP100,
90 MSTP_NR };
91
92static struct clk mstp_clks[MSTP_NR] = {
86 /* MSTPCR0 */ 93 /* MSTPCR0 */
87 SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), 94 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
88 SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), 95 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
89 SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), 96 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
90 SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), 97 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
91 SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), 98 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
92 SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), 99 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
93 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), 100 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
94 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), 101 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
95 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), 102 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
96 SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), 103 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
97 SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0), 104 [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
98 SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0), 105 [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
99 SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), 106 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
100 SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), 107 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
101 SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0), 108 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
102 SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), 109 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
103 110
104 /* MSTPCR1 */ 111 /* MSTPCR1 */
105 SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0), 112 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
106 SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0), 113 [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
107 SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), 114 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
108 SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), 115 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
109 SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0), 116 [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
117};
118
119#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
120
121static struct clk_lookup lookups[] = {
122 /* main clocks */
123 CLKDEV_CON_ID("extal", &extal_clk),
124 CLKDEV_CON_ID("pll_clk", &pll_clk),
125
126 /* DIV4 clocks */
127 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
128 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
129 CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]),
130 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
131 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
132 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
133 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
134 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
135
136 /* MSTP32 clocks */
137 {
138 /* SCIF5 */
139 .dev_id = "sh-sci.5",
140 .con_id = "sci_fck",
141 .clk = &mstp_clks[MSTP029],
142 }, {
143 /* SCIF4 */
144 .dev_id = "sh-sci.4",
145 .con_id = "sci_fck",
146 .clk = &mstp_clks[MSTP028],
147 }, {
148 /* SCIF3 */
149 .dev_id = "sh-sci.3",
150 .con_id = "sci_fck",
151 .clk = &mstp_clks[MSTP027],
152 }, {
153 /* SCIF2 */
154 .dev_id = "sh-sci.2",
155 .con_id = "sci_fck",
156 .clk = &mstp_clks[MSTP026],
157 }, {
158 /* SCIF1 */
159 .dev_id = "sh-sci.1",
160 .con_id = "sci_fck",
161 .clk = &mstp_clks[MSTP025],
162 }, {
163 /* SCIF0 */
164 .dev_id = "sh-sci.0",
165 .con_id = "sci_fck",
166 .clk = &mstp_clks[MSTP024],
167 },
168 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
169 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
170 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
171 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
172 CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]),
173 CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]),
174 {
175 /* TMU0 */
176 .dev_id = "sh_tmu.0",
177 .con_id = "tmu_fck",
178 .clk = &mstp_clks[MSTP008],
179 }, {
180 /* TMU1 */
181 .dev_id = "sh_tmu.1",
182 .con_id = "tmu_fck",
183 .clk = &mstp_clks[MSTP008],
184 }, {
185 /* TMU2 */
186 .dev_id = "sh_tmu.2",
187 .con_id = "tmu_fck",
188 .clk = &mstp_clks[MSTP008],
189 }, {
190 /* TMU3 */
191 .dev_id = "sh_tmu.3",
192 .con_id = "tmu_fck",
193 .clk = &mstp_clks[MSTP009],
194 }, {
195 /* TMU4 */
196 .dev_id = "sh_tmu.4",
197 .con_id = "tmu_fck",
198 .clk = &mstp_clks[MSTP009],
199 }, {
200 /* TMU5 */
201 .dev_id = "sh_tmu.5",
202 .con_id = "tmu_fck",
203 .clk = &mstp_clks[MSTP009],
204 },
205 CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]),
206 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
207 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
208 CLKDEV_CON_ID("ubc_fck", &mstp_clks[MSTP117]),
209 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
210 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
211 CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]),
110}; 212};
111 213
112int __init arch_clk_init(void) 214int __init arch_clk_init(void)
@@ -115,12 +217,14 @@ int __init arch_clk_init(void)
115 217
116 for (i = 0; i < ARRAY_SIZE(clks); i++) 218 for (i = 0; i < ARRAY_SIZE(clks); i++)
117 ret |= clk_register(clks[i]); 219 ret |= clk_register(clks[i]);
220 for (i = 0; i < ARRAY_SIZE(lookups); i++)
221 clkdev_add(&lookups[i]);
118 222
119 if (!ret) 223 if (!ret)
120 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), 224 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
121 &div4_table); 225 &div4_table);
122 if (!ret) 226 if (!ret)
123 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 227 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
124 228
125 return ret; 229 return ret;
126} 230}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index a0e8869071ac..42e403be9076 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -3,11 +3,7 @@
3 * 3 *
4 * SH7786 support for the clock framework 4 * SH7786 support for the clock framework
5 * 5 *
6 * Copyright (C) 2008, 2009 Renesas Solutions Corp. 6 * Copyright (C) 2010 Paul Mundt
7 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 *
9 * Based on SH7785
10 * Copyright (C) 2007 Paul Mundt
11 * 7 *
12 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -15,127 +11,263 @@
15 */ 11 */
16#include <linux/init.h> 12#include <linux/init.h>
17#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/clkdev.h>
18#include <asm/clock.h> 17#include <asm/clock.h>
19#include <asm/freq.h> 18#include <asm/freq.h>
20#include <asm/io.h>
21 19
22static int ifc_divisors[] = { 1, 2, 4, 1 }; 20/*
23static int sfc_divisors[] = { 1, 1, 4, 1 }; 21 * Default rate for the root input clock, reset this with clk_set_rate()
24static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1, 22 * from the platform code.
25 24, 32, 1, 1, 1, 1, 1, 1 }; 23 */
26static int mfc_divisors[] = { 1, 1, 4, 1 }; 24static struct clk extal_clk = {
27static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1, 25 .rate = 33333333,
28 24, 32, 1, 48, 1, 1, 1, 1 }; 26};
29 27
30static void master_clk_init(struct clk *clk) 28static unsigned long pll_recalc(struct clk *clk)
31{ 29{
32 clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f]; 30 int multiplier;
33}
34 31
35static struct clk_ops sh7786_master_clk_ops = { 32 /*
36 .init = master_clk_init, 33 * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
37}; 34 * while modes 3, 4, and 5 use an x32.
35 */
36 multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
38 37
39static unsigned long module_clk_recalc(struct clk *clk) 38 return clk->parent->rate * multiplier;
40{
41 int idx = (ctrl_inl(FRQMR1) & 0x000f);
42 return clk->parent->rate / pfc_divisors[idx];
43} 39}
44 40
45static struct clk_ops sh7786_module_clk_ops = { 41static struct clk_ops pll_clk_ops = {
46 .recalc = module_clk_recalc, 42 .recalc = pll_recalc,
47}; 43};
48 44
49static unsigned long bus_clk_recalc(struct clk *clk) 45static struct clk pll_clk = {
50{ 46 .ops = &pll_clk_ops,
51 int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f); 47 .parent = &extal_clk,
52 return clk->parent->rate / bfc_divisors[idx]; 48 .flags = CLK_ENABLE_ON_INIT,
53} 49};
54 50
55static struct clk_ops sh7786_bus_clk_ops = { 51static struct clk *clks[] = {
56 .recalc = bus_clk_recalc, 52 &extal_clk,
53 &pll_clk,
57}; 54};
58 55
59static unsigned long cpu_clk_recalc(struct clk *clk) 56static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
60{ 57 24, 32, 36, 48 };
61 int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
62 return clk->parent->rate / ifc_divisors[idx];
63}
64 58
65static struct clk_ops sh7786_cpu_clk_ops = { 59static struct clk_div_mult_table div4_div_mult_table = {
66 .recalc = cpu_clk_recalc, 60 .divisors = div2,
61 .nr_divisors = ARRAY_SIZE(div2),
67}; 62};
68 63
69static struct clk_ops *sh7786_clk_ops[] = { 64static struct clk_div4_table div4_table = {
70 &sh7786_master_clk_ops, 65 .div_mult_table = &div4_div_mult_table,
71 &sh7786_module_clk_ops,
72 &sh7786_bus_clk_ops,
73 &sh7786_cpu_clk_ops,
74}; 66};
75 67
76void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 68enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
77{
78 if (idx < ARRAY_SIZE(sh7786_clk_ops))
79 *ops = sh7786_clk_ops[idx];
80}
81 69
82static unsigned long shyway_clk_recalc(struct clk *clk) 70#define DIV4(_bit, _mask, _flags) \
83{ 71 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
84 int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
85 return clk->parent->rate / sfc_divisors[idx];
86}
87 72
88static struct clk_ops sh7786_shyway_clk_ops = { 73struct clk div4_clks[DIV4_NR] = {
89 .recalc = shyway_clk_recalc, 74 [DIV4_P] = DIV4(0, 0x0b40, 0),
75 [DIV4_DU] = DIV4(4, 0x0010, 0),
76 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
77 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
78 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
79 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
90}; 80};
91 81
92static struct clk sh7786_shyway_clk = { 82#define MSTPCR0 0xffc40030
93 .name = "shyway_clk", 83#define MSTPCR1 0xffc40034
94 .flags = CLK_ENABLE_ON_INIT,
95 .ops = &sh7786_shyway_clk_ops,
96};
97 84
98static unsigned long ddr_clk_recalc(struct clk *clk) 85enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
99{ 86 MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
100 int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003); 87 MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
101 return clk->parent->rate / mfc_divisors[idx]; 88 MSTP005, MSTP004, MSTP002,
102} 89 MSTP112, MSTP110, MSTP109, MSTP108,
90 MSTP105, MSTP104, MSTP103, MSTP102,
91 MSTP_NR };
103 92
104static struct clk_ops sh7786_ddr_clk_ops = { 93static struct clk mstp_clks[MSTP_NR] = {
105 .recalc = ddr_clk_recalc, 94 /* MSTPCR0 */
106}; 95 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
96 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
97 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
98 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
99 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
100 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
101 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
102 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
103 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
104 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
105 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
106 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
107 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
108 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
109 [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
110 [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
111 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
112 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
113 [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
114 [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
115 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
107 116
108static struct clk sh7786_ddr_clk = { 117 /* MSTPCR1 */
109 .name = "ddr_clk", 118 [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
110 .flags = CLK_ENABLE_ON_INIT, 119 [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
111 .ops = &sh7786_ddr_clk_ops, 120 [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
121 [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
122 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
123 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
124 [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
125 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
112}; 126};
113 127
114/* 128#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
115 * Additional SH7786-specific on-chip clocks that aren't already part of the 129
116 * clock framework 130static struct clk_lookup lookups[] = {
117 */ 131 /* main clocks */
118static struct clk *sh7786_onchip_clocks[] = { 132 CLKDEV_CON_ID("extal", &extal_clk),
119 &sh7786_shyway_clk, 133 CLKDEV_CON_ID("pll_clk", &pll_clk),
120 &sh7786_ddr_clk, 134
135 /* DIV4 clocks */
136 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
137 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
138 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
139 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
140 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
141 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
142
143 /* MSTP32 clocks */
144 {
145 /* SCIF5 */
146 .dev_id = "sh-sci.5",
147 .con_id = "sci_fck",
148 .clk = &mstp_clks[MSTP029],
149 }, {
150 /* SCIF4 */
151 .dev_id = "sh-sci.4",
152 .con_id = "sci_fck",
153 .clk = &mstp_clks[MSTP028],
154 }, {
155 /* SCIF3 */
156 .dev_id = "sh-sci.3",
157 .con_id = "sci_fck",
158 .clk = &mstp_clks[MSTP027],
159 }, {
160 /* SCIF2 */
161 .dev_id = "sh-sci.2",
162 .con_id = "sci_fck",
163 .clk = &mstp_clks[MSTP026],
164 }, {
165 /* SCIF1 */
166 .dev_id = "sh-sci.1",
167 .con_id = "sci_fck",
168 .clk = &mstp_clks[MSTP025],
169 }, {
170 /* SCIF0 */
171 .dev_id = "sh-sci.0",
172 .con_id = "sci_fck",
173 .clk = &mstp_clks[MSTP024],
174 },
175 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
176 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
177 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
178 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
179 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
180 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
181 CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
182 CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
183 {
184 /* TMU0 */
185 .dev_id = "sh_tmu.0",
186 .con_id = "tmu_fck",
187 .clk = &mstp_clks[MSTP008],
188 }, {
189 /* TMU1 */
190 .dev_id = "sh_tmu.1",
191 .con_id = "tmu_fck",
192 .clk = &mstp_clks[MSTP008],
193 }, {
194 /* TMU2 */
195 .dev_id = "sh_tmu.2",
196 .con_id = "tmu_fck",
197 .clk = &mstp_clks[MSTP008],
198 }, {
199 /* TMU3 */
200 .dev_id = "sh_tmu.3",
201 .con_id = "tmu_fck",
202 .clk = &mstp_clks[MSTP009],
203 }, {
204 /* TMU4 */
205 .dev_id = "sh_tmu.4",
206 .con_id = "tmu_fck",
207 .clk = &mstp_clks[MSTP009],
208 }, {
209 /* TMU5 */
210 .dev_id = "sh_tmu.5",
211 .con_id = "tmu_fck",
212 .clk = &mstp_clks[MSTP009],
213 }, {
214 /* TMU6 */
215 .dev_id = "sh_tmu.6",
216 .con_id = "tmu_fck",
217 .clk = &mstp_clks[MSTP010],
218 }, {
219 /* TMU7 */
220 .dev_id = "sh_tmu.7",
221 .con_id = "tmu_fck",
222 .clk = &mstp_clks[MSTP010],
223 }, {
224 /* TMU8 */
225 .dev_id = "sh_tmu.8",
226 .con_id = "tmu_fck",
227 .clk = &mstp_clks[MSTP010],
228 }, {
229 /* TMU9 */
230 .dev_id = "sh_tmu.9",
231 .con_id = "tmu_fck",
232 .clk = &mstp_clks[MSTP011],
233 }, {
234 /* TMU10 */
235 .dev_id = "sh_tmu.10",
236 .con_id = "tmu_fck",
237 .clk = &mstp_clks[MSTP011],
238 }, {
239 /* TMU11 */
240 .dev_id = "sh_tmu.11",
241 .con_id = "tmu_fck",
242 .clk = &mstp_clks[MSTP011],
243 },
244 CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
245 CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
246 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
247 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
248 CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
249 CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
250 CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
251 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
252 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
253 CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
254 CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
121}; 255};
122 256
123int __init arch_clk_init(void) 257int __init arch_clk_init(void)
124{ 258{
125 struct clk *clk;
126 int i, ret = 0; 259 int i, ret = 0;
127 260
128 cpg_clk_init(); 261 for (i = 0; i < ARRAY_SIZE(clks); i++)
129 262 ret |= clk_register(clks[i]);
130 clk = clk_get(NULL, "master_clk"); 263 for (i = 0; i < ARRAY_SIZE(lookups); i++)
131 for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) { 264 clkdev_add(&lookups[i]);
132 struct clk *clkp = sh7786_onchip_clocks[i];
133
134 clkp->parent = clk;
135 ret |= clk_register(clkp);
136 }
137 265
138 clk_put(clk); 266 if (!ret)
267 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
268 &div4_table);
269 if (!ret)
270 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
139 271
140 return ret; 272 return ret;
141} 273}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index 23c27d32d982..1afdb93b8ccb 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -5,7 +5,7 @@
5 * 5 *
6 * Copyright (C) 2006-2007 Renesas Technology Corp. 6 * Copyright (C) 2006-2007 Renesas Technology Corp.
7 * Copyright (C) 2006-2007 Renesas Solutions Corp. 7 * Copyright (C) 2006-2007 Renesas Solutions Corp.
8 * Copyright (C) 2006-2007 Paul Mundt 8 * Copyright (C) 2006-2010 Paul Mundt
9 * 9 *
10 * This file is subject to the terms and conditions of the GNU General Public 10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
@@ -13,116 +13,184 @@
13 */ 13 */
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/io.h>
17#include <linux/clkdev.h>
16#include <asm/clock.h> 18#include <asm/clock.h>
17#include <asm/freq.h> 19#include <asm/freq.h>
18#include <asm/io.h>
19
20static int ifc_divisors[] = { 1, 2, 4 ,6 };
21static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
22static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 };
23static int cfc_divisors[] = { 1, 1, 4, 6 };
24
25#define IFC_POS 28
26#define IFC_MSK 0x0003
27#define BFC_MSK 0x000f
28#define PFC_MSK 0x000f
29#define CFC_MSK 0x0003
30#define BFC_POS 16
31#define PFC_POS 0
32#define CFC_POS 20
33
34static void master_clk_init(struct clk *clk)
35{
36 clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK];
37}
38 20
39static struct clk_ops shx3_master_clk_ops = { 21/*
40 .init = master_clk_init, 22 * Default rate for the root input clock, reset this with clk_set_rate()
23 * from the platform code.
24 */
25static struct clk extal_clk = {
26 .rate = 16666666,
41}; 27};
42 28
43static unsigned long module_clk_recalc(struct clk *clk) 29static unsigned long pll_recalc(struct clk *clk)
44{ 30{
45 int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK); 31 /* PLL1 has a fixed x72 multiplier. */
46 return clk->parent->rate / pfc_divisors[idx]; 32 return clk->parent->rate * 72;
47} 33}
48 34
49static struct clk_ops shx3_module_clk_ops = { 35static struct clk_ops pll_clk_ops = {
50 .recalc = module_clk_recalc, 36 .recalc = pll_recalc,
51}; 37};
52 38
53static unsigned long bus_clk_recalc(struct clk *clk) 39static struct clk pll_clk = {
54{ 40 .ops = &pll_clk_ops,
55 int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK); 41 .parent = &extal_clk,
56 return clk->parent->rate / bfc_divisors[idx]; 42 .flags = CLK_ENABLE_ON_INIT,
57} 43};
58 44
59static struct clk_ops shx3_bus_clk_ops = { 45static struct clk *clks[] = {
60 .recalc = bus_clk_recalc, 46 &extal_clk,
47 &pll_clk,
61}; 48};
62 49
63static unsigned long cpu_clk_recalc(struct clk *clk) 50static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
64{ 51 24, 32, 36, 48 };
65 int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK);
66 return clk->parent->rate / ifc_divisors[idx];
67}
68 52
69static struct clk_ops shx3_cpu_clk_ops = { 53static struct clk_div_mult_table div4_div_mult_table = {
70 .recalc = cpu_clk_recalc, 54 .divisors = div2,
55 .nr_divisors = ARRAY_SIZE(div2),
71}; 56};
72 57
73static struct clk_ops *shx3_clk_ops[] = { 58static struct clk_div4_table div4_table = {
74 &shx3_master_clk_ops, 59 .div_mult_table = &div4_div_mult_table,
75 &shx3_module_clk_ops,
76 &shx3_bus_clk_ops,
77 &shx3_cpu_clk_ops,
78}; 60};
79 61
80void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 62enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR };
81{
82 if (idx < ARRAY_SIZE(shx3_clk_ops))
83 *ops = shx3_clk_ops[idx];
84}
85 63
86static unsigned long shyway_clk_recalc(struct clk *clk) 64#define DIV4(_bit, _mask, _flags) \
87{ 65 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
88 int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK);
89 return clk->parent->rate / cfc_divisors[idx];
90}
91 66
92static struct clk_ops shx3_shyway_clk_ops = { 67struct clk div4_clks[DIV4_NR] = {
93 .recalc = shyway_clk_recalc, 68 [DIV4_P] = DIV4(0, 0x0f80, 0),
69 [DIV4_SHA] = DIV4(4, 0x0ff0, 0),
70 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
71 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
72 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
73 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
94}; 74};
95 75
96static struct clk shx3_shyway_clk = { 76#define MSTPCR0 0xffc00030
97 .name = "shyway_clk", 77#define MSTPCR1 0xffc00034
98 .flags = CLK_ENABLE_ON_INIT, 78
99 .ops = &shx3_shyway_clk_ops, 79enum { MSTP027, MSTP026, MSTP025, MSTP024,
80 MSTP009, MSTP008, MSTP003, MSTP002,
81 MSTP001, MSTP000, MSTP119, MSTP105,
82 MSTP104, MSTP_NR };
83
84static struct clk mstp_clks[MSTP_NR] = {
85 /* MSTPCR0 */
86 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
87 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
88 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
89 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
90 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
91 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
92 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
93 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
94 [MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
95 [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
96
97 /* MSTPCR1 */
98 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
99 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
100 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
100}; 101};
101 102
102/* 103#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
103 * Additional SHx3-specific on-chip clocks that aren't already part of the 104
104 * clock framework 105static struct clk_lookup lookups[] = {
105 */ 106 /* main clocks */
106static struct clk *shx3_onchip_clocks[] = { 107 CLKDEV_CON_ID("extal", &extal_clk),
107 &shx3_shyway_clk, 108 CLKDEV_CON_ID("pll_clk", &pll_clk),
109
110 /* DIV4 clocks */
111 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
112 CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]),
113 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
114 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
115 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
116 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
117
118 /* MSTP32 clocks */
119 {
120 /* SCIF3 */
121 .dev_id = "sh-sci.3",
122 .con_id = "sci_fck",
123 .clk = &mstp_clks[MSTP027],
124 }, {
125 /* SCIF2 */
126 .dev_id = "sh-sci.2",
127 .con_id = "sci_fck",
128 .clk = &mstp_clks[MSTP026],
129 }, {
130 /* SCIF1 */
131 .dev_id = "sh-sci.1",
132 .con_id = "sci_fck",
133 .clk = &mstp_clks[MSTP025],
134 }, {
135 /* SCIF0 */
136 .dev_id = "sh-sci.0",
137 .con_id = "sci_fck",
138 .clk = &mstp_clks[MSTP024],
139 },
140 CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
141 CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
142 CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),
143 CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),
144 {
145 /* TMU0 */
146 .dev_id = "sh_tmu.0",
147 .con_id = "tmu_fck",
148 .clk = &mstp_clks[MSTP008],
149 }, {
150 /* TMU1 */
151 .dev_id = "sh_tmu.1",
152 .con_id = "tmu_fck",
153 .clk = &mstp_clks[MSTP008],
154 }, {
155 /* TMU2 */
156 .dev_id = "sh_tmu.2",
157 .con_id = "tmu_fck",
158 .clk = &mstp_clks[MSTP008],
159 }, {
160 /* TMU3 */
161 .dev_id = "sh_tmu.3",
162 .con_id = "tmu_fck",
163 .clk = &mstp_clks[MSTP009],
164 }, {
165 /* TMU4 */
166 .dev_id = "sh_tmu.4",
167 .con_id = "tmu_fck",
168 .clk = &mstp_clks[MSTP009],
169 }, {
170 /* TMU5 */
171 .dev_id = "sh_tmu.5",
172 .con_id = "tmu_fck",
173 .clk = &mstp_clks[MSTP009],
174 },
175 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
176 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
177 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
108}; 178};
109 179
110int __init arch_clk_init(void) 180int __init arch_clk_init(void)
111{ 181{
112 struct clk *clk;
113 int i, ret = 0; 182 int i, ret = 0;
114 183
115 cpg_clk_init(); 184 for (i = 0; i < ARRAY_SIZE(clks); i++)
116 185 ret |= clk_register(clks[i]);
117 clk = clk_get(NULL, "master_clk"); 186 for (i = 0; i < ARRAY_SIZE(lookups); i++)
118 for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) { 187 clkdev_add(&lookups[i]);
119 struct clk *clkp = shx3_onchip_clocks[i];
120
121 clkp->parent = clk;
122 ret |= clk_register(clkp);
123 }
124 188
125 clk_put(clk); 189 if (!ret)
190 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
191 &div4_table);
192 if (!ret)
193 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
126 194
127 return ret; 195 return ret;
128} 196}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
new file mode 100644
index 000000000000..a288b5d92341
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
@@ -0,0 +1,106 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
3 *
4 * SH7722 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7722.h>
27
28/* SH7722 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7722 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7722_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7722_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_URAM] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_XYMEM] = HWBLK(MSTPCR0, 26, CORE_AREA),
48 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
49 [HWBLK_DMAC] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
50 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
51 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
52 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
53 [HWBLK_TMU] = HWBLK(MSTPCR0, 15, CORE_AREA),
54 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
55 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
56 [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
57 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 7, CORE_AREA),
58 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 6, CORE_AREA),
59 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 5, CORE_AREA),
60 [HWBLK_SIO] = HWBLK(MSTPCR0, 3, CORE_AREA),
61 [HWBLK_SIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
62 [HWBLK_SIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
63
64 [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
65 [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
66
67 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
68 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
69 [HWBLK_SDHI] = HWBLK(MSTPCR2, 18, CORE_AREA),
70 [HWBLK_SIM] = HWBLK(MSTPCR2, 16, CORE_AREA),
71 [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
72 [HWBLK_TSIF] = HWBLK(MSTPCR2, 13, SUB_AREA),
73 [HWBLK_USBF] = HWBLK(MSTPCR2, 11, CORE_AREA),
74 [HWBLK_2DG] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
75 [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
76 [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
77 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
78 [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
79 [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
80 [HWBLK_VEU] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
81 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
82 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
83};
84
85static struct hwblk_info sh7722_hwblk_info = {
86 .areas = sh7722_hwblk_area,
87 .nr_areas = ARRAY_SIZE(sh7722_hwblk_area),
88 .hwblks = sh7722_hwblk,
89 .nr_hwblks = ARRAY_SIZE(sh7722_hwblk),
90};
91
92int arch_hwblk_sleep_mode(void)
93{
94 if (!sh7722_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
95 return SUSP_SH_STANDBY | SUSP_SH_SF;
96
97 if (!sh7722_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
98 return SUSP_SH_SLEEP | SUSP_SH_SF;
99
100 return SUSP_SH_SLEEP;
101}
102
103int __init arch_hwblk_init(void)
104{
105 return hwblk_register(&sh7722_hwblk_info);
106}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
new file mode 100644
index 000000000000..a7f4684d2032
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
@@ -0,0 +1,117 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
3 *
4 * SH7723 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7723.h>
27
28/* SH7723 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7723 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7723_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7723_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_L2C] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
49 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
50 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
51 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
52 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
53 [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
54 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
55 [HWBLK_SUBC] = HWBLK(MSTPCR0, 16, CORE_AREA),
56 [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59 [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60 [HWBLK_TMU1] = HWBLK(MSTPCR0, 11, CORE_AREA),
61 [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
62 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
63 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
64 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
65 [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
66 [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
67 [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
68 [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
69 [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
70 [HWBLK_MERAM] = HWBLK(MSTPCR0, 0, CORE_AREA),
71
72 [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
74
75 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
76 [HWBLK_ADC] = HWBLK(MSTPCR2, 27, CORE_AREA),
77 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
78 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
79 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
80 [HWBLK_ICB] = HWBLK(MSTPCR2, 21, CORE_AREA_BM),
81 [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
82 [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
83 [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
84 [HWBLK_USB] = HWBLK(MSTPCR2, 11, CORE_AREA),
85 [HWBLK_2DG] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
86 [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
87 [HWBLK_VEU2H1] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
88 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
89 [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
90 [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
91 [HWBLK_VEU2H0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
92 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
93 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
94};
95
96static struct hwblk_info sh7723_hwblk_info = {
97 .areas = sh7723_hwblk_area,
98 .nr_areas = ARRAY_SIZE(sh7723_hwblk_area),
99 .hwblks = sh7723_hwblk,
100 .nr_hwblks = ARRAY_SIZE(sh7723_hwblk),
101};
102
103int arch_hwblk_sleep_mode(void)
104{
105 if (!sh7723_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
106 return SUSP_SH_STANDBY | SUSP_SH_SF;
107
108 if (!sh7723_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
109 return SUSP_SH_SLEEP | SUSP_SH_SF;
110
111 return SUSP_SH_SLEEP;
112}
113
114int __init arch_hwblk_init(void)
115{
116 return hwblk_register(&sh7723_hwblk_info);
117}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
new file mode 100644
index 000000000000..1613ad6013c3
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
@@ -0,0 +1,121 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
3 *
4 * SH7724 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7724.h>
27
28/* SH7724 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7724 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7724_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7724_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_RSMEM] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48 [HWBLK_L2C] = HWBLK(MSTPCR0, 26, CORE_AREA),
49 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
50 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
51 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
52 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
53 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
54 [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
55 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
56 [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59 [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60 [HWBLK_TMU1] = HWBLK(MSTPCR0, 10, CORE_AREA),
61 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
62 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
63 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
64 [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
65 [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
66 [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
67 [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
68 [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
69
70 [HWBLK_KEYSC] = HWBLK(MSTPCR1, 12, SUB_AREA),
71 [HWBLK_RTC] = HWBLK(MSTPCR1, 11, SUB_AREA),
72 [HWBLK_IIC0] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_IIC1] = HWBLK(MSTPCR1, 8, CORE_AREA),
74
75 [HWBLK_MMC] = HWBLK(MSTPCR2, 29, CORE_AREA),
76 [HWBLK_ETHER] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
77 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 26, CORE_AREA_BM),
78 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
79 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
80 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
81 [HWBLK_USB1] = HWBLK(MSTPCR2, 21, CORE_AREA),
82 [HWBLK_USB0] = HWBLK(MSTPCR2, 20, CORE_AREA),
83 [HWBLK_2DG] = HWBLK(MSTPCR2, 19, CORE_AREA_BM),
84 [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
85 [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
86 [HWBLK_VEU1] = HWBLK(MSTPCR2, 15, CORE_AREA_BM),
87 [HWBLK_CEU1] = HWBLK(MSTPCR2, 13, CORE_AREA_BM),
88 [HWBLK_BEU1] = HWBLK(MSTPCR2, 12, CORE_AREA_BM),
89 [HWBLK_2DDMAC] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
90 [HWBLK_SPU] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
91 [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
92 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
93 [HWBLK_BEU0] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
94 [HWBLK_CEU0] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
95 [HWBLK_VEU0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
96 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
97 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
98};
99
100static struct hwblk_info sh7724_hwblk_info = {
101 .areas = sh7724_hwblk_area,
102 .nr_areas = ARRAY_SIZE(sh7724_hwblk_area),
103 .hwblks = sh7724_hwblk,
104 .nr_hwblks = ARRAY_SIZE(sh7724_hwblk),
105};
106
107int arch_hwblk_sleep_mode(void)
108{
109 if (!sh7724_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
110 return SUSP_SH_STANDBY | SUSP_SH_SF;
111
112 if (!sh7724_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
113 return SUSP_SH_SLEEP | SUSP_SH_SF;
114
115 return SUSP_SH_SLEEP;
116}
117
118int __init arch_hwblk_init(void)
119{
120 return hwblk_register(&sh7724_hwblk_info);
121}
diff --git a/arch/sh/kernel/cpu/sh4a/intc-shx3.c b/arch/sh/kernel/cpu/sh4a/intc-shx3.c
new file mode 100644
index 000000000000..78c971486b4e
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/intc-shx3.c
@@ -0,0 +1,34 @@
1/*
2 * Shared support for SH-X3 interrupt controllers.
3 *
4 * Copyright (C) 2009 - 2010 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/irq.h>
11#include <linux/io.h>
12#include <linux/init.h>
13
14#define INTACK 0xfe4100b8
15#define INTACKCLR 0xfe4100bc
16#define INTC_USERIMASK 0xfe411000
17
18#ifdef CONFIG_INTC_BALANCING
19unsigned int irq_lookup(unsigned int irq)
20{
21 return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
22}
23
24void irq_finish(unsigned int irq)
25{
26 __raw_writel(irq2evt(irq), INTACKCLR);
27}
28#endif
29
30static int __init shx3_irq_setup(void)
31{
32 return register_intc_userimask(INTC_USERIMASK);
33}
34arch_initcall(shx3_irq_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c
new file mode 100644
index 000000000000..17e6bebfede0
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/perf_event.c
@@ -0,0 +1,287 @@
1/*
2 * Performance events support for SH-4A performance counters
3 *
4 * Copyright (C) 2009, 2010 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/perf_event.h>
15#include <asm/processor.h>
16
17#define PPC_CCBR(idx) (0xff200800 + (sizeof(u32) * idx))
18#define PPC_PMCTR(idx) (0xfc100000 + (sizeof(u32) * idx))
19
20#define CCBR_CIT_MASK (0x7ff << 6)
21#define CCBR_DUC (1 << 3)
22#define CCBR_CMDS (1 << 1)
23#define CCBR_PPCE (1 << 0)
24
25#ifdef CONFIG_CPU_SHX3
26/*
27 * The PMCAT location for SH-X3 CPUs was quietly moved, while the CCBR
28 * and PMCTR locations remains tentatively constant. This change remains
29 * wholly undocumented, and was simply found through trial and error.
30 *
31 * Early cuts of SH-X3 still appear to use the SH-X/SH-X2 locations, and
32 * it's unclear when this ceased to be the case. For now we always use
33 * the new location (if future parts keep up with this trend then
34 * scanning for them at runtime also remains a viable option.)
35 *
36 * The gap in the register space also suggests that there are other
37 * undocumented counters, so this will need to be revisited at a later
38 * point in time.
39 */
40#define PPC_PMCAT 0xfc100240
41#else
42#define PPC_PMCAT 0xfc100080
43#endif
44
45#define PMCAT_OVF3 (1 << 27)
46#define PMCAT_CNN3 (1 << 26)
47#define PMCAT_CLR3 (1 << 25)
48#define PMCAT_OVF2 (1 << 19)
49#define PMCAT_CLR2 (1 << 17)
50#define PMCAT_OVF1 (1 << 11)
51#define PMCAT_CNN1 (1 << 10)
52#define PMCAT_CLR1 (1 << 9)
53#define PMCAT_OVF0 (1 << 3)
54#define PMCAT_CLR0 (1 << 1)
55
56static struct sh_pmu sh4a_pmu;
57
58/*
59 * Supported raw event codes:
60 *
61 * Event Code Description
62 * ---------- -----------
63 *
64 * 0x0000 number of elapsed cycles
65 * 0x0200 number of elapsed cycles in privileged mode
66 * 0x0280 number of elapsed cycles while SR.BL is asserted
67 * 0x0202 instruction execution
68 * 0x0203 instruction execution in parallel
69 * 0x0204 number of unconditional branches
70 * 0x0208 number of exceptions
71 * 0x0209 number of interrupts
72 * 0x0220 UTLB miss caused by instruction fetch
73 * 0x0222 UTLB miss caused by operand access
74 * 0x02a0 number of ITLB misses
75 * 0x0028 number of accesses to instruction memories
76 * 0x0029 number of accesses to instruction cache
77 * 0x002a instruction cache miss
78 * 0x022e number of access to instruction X/Y memory
79 * 0x0030 number of reads to operand memories
80 * 0x0038 number of writes to operand memories
81 * 0x0031 number of operand cache read accesses
82 * 0x0039 number of operand cache write accesses
83 * 0x0032 operand cache read miss
84 * 0x003a operand cache write miss
85 * 0x0236 number of reads to operand X/Y memory
86 * 0x023e number of writes to operand X/Y memory
87 * 0x0237 number of reads to operand U memory
88 * 0x023f number of writes to operand U memory
89 * 0x0337 number of U memory read buffer misses
90 * 0x02b4 number of wait cycles due to operand read access
91 * 0x02bc number of wait cycles due to operand write access
92 * 0x0033 number of wait cycles due to operand cache read miss
93 * 0x003b number of wait cycles due to operand cache write miss
94 */
95
96/*
97 * Special reserved bits used by hardware emulators, read values will
98 * vary, but writes must always be 0.
99 */
100#define PMCAT_EMU_CLR_MASK ((1 << 24) | (1 << 16) | (1 << 8) | (1 << 0))
101
102static const int sh4a_general_events[] = {
103 [PERF_COUNT_HW_CPU_CYCLES] = 0x0000,
104 [PERF_COUNT_HW_INSTRUCTIONS] = 0x0202,
105 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0029, /* I-cache */
106 [PERF_COUNT_HW_CACHE_MISSES] = 0x002a, /* I-cache */
107 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0204,
108 [PERF_COUNT_HW_BRANCH_MISSES] = -1,
109 [PERF_COUNT_HW_BUS_CYCLES] = -1,
110};
111
112#define C(x) PERF_COUNT_HW_CACHE_##x
113
114static const int sh4a_cache_events
115 [PERF_COUNT_HW_CACHE_MAX]
116 [PERF_COUNT_HW_CACHE_OP_MAX]
117 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
118{
119 [ C(L1D) ] = {
120 [ C(OP_READ) ] = {
121 [ C(RESULT_ACCESS) ] = 0x0031,
122 [ C(RESULT_MISS) ] = 0x0032,
123 },
124 [ C(OP_WRITE) ] = {
125 [ C(RESULT_ACCESS) ] = 0x0039,
126 [ C(RESULT_MISS) ] = 0x003a,
127 },
128 [ C(OP_PREFETCH) ] = {
129 [ C(RESULT_ACCESS) ] = 0,
130 [ C(RESULT_MISS) ] = 0,
131 },
132 },
133
134 [ C(L1I) ] = {
135 [ C(OP_READ) ] = {
136 [ C(RESULT_ACCESS) ] = 0x0029,
137 [ C(RESULT_MISS) ] = 0x002a,
138 },
139 [ C(OP_WRITE) ] = {
140 [ C(RESULT_ACCESS) ] = -1,
141 [ C(RESULT_MISS) ] = -1,
142 },
143 [ C(OP_PREFETCH) ] = {
144 [ C(RESULT_ACCESS) ] = 0,
145 [ C(RESULT_MISS) ] = 0,
146 },
147 },
148
149 [ C(LL) ] = {
150 [ C(OP_READ) ] = {
151 [ C(RESULT_ACCESS) ] = 0x0030,
152 [ C(RESULT_MISS) ] = 0,
153 },
154 [ C(OP_WRITE) ] = {
155 [ C(RESULT_ACCESS) ] = 0x0038,
156 [ C(RESULT_MISS) ] = 0,
157 },
158 [ C(OP_PREFETCH) ] = {
159 [ C(RESULT_ACCESS) ] = 0,
160 [ C(RESULT_MISS) ] = 0,
161 },
162 },
163
164 [ C(DTLB) ] = {
165 [ C(OP_READ) ] = {
166 [ C(RESULT_ACCESS) ] = 0x0222,
167 [ C(RESULT_MISS) ] = 0x0220,
168 },
169 [ C(OP_WRITE) ] = {
170 [ C(RESULT_ACCESS) ] = 0,
171 [ C(RESULT_MISS) ] = 0,
172 },
173 [ C(OP_PREFETCH) ] = {
174 [ C(RESULT_ACCESS) ] = 0,
175 [ C(RESULT_MISS) ] = 0,
176 },
177 },
178
179 [ C(ITLB) ] = {
180 [ C(OP_READ) ] = {
181 [ C(RESULT_ACCESS) ] = 0,
182 [ C(RESULT_MISS) ] = 0x02a0,
183 },
184 [ C(OP_WRITE) ] = {
185 [ C(RESULT_ACCESS) ] = -1,
186 [ C(RESULT_MISS) ] = -1,
187 },
188 [ C(OP_PREFETCH) ] = {
189 [ C(RESULT_ACCESS) ] = -1,
190 [ C(RESULT_MISS) ] = -1,
191 },
192 },
193
194 [ C(BPU) ] = {
195 [ C(OP_READ) ] = {
196 [ C(RESULT_ACCESS) ] = -1,
197 [ C(RESULT_MISS) ] = -1,
198 },
199 [ C(OP_WRITE) ] = {
200 [ C(RESULT_ACCESS) ] = -1,
201 [ C(RESULT_MISS) ] = -1,
202 },
203 [ C(OP_PREFETCH) ] = {
204 [ C(RESULT_ACCESS) ] = -1,
205 [ C(RESULT_MISS) ] = -1,
206 },
207 },
208};
209
210static int sh4a_event_map(int event)
211{
212 return sh4a_general_events[event];
213}
214
215static u64 sh4a_pmu_read(int idx)
216{
217 return __raw_readl(PPC_PMCTR(idx));
218}
219
220static void sh4a_pmu_disable(struct hw_perf_event *hwc, int idx)
221{
222 unsigned int tmp;
223
224 tmp = __raw_readl(PPC_CCBR(idx));
225 tmp &= ~(CCBR_CIT_MASK | CCBR_DUC);
226 __raw_writel(tmp, PPC_CCBR(idx));
227}
228
229static void sh4a_pmu_enable(struct hw_perf_event *hwc, int idx)
230{
231 unsigned int tmp;
232
233 tmp = __raw_readl(PPC_PMCAT);
234 tmp &= ~PMCAT_EMU_CLR_MASK;
235 tmp |= idx ? PMCAT_CLR1 : PMCAT_CLR0;
236 __raw_writel(tmp, PPC_PMCAT);
237
238 tmp = __raw_readl(PPC_CCBR(idx));
239 tmp |= (hwc->config << 6) | CCBR_CMDS | CCBR_PPCE;
240 __raw_writel(tmp, PPC_CCBR(idx));
241
242 __raw_writel(__raw_readl(PPC_CCBR(idx)) | CCBR_DUC, PPC_CCBR(idx));
243}
244
245static void sh4a_pmu_disable_all(void)
246{
247 int i;
248
249 for (i = 0; i < sh4a_pmu.num_events; i++)
250 __raw_writel(__raw_readl(PPC_CCBR(i)) & ~CCBR_DUC, PPC_CCBR(i));
251}
252
253static void sh4a_pmu_enable_all(void)
254{
255 int i;
256
257 for (i = 0; i < sh4a_pmu.num_events; i++)
258 __raw_writel(__raw_readl(PPC_CCBR(i)) | CCBR_DUC, PPC_CCBR(i));
259}
260
261static struct sh_pmu sh4a_pmu = {
262 .name = "sh4a",
263 .num_events = 2,
264 .event_map = sh4a_event_map,
265 .max_events = ARRAY_SIZE(sh4a_general_events),
266 .raw_event_mask = 0x3ff,
267 .cache_events = &sh4a_cache_events,
268 .read = sh4a_pmu_read,
269 .disable = sh4a_pmu_disable,
270 .enable = sh4a_pmu_enable,
271 .disable_all = sh4a_pmu_disable_all,
272 .enable_all = sh4a_pmu_enable_all,
273};
274
275static int __init sh4a_pmu_init(void)
276{
277 /*
278 * Make sure this CPU actually has perf counters.
279 */
280 if (!(boot_cpu_data.flags & CPU_HAS_PERF_COUNTER)) {
281 pr_notice("HW perf events unsupported, software events only.\n");
282 return -ENODEV;
283 }
284
285 return register_sh_pmu(&sh4a_pmu);
286}
287early_initcall(sh4a_pmu_init);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
index cb9d07bd59f8..0688a7502f86 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
@@ -278,6 +278,7 @@ enum {
278 HIZA8_LCDC, HIZA8_HIZ, 278 HIZA8_LCDC, HIZA8_HIZ,
279 HIZA7_LCDC, HIZA7_HIZ, 279 HIZA7_LCDC, HIZA7_HIZ,
280 HIZA6_LCDC, HIZA6_HIZ, 280 HIZA6_LCDC, HIZA6_HIZ,
281 HIZB4_SIUA, HIZB4_HIZ,
281 HIZB1_VIO, HIZB1_HIZ, 282 HIZB1_VIO, HIZB1_HIZ,
282 HIZB0_VIO, HIZB0_HIZ, 283 HIZB0_VIO, HIZB0_HIZ,
283 HIZC15_IRQ7, HIZC15_HIZ, 284 HIZC15_IRQ7, HIZC15_HIZ,
@@ -546,7 +547,7 @@ static pinmux_enum_t pinmux_data[] = {
546 PINMUX_DATA(VIO_VD2_MARK, PSE3_VIO, MSELB9_VIO2, 547 PINMUX_DATA(VIO_VD2_MARK, PSE3_VIO, MSELB9_VIO2,
547 HIZB0_VIO, FOE_VIO_VD2), 548 HIZB0_VIO, FOE_VIO_VD2),
548 PINMUX_DATA(VIO_HD2_MARK, PSE3_VIO, MSELB9_VIO2, 549 PINMUX_DATA(VIO_HD2_MARK, PSE3_VIO, MSELB9_VIO2,
549 HIZB1_VIO, HIZB1_VIO, FCE_VIO_HD2), 550 HIZB1_VIO, FCE_VIO_HD2),
550 PINMUX_DATA(VIO_CLK2_MARK, PSE3_VIO, MSELB9_VIO2, 551 PINMUX_DATA(VIO_CLK2_MARK, PSE3_VIO, MSELB9_VIO2,
551 HIZB1_VIO, FRB_VIO_CLK2), 552 HIZB1_VIO, FRB_VIO_CLK2),
552 553
@@ -658,14 +659,14 @@ static pinmux_enum_t pinmux_data[] = {
658 PINMUX_DATA(SDHICLK_MARK, SDHICLK), 659 PINMUX_DATA(SDHICLK_MARK, SDHICLK),
659 660
660 /* SIU - Port A */ 661 /* SIU - Port A */
661 PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, SIUAOLR_SIOF1_SYNC), 662 PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, HIZB4_SIUA, SIUAOLR_SIOF1_SYNC),
662 PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, SIUAOBT_SIOF1_SCK), 663 PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, HIZB4_SIUA, SIUAOBT_SIOF1_SCK),
663 PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, SIUAISLD_SIOF1_RXD), 664 PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, HIZB4_SIUA, SIUAISLD_SIOF1_RXD),
664 PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, SIUAILR_SIOF1_SS2), 665 PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, HIZB4_SIUA, SIUAILR_SIOF1_SS2),
665 PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, SIUAIBT_SIOF1_SS1), 666 PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, HIZB4_SIUA, SIUAIBT_SIOF1_SS1),
666 PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, SIUAOSLD_SIOF1_TXD), 667 PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, HIZB4_SIUA, SIUAOSLD_SIOF1_TXD),
667 PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, PSB1_SIUMCKA, PTK0), 668 PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, HIZB4_SIUA, PSB1_SIUMCKA, PTK0),
668 PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, PTK0), 669 PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, HIZB4_SIUA, PTK0),
669 670
670 /* SIU - Port B */ 671 /* SIU - Port B */
671 PINMUX_DATA(SIUBOLR_MARK, PSB11_SIUBOLR, SIOSTRB1_SIUBOLR), 672 PINMUX_DATA(SIUBOLR_MARK, PSB11_SIUBOLR, SIOSTRB1_SIUBOLR),
@@ -1612,7 +1613,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1612 0, 0, 1613 0, 0,
1613 0, 0, 1614 0, 0,
1614 0, 0, 1615 0, 0,
1615 0, 0, 1616 HIZB4_SIUA, HIZB4_HIZ,
1616 0, 0, 1617 0, 0,
1617 0, 0, 1618 0, 0,
1618 HIZB1_VIO, HIZB1_HIZ, 1619 HIZB1_VIO, HIZB1_HIZ,
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
new file mode 100644
index 000000000000..4c74bd04bba4
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
@@ -0,0 +1,2287 @@
1/*
2 * SH7757 (B0 step) Pinmux
3 *
4 * Copyright (C) 2009-2010 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 *
8 * Based on SH7723 Pinmux
9 * Copyright (C) 2008 Magnus Damm
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <cpu/sh7757.h>
20
21enum {
22 PINMUX_RESERVED = 0,
23
24 PINMUX_DATA_BEGIN,
25 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
26 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
27 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
28 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
29 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
30 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
31 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
32 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
33 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
34 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
35 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
36 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
37 PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
38 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
39 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
40 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
41 PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
42 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA,
43 PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
44 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
45 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
46 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
47 PTL6_DATA, PTL5_DATA, PTL4_DATA,
48 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
49 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
50 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
51 PTN6_DATA, PTN5_DATA, PTN4_DATA,
52 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
53 PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
54 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA,
55 PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
56 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA,
57 PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
58 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
59 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
60 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
61 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
62 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
63 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
64 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
65 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
66 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
67 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
68 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
69 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
70 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
71 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
72 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
73 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
74 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
75 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
76 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
77 PINMUX_DATA_END,
78
79 PINMUX_INPUT_BEGIN,
80 PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
81 PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
82 PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
83 PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
84 PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
85 PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
86 PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
87 PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
88 PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN,
89 PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
90 PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
91 PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
92 PTG7_IN, PTG6_IN, PTG5_IN, PTG4_IN,
93 PTG3_IN, PTG2_IN, PTG1_IN, PTG0_IN,
94 PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
95 PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
96 PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN,
97 PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN,
98 PTJ6_IN, PTJ5_IN, PTJ4_IN,
99 PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
100 PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
101 PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
102 PTL6_IN, PTL5_IN, PTL4_IN,
103 PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
104 PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
105 PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
106 PTN6_IN, PTN5_IN, PTN4_IN,
107 PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
108 PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN,
109 PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN,
110 PTP7_IN, PTP6_IN, PTP5_IN, PTP4_IN,
111 PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN,
112 PTQ6_IN, PTQ5_IN, PTQ4_IN,
113 PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
114 PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
115 PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
116 PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN,
117 PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
118 PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN,
119 PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
120 PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
121 PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
122 PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
123 PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
124 PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
125 PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
126 PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
127 PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
128 PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
129 PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
130 PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
131 PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
132 PINMUX_INPUT_END,
133
134 PINMUX_INPUT_PULLUP_BEGIN,
135 PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
136 PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
137 PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
138 PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
139 PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU,
140 PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
141 PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU,
142 PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU,
143 PTG7_IN_PU, PTG6_IN_PU, PTG4_IN_PU,
144 PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
145 PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
146 PTI7_IN_PU, PTI6_IN_PU, PTI4_IN_PU,
147 PTI3_IN_PU, PTI2_IN_PU, PTI1_IN_PU, PTI0_IN_PU,
148 PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU,
149 PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
150 PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU,
151 PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
152 PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU,
153 PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU,
154 PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
155 PTN4_IN_PU,
156 PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU,
157 PTO7_IN_PU, PTO6_IN_PU, PTO5_IN_PU, PTO4_IN_PU,
158 PTO3_IN_PU, PTO2_IN_PU, PTO1_IN_PU, PTO0_IN_PU,
159 PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU,
160 PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
161 PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
162 PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
163 PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
164 PTV3_IN_PU, PTV2_IN_PU,
165 PTW1_IN_PU, PTW0_IN_PU,
166 PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
167 PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
168 PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
169 PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
170 PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU,
171 PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU,
172 PINMUX_INPUT_PULLUP_END,
173
174 PINMUX_OUTPUT_BEGIN,
175 PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
176 PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
177 PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
178 PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
179 PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
180 PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
181 PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
182 PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
183 PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT,
184 PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
185 PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
186 PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
187 PTG7_OUT, PTG6_OUT, PTG5_OUT, PTG4_OUT,
188 PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
189 PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
190 PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
191 PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT,
192 PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT,
193 PTJ6_OUT, PTJ5_OUT, PTJ4_OUT,
194 PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
195 PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
196 PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
197 PTL6_OUT, PTL5_OUT, PTL4_OUT,
198 PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
199 PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
200 PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
201 PTN6_OUT, PTN5_OUT, PTN4_OUT,
202 PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
203 PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT,
204 PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT,
205 PTP7_OUT, PTP6_OUT, PTP5_OUT, PTP4_OUT,
206 PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT,
207 PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
208 PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
209 PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
210 PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT,
211 PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT,
212 PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
213 PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT,
214 PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
215 PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
216 PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
217 PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
218 PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
219 PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
220 PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
221 PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
222 PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
223 PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
224 PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
225 PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
226 PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
227 PINMUX_OUTPUT_END,
228
229 PINMUX_FUNCTION_BEGIN,
230 PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
231 PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
232 PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
233 PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
234 PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
235 PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
236 PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
237 PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
238 PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN,
239 PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
240 PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
241 PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
242 PTG7_FN, PTG6_FN, PTG5_FN, PTG4_FN,
243 PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
244 PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
245 PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
246 PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN,
247 PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN,
248 PTJ6_FN, PTJ5_FN, PTJ4_FN,
249 PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
250 PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
251 PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
252 PTL6_FN, PTL5_FN, PTL4_FN,
253 PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
254 PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
255 PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
256 PTN6_FN, PTN5_FN, PTN4_FN,
257 PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
258 PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN,
259 PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN,
260 PTP7_FN, PTP6_FN, PTP5_FN, PTP4_FN,
261 PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN,
262 PTQ6_FN, PTQ5_FN, PTQ4_FN,
263 PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
264 PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
265 PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
266 PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN,
267 PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
268 PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN,
269 PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
270 PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
271 PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
272 PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
273 PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
274 PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
275 PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
276 PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
277 PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
278 PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
279 PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
280 PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
281 PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
282
283 PS0_15_FN1, PS0_15_FN2,
284 PS0_14_FN1, PS0_14_FN2,
285 PS0_13_FN1, PS0_13_FN2,
286 PS0_12_FN1, PS0_12_FN2,
287 PS0_11_FN1, PS0_11_FN2,
288 PS0_10_FN1, PS0_10_FN2,
289 PS0_9_FN1, PS0_9_FN2,
290 PS0_8_FN1, PS0_8_FN2,
291 PS0_7_FN1, PS0_7_FN2,
292 PS0_6_FN1, PS0_6_FN2,
293 PS0_5_FN1, PS0_5_FN2,
294 PS0_4_FN1, PS0_4_FN2,
295 PS0_3_FN1, PS0_3_FN2,
296 PS0_2_FN1, PS0_2_FN2,
297
298 PS1_10_FN1, PS1_10_FN2,
299 PS1_9_FN1, PS1_9_FN2,
300 PS1_8_FN1, PS1_8_FN2,
301 PS1_2_FN1, PS1_2_FN2,
302
303 PS2_13_FN1, PS2_13_FN2,
304 PS2_12_FN1, PS2_12_FN2,
305 PS2_7_FN1, PS2_7_FN2,
306 PS2_6_FN1, PS2_6_FN2,
307 PS2_5_FN1, PS2_5_FN2,
308 PS2_4_FN1, PS2_4_FN2,
309 PS2_2_FN1, PS2_2_FN2,
310
311 PS3_15_FN1, PS3_15_FN2,
312 PS3_14_FN1, PS3_14_FN2,
313 PS3_13_FN1, PS3_13_FN2,
314 PS3_12_FN1, PS3_12_FN2,
315 PS3_11_FN1, PS3_11_FN2,
316 PS3_10_FN1, PS3_10_FN2,
317 PS3_9_FN1, PS3_9_FN2,
318 PS3_8_FN1, PS3_8_FN2,
319 PS3_7_FN1, PS3_7_FN2,
320 PS3_2_FN1, PS3_2_FN2,
321 PS3_1_FN1, PS3_1_FN2,
322
323 PS4_14_FN1, PS4_14_FN2,
324 PS4_13_FN1, PS4_13_FN2,
325 PS4_12_FN1, PS4_12_FN2,
326 PS4_10_FN1, PS4_10_FN2,
327 PS4_9_FN1, PS4_9_FN2,
328 PS4_8_FN1, PS4_8_FN2,
329 PS4_4_FN1, PS4_4_FN2,
330 PS4_3_FN1, PS4_3_FN2,
331 PS4_2_FN1, PS4_2_FN2,
332 PS4_1_FN1, PS4_1_FN2,
333 PS4_0_FN1, PS4_0_FN2,
334
335 PS5_11_FN1, PS5_11_FN2,
336 PS5_10_FN1, PS5_10_FN2,
337 PS5_9_FN1, PS5_9_FN2,
338 PS5_8_FN1, PS5_8_FN2,
339 PS5_7_FN1, PS5_7_FN2,
340 PS5_6_FN1, PS5_6_FN2,
341 PS5_5_FN1, PS5_5_FN2,
342 PS5_4_FN1, PS5_4_FN2,
343 PS5_3_FN1, PS5_3_FN2,
344 PS5_2_FN1, PS5_2_FN2,
345
346 PS6_15_FN1, PS6_15_FN2,
347 PS6_14_FN1, PS6_14_FN2,
348 PS6_13_FN1, PS6_13_FN2,
349 PS6_12_FN1, PS6_12_FN2,
350 PS6_11_FN1, PS6_11_FN2,
351 PS6_10_FN1, PS6_10_FN2,
352 PS6_9_FN1, PS6_9_FN2,
353 PS6_8_FN1, PS6_8_FN2,
354 PS6_7_FN1, PS6_7_FN2,
355 PS6_6_FN1, PS6_6_FN2,
356 PS6_5_FN1, PS6_5_FN2,
357 PS6_4_FN1, PS6_4_FN2,
358 PS6_3_FN1, PS6_3_FN2,
359 PS6_2_FN1, PS6_2_FN2,
360 PS6_1_FN1, PS6_1_FN2,
361 PS6_0_FN1, PS6_0_FN2,
362
363 PS7_15_FN1, PS7_15_FN2,
364 PS7_14_FN1, PS7_14_FN2,
365 PS7_13_FN1, PS7_13_FN2,
366 PS7_12_FN1, PS7_12_FN2,
367 PS7_11_FN1, PS7_11_FN2,
368 PS7_10_FN1, PS7_10_FN2,
369 PS7_9_FN1, PS7_9_FN2,
370 PS7_8_FN1, PS7_8_FN2,
371 PS7_7_FN1, PS7_7_FN2,
372 PS7_6_FN1, PS7_6_FN2,
373 PS7_5_FN1, PS7_5_FN2,
374 PS7_4_FN1, PS7_4_FN2,
375
376 PS8_15_FN1, PS8_15_FN2,
377 PS8_14_FN1, PS8_14_FN2,
378 PS8_13_FN1, PS8_13_FN2,
379 PS8_12_FN1, PS8_12_FN2,
380 PS8_11_FN1, PS8_11_FN2,
381 PS8_10_FN1, PS8_10_FN2,
382 PS8_9_FN1, PS8_9_FN2,
383 PS8_8_FN1, PS8_8_FN2,
384 PINMUX_FUNCTION_END,
385
386 PINMUX_MARK_BEGIN,
387 /* PTA (mobule: LBSC, RGMII) */
388 BS_MARK, RDWR_MARK, WE1_MARK, RDY_MARK,
389 ET0_MDC_MARK, ET0_MDIO_MARK, ET1_MDC_MARK, ET1_MDIO_MARK,
390
391 /* PTB (mobule: INTC, ONFI, TMU) */
392 IRQ15_MARK, IRQ14_MARK, IRQ13_MARK, IRQ12_MARK,
393 IRQ11_MARK, IRQ10_MARK, IRQ9_MARK, IRQ8_MARK,
394 ON_NRE_MARK, ON_NWE_MARK, ON_NWP_MARK, ON_NCE0_MARK,
395 ON_R_B0_MARK, ON_ALE_MARK, ON_CLE_MARK, TCLK_MARK,
396
397 /* PTC (mobule: IRQ, PWMU) */
398 IRQ7_MARK, IRQ6_MARK, IRQ5_MARK, IRQ4_MARK,
399 IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
400 PWMU0_MARK, PWMU1_MARK, PWMU2_MARK, PWMU3_MARK,
401 PWMU4_MARK, PWMU5_MARK,
402
403 /* PTD (mobule: SPI0, DMAC) */
404 SP0_MOSI_MARK, SP0_MISO_MARK, SP0_SCK_MARK, SP0_SCK_FB_MARK,
405 SP0_SS0_MARK, SP0_SS1_MARK, SP0_SS2_MARK, SP0_SS3_MARK,
406 DREQ0_MARK, DACK0_MARK, TEND0_MARK,
407
408 /* PTE (mobule: RMII) */
409 RMII0_CRS_DV_MARK, RMII0_TXD1_MARK,
410 RMII0_TXD0_MARK, RMII0_TXEN_MARK,
411 RMII0_REFCLK_MARK, RMII0_RXD1_MARK,
412 RMII0_RXD0_MARK, RMII0_RX_ER_MARK,
413
414 /* PTF (mobule: RMII, SerMux) */
415 RMII1_CRS_DV_MARK, RMII1_TXD1_MARK,
416 RMII1_TXD0_MARK, RMII1_TXEN_MARK,
417 RMII1_REFCLK_MARK, RMII1_RXD1_MARK,
418 RMII1_RXD0_MARK, RMII1_RX_ER_MARK,
419 RAC_RI_MARK,
420
421 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
422 BOOTFMS_MARK, BOOTWP_MARK, A25_MARK, A24_MARK,
423 SERIRQ_MARK, WDTOVF_MARK, LPCPD_MARK, LDRQ_MARK,
424 MMCCLK_MARK, MMCCMD_MARK,
425
426 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
427 SP1_MOSI_MARK, SP1_MISO_MARK, SP1_SCK_MARK, SP1_SCK_FB_MARK,
428 SP1_SS0_MARK, SP1_SS1_MARK, WP_MARK, FMS0_MARK,
429 TEND1_MARK, DREQ1_MARK, DACK1_MARK, ADTRG1_MARK,
430 ADTRG0_MARK,
431
432 /* PTI (mobule: LBSC, SDHI) */
433 D15_MARK, D14_MARK, D13_MARK, D12_MARK,
434 D11_MARK, D10_MARK, D9_MARK, D8_MARK,
435 SD_WP_MARK, SD_CD_MARK, SD_CLK_MARK, SD_CMD_MARK,
436 SD_D3_MARK, SD_D2_MARK, SD_D1_MARK, SD_D0_MARK,
437
438 /* PTJ (mobule: SCIF234) */
439 RTS3_MARK, CTS3_MARK, TXD3_MARK, RXD3_MARK,
440 RTS4_MARK, RXD4_MARK, TXD4_MARK,
441
442 /* PTK (mobule: SERMUX, LBSC, SCIF) */
443 COM2_TXD_MARK, COM2_RXD_MARK, COM2_RTS_MARK, COM2_CTS_MARK,
444 COM2_DTR_MARK, COM2_DSR_MARK, COM2_DCD_MARK, CLKOUT_MARK,
445 SCK2_MARK, SCK4_MARK, SCK3_MARK,
446
447 /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
448 RAC_RXD_MARK, RAC_RTS_MARK, RAC_CTS_MARK, RAC_DTR_MARK,
449 RAC_DSR_MARK, RAC_DCD_MARK, RAC_TXD_MARK, RXD2_MARK,
450 CS5_MARK, CS6_MARK, AUDSYNC_MARK, AUDCK_MARK,
451 TXD2_MARK,
452
453 /* PTM (mobule: LBSC, IIC) */
454 CS4_MARK, RD_MARK, WE0_MARK, CS0_MARK,
455 SDA6_MARK, SCL6_MARK, SDA7_MARK, SCL7_MARK,
456
457 /* PTN (mobule: USB, JMC, SGPIO, WDT) */
458 VBUS_EN_MARK, VBUS_OC_MARK, JMCTCK_MARK, JMCTMS_MARK,
459 JMCTDO_MARK, JMCTDI_MARK, JMCTRST_MARK,
460 SGPIO1_CLK_MARK, SGPIO1_LOAD_MARK, SGPIO1_DI_MARK,
461 SGPIO1_DO_MARK, SUB_CLKIN_MARK,
462
463 /* PTO (mobule: SGPIO, SerMux) */
464 SGPIO0_CLK_MARK, SGPIO0_LOAD_MARK, SGPIO0_DI_MARK,
465 SGPIO0_DO_MARK, SGPIO2_CLK_MARK, SGPIO2_LOAD_MARK,
466 SGPIO2_DI_MARK, SGPIO2_DO_MARK,
467 COM1_TXD_MARK, COM1_RXD_MARK, COM1_RTS_MARK, COM1_CTS_MARK,
468
469 /* PTQ (mobule: LPC) */
470 LAD3_MARK, LAD2_MARK, LAD1_MARK, LAD0_MARK,
471 LFRAME_MARK, LRESET_MARK, LCLK_MARK,
472
473 /* PTR (mobule: GRA, IIC) */
474 DDC3_MARK, DDC2_MARK, SDA2_MARK, SCL2_MARK,
475 SDA1_MARK, SCL1_MARK, SDA0_MARK, SCL0_MARK,
476 SDA8_MARK, SCL8_MARK,
477
478 /* PTS (mobule: GRA, IIC) */
479 DDC1_MARK, DDC0_MARK, SDA5_MARK, SCL5_MARK,
480 SDA4_MARK, SCL4_MARK, SDA3_MARK, SCL3_MARK,
481 SDA9_MARK, SCL9_MARK,
482
483 /* PTT (mobule: PWMX, AUD) */
484 PWMX7_MARK, PWMX6_MARK, PWMX5_MARK, PWMX4_MARK,
485 PWMX3_MARK, PWMX2_MARK, PWMX1_MARK, PWMX0_MARK,
486 AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK,
487 STATUS1_MARK, STATUS0_MARK,
488
489 /* PTU (mobule: LPC, APM) */
490 LGPIO7_MARK, LGPIO6_MARK, LGPIO5_MARK, LGPIO4_MARK,
491 LGPIO3_MARK, LGPIO2_MARK, LGPIO1_MARK, LGPIO0_MARK,
492 APMONCTL_O_MARK, APMPWBTOUT_O_MARK, APMSCI_O_MARK,
493 APMVDDON_MARK, APMSLPBTN_MARK, APMPWRBTN_MARK, APMS5N_MARK,
494 APMS3N_MARK,
495
496 /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
497 A23_MARK, A22_MARK, A21_MARK, A20_MARK,
498 A19_MARK, A18_MARK, A17_MARK, A16_MARK,
499 COM2_RI_MARK, R_SPI_MOSI_MARK, R_SPI_MISO_MARK,
500 R_SPI_RSPCK_MARK, R_SPI_SSL0_MARK, R_SPI_SSL1_MARK,
501 EVENT7_MARK, EVENT6_MARK, VBIOS_DI_MARK, VBIOS_DO_MARK,
502 VBIOS_CLK_MARK, VBIOS_CS_MARK,
503
504 /* PTW (mobule: LBSC, EVC, SCIF) */
505 A15_MARK, A14_MARK, A13_MARK, A12_MARK,
506 A11_MARK, A10_MARK, A9_MARK, A8_MARK,
507 EVENT5_MARK, EVENT4_MARK, EVENT3_MARK, EVENT2_MARK,
508 EVENT1_MARK, EVENT0_MARK, CTS4_MARK, CTS2_MARK,
509
510 /* PTX (mobule: LBSC, SCIF, SIM) */
511 A7_MARK, A6_MARK, A5_MARK, A4_MARK,
512 A3_MARK, A2_MARK, A1_MARK, A0_MARK,
513 RTS2_MARK, SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK,
514
515 /* PTY (mobule: LBSC) */
516 D7_MARK, D6_MARK, D5_MARK, D4_MARK,
517 D3_MARK, D2_MARK, D1_MARK, D0_MARK,
518
519 /* PTZ (mobule: eMMC, ONFI) */
520 MMCDAT7_MARK, MMCDAT6_MARK, MMCDAT5_MARK, MMCDAT4_MARK,
521 MMCDAT3_MARK, MMCDAT2_MARK, MMCDAT1_MARK, MMCDAT0_MARK,
522 ON_DQ7_MARK, ON_DQ6_MARK, ON_DQ5_MARK, ON_DQ4_MARK,
523 ON_DQ3_MARK, ON_DQ2_MARK, ON_DQ1_MARK, ON_DQ0_MARK,
524
525 PINMUX_MARK_END,
526};
527
528static pinmux_enum_t pinmux_data[] = {
529 /* PTA GPIO */
530 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
531 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
532 PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
533 PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT),
534 PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT),
535 PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT),
536 PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT),
537 PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT),
538
539 /* PTB GPIO */
540 PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
541 PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
542 PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
543 PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
544 PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
545 PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
546 PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
547 PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
548
549 /* PTC GPIO */
550 PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT),
551 PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT),
552 PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT),
553 PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
554 PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
555 PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
556 PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT),
557 PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
558
559 /* PTD GPIO */
560 PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT),
561 PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT),
562 PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT),
563 PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT),
564 PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT),
565 PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT),
566 PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT),
567 PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
568
569 /* PTE GPIO */
570 PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT),
571 PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT),
572 PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT),
573 PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
574 PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
575 PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT),
576 PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT),
577 PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT),
578
579 /* PTF GPIO */
580 PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT),
581 PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT),
582 PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT),
583 PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT),
584 PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT),
585 PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT),
586 PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT),
587 PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT),
588
589 /* PTG GPIO */
590 PINMUX_DATA(PTG7_DATA, PTG7_IN, PTG7_OUT),
591 PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT),
592 PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT),
593 PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT),
594 PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT),
595 PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT),
596 PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT),
597 PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT),
598
599 /* PTH GPIO */
600 PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT),
601 PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT),
602 PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT),
603 PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT),
604 PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT),
605 PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT),
606 PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT),
607 PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT),
608
609 /* PTI GPIO */
610 PINMUX_DATA(PTI7_DATA, PTI7_IN, PTI7_OUT),
611 PINMUX_DATA(PTI6_DATA, PTI6_IN, PTI6_OUT),
612 PINMUX_DATA(PTI5_DATA, PTI5_IN, PTI5_OUT),
613 PINMUX_DATA(PTI4_DATA, PTI4_IN, PTI4_OUT),
614 PINMUX_DATA(PTI3_DATA, PTI3_IN, PTI3_OUT),
615 PINMUX_DATA(PTI2_DATA, PTI2_IN, PTI2_OUT),
616 PINMUX_DATA(PTI1_DATA, PTI1_IN, PTI1_OUT),
617 PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT),
618
619 /* PTJ GPIO */
620 PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT),
621 PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT),
622 PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT),
623 PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT),
624 PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT),
625 PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT),
626 PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT),
627
628 /* PTK GPIO */
629 PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT),
630 PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT),
631 PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT),
632 PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT),
633 PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT),
634 PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT),
635 PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT),
636 PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
637
638 /* PTL GPIO */
639 PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
640 PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
641 PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
642 PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT),
643 PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT),
644 PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT),
645 PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT),
646
647 /* PTM GPIO */
648 PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT),
649 PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT),
650 PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT),
651 PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT),
652 PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT),
653 PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT),
654 PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
655
656 /* PTN GPIO */
657 PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT),
658 PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT),
659 PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT),
660 PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT),
661 PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT),
662 PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT),
663 PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT),
664
665 /* PTO GPIO */
666 PINMUX_DATA(PTO7_DATA, PTO7_IN, PTO7_OUT),
667 PINMUX_DATA(PTO6_DATA, PTO6_IN, PTO6_OUT),
668 PINMUX_DATA(PTO5_DATA, PTO5_IN, PTO5_OUT),
669 PINMUX_DATA(PTO4_DATA, PTO4_IN, PTO4_OUT),
670 PINMUX_DATA(PTO3_DATA, PTO3_IN, PTO3_OUT),
671 PINMUX_DATA(PTO2_DATA, PTO2_IN, PTO2_OUT),
672 PINMUX_DATA(PTO1_DATA, PTO1_IN, PTO1_OUT),
673 PINMUX_DATA(PTO0_DATA, PTO0_IN, PTO0_OUT),
674
675 /* PTQ GPIO */
676 PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT),
677 PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT),
678 PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT),
679 PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT),
680 PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT),
681 PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT),
682 PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT),
683
684 /* PTR GPIO */
685 PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT),
686 PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT),
687 PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT),
688 PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT),
689 PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT),
690 PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT),
691 PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT),
692 PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT),
693
694 /* PTS GPIO */
695 PINMUX_DATA(PTS7_DATA, PTS7_IN, PTS7_OUT),
696 PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT),
697 PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT),
698 PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT),
699 PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT),
700 PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT),
701 PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT),
702 PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
703
704 /* PTT GPIO */
705 PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT),
706 PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT),
707 PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT),
708 PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
709 PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
710 PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT),
711 PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT),
712 PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT),
713
714 /* PTU GPIO */
715 PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT),
716 PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT),
717 PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT),
718 PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT),
719 PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT),
720 PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT),
721 PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT),
722 PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT),
723
724 /* PTV GPIO */
725 PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT),
726 PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT),
727 PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT),
728 PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT),
729 PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT),
730 PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT),
731 PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT),
732 PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT),
733
734 /* PTW GPIO */
735 PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT),
736 PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT),
737 PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT),
738 PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT),
739 PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT),
740 PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT),
741 PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT),
742 PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT),
743
744 /* PTX GPIO */
745 PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT),
746 PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT),
747 PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT),
748 PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT),
749 PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT),
750 PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT),
751 PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT),
752 PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT),
753
754 /* PTY GPIO */
755 PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT),
756 PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT),
757 PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT),
758 PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT),
759 PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT),
760 PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT),
761 PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT),
762 PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT),
763
764 /* PTZ GPIO */
765 PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT),
766 PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT),
767 PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT),
768 PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT),
769 PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT),
770 PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT),
771 PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT),
772 PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT),
773
774 /* PTA FN */
775 PINMUX_DATA(BS_MARK, PTA7_FN),
776 PINMUX_DATA(RDWR_MARK, PTA6_FN),
777 PINMUX_DATA(WE1_MARK, PTA5_FN),
778 PINMUX_DATA(RDY_MARK, PTA4_FN),
779 PINMUX_DATA(ET0_MDC_MARK, PTA3_FN),
780 PINMUX_DATA(ET0_MDIO_MARK, PTA2_FN),
781 PINMUX_DATA(ET1_MDC_MARK, PTA1_FN),
782 PINMUX_DATA(ET1_MDIO_MARK, PTA0_FN),
783
784 /* PTB FN */
785 PINMUX_DATA(IRQ15_MARK, PS0_15_FN1, PTB7_FN),
786 PINMUX_DATA(ON_NRE_MARK, PS0_15_FN2, PTB7_FN),
787 PINMUX_DATA(IRQ14_MARK, PS0_14_FN1, PTB6_FN),
788 PINMUX_DATA(ON_NWE_MARK, PS0_14_FN2, PTB6_FN),
789 PINMUX_DATA(IRQ13_MARK, PS0_13_FN1, PTB5_FN),
790 PINMUX_DATA(ON_NWP_MARK, PS0_13_FN2, PTB5_FN),
791 PINMUX_DATA(IRQ12_MARK, PS0_12_FN1, PTB4_FN),
792 PINMUX_DATA(ON_NCE0_MARK, PS0_12_FN2, PTB4_FN),
793 PINMUX_DATA(IRQ11_MARK, PS0_11_FN1, PTB3_FN),
794 PINMUX_DATA(ON_R_B0_MARK, PS0_11_FN2, PTB3_FN),
795 PINMUX_DATA(IRQ10_MARK, PS0_10_FN1, PTB2_FN),
796 PINMUX_DATA(ON_ALE_MARK, PS0_10_FN2, PTB2_FN),
797 PINMUX_DATA(IRQ9_MARK, PS0_9_FN1, PTB1_FN),
798 PINMUX_DATA(ON_CLE_MARK, PS0_9_FN2, PTB1_FN),
799 PINMUX_DATA(IRQ8_MARK, PS0_8_FN1, PTB0_FN),
800 PINMUX_DATA(TCLK_MARK, PS0_8_FN2, PTB0_FN),
801
802 /* PTC FN */
803 PINMUX_DATA(IRQ7_MARK, PS0_7_FN1, PTC7_FN),
804 PINMUX_DATA(PWMU0_MARK, PS0_7_FN2, PTC7_FN),
805 PINMUX_DATA(IRQ6_MARK, PS0_6_FN1, PTC6_FN),
806 PINMUX_DATA(PWMU1_MARK, PS0_6_FN2, PTC6_FN),
807 PINMUX_DATA(IRQ5_MARK, PS0_5_FN1, PTC5_FN),
808 PINMUX_DATA(PWMU2_MARK, PS0_5_FN2, PTC5_FN),
809 PINMUX_DATA(IRQ4_MARK, PS0_4_FN1, PTC5_FN),
810 PINMUX_DATA(PWMU3_MARK, PS0_4_FN2, PTC4_FN),
811 PINMUX_DATA(IRQ3_MARK, PS0_3_FN1, PTC3_FN),
812 PINMUX_DATA(PWMU4_MARK, PS0_3_FN2, PTC3_FN),
813 PINMUX_DATA(IRQ2_MARK, PS0_2_FN1, PTC2_FN),
814 PINMUX_DATA(PWMU5_MARK, PS0_2_FN2, PTC2_FN),
815 PINMUX_DATA(IRQ1_MARK, PTC1_FN),
816 PINMUX_DATA(IRQ0_MARK, PTC0_FN),
817
818 /* PTD FN */
819 PINMUX_DATA(SP0_MOSI_MARK, PTD7_FN),
820 PINMUX_DATA(SP0_MISO_MARK, PTD6_FN),
821 PINMUX_DATA(SP0_SCK_MARK, PTD5_FN),
822 PINMUX_DATA(SP0_SCK_FB_MARK, PTD4_FN),
823 PINMUX_DATA(SP0_SS0_MARK, PTD3_FN),
824 PINMUX_DATA(SP0_SS1_MARK, PS1_10_FN1, PTD2_FN),
825 PINMUX_DATA(DREQ0_MARK, PS1_10_FN2, PTD2_FN),
826 PINMUX_DATA(SP0_SS2_MARK, PS1_9_FN1, PTD1_FN),
827 PINMUX_DATA(DACK0_MARK, PS1_9_FN2, PTD1_FN),
828 PINMUX_DATA(SP0_SS3_MARK, PS1_8_FN1, PTD0_FN),
829 PINMUX_DATA(TEND0_MARK, PS1_8_FN2, PTD0_FN),
830
831 /* PTE FN */
832 PINMUX_DATA(RMII0_CRS_DV_MARK, PTE7_FN),
833 PINMUX_DATA(RMII0_TXD1_MARK, PTE6_FN),
834 PINMUX_DATA(RMII0_TXD0_MARK, PTE5_FN),
835 PINMUX_DATA(RMII0_TXEN_MARK, PTE4_FN),
836 PINMUX_DATA(RMII0_REFCLK_MARK, PTE3_FN),
837 PINMUX_DATA(RMII0_RXD1_MARK, PTE2_FN),
838 PINMUX_DATA(RMII0_RXD0_MARK, PTE1_FN),
839 PINMUX_DATA(RMII0_RX_ER_MARK, PTE0_FN),
840
841 /* PTF FN */
842 PINMUX_DATA(RMII1_CRS_DV_MARK, PTF7_FN),
843 PINMUX_DATA(RMII1_TXD1_MARK, PTF6_FN),
844 PINMUX_DATA(RMII1_TXD0_MARK, PTF5_FN),
845 PINMUX_DATA(RMII1_TXEN_MARK, PTF4_FN),
846 PINMUX_DATA(RMII1_REFCLK_MARK, PTF3_FN),
847 PINMUX_DATA(RMII1_RXD1_MARK, PS1_2_FN1, PTF2_FN),
848 PINMUX_DATA(RAC_RI_MARK, PS1_2_FN2, PTF2_FN),
849 PINMUX_DATA(RMII1_RXD0_MARK, PTF1_FN),
850 PINMUX_DATA(RMII1_RX_ER_MARK, PTF0_FN),
851
852 /* PTG FN */
853 PINMUX_DATA(BOOTFMS_MARK, PTG7_FN),
854 PINMUX_DATA(BOOTWP_MARK, PTG6_FN),
855 PINMUX_DATA(A25_MARK, PS2_13_FN1, PTG5_FN),
856 PINMUX_DATA(MMCCLK_MARK, PS2_13_FN2, PTG5_FN),
857 PINMUX_DATA(A24_MARK, PS2_12_FN1, PTG4_FN),
858 PINMUX_DATA(MMCCMD_MARK, PS2_12_FN2, PTG4_FN),
859 PINMUX_DATA(SERIRQ_MARK, PTG3_FN),
860 PINMUX_DATA(WDTOVF_MARK, PTG2_FN),
861 PINMUX_DATA(LPCPD_MARK, PTG1_FN),
862 PINMUX_DATA(LDRQ_MARK, PTG0_FN),
863
864 /* PTH FN */
865 PINMUX_DATA(SP1_MOSI_MARK, PS2_7_FN1, PTH7_FN),
866 PINMUX_DATA(TEND1_MARK, PS2_7_FN2, PTH7_FN),
867 PINMUX_DATA(SP1_MISO_MARK, PS2_6_FN1, PTH6_FN),
868 PINMUX_DATA(DREQ1_MARK, PS2_6_FN2, PTH6_FN),
869 PINMUX_DATA(SP1_SCK_MARK, PS2_5_FN1, PTH5_FN),
870 PINMUX_DATA(DACK1_MARK, PS2_5_FN2, PTH5_FN),
871 PINMUX_DATA(SP1_SCK_FB_MARK, PS2_4_FN1, PTH4_FN),
872 PINMUX_DATA(ADTRG1_MARK, PS2_4_FN2, PTH4_FN),
873 PINMUX_DATA(SP1_SS0_MARK, PTH3_FN),
874 PINMUX_DATA(SP1_SS1_MARK, PS2_2_FN1, PTH2_FN),
875 PINMUX_DATA(ADTRG0_MARK, PS2_2_FN2, PTH2_FN),
876 PINMUX_DATA(WP_MARK, PTH1_FN),
877 PINMUX_DATA(FMS0_MARK, PTH0_FN),
878
879 /* PTI FN */
880 PINMUX_DATA(D15_MARK, PS3_15_FN1, PTI7_FN),
881 PINMUX_DATA(SD_WP_MARK, PS3_15_FN2, PTI7_FN),
882 PINMUX_DATA(D14_MARK, PS3_14_FN1, PTI6_FN),
883 PINMUX_DATA(SD_CD_MARK, PS3_14_FN2, PTI6_FN),
884 PINMUX_DATA(D13_MARK, PS3_13_FN1, PTI5_FN),
885 PINMUX_DATA(SD_CLK_MARK, PS3_13_FN2, PTI5_FN),
886 PINMUX_DATA(D12_MARK, PS3_12_FN1, PTI4_FN),
887 PINMUX_DATA(SD_CMD_MARK, PS3_12_FN2, PTI4_FN),
888 PINMUX_DATA(D11_MARK, PS3_11_FN1, PTI3_FN),
889 PINMUX_DATA(SD_D3_MARK, PS3_11_FN2, PTI3_FN),
890 PINMUX_DATA(D10_MARK, PS3_10_FN1, PTI2_FN),
891 PINMUX_DATA(SD_D2_MARK, PS3_10_FN2, PTI2_FN),
892 PINMUX_DATA(D9_MARK, PS3_9_FN1, PTI1_FN),
893 PINMUX_DATA(SD_D1_MARK, PS3_9_FN2, PTI1_FN),
894 PINMUX_DATA(D8_MARK, PS3_8_FN1, PTI0_FN),
895 PINMUX_DATA(SD_D0_MARK, PS3_8_FN2, PTI0_FN),
896
897 /* PTJ FN */
898 PINMUX_DATA(RTS3_MARK, PTJ6_FN),
899 PINMUX_DATA(CTS3_MARK, PTJ5_FN),
900 PINMUX_DATA(TXD3_MARK, PTJ4_FN),
901 PINMUX_DATA(RXD3_MARK, PTJ3_FN),
902 PINMUX_DATA(RTS4_MARK, PTJ2_FN),
903 PINMUX_DATA(RXD4_MARK, PTJ1_FN),
904 PINMUX_DATA(TXD4_MARK, PTJ0_FN),
905
906 /* PTK FN */
907 PINMUX_DATA(COM2_TXD_MARK, PS3_7_FN1, PTK7_FN),
908 PINMUX_DATA(SCK2_MARK, PS3_7_FN2, PTK7_FN),
909 PINMUX_DATA(COM2_RXD_MARK, PTK6_FN),
910 PINMUX_DATA(COM2_RTS_MARK, PTK5_FN),
911 PINMUX_DATA(COM2_CTS_MARK, PTK4_FN),
912 PINMUX_DATA(COM2_DTR_MARK, PTK3_FN),
913 PINMUX_DATA(COM2_DSR_MARK, PS3_2_FN1, PTK2_FN),
914 PINMUX_DATA(SCK4_MARK, PS3_2_FN2, PTK2_FN),
915 PINMUX_DATA(COM2_DCD_MARK, PS3_1_FN1, PTK1_FN),
916 PINMUX_DATA(SCK3_MARK, PS3_1_FN2, PTK1_FN),
917 PINMUX_DATA(CLKOUT_MARK, PTK0_FN),
918
919 /* PTL FN */
920 PINMUX_DATA(RAC_RXD_MARK, PS4_14_FN1, PTL6_FN),
921 PINMUX_DATA(RXD2_MARK, PS4_14_FN2, PTL6_FN),
922 PINMUX_DATA(RAC_RTS_MARK, PS4_13_FN1, PTL5_FN),
923 PINMUX_DATA(CS5_MARK, PS4_13_FN2, PTL5_FN),
924 PINMUX_DATA(RAC_CTS_MARK, PS4_12_FN1, PTL4_FN),
925 PINMUX_DATA(CS6_MARK, PS4_12_FN2, PTL4_FN),
926 PINMUX_DATA(RAC_DTR_MARK, PTL3_FN),
927 PINMUX_DATA(RAC_DSR_MARK, PS4_10_FN1, PTL2_FN),
928 PINMUX_DATA(AUDSYNC_MARK, PS4_10_FN2, PTL2_FN),
929 PINMUX_DATA(RAC_DCD_MARK, PS4_9_FN1, PTL1_FN),
930 PINMUX_DATA(AUDCK_MARK, PS4_9_FN2, PTL1_FN),
931 PINMUX_DATA(RAC_TXD_MARK, PS4_8_FN1, PTL0_FN),
932 PINMUX_DATA(TXD2_MARK, PS4_8_FN1, PTL0_FN),
933
934 /* PTM FN */
935 PINMUX_DATA(CS4_MARK, PTM7_FN),
936 PINMUX_DATA(RD_MARK, PTM6_FN),
937 PINMUX_DATA(WE0_MARK, PTM7_FN),
938 PINMUX_DATA(CS0_MARK, PTM4_FN),
939 PINMUX_DATA(SDA6_MARK, PTM3_FN),
940 PINMUX_DATA(SCL6_MARK, PTM2_FN),
941 PINMUX_DATA(SDA7_MARK, PTM1_FN),
942 PINMUX_DATA(SCL7_MARK, PTM0_FN),
943
944 /* PTN FN */
945 PINMUX_DATA(VBUS_EN_MARK, PTN6_FN),
946 PINMUX_DATA(VBUS_OC_MARK, PTN5_FN),
947 PINMUX_DATA(JMCTCK_MARK, PS4_4_FN1, PTN4_FN),
948 PINMUX_DATA(SGPIO1_CLK_MARK, PS4_4_FN2, PTN4_FN),
949 PINMUX_DATA(JMCTMS_MARK, PS4_3_FN1, PTN5_FN),
950 PINMUX_DATA(SGPIO1_LOAD_MARK, PS4_3_FN2, PTN5_FN),
951 PINMUX_DATA(JMCTDO_MARK, PS4_2_FN1, PTN2_FN),
952 PINMUX_DATA(SGPIO1_DO_MARK, PS4_2_FN2, PTN2_FN),
953 PINMUX_DATA(JMCTDI_MARK, PS4_1_FN1, PTN1_FN),
954 PINMUX_DATA(SGPIO1_DI_MARK, PS4_1_FN2, PTN1_FN),
955 PINMUX_DATA(JMCTRST_MARK, PS4_0_FN1, PTN0_FN),
956 PINMUX_DATA(SUB_CLKIN_MARK, PS4_0_FN2, PTN0_FN),
957
958 /* PTO FN */
959 PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN),
960 PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN),
961 PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN),
962 PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN),
963 PINMUX_DATA(SGPIO2_CLK_MARK, PS5_11_FN1, PTO3_FN),
964 PINMUX_DATA(COM1_TXD_MARK, PS5_11_FN2, PTO3_FN),
965 PINMUX_DATA(SGPIO2_LOAD_MARK, PS5_10_FN1, PTO2_FN),
966 PINMUX_DATA(COM1_RXD_MARK, PS5_10_FN2, PTO2_FN),
967 PINMUX_DATA(SGPIO2_DI_MARK, PS5_9_FN1, PTO1_FN),
968 PINMUX_DATA(COM1_RTS_MARK, PS5_9_FN2, PTO1_FN),
969 PINMUX_DATA(SGPIO2_DO_MARK, PS5_8_FN1, PTO0_FN),
970 PINMUX_DATA(COM1_CTS_MARK, PS5_8_FN2, PTO0_FN),
971
972 /* PTP FN */
973
974 /* PTQ FN */
975 PINMUX_DATA(LAD3_MARK, PTQ6_FN),
976 PINMUX_DATA(LAD2_MARK, PTQ5_FN),
977 PINMUX_DATA(LAD1_MARK, PTQ4_FN),
978 PINMUX_DATA(LAD0_MARK, PTQ3_FN),
979 PINMUX_DATA(LFRAME_MARK, PTQ2_FN),
980 PINMUX_DATA(LRESET_MARK, PTQ1_FN),
981 PINMUX_DATA(LCLK_MARK, PTQ0_FN),
982
983 /* PTR FN */
984 PINMUX_DATA(SDA8_MARK, PTR7_FN), /* DDC3? */
985 PINMUX_DATA(SCL8_MARK, PTR6_FN), /* DDC2? */
986 PINMUX_DATA(SDA2_MARK, PTR5_FN),
987 PINMUX_DATA(SCL2_MARK, PTR4_FN),
988 PINMUX_DATA(SDA1_MARK, PTR3_FN),
989 PINMUX_DATA(SCL1_MARK, PTR2_FN),
990 PINMUX_DATA(SDA0_MARK, PTR1_FN),
991 PINMUX_DATA(SCL0_MARK, PTR0_FN),
992
993 /* PTS FN */
994 PINMUX_DATA(SDA9_MARK, PTS7_FN), /* DDC1? */
995 PINMUX_DATA(SCL9_MARK, PTS6_FN), /* DDC0? */
996 PINMUX_DATA(SDA5_MARK, PTS5_FN),
997 PINMUX_DATA(SCL5_MARK, PTS4_FN),
998 PINMUX_DATA(SDA4_MARK, PTS3_FN),
999 PINMUX_DATA(SCL4_MARK, PTS2_FN),
1000 PINMUX_DATA(SDA3_MARK, PTS1_FN),
1001 PINMUX_DATA(SCL3_MARK, PTS0_FN),
1002
1003 /* PTT FN */
1004 PINMUX_DATA(PWMX7_MARK, PS5_7_FN1, PTT7_FN),
1005 PINMUX_DATA(AUDATA3_MARK, PS5_7_FN2, PTT7_FN),
1006 PINMUX_DATA(PWMX6_MARK, PS5_6_FN1, PTT6_FN),
1007 PINMUX_DATA(AUDATA2_MARK, PS5_6_FN2, PTT6_FN),
1008 PINMUX_DATA(PWMX5_MARK, PS5_5_FN1, PTT5_FN),
1009 PINMUX_DATA(AUDATA1_MARK, PS5_5_FN2, PTT5_FN),
1010 PINMUX_DATA(PWMX4_MARK, PS5_4_FN1, PTT4_FN),
1011 PINMUX_DATA(AUDATA0_MARK, PS5_4_FN2, PTT4_FN),
1012 PINMUX_DATA(PWMX3_MARK, PS5_3_FN1, PTT3_FN),
1013 PINMUX_DATA(STATUS1_MARK, PS5_3_FN2, PTT3_FN),
1014 PINMUX_DATA(PWMX2_MARK, PS5_2_FN1, PTT2_FN),
1015 PINMUX_DATA(STATUS0_MARK, PS5_2_FN2, PTT2_FN),
1016 PINMUX_DATA(PWMX1_MARK, PTT1_FN),
1017 PINMUX_DATA(PWMX0_MARK, PTT0_FN),
1018
1019 /* PTU FN */
1020 PINMUX_DATA(LGPIO7_MARK, PS6_15_FN1, PTU7_FN),
1021 PINMUX_DATA(APMONCTL_O_MARK, PS6_15_FN2, PTU7_FN),
1022 PINMUX_DATA(LGPIO6_MARK, PS6_14_FN1, PTU6_FN),
1023 PINMUX_DATA(APMPWBTOUT_O_MARK, PS6_14_FN2, PTU6_FN),
1024 PINMUX_DATA(LGPIO5_MARK, PS6_13_FN1, PTU5_FN),
1025 PINMUX_DATA(APMSCI_O_MARK, PS6_13_FN2, PTU5_FN),
1026 PINMUX_DATA(LGPIO4_MARK, PS6_12_FN1, PTU4_FN),
1027 PINMUX_DATA(APMVDDON_MARK, PS6_12_FN2, PTU4_FN),
1028 PINMUX_DATA(LGPIO3_MARK, PS6_11_FN1, PTU3_FN),
1029 PINMUX_DATA(APMSLPBTN_MARK, PS6_11_FN2, PTU3_FN),
1030 PINMUX_DATA(LGPIO2_MARK, PS6_10_FN1, PTU2_FN),
1031 PINMUX_DATA(APMPWRBTN_MARK, PS6_10_FN2, PTU2_FN),
1032 PINMUX_DATA(LGPIO1_MARK, PS6_9_FN1, PTU1_FN),
1033 PINMUX_DATA(APMS5N_MARK, PS6_9_FN2, PTU1_FN),
1034 PINMUX_DATA(LGPIO0_MARK, PS6_8_FN1, PTU0_FN),
1035 PINMUX_DATA(APMS3N_MARK, PS6_8_FN2, PTU0_FN),
1036
1037 /* PTV FN */
1038 PINMUX_DATA(A23_MARK, PS6_7_FN1, PTV7_FN),
1039 PINMUX_DATA(COM2_RI_MARK, PS6_7_FN2, PTV7_FN),
1040 PINMUX_DATA(A22_MARK, PS6_6_FN1, PTV6_FN),
1041 PINMUX_DATA(R_SPI_MOSI_MARK, PS6_6_FN2, PTV6_FN),
1042 PINMUX_DATA(A21_MARK, PS6_5_FN1, PTV5_FN),
1043 PINMUX_DATA(R_SPI_MISO_MARK, PS6_5_FN2, PTV5_FN),
1044 PINMUX_DATA(A20_MARK, PS6_4_FN1, PTV4_FN),
1045 PINMUX_DATA(R_SPI_RSPCK_MARK, PS6_4_FN2, PTV4_FN),
1046 PINMUX_DATA(A19_MARK, PS6_3_FN1, PTV3_FN),
1047 PINMUX_DATA(R_SPI_SSL0_MARK, PS6_3_FN2, PTV3_FN),
1048 PINMUX_DATA(A18_MARK, PS6_2_FN1, PTV2_FN),
1049 PINMUX_DATA(R_SPI_SSL1_MARK, PS6_2_FN2, PTV2_FN),
1050 PINMUX_DATA(A17_MARK, PS6_1_FN1, PTV1_FN),
1051 PINMUX_DATA(EVENT7_MARK, PS6_1_FN2, PTV1_FN),
1052 PINMUX_DATA(A16_MARK, PS6_0_FN1, PTV0_FN),
1053 PINMUX_DATA(EVENT6_MARK, PS6_0_FN1, PTV0_FN),
1054
1055 /* PTW FN */
1056 PINMUX_DATA(A15_MARK, PS7_15_FN1, PTW7_FN),
1057 PINMUX_DATA(EVENT5_MARK, PS7_15_FN2, PTW7_FN),
1058 PINMUX_DATA(A14_MARK, PS7_14_FN1, PTW6_FN),
1059 PINMUX_DATA(EVENT4_MARK, PS7_14_FN2, PTW6_FN),
1060 PINMUX_DATA(A13_MARK, PS7_13_FN1, PTW5_FN),
1061 PINMUX_DATA(EVENT3_MARK, PS7_13_FN2, PTW5_FN),
1062 PINMUX_DATA(A12_MARK, PS7_12_FN1, PTW4_FN),
1063 PINMUX_DATA(EVENT2_MARK, PS7_12_FN2, PTW4_FN),
1064 PINMUX_DATA(A11_MARK, PS7_11_FN1, PTW3_FN),
1065 PINMUX_DATA(EVENT1_MARK, PS7_11_FN2, PTW3_FN),
1066 PINMUX_DATA(A10_MARK, PS7_10_FN1, PTW2_FN),
1067 PINMUX_DATA(EVENT0_MARK, PS7_10_FN2, PTW2_FN),
1068 PINMUX_DATA(A9_MARK, PS7_9_FN1, PTW1_FN),
1069 PINMUX_DATA(CTS4_MARK, PS7_9_FN2, PTW1_FN),
1070 PINMUX_DATA(A8_MARK, PS7_8_FN1, PTW0_FN),
1071 PINMUX_DATA(CTS2_MARK, PS7_8_FN2, PTW0_FN),
1072
1073 /* PTX FN */
1074 PINMUX_DATA(A7_MARK, PS7_7_FN1, PTX7_FN),
1075 PINMUX_DATA(RTS2_MARK, PS7_7_FN2, PTX7_FN),
1076 PINMUX_DATA(A6_MARK, PS7_6_FN1, PTX6_FN),
1077 PINMUX_DATA(SIM_D_MARK, PS7_6_FN2, PTX6_FN),
1078 PINMUX_DATA(A5_MARK, PS7_5_FN1, PTX5_FN),
1079 PINMUX_DATA(SIM_CLK_MARK, PS7_5_FN2, PTX5_FN),
1080 PINMUX_DATA(A4_MARK, PS7_4_FN1, PTX4_FN),
1081 PINMUX_DATA(SIM_RST_MARK, PS7_4_FN2, PTX4_FN),
1082 PINMUX_DATA(A3_MARK, PTX3_FN),
1083 PINMUX_DATA(A2_MARK, PTX2_FN),
1084 PINMUX_DATA(A1_MARK, PTX1_FN),
1085 PINMUX_DATA(A0_MARK, PTX0_FN),
1086
1087 /* PTY FN */
1088 PINMUX_DATA(D7_MARK, PTY7_FN),
1089 PINMUX_DATA(D6_MARK, PTY6_FN),
1090 PINMUX_DATA(D5_MARK, PTY5_FN),
1091 PINMUX_DATA(D4_MARK, PTY4_FN),
1092 PINMUX_DATA(D3_MARK, PTY3_FN),
1093 PINMUX_DATA(D2_MARK, PTY2_FN),
1094 PINMUX_DATA(D1_MARK, PTY1_FN),
1095 PINMUX_DATA(D0_MARK, PTY0_FN),
1096
1097 /* PTZ FN */
1098 PINMUX_DATA(MMCDAT7_MARK, PS8_15_FN1, PTZ7_FN),
1099 PINMUX_DATA(ON_DQ7_MARK, PS8_15_FN2, PTZ7_FN),
1100 PINMUX_DATA(MMCDAT6_MARK, PS8_14_FN1, PTZ6_FN),
1101 PINMUX_DATA(ON_DQ6_MARK, PS8_14_FN2, PTZ6_FN),
1102 PINMUX_DATA(MMCDAT5_MARK, PS8_13_FN1, PTZ5_FN),
1103 PINMUX_DATA(ON_DQ5_MARK, PS8_13_FN2, PTZ5_FN),
1104 PINMUX_DATA(MMCDAT4_MARK, PS8_12_FN1, PTZ4_FN),
1105 PINMUX_DATA(ON_DQ4_MARK, PS8_12_FN2, PTZ4_FN),
1106 PINMUX_DATA(MMCDAT3_MARK, PS8_11_FN1, PTZ3_FN),
1107 PINMUX_DATA(ON_DQ3_MARK, PS8_11_FN2, PTZ3_FN),
1108 PINMUX_DATA(MMCDAT2_MARK, PS8_10_FN1, PTZ2_FN),
1109 PINMUX_DATA(ON_DQ2_MARK, PS8_10_FN2, PTZ2_FN),
1110 PINMUX_DATA(MMCDAT1_MARK, PS8_9_FN1, PTZ1_FN),
1111 PINMUX_DATA(ON_DQ1_MARK, PS8_9_FN2, PTZ1_FN),
1112 PINMUX_DATA(MMCDAT0_MARK, PS8_8_FN1, PTZ0_FN),
1113 PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN),
1114};
1115
1116static struct pinmux_gpio pinmux_gpios[] = {
1117 /* PTA */
1118 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
1119 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
1120 PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
1121 PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
1122 PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
1123 PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
1124 PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
1125 PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
1126
1127 /* PTB */
1128 PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
1129 PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
1130 PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
1131 PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
1132 PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
1133 PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
1134 PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
1135 PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
1136
1137 /* PTC */
1138 PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
1139 PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
1140 PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
1141 PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
1142 PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
1143 PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
1144 PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
1145 PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
1146
1147 /* PTD */
1148 PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
1149 PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
1150 PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
1151 PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
1152 PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
1153 PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
1154 PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
1155 PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
1156
1157 /* PTE */
1158 PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
1159 PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
1160 PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
1161 PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
1162 PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
1163 PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
1164 PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
1165 PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
1166
1167 /* PTF */
1168 PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
1169 PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
1170 PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
1171 PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
1172 PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
1173 PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
1174 PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
1175 PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
1176
1177 /* PTG */
1178 PINMUX_GPIO(GPIO_PTG7, PTG7_DATA),
1179 PINMUX_GPIO(GPIO_PTG6, PTG6_DATA),
1180 PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
1181 PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
1182 PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
1183 PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
1184 PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
1185 PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
1186
1187 /* PTH */
1188 PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
1189 PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
1190 PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
1191 PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
1192 PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
1193 PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
1194 PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
1195 PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
1196
1197 /* PTI */
1198 PINMUX_GPIO(GPIO_PTI7, PTI7_DATA),
1199 PINMUX_GPIO(GPIO_PTI6, PTI6_DATA),
1200 PINMUX_GPIO(GPIO_PTI5, PTI5_DATA),
1201 PINMUX_GPIO(GPIO_PTI4, PTI4_DATA),
1202 PINMUX_GPIO(GPIO_PTI3, PTI3_DATA),
1203 PINMUX_GPIO(GPIO_PTI2, PTI2_DATA),
1204 PINMUX_GPIO(GPIO_PTI1, PTI1_DATA),
1205 PINMUX_GPIO(GPIO_PTI0, PTI0_DATA),
1206
1207 /* PTJ */
1208 PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
1209 PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
1210 PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA),
1211 PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
1212 PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
1213 PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
1214 PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
1215
1216 /* PTK */
1217 PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
1218 PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
1219 PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
1220 PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
1221 PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
1222 PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
1223 PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
1224 PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
1225
1226 /* PTL */
1227 PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
1228 PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
1229 PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
1230 PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
1231 PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
1232 PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
1233 PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
1234
1235 /* PTM */
1236 PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
1237 PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
1238 PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
1239 PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
1240 PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
1241 PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
1242 PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
1243 PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
1244
1245 /* PTN */
1246 PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
1247 PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
1248 PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
1249 PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
1250 PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
1251 PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
1252 PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
1253
1254 /* PTO */
1255 PINMUX_GPIO(GPIO_PTO7, PTO7_DATA),
1256 PINMUX_GPIO(GPIO_PTO6, PTO6_DATA),
1257 PINMUX_GPIO(GPIO_PTO5, PTO5_DATA),
1258 PINMUX_GPIO(GPIO_PTO4, PTO4_DATA),
1259 PINMUX_GPIO(GPIO_PTO3, PTO3_DATA),
1260 PINMUX_GPIO(GPIO_PTO2, PTO2_DATA),
1261 PINMUX_GPIO(GPIO_PTO1, PTO1_DATA),
1262 PINMUX_GPIO(GPIO_PTO0, PTO0_DATA),
1263
1264 /* PTP */
1265 PINMUX_GPIO(GPIO_PTP7, PTP7_DATA),
1266 PINMUX_GPIO(GPIO_PTP6, PTP6_DATA),
1267 PINMUX_GPIO(GPIO_PTP5, PTP5_DATA),
1268 PINMUX_GPIO(GPIO_PTP4, PTP4_DATA),
1269 PINMUX_GPIO(GPIO_PTP3, PTP3_DATA),
1270 PINMUX_GPIO(GPIO_PTP2, PTP2_DATA),
1271 PINMUX_GPIO(GPIO_PTP1, PTP1_DATA),
1272 PINMUX_GPIO(GPIO_PTP0, PTP0_DATA),
1273
1274 /* PTQ */
1275 PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
1276 PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
1277 PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
1278 PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
1279 PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
1280 PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
1281 PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
1282
1283 /* PTR */
1284 PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
1285 PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
1286 PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
1287 PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
1288 PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
1289 PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
1290 PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
1291 PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
1292
1293 /* PTS */
1294 PINMUX_GPIO(GPIO_PTS7, PTS7_DATA),
1295 PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
1296 PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
1297 PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
1298 PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
1299 PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
1300 PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
1301 PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
1302
1303 /* PTT */
1304 PINMUX_GPIO(GPIO_PTT7, PTT7_DATA),
1305 PINMUX_GPIO(GPIO_PTT6, PTT6_DATA),
1306 PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
1307 PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
1308 PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
1309 PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
1310 PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
1311 PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
1312
1313 /* PTU */
1314 PINMUX_GPIO(GPIO_PTU7, PTU7_DATA),
1315 PINMUX_GPIO(GPIO_PTU6, PTU6_DATA),
1316 PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
1317 PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
1318 PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
1319 PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
1320 PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
1321 PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
1322
1323 /* PTV */
1324 PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
1325 PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
1326 PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
1327 PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
1328 PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
1329 PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
1330 PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
1331 PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
1332
1333 /* PTW */
1334 PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
1335 PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
1336 PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
1337 PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
1338 PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
1339 PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
1340 PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
1341 PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
1342
1343 /* PTX */
1344 PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
1345 PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
1346 PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
1347 PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
1348 PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
1349 PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
1350 PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
1351 PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
1352
1353 /* PTY */
1354 PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
1355 PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
1356 PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
1357 PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
1358 PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
1359 PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
1360 PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
1361 PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
1362
1363 /* PTZ */
1364 PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
1365 PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
1366 PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
1367 PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
1368 PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
1369 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
1370 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1371 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1372
1373 /* PTA (mobule: LBSC, RGMII) */
1374 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
1375 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
1376 PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK),
1377 PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK),
1378 PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK),
1379 PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDC_MARK),
1380 PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK),
1381 PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDC_MARK),
1382
1383 /* PTB (mobule: INTC, ONFI, TMU) */
1384 PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK),
1385 PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK),
1386 PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK),
1387 PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK),
1388 PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK),
1389 PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK),
1390 PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK),
1391 PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK),
1392 PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK),
1393 PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK),
1394 PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK),
1395 PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK),
1396 PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK),
1397 PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK),
1398 PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK),
1399 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
1400
1401 /* PTC (mobule: IRQ, PWMU) */
1402 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
1403 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
1404 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
1405 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
1406 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
1407 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
1408 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
1409 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
1410 PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK),
1411 PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK),
1412 PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK),
1413 PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK),
1414 PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK),
1415 PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK),
1416
1417 /* PTD (mobule: SPI0, DMAC) */
1418 PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK),
1419 PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK),
1420 PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK),
1421 PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK),
1422 PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK),
1423 PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK),
1424 PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK),
1425 PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK),
1426 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
1427 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
1428 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
1429
1430 /* PTE (mobule: RMII) */
1431 PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK),
1432 PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK),
1433 PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK),
1434 PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK),
1435 PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK),
1436 PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK),
1437 PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK),
1438 PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK),
1439
1440 /* PTF (mobule: RMII, SerMux) */
1441 PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK),
1442 PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK),
1443 PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK),
1444 PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK),
1445 PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK),
1446 PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK),
1447 PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK),
1448 PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK),
1449 PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK),
1450
1451 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
1452 PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK),
1453 PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK),
1454 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1455 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1456 PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK),
1457 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
1458 PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK),
1459 PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK),
1460 PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK),
1461 PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK),
1462
1463 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
1464 PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK),
1465 PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK),
1466 PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK),
1467 PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK),
1468 PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK),
1469 PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK),
1470 PINMUX_GPIO(GPIO_FN_WP, WP_MARK),
1471 PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK),
1472 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
1473 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
1474 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
1475 PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK),
1476 PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK),
1477
1478 /* PTI (mobule: LBSC, SDHI) */
1479 PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
1480 PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
1481 PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
1482 PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
1483 PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
1484 PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
1485 PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
1486 PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
1487 PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK),
1488 PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK),
1489 PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK),
1490 PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK),
1491 PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK),
1492 PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK),
1493 PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK),
1494 PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK),
1495
1496 /* PTJ (mobule: SCIF234, SERMUX) */
1497 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
1498 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
1499 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
1500 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
1501 PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK),
1502 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
1503 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
1504
1505 /* PTK (mobule: SERMUX, LBSC, SCIF) */
1506 PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK),
1507 PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK),
1508 PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK),
1509 PINMUX_GPIO(GPIO_FN_COM2_CTS, COM2_CTS_MARK),
1510 PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK),
1511 PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK),
1512 PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK),
1513 PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK),
1514 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
1515 PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
1516 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
1517
1518 /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
1519 PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK),
1520 PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK),
1521 PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK),
1522 PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK),
1523 PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK),
1524 PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK),
1525 PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK),
1526 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
1527 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
1528 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
1529 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
1530 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
1531 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
1532
1533 /* PTM (mobule: LBSC, IIC) */
1534 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
1535 PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
1536 PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK),
1537 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
1538 PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK),
1539 PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK),
1540 PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK),
1541 PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK),
1542
1543 /* PTN (mobule: USB, JMC, SGPIO, WDT) */
1544 PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK),
1545 PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK),
1546 PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK),
1547 PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK),
1548 PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK),
1549 PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK),
1550 PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK),
1551 PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK),
1552 PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK),
1553 PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK),
1554 PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK),
1555 PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK),
1556
1557 /* PTO (mobule: SGPIO, SerMux) */
1558 PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK),
1559 PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK),
1560 PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK),
1561 PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK),
1562 PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK),
1563 PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK),
1564 PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK),
1565 PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK),
1566 PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK),
1567 PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK),
1568 PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK),
1569 PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK),
1570
1571 /* PTP (mobule: EVC, ADC) */
1572
1573 /* PTQ (mobule: LPC) */
1574 PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK),
1575 PINMUX_GPIO(GPIO_FN_LAD2, LAD2_MARK),
1576 PINMUX_GPIO(GPIO_FN_LAD1, LAD1_MARK),
1577 PINMUX_GPIO(GPIO_FN_LAD0, LAD0_MARK),
1578 PINMUX_GPIO(GPIO_FN_LFRAME, LFRAME_MARK),
1579 PINMUX_GPIO(GPIO_FN_LRESET, LRESET_MARK),
1580 PINMUX_GPIO(GPIO_FN_LCLK, LCLK_MARK),
1581
1582 /* PTR (mobule: GRA, IIC) */
1583 PINMUX_GPIO(GPIO_FN_DDC3, DDC3_MARK),
1584 PINMUX_GPIO(GPIO_FN_DDC2, DDC2_MARK),
1585 PINMUX_GPIO(GPIO_FN_SDA8, SDA8_MARK),
1586 PINMUX_GPIO(GPIO_FN_SCL8, SCL8_MARK),
1587 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
1588 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
1589 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
1590 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
1591 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
1592 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
1593
1594 /* PTS (mobule: GRA, IIC) */
1595 PINMUX_GPIO(GPIO_FN_DDC1, DDC1_MARK),
1596 PINMUX_GPIO(GPIO_FN_DDC0, DDC0_MARK),
1597 PINMUX_GPIO(GPIO_FN_SDA9, SDA9_MARK),
1598 PINMUX_GPIO(GPIO_FN_SCL9, SCL9_MARK),
1599 PINMUX_GPIO(GPIO_FN_SDA5, SDA5_MARK),
1600 PINMUX_GPIO(GPIO_FN_SCL5, SCL5_MARK),
1601 PINMUX_GPIO(GPIO_FN_SDA4, SDA4_MARK),
1602 PINMUX_GPIO(GPIO_FN_SCL4, SCL4_MARK),
1603 PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
1604 PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
1605
1606 /* PTT (mobule: PWMX, AUD) */
1607 PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK),
1608 PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK),
1609 PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK),
1610 PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK),
1611 PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK),
1612 PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK),
1613 PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK),
1614 PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK),
1615 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
1616 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
1617 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
1618 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
1619 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
1620 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
1621
1622 /* PTU (mobule: LPC, APM) */
1623 PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK),
1624 PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK),
1625 PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK),
1626 PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK),
1627 PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK),
1628 PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK),
1629 PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK),
1630 PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK),
1631 PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK),
1632 PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK),
1633 PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK),
1634 PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK),
1635 PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK),
1636 PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK),
1637 PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK),
1638 PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK),
1639
1640 /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
1641 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
1642 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
1643 PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
1644 PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
1645 PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
1646 PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
1647 PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
1648 PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
1649 PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK),
1650 PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK),
1651 PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK),
1652 PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK),
1653 PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK),
1654 PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK),
1655 PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK),
1656 PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK),
1657 PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK),
1658 PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK),
1659 PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK),
1660 PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK),
1661
1662 /* PTW (mobule: LBSC, EVC, SCIF) */
1663 PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
1664 PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
1665 PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
1666 PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
1667 PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
1668 PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
1669 PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
1670 PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
1671 PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
1672 PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK),
1673 PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK),
1674 PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK),
1675 PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK),
1676 PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK),
1677 PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK),
1678 PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK),
1679 PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK),
1680
1681 /* PTX (mobule: LBSC) */
1682 PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
1683 PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
1684 PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
1685 PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
1686 PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
1687 PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
1688 PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
1689 PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
1690 PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK),
1691 PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
1692 PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
1693 PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
1694
1695 /* PTY (mobule: LBSC) */
1696 PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
1697 PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
1698 PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
1699 PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
1700 PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
1701 PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
1702 PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
1703 PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
1704
1705 /* PTZ (mobule: eMMC, ONFI) */
1706 PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK),
1707 PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK),
1708 PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK),
1709 PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK),
1710 PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK),
1711 PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK),
1712 PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK),
1713 PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK),
1714 PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK),
1715 PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK),
1716 PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK),
1717 PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK),
1718 PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK),
1719 PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK),
1720 PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK),
1721 PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK),
1722 };
1723
1724static struct pinmux_cfg_reg pinmux_config_regs[] = {
1725 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
1726 PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU,
1727 PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU,
1728 PTA5_FN, PTA5_OUT, PTA5_IN, PTA5_IN_PU,
1729 PTA4_FN, PTA4_OUT, PTA4_IN, PTA4_IN_PU,
1730 PTA3_FN, PTA3_OUT, PTA3_IN, PTA3_IN_PU,
1731 PTA2_FN, PTA2_OUT, PTA2_IN, PTA2_IN_PU,
1732 PTA1_FN, PTA1_OUT, PTA1_IN, PTA1_IN_PU,
1733 PTA0_FN, PTA0_OUT, PTA0_IN, PTA0_IN_PU }
1734 },
1735 { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) {
1736 PTB7_FN, PTB7_OUT, PTB7_IN, 0,
1737 PTB6_FN, PTB6_OUT, PTB6_IN, 0,
1738 PTB5_FN, PTB5_OUT, PTB5_IN, 0,
1739 PTB4_FN, PTB4_OUT, PTB4_IN, 0,
1740 PTB3_FN, PTB3_OUT, PTB3_IN, 0,
1741 PTB2_FN, PTB2_OUT, PTB2_IN, 0,
1742 PTB1_FN, PTB1_OUT, PTB1_IN, 0,
1743 PTB0_FN, PTB0_OUT, PTB0_IN, 0 }
1744 },
1745 { PINMUX_CFG_REG("PCCR", 0xffec0004, 16, 2) {
1746 PTC7_FN, PTC7_OUT, PTC7_IN, 0,
1747 PTC6_FN, PTC6_OUT, PTC6_IN, 0,
1748 PTC5_FN, PTC5_OUT, PTC5_IN, 0,
1749 PTC4_FN, PTC4_OUT, PTC4_IN, 0,
1750 PTC3_FN, PTC3_OUT, PTC3_IN, 0,
1751 PTC2_FN, PTC2_OUT, PTC2_IN, 0,
1752 PTC1_FN, PTC1_OUT, PTC1_IN, 0,
1753 PTC0_FN, PTC0_OUT, PTC0_IN, 0 }
1754 },
1755 { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) {
1756 PTD7_FN, PTD7_OUT, PTD7_IN, PTD7_IN_PU,
1757 PTD6_FN, PTD6_OUT, PTD6_IN, PTD6_IN_PU,
1758 PTD5_FN, PTD5_OUT, PTD5_IN, PTD5_IN_PU,
1759 PTD4_FN, PTD4_OUT, PTD4_IN, PTD4_IN_PU,
1760 PTD3_FN, PTD3_OUT, PTD3_IN, PTD3_IN_PU,
1761 PTD2_FN, PTD2_OUT, PTD2_IN, PTD2_IN_PU,
1762 PTD1_FN, PTD1_OUT, PTD1_IN, PTD1_IN_PU,
1763 PTD0_FN, PTD0_OUT, PTD0_IN, PTD0_IN_PU }
1764 },
1765 { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) {
1766 PTE7_FN, PTE7_OUT, PTE7_IN, PTE7_IN_PU,
1767 PTE6_FN, PTE6_OUT, PTE6_IN, PTE6_IN_PU,
1768 PTE5_FN, PTE5_OUT, PTE5_IN, PTE5_IN_PU,
1769 PTE4_FN, PTE4_OUT, PTE4_IN, PTE4_IN_PU,
1770 PTE3_FN, PTE3_OUT, PTE3_IN, PTE3_IN_PU,
1771 PTE2_FN, PTE2_OUT, PTE2_IN, PTE2_IN_PU,
1772 PTE1_FN, PTE1_OUT, PTE1_IN, PTE1_IN_PU,
1773 PTE0_FN, PTE0_OUT, PTE0_IN, PTE0_IN_PU }
1774 },
1775 { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) {
1776 PTF7_FN, PTF7_OUT, PTF7_IN, PTF7_IN_PU,
1777 PTF6_FN, PTF6_OUT, PTF6_IN, PTF6_IN_PU,
1778 PTF5_FN, PTF5_OUT, PTF5_IN, PTF5_IN_PU,
1779 PTF4_FN, PTF4_OUT, PTF4_IN, PTF4_IN_PU,
1780 PTF3_FN, PTF3_OUT, PTF3_IN, PTF3_IN_PU,
1781 PTF2_FN, PTF2_OUT, PTF2_IN, PTF2_IN_PU,
1782 PTF1_FN, PTF1_OUT, PTF1_IN, PTF1_IN_PU,
1783 PTF0_FN, PTF0_OUT, PTF0_IN, PTF0_IN_PU }
1784 },
1785 { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) {
1786 PTG7_FN, PTG7_OUT, PTG7_IN, PTG7_IN_PU ,
1787 PTG6_FN, PTG6_OUT, PTG6_IN, PTG6_IN_PU ,
1788 PTG5_FN, PTG5_OUT, PTG5_IN, 0,
1789 PTG4_FN, PTG4_OUT, PTG4_IN, PTG4_IN_PU ,
1790 PTG3_FN, PTG3_OUT, PTG3_IN, 0,
1791 PTG2_FN, PTG2_OUT, PTG2_IN, 0,
1792 PTG1_FN, PTG1_OUT, PTG1_IN, 0,
1793 PTG0_FN, PTG0_OUT, PTG0_IN, 0 }
1794 },
1795 { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) {
1796 PTH7_FN, PTH7_OUT, PTH7_IN, PTH7_IN_PU,
1797 PTH6_FN, PTH6_OUT, PTH6_IN, PTH6_IN_PU,
1798 PTH5_FN, PTH5_OUT, PTH5_IN, PTH5_IN_PU,
1799 PTH4_FN, PTH4_OUT, PTH4_IN, PTH4_IN_PU,
1800 PTH3_FN, PTH3_OUT, PTH3_IN, PTH3_IN_PU,
1801 PTH2_FN, PTH2_OUT, PTH2_IN, PTH2_IN_PU,
1802 PTH1_FN, PTH1_OUT, PTH1_IN, PTH1_IN_PU,
1803 PTH0_FN, PTH0_OUT, PTH0_IN, PTH0_IN_PU }
1804 },
1805 { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) {
1806 PTI7_FN, PTI7_OUT, PTI7_IN, PTI7_IN_PU,
1807 PTI6_FN, PTI6_OUT, PTI6_IN, PTI6_IN_PU,
1808 PTI5_FN, PTI5_OUT, PTI5_IN, 0,
1809 PTI4_FN, PTI4_OUT, PTI4_IN, PTI4_IN_PU,
1810 PTI3_FN, PTI3_OUT, PTI3_IN, PTI3_IN_PU,
1811 PTI2_FN, PTI2_OUT, PTI2_IN, PTI2_IN_PU,
1812 PTI1_FN, PTI1_OUT, PTI1_IN, PTI1_IN_PU,
1813 PTI0_FN, PTI0_OUT, PTI0_IN, PTI0_IN_PU }
1814 },
1815 { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) {
1816 0, 0, 0, 0, /* reserved: always set 1 */
1817 PTJ6_FN, PTJ6_OUT, PTJ6_IN, PTJ6_IN_PU,
1818 PTJ5_FN, PTJ5_OUT, PTJ5_IN, PTJ5_IN_PU,
1819 PTJ4_FN, PTJ4_OUT, PTJ4_IN, PTJ4_IN_PU,
1820 PTJ3_FN, PTJ3_OUT, PTJ3_IN, PTJ3_IN_PU,
1821 PTJ2_FN, PTJ2_OUT, PTJ2_IN, PTJ2_IN_PU,
1822 PTJ1_FN, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU,
1823 PTJ0_FN, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU }
1824 },
1825 { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) {
1826 PTK7_FN, PTK7_OUT, PTK7_IN, PTK7_IN_PU,
1827 PTK6_FN, PTK6_OUT, PTK6_IN, PTK6_IN_PU,
1828 PTK5_FN, PTK5_OUT, PTK5_IN, PTK5_IN_PU,
1829 PTK4_FN, PTK4_OUT, PTK4_IN, PTK4_IN_PU,
1830 PTK3_FN, PTK3_OUT, PTK3_IN, PTK3_IN_PU,
1831 PTK2_FN, PTK2_OUT, PTK2_IN, PTK2_IN_PU,
1832 PTK1_FN, PTK1_OUT, PTK1_IN, PTK1_IN_PU,
1833 PTK0_FN, PTK0_OUT, PTK0_IN, PTK0_IN_PU }
1834 },
1835 { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) {
1836 0, 0, 0, 0, /* reserved: always set 1 */
1837 PTL6_FN, PTL6_OUT, PTL6_IN, PTL6_IN_PU,
1838 PTL5_FN, PTL5_OUT, PTL5_IN, PTL5_IN_PU,
1839 PTL4_FN, PTL4_OUT, PTL4_IN, PTL4_IN_PU,
1840 PTL3_FN, PTL3_OUT, PTL3_IN, PTL3_IN_PU,
1841 PTL2_FN, PTL2_OUT, PTL2_IN, PTL2_IN_PU,
1842 PTL1_FN, PTL1_OUT, PTL1_IN, PTL1_IN_PU,
1843 PTL0_FN, PTL0_OUT, PTL0_IN, PTL0_IN_PU }
1844 },
1845 { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) {
1846 PTM7_FN, PTM7_OUT, PTM7_IN, PTM7_IN_PU,
1847 PTM6_FN, PTM6_OUT, PTM6_IN, PTM6_IN_PU,
1848 PTM5_FN, PTM5_OUT, PTM5_IN, PTM5_IN_PU,
1849 PTM4_FN, PTM4_OUT, PTM4_IN, PTM4_IN_PU,
1850 PTM3_FN, PTM3_OUT, PTM3_IN, 0,
1851 PTM2_FN, PTM2_OUT, PTM2_IN, 0,
1852 PTM1_FN, PTM1_OUT, PTM1_IN, 0,
1853 PTM0_FN, PTM0_OUT, PTM0_IN, 0 }
1854 },
1855 { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) {
1856 0, 0, 0, 0, /* reserved: always set 1 */
1857 PTN6_FN, PTN6_OUT, PTN6_IN, 0,
1858 PTN5_FN, PTN5_OUT, PTN5_IN, 0,
1859 PTN4_FN, PTN4_OUT, PTN4_IN, PTN4_IN_PU,
1860 PTN3_FN, PTN3_OUT, PTN3_IN, PTN3_IN_PU,
1861 PTN2_FN, PTN2_OUT, PTN2_IN, PTN2_IN_PU,
1862 PTN1_FN, PTN1_OUT, PTN1_IN, PTN1_IN_PU,
1863 PTN0_FN, PTN0_OUT, PTN0_IN, PTN0_IN_PU }
1864 },
1865 { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) {
1866 PTO7_FN, PTO7_OUT, PTO7_IN, PTO7_IN_PU,
1867 PTO6_FN, PTO6_OUT, PTO6_IN, PTO6_IN_PU,
1868 PTO5_FN, PTO5_OUT, PTO5_IN, PTO5_IN_PU,
1869 PTO4_FN, PTO4_OUT, PTO4_IN, PTO4_IN_PU,
1870 PTO3_FN, PTO3_OUT, PTO3_IN, PTO3_IN_PU,
1871 PTO2_FN, PTO2_OUT, PTO2_IN, PTO2_IN_PU,
1872 PTO1_FN, PTO1_OUT, PTO1_IN, PTO1_IN_PU,
1873 PTO0_FN, PTO0_OUT, PTO0_IN, PTO0_IN_PU }
1874 },
1875#if 0 /* FIXME: Remove it? */
1876 { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) {
1877 0, 0, 0, 0, /* reserved: always set 1 */
1878 PTP6_FN, PTP6_OUT, PTP6_IN, 0,
1879 PTP5_FN, PTP5_OUT, PTP5_IN, 0,
1880 PTP4_FN, PTP4_OUT, PTP4_IN, 0,
1881 PTP3_FN, PTP3_OUT, PTP3_IN, 0,
1882 PTP2_FN, PTP2_OUT, PTP2_IN, 0,
1883 PTP1_FN, PTP1_OUT, PTP1_IN, 0,
1884 PTP0_FN, PTP0_OUT, PTP0_IN, 0 }
1885 },
1886#endif
1887 { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) {
1888 0, 0, 0, 0, /* reserved: always set 1 */
1889 PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0,
1890 PTQ5_FN, PTQ5_OUT, PTQ5_IN, 0,
1891 PTQ4_FN, PTQ4_OUT, PTQ4_IN, 0,
1892 PTQ3_FN, PTQ3_OUT, PTQ3_IN, 0,
1893 PTQ2_FN, PTQ2_OUT, PTQ2_IN, 0,
1894 PTQ1_FN, PTQ1_OUT, PTQ1_IN, 0,
1895 PTQ0_FN, PTQ0_OUT, PTQ0_IN, 0 }
1896 },
1897 { PINMUX_CFG_REG("PRCR", 0xffec0022, 16, 2) {
1898 PTR7_FN, PTR7_OUT, PTR7_IN, 0,
1899 PTR6_FN, PTR6_OUT, PTR6_IN, 0,
1900 PTR5_FN, PTR5_OUT, PTR5_IN, 0,
1901 PTR4_FN, PTR4_OUT, PTR4_IN, 0,
1902 PTR3_FN, PTR3_OUT, PTR3_IN, 0,
1903 PTR2_FN, PTR2_OUT, PTR2_IN, 0,
1904 PTR1_FN, PTR1_OUT, PTR1_IN, 0,
1905 PTR0_FN, PTR0_OUT, PTR0_IN, 0 }
1906 },
1907 { PINMUX_CFG_REG("PSCR", 0xffec0024, 16, 2) {
1908 PTS7_FN, PTS7_OUT, PTS7_IN, 0,
1909 PTS6_FN, PTS6_OUT, PTS6_IN, 0,
1910 PTS5_FN, PTS5_OUT, PTS5_IN, 0,
1911 PTS4_FN, PTS4_OUT, PTS4_IN, 0,
1912 PTS3_FN, PTS3_OUT, PTS3_IN, 0,
1913 PTS2_FN, PTS2_OUT, PTS2_IN, 0,
1914 PTS1_FN, PTS1_OUT, PTS1_IN, 0,
1915 PTS0_FN, PTS0_OUT, PTS0_IN, 0 }
1916 },
1917 { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) {
1918 PTT7_FN, PTT7_OUT, PTT7_IN, PTO7_IN_PU,
1919 PTT6_FN, PTT6_OUT, PTT6_IN, PTO6_IN_PU,
1920 PTT5_FN, PTT5_OUT, PTT5_IN, PTO5_IN_PU,
1921 PTT4_FN, PTT4_OUT, PTT4_IN, PTO4_IN_PU,
1922 PTT3_FN, PTT3_OUT, PTT3_IN, PTO3_IN_PU,
1923 PTT2_FN, PTT2_OUT, PTT2_IN, PTO2_IN_PU,
1924 PTT1_FN, PTT1_OUT, PTT1_IN, PTO1_IN_PU,
1925 PTT0_FN, PTT0_OUT, PTT0_IN, PTO0_IN_PU }
1926 },
1927 { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) {
1928 PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU,
1929 PTU6_FN, PTU6_OUT, PTU6_IN, PTU6_IN_PU,
1930 PTU5_FN, PTU5_OUT, PTU5_IN, PTU5_IN_PU,
1931 PTU4_FN, PTU4_OUT, PTU4_IN, PTU4_IN_PU,
1932 PTU3_FN, PTU3_OUT, PTU3_IN, PTU3_IN_PU,
1933 PTU2_FN, PTU2_OUT, PTU2_IN, PTU2_IN_PU,
1934 PTU1_FN, PTU1_OUT, PTU1_IN, PTU1_IN_PU,
1935 PTU0_FN, PTU0_OUT, PTU0_IN, PTU0_IN_PU }
1936 },
1937 { PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2) {
1938 PTV7_FN, PTV7_OUT, PTV7_IN, PTV7_IN_PU,
1939 PTV6_FN, PTV6_OUT, PTV6_IN, PTV6_IN_PU,
1940 PTV5_FN, PTV5_OUT, PTV5_IN, PTV5_IN_PU,
1941 PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU,
1942 PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU,
1943 PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU,
1944 PTV1_FN, PTV1_OUT, PTV1_IN, 0,
1945 PTV0_FN, PTV0_OUT, PTV0_IN, 0 }
1946 },
1947 { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) {
1948 PTW7_FN, PTW7_OUT, PTW7_IN, 0,
1949 PTW6_FN, PTW6_OUT, PTW6_IN, 0,
1950 PTW5_FN, PTW5_OUT, PTW5_IN, 0,
1951 PTW4_FN, PTW4_OUT, PTW4_IN, 0,
1952 PTW3_FN, PTW3_OUT, PTW3_IN, 0,
1953 PTW2_FN, PTW2_OUT, PTW2_IN, 0,
1954 PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU,
1955 PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU }
1956 },
1957 { PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2) {
1958 PTX7_FN, PTX7_OUT, PTX7_IN, PTX7_IN_PU,
1959 PTX6_FN, PTX6_OUT, PTX6_IN, PTX6_IN_PU,
1960 PTX5_FN, PTX5_OUT, PTX5_IN, PTX5_IN_PU,
1961 PTX4_FN, PTX4_OUT, PTX4_IN, PTX4_IN_PU,
1962 PTX3_FN, PTX3_OUT, PTX3_IN, PTX3_IN_PU,
1963 PTX2_FN, PTX2_OUT, PTX2_IN, PTX2_IN_PU,
1964 PTX1_FN, PTX1_OUT, PTX1_IN, PTX1_IN_PU,
1965 PTX0_FN, PTX0_OUT, PTX0_IN, PTX0_IN_PU }
1966 },
1967 { PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2) {
1968 PTY7_FN, PTY7_OUT, PTY7_IN, PTY7_IN_PU,
1969 PTY6_FN, PTY6_OUT, PTY6_IN, PTY6_IN_PU,
1970 PTY5_FN, PTY5_OUT, PTY5_IN, PTY5_IN_PU,
1971 PTY4_FN, PTY4_OUT, PTY4_IN, PTY4_IN_PU,
1972 PTY3_FN, PTY3_OUT, PTY3_IN, PTY3_IN_PU,
1973 PTY2_FN, PTY2_OUT, PTY2_IN, PTY2_IN_PU,
1974 PTY1_FN, PTY1_OUT, PTY1_IN, PTY1_IN_PU,
1975 PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU }
1976 },
1977 { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) {
1978 PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0,
1979 PTZ6_FN, PTZ6_OUT, PTZ6_IN, 0,
1980 PTZ5_FN, PTZ5_OUT, PTZ5_IN, 0,
1981 PTZ4_FN, PTZ4_OUT, PTZ4_IN, 0,
1982 PTZ3_FN, PTZ3_OUT, PTZ3_IN, 0,
1983 PTZ2_FN, PTZ2_OUT, PTZ2_IN, 0,
1984 PTZ1_FN, PTZ1_OUT, PTZ1_IN, 0,
1985 PTZ0_FN, PTZ0_OUT, PTZ0_IN, 0 }
1986 },
1987
1988 { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) {
1989 PS0_15_FN1, PS0_15_FN2,
1990 PS0_14_FN1, PS0_14_FN2,
1991 PS0_13_FN1, PS0_13_FN2,
1992 PS0_12_FN1, PS0_12_FN2,
1993 PS0_11_FN1, PS0_11_FN2,
1994 PS0_10_FN1, PS0_10_FN2,
1995 PS0_9_FN1, PS0_9_FN2,
1996 PS0_8_FN1, PS0_8_FN2,
1997 PS0_7_FN1, PS0_7_FN2,
1998 PS0_6_FN1, PS0_6_FN2,
1999 PS0_5_FN1, PS0_5_FN2,
2000 PS0_4_FN1, PS0_4_FN2,
2001 PS0_3_FN1, PS0_3_FN2,
2002 PS0_2_FN1, PS0_2_FN2,
2003 0, 0,
2004 0, 0, }
2005 },
2006 { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) {
2007 0, 0,
2008 0, 0,
2009 0, 0,
2010 0, 0,
2011 0, 0,
2012 PS1_10_FN1, PS1_10_FN2,
2013 PS1_9_FN1, PS1_9_FN2,
2014 PS1_8_FN1, PS1_8_FN2,
2015 0, 0,
2016 0, 0,
2017 0, 0,
2018 0, 0,
2019 0, 0,
2020 PS1_2_FN1, PS1_2_FN2,
2021 0, 0,
2022 0, 0, }
2023 },
2024 { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) {
2025 0, 0,
2026 0, 0,
2027 PS2_13_FN1, PS2_13_FN2,
2028 PS2_12_FN1, PS2_12_FN2,
2029 0, 0,
2030 0, 0,
2031 0, 0,
2032 0, 0,
2033 PS2_7_FN1, PS2_7_FN2,
2034 PS2_6_FN1, PS2_6_FN2,
2035 PS2_5_FN1, PS2_5_FN2,
2036 PS2_4_FN1, PS2_4_FN2,
2037 0, 0,
2038 PS2_2_FN1, PS2_2_FN2,
2039 0, 0,
2040 0, 0, }
2041 },
2042 { PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1) {
2043 PS3_15_FN1, PS3_15_FN2,
2044 PS3_14_FN1, PS3_14_FN2,
2045 PS3_13_FN1, PS3_13_FN2,
2046 PS3_12_FN1, PS3_12_FN2,
2047 PS3_11_FN1, PS3_11_FN2,
2048 PS3_10_FN1, PS3_10_FN2,
2049 PS3_9_FN1, PS3_9_FN2,
2050 PS3_8_FN1, PS3_8_FN2,
2051 PS3_7_FN1, PS3_7_FN2,
2052 0, 0,
2053 0, 0,
2054 0, 0,
2055 0, 0,
2056 PS3_2_FN1, PS3_2_FN2,
2057 PS3_1_FN1, PS3_1_FN2,
2058 0, 0, }
2059 },
2060
2061 { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) {
2062 0, 0,
2063 PS4_14_FN1, PS4_14_FN2,
2064 PS4_13_FN1, PS4_13_FN2,
2065 PS4_12_FN1, PS4_12_FN2,
2066 0, 0,
2067 PS4_10_FN1, PS4_10_FN2,
2068 PS4_9_FN1, PS4_9_FN2,
2069 PS4_8_FN1, PS4_8_FN2,
2070 0, 0,
2071 0, 0,
2072 0, 0,
2073 PS4_4_FN1, PS4_4_FN2,
2074 PS4_3_FN1, PS4_3_FN2,
2075 PS4_2_FN1, PS4_2_FN2,
2076 PS4_1_FN1, PS4_1_FN2,
2077 PS4_0_FN1, PS4_0_FN2, }
2078 },
2079 { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) {
2080 0, 0,
2081 0, 0,
2082 0, 0,
2083 0, 0,
2084 PS5_11_FN1, PS5_11_FN2,
2085 PS5_10_FN1, PS5_10_FN2,
2086 PS5_9_FN1, PS5_9_FN2,
2087 PS5_8_FN1, PS5_8_FN2,
2088 PS5_7_FN1, PS5_7_FN2,
2089 PS5_6_FN1, PS5_6_FN2,
2090 PS5_5_FN1, PS5_5_FN2,
2091 PS5_4_FN1, PS5_4_FN2,
2092 PS5_3_FN1, PS5_3_FN2,
2093 PS5_2_FN1, PS5_2_FN2,
2094 0, 0,
2095 0, 0, }
2096 },
2097 { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) {
2098 PS6_15_FN1, PS6_15_FN2,
2099 PS6_14_FN1, PS6_14_FN2,
2100 PS6_13_FN1, PS6_13_FN2,
2101 PS6_12_FN1, PS6_12_FN2,
2102 PS6_11_FN1, PS6_11_FN2,
2103 PS6_10_FN1, PS6_10_FN2,
2104 PS6_9_FN1, PS6_9_FN2,
2105 PS6_8_FN1, PS6_8_FN2,
2106 PS6_7_FN1, PS6_7_FN2,
2107 PS6_6_FN1, PS6_6_FN2,
2108 PS6_5_FN1, PS6_5_FN2,
2109 PS6_4_FN1, PS6_4_FN2,
2110 PS6_3_FN1, PS6_3_FN2,
2111 PS6_2_FN1, PS6_2_FN2,
2112 PS6_1_FN1, PS6_1_FN2,
2113 PS6_0_FN1, PS6_0_FN2, }
2114 },
2115 { PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1) {
2116 PS7_15_FN1, PS7_15_FN2,
2117 PS7_14_FN1, PS7_14_FN2,
2118 PS7_13_FN1, PS7_13_FN2,
2119 PS7_12_FN1, PS7_12_FN2,
2120 PS7_11_FN1, PS7_11_FN2,
2121 PS7_10_FN1, PS7_10_FN2,
2122 PS7_9_FN1, PS7_9_FN2,
2123 PS7_8_FN1, PS7_8_FN2,
2124 PS7_7_FN1, PS7_7_FN2,
2125 PS7_6_FN1, PS7_6_FN2,
2126 PS7_5_FN1, PS7_5_FN2,
2127 0, 0,
2128 0, 0,
2129 0, 0,
2130 0, 0,
2131 0, 0, }
2132 },
2133 { PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1) {
2134 PS8_15_FN1, PS8_15_FN2,
2135 PS8_14_FN1, PS8_14_FN2,
2136 PS8_13_FN1, PS8_13_FN2,
2137 PS8_12_FN1, PS8_12_FN2,
2138 PS8_11_FN1, PS8_11_FN2,
2139 PS8_10_FN1, PS8_10_FN2,
2140 PS8_9_FN1, PS8_9_FN2,
2141 PS8_8_FN1, PS8_8_FN2,
2142 0, 0,
2143 0, 0,
2144 0, 0,
2145 0, 0,
2146 0, 0,
2147 0, 0,
2148 0, 0,
2149 0, 0, }
2150 },
2151 {}
2152};
2153
2154static struct pinmux_data_reg pinmux_data_regs[] = {
2155 { PINMUX_DATA_REG("PADR", 0xffec0034, 8) {
2156 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
2157 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
2158 },
2159 { PINMUX_DATA_REG("PBDR", 0xffec0036, 8) {
2160 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
2161 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
2162 },
2163 { PINMUX_DATA_REG("PCDR", 0xffec0038, 8) {
2164 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
2165 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
2166 },
2167 { PINMUX_DATA_REG("PDDR", 0xffec003a, 8) {
2168 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
2169 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
2170 },
2171 { PINMUX_DATA_REG("PEDR", 0xffec003c, 8) {
2172 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
2173 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
2174 },
2175 { PINMUX_DATA_REG("PFDR", 0xffec003e, 8) {
2176 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
2177 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
2178 },
2179 { PINMUX_DATA_REG("PGDR", 0xffec0040, 8) {
2180 PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
2181 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
2182 },
2183 { PINMUX_DATA_REG("PHDR", 0xffec0042, 8) {
2184 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
2185 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
2186 },
2187 { PINMUX_DATA_REG("PIDR", 0xffec0044, 8) {
2188 PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
2189 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA }
2190 },
2191 { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) {
2192 0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
2193 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
2194 },
2195 { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) {
2196 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
2197 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
2198 },
2199 { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) {
2200 0, PTL6_DATA, PTL5_DATA, PTL4_DATA,
2201 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
2202 },
2203 { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) {
2204 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
2205 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
2206 },
2207 { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) {
2208 0, PTN6_DATA, PTN5_DATA, PTN4_DATA,
2209 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
2210 },
2211 { PINMUX_DATA_REG("PODR", 0xffec0050, 8) {
2212 PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
2213 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA }
2214 },
2215 { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) {
2216 PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
2217 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
2218 },
2219 { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) {
2220 0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
2221 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
2222 },
2223 { PINMUX_DATA_REG("PRDR", 0xffec0056, 8) {
2224 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
2225 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
2226 },
2227 { PINMUX_DATA_REG("PSDR", 0xffec0058, 8) {
2228 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
2229 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
2230 },
2231 { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) {
2232 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
2233 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
2234 },
2235 { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) {
2236 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
2237 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
2238 },
2239 { PINMUX_DATA_REG("PVDR", 0xffec005e, 8) {
2240 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
2241 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
2242 },
2243 { PINMUX_DATA_REG("PWDR", 0xffec0060, 8) {
2244 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
2245 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
2246 },
2247 { PINMUX_DATA_REG("PXDR", 0xffec0062, 8) {
2248 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
2249 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
2250 },
2251 { PINMUX_DATA_REG("PYDR", 0xffec0064, 8) {
2252 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
2253 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
2254 },
2255 { PINMUX_DATA_REG("PZDR", 0xffec0066, 8) {
2256 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
2257 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
2258 },
2259 { },
2260};
2261
2262static struct pinmux_info sh7757_pinmux_info = {
2263 .name = "sh7757_pfc",
2264 .reserved_id = PINMUX_RESERVED,
2265 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2266 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2267 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
2268 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2269 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2270 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2271
2272 .first_gpio = GPIO_PTA0,
2273 .last_gpio = GPIO_FN_ON_DQ0,
2274
2275 .gpios = pinmux_gpios,
2276 .cfg_regs = pinmux_config_regs,
2277 .data_regs = pinmux_data_regs,
2278
2279 .gpio_data = pinmux_data,
2280 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2281};
2282
2283static int __init plat_pinmux_setup(void)
2284{
2285 return register_pinmux(&sh7757_pinmux_info);
2286}
2287arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
new file mode 100644
index 000000000000..aaa5338abbff
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
@@ -0,0 +1,587 @@
1/*
2 * SH-X3 prototype CPU pinmux
3 *
4 * Copyright (C) 2010 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/gpio.h>
13#include <cpu/shx3.h>
14
15enum {
16 PINMUX_RESERVED = 0,
17
18 PINMUX_DATA_BEGIN,
19 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
20 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
21 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
22 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
23 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
24 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
25 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
26 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
27 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
28 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
29 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
30 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
31 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
32 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
33
34 PH5_DATA, PH4_DATA,
35 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
36 PINMUX_DATA_END,
37
38 PINMUX_INPUT_BEGIN,
39 PA7_IN, PA6_IN, PA5_IN, PA4_IN,
40 PA3_IN, PA2_IN, PA1_IN, PA0_IN,
41 PB7_IN, PB6_IN, PB5_IN, PB4_IN,
42 PB3_IN, PB2_IN, PB1_IN, PB0_IN,
43 PC7_IN, PC6_IN, PC5_IN, PC4_IN,
44 PC3_IN, PC2_IN, PC1_IN, PC0_IN,
45 PD7_IN, PD6_IN, PD5_IN, PD4_IN,
46 PD3_IN, PD2_IN, PD1_IN, PD0_IN,
47 PE7_IN, PE6_IN, PE5_IN, PE4_IN,
48 PE3_IN, PE2_IN, PE1_IN, PE0_IN,
49 PF7_IN, PF6_IN, PF5_IN, PF4_IN,
50 PF3_IN, PF2_IN, PF1_IN, PF0_IN,
51 PG7_IN, PG6_IN, PG5_IN, PG4_IN,
52 PG3_IN, PG2_IN, PG1_IN, PG0_IN,
53
54 PH5_IN, PH4_IN,
55 PH3_IN, PH2_IN, PH1_IN, PH0_IN,
56 PINMUX_INPUT_END,
57
58 PINMUX_INPUT_PULLUP_BEGIN,
59 PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
60 PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
61 PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
62 PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
63 PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
64 PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
65 PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
66 PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
67 PE7_IN_PU, PE6_IN_PU, PE5_IN_PU, PE4_IN_PU,
68 PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU,
69 PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
70 PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
71 PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU,
72 PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU,
73
74 PH5_IN_PU, PH4_IN_PU,
75 PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
76 PINMUX_INPUT_PULLUP_END,
77
78 PINMUX_OUTPUT_BEGIN,
79 PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
80 PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
81 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
82 PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
83 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
84 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
85 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
86 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
87 PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
88 PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
89 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
90 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
91 PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
92 PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
93
94 PH5_OUT, PH4_OUT,
95 PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
96 PINMUX_OUTPUT_END,
97
98 PINMUX_FUNCTION_BEGIN,
99 PA7_FN, PA6_FN, PA5_FN, PA4_FN,
100 PA3_FN, PA2_FN, PA1_FN, PA0_FN,
101 PB7_FN, PB6_FN, PB5_FN, PB4_FN,
102 PB3_FN, PB2_FN, PB1_FN, PB0_FN,
103 PC7_FN, PC6_FN, PC5_FN, PC4_FN,
104 PC3_FN, PC2_FN, PC1_FN, PC0_FN,
105 PD7_FN, PD6_FN, PD5_FN, PD4_FN,
106 PD3_FN, PD2_FN, PD1_FN, PD0_FN,
107 PE7_FN, PE6_FN, PE5_FN, PE4_FN,
108 PE3_FN, PE2_FN, PE1_FN, PE0_FN,
109 PF7_FN, PF6_FN, PF5_FN, PF4_FN,
110 PF3_FN, PF2_FN, PF1_FN, PF0_FN,
111 PG7_FN, PG6_FN, PG5_FN, PG4_FN,
112 PG3_FN, PG2_FN, PG1_FN, PG0_FN,
113
114 PH5_FN, PH4_FN,
115 PH3_FN, PH2_FN, PH1_FN, PH0_FN,
116 PINMUX_FUNCTION_END,
117
118 PINMUX_MARK_BEGIN,
119
120 D31_MARK, D30_MARK, D29_MARK, D28_MARK, D27_MARK, D26_MARK,
121 D25_MARK, D24_MARK, D23_MARK, D22_MARK, D21_MARK, D20_MARK,
122 D19_MARK, D18_MARK, D17_MARK, D16_MARK,
123
124 BACK_MARK, BREQ_MARK,
125 WE3_MARK, WE2_MARK,
126 CS6_MARK, CS5_MARK, CS4_MARK,
127 CLKOUTENB_MARK,
128
129 DACK3_MARK, DACK2_MARK, DACK1_MARK, DACK0_MARK,
130 DREQ3_MARK, DREQ2_MARK, DREQ1_MARK, DREQ0_MARK,
131
132 IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
133
134 DRAK3_MARK, DRAK2_MARK, DRAK1_MARK, DRAK0_MARK,
135
136 SCK3_MARK, SCK2_MARK, SCK1_MARK, SCK0_MARK,
137 IRL3_MARK, IRL2_MARK, IRL1_MARK, IRL0_MARK,
138 TXD3_MARK, TXD2_MARK, TXD1_MARK, TXD0_MARK,
139 RXD3_MARK, RXD2_MARK, RXD1_MARK, RXD0_MARK,
140
141 CE2B_MARK, CE2A_MARK, IOIS16_MARK,
142 STATUS1_MARK, STATUS0_MARK,
143
144 IRQOUT_MARK,
145
146 PINMUX_MARK_END,
147};
148
149static pinmux_enum_t shx3_pinmux_data[] = {
150
151 /* PA GPIO */
152 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
153 PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
154 PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
155 PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
156 PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
157 PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
158 PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
159 PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
160
161 /* PB GPIO */
162 PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
163 PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
164 PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
165 PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
166 PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
167 PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
168 PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
169 PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
170
171 /* PC GPIO */
172 PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
173 PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
174 PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
175 PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
176 PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
177 PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
178 PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
179 PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
180
181 /* PD GPIO */
182 PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
183 PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
184 PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
185 PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
186 PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
187 PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
188 PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
189 PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
190
191 /* PE GPIO */
192 PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
193 PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
194 PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU),
195 PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU),
196 PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU),
197 PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU),
198 PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU),
199 PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU),
200
201 /* PF GPIO */
202 PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
203 PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
204 PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
205 PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
206 PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
207 PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
208 PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
209 PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
210
211 /* PG GPIO */
212 PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
213 PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
214 PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
215 PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU),
216 PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU),
217 PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU),
218 PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU),
219 PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU),
220
221 /* PH GPIO */
222 PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
223 PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
224 PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
225 PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
226 PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
227 PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
228
229 /* PA FN */
230 PINMUX_DATA(D31_MARK, PA7_FN),
231 PINMUX_DATA(D30_MARK, PA6_FN),
232 PINMUX_DATA(D29_MARK, PA5_FN),
233 PINMUX_DATA(D28_MARK, PA4_FN),
234 PINMUX_DATA(D27_MARK, PA3_FN),
235 PINMUX_DATA(D26_MARK, PA2_FN),
236 PINMUX_DATA(D25_MARK, PA1_FN),
237 PINMUX_DATA(D24_MARK, PA0_FN),
238
239 /* PB FN */
240 PINMUX_DATA(D23_MARK, PB7_FN),
241 PINMUX_DATA(D22_MARK, PB6_FN),
242 PINMUX_DATA(D21_MARK, PB5_FN),
243 PINMUX_DATA(D20_MARK, PB4_FN),
244 PINMUX_DATA(D19_MARK, PB3_FN),
245 PINMUX_DATA(D18_MARK, PB2_FN),
246 PINMUX_DATA(D17_MARK, PB1_FN),
247 PINMUX_DATA(D16_MARK, PB0_FN),
248
249 /* PC FN */
250 PINMUX_DATA(BACK_MARK, PC7_FN),
251 PINMUX_DATA(BREQ_MARK, PC6_FN),
252 PINMUX_DATA(WE3_MARK, PC5_FN),
253 PINMUX_DATA(WE2_MARK, PC4_FN),
254 PINMUX_DATA(CS6_MARK, PC3_FN),
255 PINMUX_DATA(CS5_MARK, PC2_FN),
256 PINMUX_DATA(CS4_MARK, PC1_FN),
257 PINMUX_DATA(CLKOUTENB_MARK, PC0_FN),
258
259 /* PD FN */
260 PINMUX_DATA(DACK3_MARK, PD7_FN),
261 PINMUX_DATA(DACK2_MARK, PD6_FN),
262 PINMUX_DATA(DACK1_MARK, PD5_FN),
263 PINMUX_DATA(DACK0_MARK, PD4_FN),
264 PINMUX_DATA(DREQ3_MARK, PD3_FN),
265 PINMUX_DATA(DREQ2_MARK, PD2_FN),
266 PINMUX_DATA(DREQ1_MARK, PD1_FN),
267 PINMUX_DATA(DREQ0_MARK, PD0_FN),
268
269 /* PE FN */
270 PINMUX_DATA(IRQ3_MARK, PE7_FN),
271 PINMUX_DATA(IRQ2_MARK, PE6_FN),
272 PINMUX_DATA(IRQ1_MARK, PE5_FN),
273 PINMUX_DATA(IRQ0_MARK, PE4_FN),
274 PINMUX_DATA(DRAK3_MARK, PE3_FN),
275 PINMUX_DATA(DRAK2_MARK, PE2_FN),
276 PINMUX_DATA(DRAK1_MARK, PE1_FN),
277 PINMUX_DATA(DRAK0_MARK, PE0_FN),
278
279 /* PF FN */
280 PINMUX_DATA(SCK3_MARK, PF7_FN),
281 PINMUX_DATA(SCK2_MARK, PF6_FN),
282 PINMUX_DATA(SCK1_MARK, PF5_FN),
283 PINMUX_DATA(SCK0_MARK, PF4_FN),
284 PINMUX_DATA(IRL3_MARK, PF3_FN),
285 PINMUX_DATA(IRL2_MARK, PF2_FN),
286 PINMUX_DATA(IRL1_MARK, PF1_FN),
287 PINMUX_DATA(IRL0_MARK, PF0_FN),
288
289 /* PG FN */
290 PINMUX_DATA(TXD3_MARK, PG7_FN),
291 PINMUX_DATA(TXD2_MARK, PG6_FN),
292 PINMUX_DATA(TXD1_MARK, PG5_FN),
293 PINMUX_DATA(TXD0_MARK, PG4_FN),
294 PINMUX_DATA(RXD3_MARK, PG3_FN),
295 PINMUX_DATA(RXD2_MARK, PG2_FN),
296 PINMUX_DATA(RXD1_MARK, PG1_FN),
297 PINMUX_DATA(RXD0_MARK, PG0_FN),
298
299 /* PH FN */
300 PINMUX_DATA(CE2B_MARK, PH5_FN),
301 PINMUX_DATA(CE2A_MARK, PH4_FN),
302 PINMUX_DATA(IOIS16_MARK, PH3_FN),
303 PINMUX_DATA(STATUS1_MARK, PH2_FN),
304 PINMUX_DATA(STATUS0_MARK, PH1_FN),
305 PINMUX_DATA(IRQOUT_MARK, PH0_FN),
306};
307
308static struct pinmux_gpio shx3_pinmux_gpios[] = {
309 /* PA */
310 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
311 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
312 PINMUX_GPIO(GPIO_PA5, PA5_DATA),
313 PINMUX_GPIO(GPIO_PA4, PA4_DATA),
314 PINMUX_GPIO(GPIO_PA3, PA3_DATA),
315 PINMUX_GPIO(GPIO_PA2, PA2_DATA),
316 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
317 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
318
319 /* PB */
320 PINMUX_GPIO(GPIO_PB7, PB7_DATA),
321 PINMUX_GPIO(GPIO_PB6, PB6_DATA),
322 PINMUX_GPIO(GPIO_PB5, PB5_DATA),
323 PINMUX_GPIO(GPIO_PB4, PB4_DATA),
324 PINMUX_GPIO(GPIO_PB3, PB3_DATA),
325 PINMUX_GPIO(GPIO_PB2, PB2_DATA),
326 PINMUX_GPIO(GPIO_PB1, PB1_DATA),
327 PINMUX_GPIO(GPIO_PB0, PB0_DATA),
328
329 /* PC */
330 PINMUX_GPIO(GPIO_PC7, PC7_DATA),
331 PINMUX_GPIO(GPIO_PC6, PC6_DATA),
332 PINMUX_GPIO(GPIO_PC5, PC5_DATA),
333 PINMUX_GPIO(GPIO_PC4, PC4_DATA),
334 PINMUX_GPIO(GPIO_PC3, PC3_DATA),
335 PINMUX_GPIO(GPIO_PC2, PC2_DATA),
336 PINMUX_GPIO(GPIO_PC1, PC1_DATA),
337 PINMUX_GPIO(GPIO_PC0, PC0_DATA),
338
339 /* PD */
340 PINMUX_GPIO(GPIO_PD7, PD7_DATA),
341 PINMUX_GPIO(GPIO_PD6, PD6_DATA),
342 PINMUX_GPIO(GPIO_PD5, PD5_DATA),
343 PINMUX_GPIO(GPIO_PD4, PD4_DATA),
344 PINMUX_GPIO(GPIO_PD3, PD3_DATA),
345 PINMUX_GPIO(GPIO_PD2, PD2_DATA),
346 PINMUX_GPIO(GPIO_PD1, PD1_DATA),
347 PINMUX_GPIO(GPIO_PD0, PD0_DATA),
348
349 /* PE */
350 PINMUX_GPIO(GPIO_PE7, PE7_DATA),
351 PINMUX_GPIO(GPIO_PE6, PE6_DATA),
352 PINMUX_GPIO(GPIO_PE5, PE5_DATA),
353 PINMUX_GPIO(GPIO_PE4, PE4_DATA),
354 PINMUX_GPIO(GPIO_PE3, PE3_DATA),
355 PINMUX_GPIO(GPIO_PE2, PE2_DATA),
356 PINMUX_GPIO(GPIO_PE1, PE1_DATA),
357 PINMUX_GPIO(GPIO_PE0, PE0_DATA),
358
359 /* PF */
360 PINMUX_GPIO(GPIO_PF7, PF7_DATA),
361 PINMUX_GPIO(GPIO_PF6, PF6_DATA),
362 PINMUX_GPIO(GPIO_PF5, PF5_DATA),
363 PINMUX_GPIO(GPIO_PF4, PF4_DATA),
364 PINMUX_GPIO(GPIO_PF3, PF3_DATA),
365 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
366 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
367 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
368
369 /* PG */
370 PINMUX_GPIO(GPIO_PG7, PG7_DATA),
371 PINMUX_GPIO(GPIO_PG6, PG6_DATA),
372 PINMUX_GPIO(GPIO_PG5, PG5_DATA),
373 PINMUX_GPIO(GPIO_PG4, PG4_DATA),
374 PINMUX_GPIO(GPIO_PG3, PG3_DATA),
375 PINMUX_GPIO(GPIO_PG2, PG2_DATA),
376 PINMUX_GPIO(GPIO_PG1, PG1_DATA),
377 PINMUX_GPIO(GPIO_PG0, PG0_DATA),
378
379 /* PH */
380 PINMUX_GPIO(GPIO_PH5, PH5_DATA),
381 PINMUX_GPIO(GPIO_PH4, PH4_DATA),
382 PINMUX_GPIO(GPIO_PH3, PH3_DATA),
383 PINMUX_GPIO(GPIO_PH2, PH2_DATA),
384 PINMUX_GPIO(GPIO_PH1, PH1_DATA),
385 PINMUX_GPIO(GPIO_PH0, PH0_DATA),
386
387 /* FN */
388 PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
389 PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
390 PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
391 PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
392 PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
393 PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
394 PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
395 PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
396 PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
397 PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
398 PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
399 PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
400 PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
401 PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
402 PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
403 PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
404 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
405 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
406 PINMUX_GPIO(GPIO_FN_WE3, WE3_MARK),
407 PINMUX_GPIO(GPIO_FN_WE2, WE2_MARK),
408 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
409 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
410 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
411 PINMUX_GPIO(GPIO_FN_CLKOUTENB, CLKOUTENB_MARK),
412 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
413 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
414 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
415 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
416 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
417 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
418 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
419 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
420 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
421 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
422 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
423 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
424 PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
425 PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
426 PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
427 PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
428 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
429 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
430 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
431 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
432 PINMUX_GPIO(GPIO_FN_IRL3, IRL3_MARK),
433 PINMUX_GPIO(GPIO_FN_IRL2, IRL2_MARK),
434 PINMUX_GPIO(GPIO_FN_IRL1, IRL1_MARK),
435 PINMUX_GPIO(GPIO_FN_IRL0, IRL0_MARK),
436 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
437 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
438 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
439 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
440 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
441 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
442 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
443 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
444 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
445 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
446 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
447 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
448 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
449 PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
450};
451
452static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
453 { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
454 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
455 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
456 PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
457 PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
458 PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
459 PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
460 PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
461 PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU,
462 PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
463 PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
464 PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
465 PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
466 PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
467 PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
468 PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
469 PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU, },
470 },
471 { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) {
472 PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
473 PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
474 PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
475 PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
476 PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
477 PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
478 PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
479 PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU,
480 PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
481 PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
482 PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
483 PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
484 PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
485 PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
486 PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
487 PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU, },
488 },
489 { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) {
490 PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
491 PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
492 PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU,
493 PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU,
494 PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU,
495 PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU,
496 PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU,
497 PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU,
498 PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
499 PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
500 PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
501 PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
502 PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
503 PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
504 PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
505 PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU, },
506 },
507 { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) {
508 PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
509 PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
510 PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
511 PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU,
512 PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU,
513 PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU,
514 PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU,
515 PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU,
516 0, 0, 0, 0,
517 0, 0, 0, 0,
518 PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
519 PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
520 PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
521 PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
522 PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
523 PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU, },
524 },
525 { },
526};
527
528static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
529 { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
530 0, 0, 0, 0, 0, 0, 0, 0,
531 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
532 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
533 0, 0, 0, 0, 0, 0, 0, 0,
534 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
535 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, },
536 },
537 { PINMUX_DATA_REG("PCDDR", 0xffc70014, 32) {
538 0, 0, 0, 0, 0, 0, 0, 0,
539 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
540 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
541 0, 0, 0, 0, 0, 0, 0, 0,
542 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
543 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, },
544 },
545 { PINMUX_DATA_REG("PEFDR", 0xffc70018, 32) {
546 0, 0, 0, 0, 0, 0, 0, 0,
547 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
548 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
549 0, 0, 0, 0, 0, 0, 0, 0,
550 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
551 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, },
552 },
553 { PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32) {
554 0, 0, 0, 0, 0, 0, 0, 0,
555 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
556 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
557 0, 0, 0, 0, 0, 0, 0, 0,
558 0, 0, PH5_DATA, PH4_DATA,
559 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, },
560 },
561 { },
562};
563
564static struct pinmux_info shx3_pinmux_info = {
565 .name = "shx3_pfc",
566 .reserved_id = PINMUX_RESERVED,
567 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
568 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
569 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
570 PINMUX_INPUT_PULLUP_END },
571 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
572 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
573 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
574 .first_gpio = GPIO_PA7,
575 .last_gpio = GPIO_FN_IRQOUT,
576 .gpios = shx3_pinmux_gpios,
577 .gpio_data = shx3_pinmux_data,
578 .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
579 .cfg_regs = shx3_pinmux_config_regs,
580 .data_regs = shx3_pinmux_data_regs,
581};
582
583static int __init shx3_pinmux_setup(void)
584{
585 return register_pinmux(&shx3_pinmux_info);
586}
587arch_initcall(shx3_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index fbae06b1c98d..0d1be5d1fb86 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -15,6 +15,75 @@
15#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <asm/clock.h> 16#include <asm/clock.h>
17 17
18/* Serial */
19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = 0xffe00000,
21 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
23 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF,
25 .irqs = { 80, 80, 80, 80 },
26};
27
28static struct platform_device scif0_device = {
29 .name = "sh-sci",
30 .id = 0,
31 .dev = {
32 .platform_data = &scif0_platform_data,
33 },
34};
35
36static struct plat_sci_port scif1_platform_data = {
37 .mapbase = 0xffe10000,
38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
40 .scbrr_algo_id = SCBRR_ALGO_2,
41 .type = PORT_SCIF,
42 .irqs = { 81, 81, 81, 81 },
43};
44
45static struct platform_device scif1_device = {
46 .name = "sh-sci",
47 .id = 1,
48 .dev = {
49 .platform_data = &scif1_platform_data,
50 },
51};
52
53static struct plat_sci_port scif2_platform_data = {
54 .mapbase = 0xffe20000,
55 .flags = UPF_BOOT_AUTOCONF,
56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
57 .scbrr_algo_id = SCBRR_ALGO_2,
58 .type = PORT_SCIF,
59 .irqs = { 82, 82, 82, 82 },
60};
61
62static struct platform_device scif2_device = {
63 .name = "sh-sci",
64 .id = 2,
65 .dev = {
66 .platform_data = &scif2_platform_data,
67 },
68};
69
70static struct plat_sci_port scif3_platform_data = {
71 .mapbase = 0xffe30000,
72 .flags = UPF_BOOT_AUTOCONF,
73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
74 .scbrr_algo_id = SCBRR_ALGO_2,
75 .type = PORT_SCIF,
76 .irqs = { 83, 83, 83, 83 },
77};
78
79static struct platform_device scif3_device = {
80 .name = "sh-sci",
81 .id = 3,
82 .dev = {
83 .platform_data = &scif3_platform_data,
84 },
85};
86
18static struct resource iic0_resources[] = { 87static struct resource iic0_resources[] = {
19 [0] = { 88 [0] = {
20 .name = "IIC0", 89 .name = "IIC0",
@@ -142,17 +211,14 @@ static struct platform_device jpu_device = {
142}; 211};
143 212
144static struct sh_timer_config cmt_platform_data = { 213static struct sh_timer_config cmt_platform_data = {
145 .name = "CMT",
146 .channel_offset = 0x60, 214 .channel_offset = 0x60,
147 .timer_bit = 5, 215 .timer_bit = 5,
148 .clk = "cmt0",
149 .clockevent_rating = 125, 216 .clockevent_rating = 125,
150 .clocksource_rating = 200, 217 .clocksource_rating = 200,
151}; 218};
152 219
153static struct resource cmt_resources[] = { 220static struct resource cmt_resources[] = {
154 [0] = { 221 [0] = {
155 .name = "CMT",
156 .start = 0x044a0060, 222 .start = 0x044a0060,
157 .end = 0x044a006b, 223 .end = 0x044a006b,
158 .flags = IORESOURCE_MEM, 224 .flags = IORESOURCE_MEM,
@@ -174,16 +240,13 @@ static struct platform_device cmt_device = {
174}; 240};
175 241
176static struct sh_timer_config tmu0_platform_data = { 242static struct sh_timer_config tmu0_platform_data = {
177 .name = "TMU0",
178 .channel_offset = 0x04, 243 .channel_offset = 0x04,
179 .timer_bit = 0, 244 .timer_bit = 0,
180 .clk = "tmu0",
181 .clockevent_rating = 200, 245 .clockevent_rating = 200,
182}; 246};
183 247
184static struct resource tmu0_resources[] = { 248static struct resource tmu0_resources[] = {
185 [0] = { 249 [0] = {
186 .name = "TMU0",
187 .start = 0xffd80008, 250 .start = 0xffd80008,
188 .end = 0xffd80013, 251 .end = 0xffd80013,
189 .flags = IORESOURCE_MEM, 252 .flags = IORESOURCE_MEM,
@@ -205,16 +268,13 @@ static struct platform_device tmu0_device = {
205}; 268};
206 269
207static struct sh_timer_config tmu1_platform_data = { 270static struct sh_timer_config tmu1_platform_data = {
208 .name = "TMU1",
209 .channel_offset = 0x10, 271 .channel_offset = 0x10,
210 .timer_bit = 1, 272 .timer_bit = 1,
211 .clk = "tmu0",
212 .clocksource_rating = 200, 273 .clocksource_rating = 200,
213}; 274};
214 275
215static struct resource tmu1_resources[] = { 276static struct resource tmu1_resources[] = {
216 [0] = { 277 [0] = {
217 .name = "TMU1",
218 .start = 0xffd80014, 278 .start = 0xffd80014,
219 .end = 0xffd8001f, 279 .end = 0xffd8001f,
220 .flags = IORESOURCE_MEM, 280 .flags = IORESOURCE_MEM,
@@ -236,15 +296,12 @@ static struct platform_device tmu1_device = {
236}; 296};
237 297
238static struct sh_timer_config tmu2_platform_data = { 298static struct sh_timer_config tmu2_platform_data = {
239 .name = "TMU2",
240 .channel_offset = 0x1c, 299 .channel_offset = 0x1c,
241 .timer_bit = 2, 300 .timer_bit = 2,
242 .clk = "tmu0",
243}; 301};
244 302
245static struct resource tmu2_resources[] = { 303static struct resource tmu2_resources[] = {
246 [0] = { 304 [0] = {
247 .name = "TMU2",
248 .start = 0xffd80020, 305 .start = 0xffd80020,
249 .end = 0xffd8002b, 306 .end = 0xffd8002b,
250 .flags = IORESOURCE_MEM, 307 .flags = IORESOURCE_MEM,
@@ -265,60 +322,17 @@ static struct platform_device tmu2_device = {
265 .num_resources = ARRAY_SIZE(tmu2_resources), 322 .num_resources = ARRAY_SIZE(tmu2_resources),
266}; 323};
267 324
268static struct plat_sci_port sci_platform_data[] = {
269 {
270 .mapbase = 0xffe00000,
271 .flags = UPF_BOOT_AUTOCONF,
272 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
273 .scbrr_algo_id = SCBRR_ALGO_2,
274 .type = PORT_SCIF,
275 .irqs = { 80, 80, 80, 80 },
276 .clk = "scif0",
277 }, {
278 .mapbase = 0xffe10000,
279 .flags = UPF_BOOT_AUTOCONF,
280 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
281 .scbrr_algo_id = SCBRR_ALGO_2,
282 .type = PORT_SCIF,
283 .irqs = { 81, 81, 81, 81 },
284 .clk = "scif1",
285 }, {
286 .mapbase = 0xffe20000,
287 .flags = UPF_BOOT_AUTOCONF,
288 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
289 .scbrr_algo_id = SCBRR_ALGO_2,
290 .type = PORT_SCIF,
291 .irqs = { 82, 82, 82, 82 },
292 .clk = "scif2",
293 }, {
294 .mapbase = 0xffe30000,
295 .flags = UPF_BOOT_AUTOCONF,
296 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
297 .scbrr_algo_id = SCBRR_ALGO_2,
298 .type = PORT_SCIF,
299 .irqs = { 83, 83, 83, 83 },
300 .clk = "scif3",
301 }, {
302 .flags = 0,
303 }
304};
305
306static struct platform_device sci_device = {
307 .name = "sh-sci",
308 .id = -1,
309 .dev = {
310 .platform_data = sci_platform_data,
311 },
312};
313
314static struct platform_device *sh7343_devices[] __initdata = { 325static struct platform_device *sh7343_devices[] __initdata = {
326 &scif0_device,
327 &scif1_device,
328 &scif2_device,
329 &scif3_device,
315 &cmt_device, 330 &cmt_device,
316 &tmu0_device, 331 &tmu0_device,
317 &tmu1_device, 332 &tmu1_device,
318 &tmu2_device, 333 &tmu2_device,
319 &iic0_device, 334 &iic0_device,
320 &iic1_device, 335 &iic1_device,
321 &sci_device,
322 &vpu_device, 336 &vpu_device,
323 &veu_device, 337 &veu_device,
324 &jpu_device, 338 &jpu_device,
@@ -333,9 +347,13 @@ static int __init sh7343_devices_setup(void)
333 return platform_add_devices(sh7343_devices, 347 return platform_add_devices(sh7343_devices,
334 ARRAY_SIZE(sh7343_devices)); 348 ARRAY_SIZE(sh7343_devices));
335} 349}
336__initcall(sh7343_devices_setup); 350arch_initcall(sh7343_devices_setup);
337 351
338static struct platform_device *sh7343_early_devices[] __initdata = { 352static struct platform_device *sh7343_early_devices[] __initdata = {
353 &scif0_device,
354 &scif1_device,
355 &scif2_device,
356 &scif3_device,
339 &cmt_device, 357 &cmt_device,
340 &tmu0_device, 358 &tmu0_device,
341 &tmu1_device, 359 &tmu1_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index d4ee429032b1..f96b7eeb21eb 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -18,6 +18,23 @@
18#include <linux/usb/r8a66597.h> 18#include <linux/usb/r8a66597.h>
19#include <asm/clock.h> 19#include <asm/clock.h>
20 20
21static struct plat_sci_port scif0_platform_data = {
22 .mapbase = 0xffe00000,
23 .flags = UPF_BOOT_AUTOCONF,
24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
25 .scbrr_algo_id = SCBRR_ALGO_2,
26 .type = PORT_SCIF,
27 .irqs = { 80, 80, 80, 80 },
28};
29
30static struct platform_device scif0_device = {
31 .name = "sh-sci",
32 .id = 0,
33 .dev = {
34 .platform_data = &scif0_platform_data,
35 },
36};
37
21static struct resource iic_resources[] = { 38static struct resource iic_resources[] = {
22 [0] = { 39 [0] = {
23 .name = "IIC", 40 .name = "IIC",
@@ -40,7 +57,7 @@ static struct platform_device iic_device = {
40}; 57};
41 58
42static struct r8a66597_platdata r8a66597_data = { 59static struct r8a66597_platdata r8a66597_data = {
43 /* This set zero to all members */ 60 .on_chip = 1,
44}; 61};
45 62
46static struct resource usb_host_resources[] = { 63static struct resource usb_host_resources[] = {
@@ -153,17 +170,14 @@ static struct platform_device veu1_device = {
153}; 170};
154 171
155static struct sh_timer_config cmt_platform_data = { 172static struct sh_timer_config cmt_platform_data = {
156 .name = "CMT",
157 .channel_offset = 0x60, 173 .channel_offset = 0x60,
158 .timer_bit = 5, 174 .timer_bit = 5,
159 .clk = "cmt0",
160 .clockevent_rating = 125, 175 .clockevent_rating = 125,
161 .clocksource_rating = 200, 176 .clocksource_rating = 200,
162}; 177};
163 178
164static struct resource cmt_resources[] = { 179static struct resource cmt_resources[] = {
165 [0] = { 180 [0] = {
166 .name = "CMT",
167 .start = 0x044a0060, 181 .start = 0x044a0060,
168 .end = 0x044a006b, 182 .end = 0x044a006b,
169 .flags = IORESOURCE_MEM, 183 .flags = IORESOURCE_MEM,
@@ -185,16 +199,13 @@ static struct platform_device cmt_device = {
185}; 199};
186 200
187static struct sh_timer_config tmu0_platform_data = { 201static struct sh_timer_config tmu0_platform_data = {
188 .name = "TMU0",
189 .channel_offset = 0x04, 202 .channel_offset = 0x04,
190 .timer_bit = 0, 203 .timer_bit = 0,
191 .clk = "tmu0",
192 .clockevent_rating = 200, 204 .clockevent_rating = 200,
193}; 205};
194 206
195static struct resource tmu0_resources[] = { 207static struct resource tmu0_resources[] = {
196 [0] = { 208 [0] = {
197 .name = "TMU0",
198 .start = 0xffd80008, 209 .start = 0xffd80008,
199 .end = 0xffd80013, 210 .end = 0xffd80013,
200 .flags = IORESOURCE_MEM, 211 .flags = IORESOURCE_MEM,
@@ -216,16 +227,13 @@ static struct platform_device tmu0_device = {
216}; 227};
217 228
218static struct sh_timer_config tmu1_platform_data = { 229static struct sh_timer_config tmu1_platform_data = {
219 .name = "TMU1",
220 .channel_offset = 0x10, 230 .channel_offset = 0x10,
221 .timer_bit = 1, 231 .timer_bit = 1,
222 .clk = "tmu0",
223 .clocksource_rating = 200, 232 .clocksource_rating = 200,
224}; 233};
225 234
226static struct resource tmu1_resources[] = { 235static struct resource tmu1_resources[] = {
227 [0] = { 236 [0] = {
228 .name = "TMU1",
229 .start = 0xffd80014, 237 .start = 0xffd80014,
230 .end = 0xffd8001f, 238 .end = 0xffd8001f,
231 .flags = IORESOURCE_MEM, 239 .flags = IORESOURCE_MEM,
@@ -247,15 +255,12 @@ static struct platform_device tmu1_device = {
247}; 255};
248 256
249static struct sh_timer_config tmu2_platform_data = { 257static struct sh_timer_config tmu2_platform_data = {
250 .name = "TMU2",
251 .channel_offset = 0x1c, 258 .channel_offset = 0x1c,
252 .timer_bit = 2, 259 .timer_bit = 2,
253 .clk = "tmu0",
254}; 260};
255 261
256static struct resource tmu2_resources[] = { 262static struct resource tmu2_resources[] = {
257 [0] = { 263 [0] = {
258 .name = "TMU2",
259 .start = 0xffd80020, 264 .start = 0xffd80020,
260 .end = 0xffd8002b, 265 .end = 0xffd8002b,
261 .flags = IORESOURCE_MEM, 266 .flags = IORESOURCE_MEM,
@@ -276,35 +281,13 @@ static struct platform_device tmu2_device = {
276 .num_resources = ARRAY_SIZE(tmu2_resources), 281 .num_resources = ARRAY_SIZE(tmu2_resources),
277}; 282};
278 283
279static struct plat_sci_port sci_platform_data[] = {
280 {
281 .mapbase = 0xffe00000,
282 .flags = UPF_BOOT_AUTOCONF,
283 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
284 .scbrr_algo_id = SCBRR_ALGO_2,
285 .type = PORT_SCIF,
286 .irqs = { 80, 80, 80, 80 },
287 .clk = "scif0",
288 }, {
289 .flags = 0,
290 }
291};
292
293static struct platform_device sci_device = {
294 .name = "sh-sci",
295 .id = -1,
296 .dev = {
297 .platform_data = sci_platform_data,
298 },
299};
300
301static struct platform_device *sh7366_devices[] __initdata = { 284static struct platform_device *sh7366_devices[] __initdata = {
285 &scif0_device,
302 &cmt_device, 286 &cmt_device,
303 &tmu0_device, 287 &tmu0_device,
304 &tmu1_device, 288 &tmu1_device,
305 &tmu2_device, 289 &tmu2_device,
306 &iic_device, 290 &iic_device,
307 &sci_device,
308 &usb_host_device, 291 &usb_host_device,
309 &vpu_device, 292 &vpu_device,
310 &veu0_device, 293 &veu0_device,
@@ -320,9 +303,10 @@ static int __init sh7366_devices_setup(void)
320 return platform_add_devices(sh7366_devices, 303 return platform_add_devices(sh7366_devices,
321 ARRAY_SIZE(sh7366_devices)); 304 ARRAY_SIZE(sh7366_devices));
322} 305}
323__initcall(sh7366_devices_setup); 306arch_initcall(sh7366_devices_setup);
324 307
325static struct platform_device *sh7366_early_devices[] __initdata = { 308static struct platform_device *sh7366_early_devices[] __initdata = {
309 &scif0_device,
326 &cmt_device, 310 &cmt_device,
327 &tmu0_device, 311 &tmu0_device,
328 &tmu1_device, 312 &tmu1_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index f7b0551bf104..73737d00e2e7 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -7,15 +7,227 @@
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details. 8 * for more details.
9 */ 9 */
10#include <linux/platform_device.h>
11#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/mm.h>
12#include <linux/platform_device.h>
12#include <linux/serial.h> 13#include <linux/serial.h>
13#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
14#include <linux/mm.h>
15#include <linux/uio_driver.h>
16#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <linux/uio_driver.h>
17#include <linux/usb/m66592.h>
18
17#include <asm/clock.h> 19#include <asm/clock.h>
18#include <asm/mmzone.h> 20#include <asm/mmzone.h>
21#include <asm/siu.h>
22
23#include <cpu/dma-register.h>
24#include <cpu/sh7722.h>
25
26static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
27 {
28 .slave_id = SHDMA_SLAVE_SCIF0_TX,
29 .addr = 0xffe0000c,
30 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
31 .mid_rid = 0x21,
32 }, {
33 .slave_id = SHDMA_SLAVE_SCIF0_RX,
34 .addr = 0xffe00014,
35 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
36 .mid_rid = 0x22,
37 }, {
38 .slave_id = SHDMA_SLAVE_SCIF1_TX,
39 .addr = 0xffe1000c,
40 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
41 .mid_rid = 0x25,
42 }, {
43 .slave_id = SHDMA_SLAVE_SCIF1_RX,
44 .addr = 0xffe10014,
45 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
46 .mid_rid = 0x26,
47 }, {
48 .slave_id = SHDMA_SLAVE_SCIF2_TX,
49 .addr = 0xffe2000c,
50 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
51 .mid_rid = 0x29,
52 }, {
53 .slave_id = SHDMA_SLAVE_SCIF2_RX,
54 .addr = 0xffe20014,
55 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
56 .mid_rid = 0x2a,
57 }, {
58 .slave_id = SHDMA_SLAVE_SIUA_TX,
59 .addr = 0xa454c098,
60 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
61 .mid_rid = 0xb1,
62 }, {
63 .slave_id = SHDMA_SLAVE_SIUA_RX,
64 .addr = 0xa454c090,
65 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
66 .mid_rid = 0xb2,
67 }, {
68 .slave_id = SHDMA_SLAVE_SIUB_TX,
69 .addr = 0xa454c09c,
70 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
71 .mid_rid = 0xb5,
72 }, {
73 .slave_id = SHDMA_SLAVE_SIUB_RX,
74 .addr = 0xa454c094,
75 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
76 .mid_rid = 0xb6,
77 }, {
78 .slave_id = SHDMA_SLAVE_SDHI0_TX,
79 .addr = 0x04ce0030,
80 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
81 .mid_rid = 0xc1,
82 }, {
83 .slave_id = SHDMA_SLAVE_SDHI0_RX,
84 .addr = 0x04ce0030,
85 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
86 .mid_rid = 0xc2,
87 },
88};
89
90static const struct sh_dmae_channel sh7722_dmae_channels[] = {
91 {
92 .offset = 0,
93 .dmars = 0,
94 .dmars_bit = 0,
95 }, {
96 .offset = 0x10,
97 .dmars = 0,
98 .dmars_bit = 8,
99 }, {
100 .offset = 0x20,
101 .dmars = 4,
102 .dmars_bit = 0,
103 }, {
104 .offset = 0x30,
105 .dmars = 4,
106 .dmars_bit = 8,
107 }, {
108 .offset = 0x50,
109 .dmars = 8,
110 .dmars_bit = 0,
111 }, {
112 .offset = 0x60,
113 .dmars = 8,
114 .dmars_bit = 8,
115 }
116};
117
118static const unsigned int ts_shift[] = TS_SHIFT;
119
120static struct sh_dmae_pdata dma_platform_data = {
121 .slave = sh7722_dmae_slaves,
122 .slave_num = ARRAY_SIZE(sh7722_dmae_slaves),
123 .channel = sh7722_dmae_channels,
124 .channel_num = ARRAY_SIZE(sh7722_dmae_channels),
125 .ts_low_shift = CHCR_TS_LOW_SHIFT,
126 .ts_low_mask = CHCR_TS_LOW_MASK,
127 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
128 .ts_high_mask = CHCR_TS_HIGH_MASK,
129 .ts_shift = ts_shift,
130 .ts_shift_num = ARRAY_SIZE(ts_shift),
131 .dmaor_init = DMAOR_INIT,
132};
133
134static struct resource sh7722_dmae_resources[] = {
135 [0] = {
136 /* Channel registers and DMAOR */
137 .start = 0xfe008020,
138 .end = 0xfe00808f,
139 .flags = IORESOURCE_MEM,
140 },
141 [1] = {
142 /* DMARSx */
143 .start = 0xfe009000,
144 .end = 0xfe00900b,
145 .flags = IORESOURCE_MEM,
146 },
147 {
148 /* DMA error IRQ */
149 .start = 78,
150 .end = 78,
151 .flags = IORESOURCE_IRQ,
152 },
153 {
154 /* IRQ for channels 0-3 */
155 .start = 48,
156 .end = 51,
157 .flags = IORESOURCE_IRQ,
158 },
159 {
160 /* IRQ for channels 4-5 */
161 .start = 76,
162 .end = 77,
163 .flags = IORESOURCE_IRQ,
164 },
165};
166
167struct platform_device dma_device = {
168 .name = "sh-dma-engine",
169 .id = -1,
170 .resource = sh7722_dmae_resources,
171 .num_resources = ARRAY_SIZE(sh7722_dmae_resources),
172 .dev = {
173 .platform_data = &dma_platform_data,
174 },
175 .archdata = {
176 .hwblk_id = HWBLK_DMAC,
177 },
178};
179
180/* Serial */
181static struct plat_sci_port scif0_platform_data = {
182 .mapbase = 0xffe00000,
183 .flags = UPF_BOOT_AUTOCONF,
184 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
185 .scbrr_algo_id = SCBRR_ALGO_2,
186 .type = PORT_SCIF,
187 .irqs = { 80, 80, 80, 80 },
188};
189
190static struct platform_device scif0_device = {
191 .name = "sh-sci",
192 .id = 0,
193 .dev = {
194 .platform_data = &scif0_platform_data,
195 },
196};
197
198static struct plat_sci_port scif1_platform_data = {
199 .mapbase = 0xffe10000,
200 .flags = UPF_BOOT_AUTOCONF,
201 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
202 .scbrr_algo_id = SCBRR_ALGO_2,
203 .type = PORT_SCIF,
204 .irqs = { 81, 81, 81, 81 },
205};
206
207static struct platform_device scif1_device = {
208 .name = "sh-sci",
209 .id = 1,
210 .dev = {
211 .platform_data = &scif1_platform_data,
212 },
213};
214
215static struct plat_sci_port scif2_platform_data = {
216 .mapbase = 0xffe20000,
217 .flags = UPF_BOOT_AUTOCONF,
218 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
219 .scbrr_algo_id = SCBRR_ALGO_2,
220 .type = PORT_SCIF,
221 .irqs = { 82, 82, 82, 82 },
222};
223
224static struct platform_device scif2_device = {
225 .name = "sh-sci",
226 .id = 2,
227 .dev = {
228 .platform_data = &scif2_platform_data,
229 },
230};
19 231
20static struct resource rtc_resources[] = { 232static struct resource rtc_resources[] = {
21 [0] = { 233 [0] = {
@@ -45,11 +257,18 @@ static struct platform_device rtc_device = {
45 .id = -1, 257 .id = -1,
46 .num_resources = ARRAY_SIZE(rtc_resources), 258 .num_resources = ARRAY_SIZE(rtc_resources),
47 .resource = rtc_resources, 259 .resource = rtc_resources,
260 .archdata = {
261 .hwblk_id = HWBLK_RTC,
262 },
263};
264
265static struct m66592_platdata usbf_platdata = {
266 .on_chip = 1,
48}; 267};
49 268
50static struct resource usbf_resources[] = { 269static struct resource usbf_resources[] = {
51 [0] = { 270 [0] = {
52 .name = "m66592_udc", 271 .name = "USBF",
53 .start = 0x04480000, 272 .start = 0x04480000,
54 .end = 0x044800FF, 273 .end = 0x044800FF,
55 .flags = IORESOURCE_MEM, 274 .flags = IORESOURCE_MEM,
@@ -67,9 +286,13 @@ static struct platform_device usbf_device = {
67 .dev = { 286 .dev = {
68 .dma_mask = NULL, 287 .dma_mask = NULL,
69 .coherent_dma_mask = 0xffffffff, 288 .coherent_dma_mask = 0xffffffff,
289 .platform_data = &usbf_platdata,
70 }, 290 },
71 .num_resources = ARRAY_SIZE(usbf_resources), 291 .num_resources = ARRAY_SIZE(usbf_resources),
72 .resource = usbf_resources, 292 .resource = usbf_resources,
293 .archdata = {
294 .hwblk_id = HWBLK_USBF,
295 },
73}; 296};
74 297
75static struct resource iic_resources[] = { 298static struct resource iic_resources[] = {
@@ -91,6 +314,9 @@ static struct platform_device iic_device = {
91 .id = 0, /* "i2c0" clock */ 314 .id = 0, /* "i2c0" clock */
92 .num_resources = ARRAY_SIZE(iic_resources), 315 .num_resources = ARRAY_SIZE(iic_resources),
93 .resource = iic_resources, 316 .resource = iic_resources,
317 .archdata = {
318 .hwblk_id = HWBLK_IIC,
319 },
94}; 320};
95 321
96static struct uio_info vpu_platform_data = { 322static struct uio_info vpu_platform_data = {
@@ -119,6 +345,9 @@ static struct platform_device vpu_device = {
119 }, 345 },
120 .resource = vpu_resources, 346 .resource = vpu_resources,
121 .num_resources = ARRAY_SIZE(vpu_resources), 347 .num_resources = ARRAY_SIZE(vpu_resources),
348 .archdata = {
349 .hwblk_id = HWBLK_VPU,
350 },
122}; 351};
123 352
124static struct uio_info veu_platform_data = { 353static struct uio_info veu_platform_data = {
@@ -147,6 +376,9 @@ static struct platform_device veu_device = {
147 }, 376 },
148 .resource = veu_resources, 377 .resource = veu_resources,
149 .num_resources = ARRAY_SIZE(veu_resources), 378 .num_resources = ARRAY_SIZE(veu_resources),
379 .archdata = {
380 .hwblk_id = HWBLK_VEU,
381 },
150}; 382};
151 383
152static struct uio_info jpu_platform_data = { 384static struct uio_info jpu_platform_data = {
@@ -175,20 +407,20 @@ static struct platform_device jpu_device = {
175 }, 407 },
176 .resource = jpu_resources, 408 .resource = jpu_resources,
177 .num_resources = ARRAY_SIZE(jpu_resources), 409 .num_resources = ARRAY_SIZE(jpu_resources),
410 .archdata = {
411 .hwblk_id = HWBLK_JPU,
412 },
178}; 413};
179 414
180static struct sh_timer_config cmt_platform_data = { 415static struct sh_timer_config cmt_platform_data = {
181 .name = "CMT",
182 .channel_offset = 0x60, 416 .channel_offset = 0x60,
183 .timer_bit = 5, 417 .timer_bit = 5,
184 .clk = "cmt0",
185 .clockevent_rating = 125, 418 .clockevent_rating = 125,
186 .clocksource_rating = 125, 419 .clocksource_rating = 125,
187}; 420};
188 421
189static struct resource cmt_resources[] = { 422static struct resource cmt_resources[] = {
190 [0] = { 423 [0] = {
191 .name = "CMT",
192 .start = 0x044a0060, 424 .start = 0x044a0060,
193 .end = 0x044a006b, 425 .end = 0x044a006b,
194 .flags = IORESOURCE_MEM, 426 .flags = IORESOURCE_MEM,
@@ -207,19 +439,19 @@ static struct platform_device cmt_device = {
207 }, 439 },
208 .resource = cmt_resources, 440 .resource = cmt_resources,
209 .num_resources = ARRAY_SIZE(cmt_resources), 441 .num_resources = ARRAY_SIZE(cmt_resources),
442 .archdata = {
443 .hwblk_id = HWBLK_CMT,
444 },
210}; 445};
211 446
212static struct sh_timer_config tmu0_platform_data = { 447static struct sh_timer_config tmu0_platform_data = {
213 .name = "TMU0",
214 .channel_offset = 0x04, 448 .channel_offset = 0x04,
215 .timer_bit = 0, 449 .timer_bit = 0,
216 .clk = "tmu0",
217 .clockevent_rating = 200, 450 .clockevent_rating = 200,
218}; 451};
219 452
220static struct resource tmu0_resources[] = { 453static struct resource tmu0_resources[] = {
221 [0] = { 454 [0] = {
222 .name = "TMU0",
223 .start = 0xffd80008, 455 .start = 0xffd80008,
224 .end = 0xffd80013, 456 .end = 0xffd80013,
225 .flags = IORESOURCE_MEM, 457 .flags = IORESOURCE_MEM,
@@ -238,19 +470,19 @@ static struct platform_device tmu0_device = {
238 }, 470 },
239 .resource = tmu0_resources, 471 .resource = tmu0_resources,
240 .num_resources = ARRAY_SIZE(tmu0_resources), 472 .num_resources = ARRAY_SIZE(tmu0_resources),
473 .archdata = {
474 .hwblk_id = HWBLK_TMU,
475 },
241}; 476};
242 477
243static struct sh_timer_config tmu1_platform_data = { 478static struct sh_timer_config tmu1_platform_data = {
244 .name = "TMU1",
245 .channel_offset = 0x10, 479 .channel_offset = 0x10,
246 .timer_bit = 1, 480 .timer_bit = 1,
247 .clk = "tmu0",
248 .clocksource_rating = 200, 481 .clocksource_rating = 200,
249}; 482};
250 483
251static struct resource tmu1_resources[] = { 484static struct resource tmu1_resources[] = {
252 [0] = { 485 [0] = {
253 .name = "TMU1",
254 .start = 0xffd80014, 486 .start = 0xffd80014,
255 .end = 0xffd8001f, 487 .end = 0xffd8001f,
256 .flags = IORESOURCE_MEM, 488 .flags = IORESOURCE_MEM,
@@ -269,18 +501,18 @@ static struct platform_device tmu1_device = {
269 }, 501 },
270 .resource = tmu1_resources, 502 .resource = tmu1_resources,
271 .num_resources = ARRAY_SIZE(tmu1_resources), 503 .num_resources = ARRAY_SIZE(tmu1_resources),
504 .archdata = {
505 .hwblk_id = HWBLK_TMU,
506 },
272}; 507};
273 508
274static struct sh_timer_config tmu2_platform_data = { 509static struct sh_timer_config tmu2_platform_data = {
275 .name = "TMU2",
276 .channel_offset = 0x1c, 510 .channel_offset = 0x1c,
277 .timer_bit = 2, 511 .timer_bit = 2,
278 .clk = "tmu0",
279}; 512};
280 513
281static struct resource tmu2_resources[] = { 514static struct resource tmu2_resources[] = {
282 [0] = { 515 [0] = {
283 .name = "TMU2",
284 .start = 0xffd80020, 516 .start = 0xffd80020,
285 .end = 0xffd8002b, 517 .end = 0xffd8002b,
286 .flags = IORESOURCE_MEM, 518 .flags = IORESOURCE_MEM,
@@ -299,47 +531,48 @@ static struct platform_device tmu2_device = {
299 }, 531 },
300 .resource = tmu2_resources, 532 .resource = tmu2_resources,
301 .num_resources = ARRAY_SIZE(tmu2_resources), 533 .num_resources = ARRAY_SIZE(tmu2_resources),
534 .archdata = {
535 .hwblk_id = HWBLK_TMU,
536 },
302}; 537};
303 538
304static struct plat_sci_port sci_platform_data[] = { 539static struct siu_platform siu_platform_data = {
305 { 540 .dma_dev = &dma_device.dev,
306 .mapbase = 0xffe00000, 541 .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
307 .flags = UPF_BOOT_AUTOCONF, 542 .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
308 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 543 .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
309 .scbrr_algo_id = SCBRR_ALGO_2, 544 .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
310 .type = PORT_SCIF,
311 .irqs = { 80, 80, 80, 80 },
312 .clk = "scif0",
313 }, {
314 .mapbase = 0xffe10000,
315 .flags = UPF_BOOT_AUTOCONF,
316 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
317 .scbrr_algo_id = SCBRR_ALGO_2,
318 .type = PORT_SCIF,
319 .irqs = { 81, 81, 81, 81 },
320 .clk = "scif1",
321 }, {
322 .mapbase = 0xffe20000,
323 .flags = UPF_BOOT_AUTOCONF,
324 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
325 .scbrr_algo_id = SCBRR_ALGO_2,
326 .type = PORT_SCIF,
327 .irqs = { 82, 82, 82, 82 },
328 .clk = "scif2",
329 }, {
330 .flags = 0,
331 }
332}; 545};
333 546
334static struct platform_device sci_device = { 547static struct resource siu_resources[] = {
335 .name = "sh-sci", 548 [0] = {
549 .start = 0xa4540000,
550 .end = 0xa454c10f,
551 .flags = IORESOURCE_MEM,
552 },
553 [1] = {
554 .start = 108,
555 .flags = IORESOURCE_IRQ,
556 },
557};
558
559static struct platform_device siu_device = {
560 .name = "siu-pcm-audio",
336 .id = -1, 561 .id = -1,
337 .dev = { 562 .dev = {
338 .platform_data = sci_platform_data, 563 .platform_data = &siu_platform_data,
564 },
565 .resource = siu_resources,
566 .num_resources = ARRAY_SIZE(siu_resources),
567 .archdata = {
568 .hwblk_id = HWBLK_SIU,
339 }, 569 },
340}; 570};
341 571
342static struct platform_device *sh7722_devices[] __initdata = { 572static struct platform_device *sh7722_devices[] __initdata = {
573 &scif0_device,
574 &scif1_device,
575 &scif2_device,
343 &cmt_device, 576 &cmt_device,
344 &tmu0_device, 577 &tmu0_device,
345 &tmu1_device, 578 &tmu1_device,
@@ -347,10 +580,11 @@ static struct platform_device *sh7722_devices[] __initdata = {
347 &rtc_device, 580 &rtc_device,
348 &usbf_device, 581 &usbf_device,
349 &iic_device, 582 &iic_device,
350 &sci_device,
351 &vpu_device, 583 &vpu_device,
352 &veu_device, 584 &veu_device,
353 &jpu_device, 585 &jpu_device,
586 &siu_device,
587 &dma_device,
354}; 588};
355 589
356static int __init sh7722_devices_setup(void) 590static int __init sh7722_devices_setup(void)
@@ -362,9 +596,12 @@ static int __init sh7722_devices_setup(void)
362 return platform_add_devices(sh7722_devices, 596 return platform_add_devices(sh7722_devices,
363 ARRAY_SIZE(sh7722_devices)); 597 ARRAY_SIZE(sh7722_devices));
364} 598}
365__initcall(sh7722_devices_setup); 599arch_initcall(sh7722_devices_setup);
366 600
367static struct platform_device *sh7722_early_devices[] __initdata = { 601static struct platform_device *sh7722_early_devices[] __initdata = {
602 &scif0_device,
603 &scif1_device,
604 &scif2_device,
368 &cmt_device, 605 &cmt_device,
369 &tmu0_device, 606 &tmu0_device,
370 &tmu1_device, 607 &tmu1_device,
@@ -379,6 +616,8 @@ void __init plat_early_device_setup(void)
379 616
380enum { 617enum {
381 UNUSED=0, 618 UNUSED=0,
619 ENABLED,
620 DISABLED,
382 621
383 /* interrupt sources */ 622 /* interrupt sources */
384 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 623 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -394,7 +633,6 @@ enum {
394 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO, 633 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
395 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 634 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
396 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 635 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
397 SDHI0, SDHI1, SDHI2, SDHI3,
398 CMT, TSIF, SIU, TWODG, 636 CMT, TSIF, SIU, TWODG,
399 TMU0, TMU1, TMU2, 637 TMU0, TMU1, TMU2,
400 IRDA, JPU, LCDC, 638 IRDA, JPU, LCDC,
@@ -427,8 +665,8 @@ static struct intc_vect vectors[] __initdata = {
427 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 665 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
428 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 666 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
429 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 667 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
430 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 668 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
431 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 669 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
432 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 670 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
433 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0), 671 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
434 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 672 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
@@ -446,7 +684,6 @@ static struct intc_group groups[] __initdata = {
446 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 684 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
447 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 685 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
448 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 686 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
449 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
450}; 687};
451 688
452static struct intc_mask_reg mask_registers[] __initdata = { 689static struct intc_mask_reg mask_registers[] __initdata = {
@@ -468,7 +705,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
468 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 705 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
469 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 706 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
470 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 707 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
471 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } }, 708 { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
472 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 709 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
473 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, 710 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
474 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 711 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -506,9 +743,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
506 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 743 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
507}; 744};
508 745
509static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups, 746static struct intc_desc intc_desc __initdata = {
510 mask_registers, prio_registers, sense_registers, 747 .name = "sh7722",
511 ack_registers); 748 .force_enable = ENABLED,
749 .force_disable = DISABLED,
750 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
751 prio_registers, sense_registers, ack_registers),
752};
512 753
513void __init plat_irq_setup(void) 754void __init plat_irq_setup(void)
514{ 755{
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index bb4837b9dcf4..264983ddc8da 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -18,6 +18,110 @@
18#include <linux/io.h> 18#include <linux/io.h>
19#include <asm/clock.h> 19#include <asm/clock.h>
20#include <asm/mmzone.h> 20#include <asm/mmzone.h>
21#include <cpu/sh7723.h>
22
23/* Serial */
24static struct plat_sci_port scif0_platform_data = {
25 .mapbase = 0xffe00000,
26 .flags = UPF_BOOT_AUTOCONF,
27 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
28 .scbrr_algo_id = SCBRR_ALGO_2,
29 .type = PORT_SCIF,
30 .irqs = { 80, 80, 80, 80 },
31};
32
33static struct platform_device scif0_device = {
34 .name = "sh-sci",
35 .id = 0,
36 .dev = {
37 .platform_data = &scif0_platform_data,
38 },
39};
40
41static struct plat_sci_port scif1_platform_data = {
42 .mapbase = 0xffe10000,
43 .flags = UPF_BOOT_AUTOCONF,
44 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
45 .scbrr_algo_id = SCBRR_ALGO_2,
46 .type = PORT_SCIF,
47 .irqs = { 81, 81, 81, 81 },
48};
49
50static struct platform_device scif1_device = {
51 .name = "sh-sci",
52 .id = 1,
53 .dev = {
54 .platform_data = &scif1_platform_data,
55 },
56};
57
58static struct plat_sci_port scif2_platform_data = {
59 .mapbase = 0xffe20000,
60 .flags = UPF_BOOT_AUTOCONF,
61 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
62 .scbrr_algo_id = SCBRR_ALGO_2,
63 .type = PORT_SCIF,
64 .irqs = { 82, 82, 82, 82 },
65};
66
67static struct platform_device scif2_device = {
68 .name = "sh-sci",
69 .id = 2,
70 .dev = {
71 .platform_data = &scif2_platform_data,
72 },
73};
74
75static struct plat_sci_port scif3_platform_data = {
76 .mapbase = 0xa4e30000,
77 .flags = UPF_BOOT_AUTOCONF,
78 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
79 .scbrr_algo_id = SCBRR_ALGO_3,
80 .type = PORT_SCIFA,
81 .irqs = { 56, 56, 56, 56 },
82};
83
84static struct platform_device scif3_device = {
85 .name = "sh-sci",
86 .id = 3,
87 .dev = {
88 .platform_data = &scif3_platform_data,
89 },
90};
91
92static struct plat_sci_port scif4_platform_data = {
93 .mapbase = 0xa4e40000,
94 .flags = UPF_BOOT_AUTOCONF,
95 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
96 .scbrr_algo_id = SCBRR_ALGO_3,
97 .type = PORT_SCIFA,
98 .irqs = { 88, 88, 88, 88 },
99};
100
101static struct platform_device scif4_device = {
102 .name = "sh-sci",
103 .id = 4,
104 .dev = {
105 .platform_data = &scif4_platform_data,
106 },
107};
108
109static struct plat_sci_port scif5_platform_data = {
110 .mapbase = 0xa4e50000,
111 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
113 .scbrr_algo_id = SCBRR_ALGO_3,
114 .type = PORT_SCIFA,
115 .irqs = { 109, 109, 109, 109 },
116};
117
118static struct platform_device scif5_device = {
119 .name = "sh-sci",
120 .id = 5,
121 .dev = {
122 .platform_data = &scif5_platform_data,
123 },
124};
21 125
22static struct uio_info vpu_platform_data = { 126static struct uio_info vpu_platform_data = {
23 .name = "VPU5", 127 .name = "VPU5",
@@ -45,6 +149,9 @@ static struct platform_device vpu_device = {
45 }, 149 },
46 .resource = vpu_resources, 150 .resource = vpu_resources,
47 .num_resources = ARRAY_SIZE(vpu_resources), 151 .num_resources = ARRAY_SIZE(vpu_resources),
152 .archdata = {
153 .hwblk_id = HWBLK_VPU,
154 },
48}; 155};
49 156
50static struct uio_info veu0_platform_data = { 157static struct uio_info veu0_platform_data = {
@@ -73,6 +180,9 @@ static struct platform_device veu0_device = {
73 }, 180 },
74 .resource = veu0_resources, 181 .resource = veu0_resources,
75 .num_resources = ARRAY_SIZE(veu0_resources), 182 .num_resources = ARRAY_SIZE(veu0_resources),
183 .archdata = {
184 .hwblk_id = HWBLK_VEU2H0,
185 },
76}; 186};
77 187
78static struct uio_info veu1_platform_data = { 188static struct uio_info veu1_platform_data = {
@@ -101,20 +211,20 @@ static struct platform_device veu1_device = {
101 }, 211 },
102 .resource = veu1_resources, 212 .resource = veu1_resources,
103 .num_resources = ARRAY_SIZE(veu1_resources), 213 .num_resources = ARRAY_SIZE(veu1_resources),
214 .archdata = {
215 .hwblk_id = HWBLK_VEU2H1,
216 },
104}; 217};
105 218
106static struct sh_timer_config cmt_platform_data = { 219static struct sh_timer_config cmt_platform_data = {
107 .name = "CMT",
108 .channel_offset = 0x60, 220 .channel_offset = 0x60,
109 .timer_bit = 5, 221 .timer_bit = 5,
110 .clk = "cmt0",
111 .clockevent_rating = 125, 222 .clockevent_rating = 125,
112 .clocksource_rating = 125, 223 .clocksource_rating = 125,
113}; 224};
114 225
115static struct resource cmt_resources[] = { 226static struct resource cmt_resources[] = {
116 [0] = { 227 [0] = {
117 .name = "CMT",
118 .start = 0x044a0060, 228 .start = 0x044a0060,
119 .end = 0x044a006b, 229 .end = 0x044a006b,
120 .flags = IORESOURCE_MEM, 230 .flags = IORESOURCE_MEM,
@@ -133,19 +243,19 @@ static struct platform_device cmt_device = {
133 }, 243 },
134 .resource = cmt_resources, 244 .resource = cmt_resources,
135 .num_resources = ARRAY_SIZE(cmt_resources), 245 .num_resources = ARRAY_SIZE(cmt_resources),
246 .archdata = {
247 .hwblk_id = HWBLK_CMT,
248 },
136}; 249};
137 250
138static struct sh_timer_config tmu0_platform_data = { 251static struct sh_timer_config tmu0_platform_data = {
139 .name = "TMU0",
140 .channel_offset = 0x04, 252 .channel_offset = 0x04,
141 .timer_bit = 0, 253 .timer_bit = 0,
142 .clk = "tmu0",
143 .clockevent_rating = 200, 254 .clockevent_rating = 200,
144}; 255};
145 256
146static struct resource tmu0_resources[] = { 257static struct resource tmu0_resources[] = {
147 [0] = { 258 [0] = {
148 .name = "TMU0",
149 .start = 0xffd80008, 259 .start = 0xffd80008,
150 .end = 0xffd80013, 260 .end = 0xffd80013,
151 .flags = IORESOURCE_MEM, 261 .flags = IORESOURCE_MEM,
@@ -164,19 +274,19 @@ static struct platform_device tmu0_device = {
164 }, 274 },
165 .resource = tmu0_resources, 275 .resource = tmu0_resources,
166 .num_resources = ARRAY_SIZE(tmu0_resources), 276 .num_resources = ARRAY_SIZE(tmu0_resources),
277 .archdata = {
278 .hwblk_id = HWBLK_TMU0,
279 },
167}; 280};
168 281
169static struct sh_timer_config tmu1_platform_data = { 282static struct sh_timer_config tmu1_platform_data = {
170 .name = "TMU1",
171 .channel_offset = 0x10, 283 .channel_offset = 0x10,
172 .timer_bit = 1, 284 .timer_bit = 1,
173 .clk = "tmu0",
174 .clocksource_rating = 200, 285 .clocksource_rating = 200,
175}; 286};
176 287
177static struct resource tmu1_resources[] = { 288static struct resource tmu1_resources[] = {
178 [0] = { 289 [0] = {
179 .name = "TMU1",
180 .start = 0xffd80014, 290 .start = 0xffd80014,
181 .end = 0xffd8001f, 291 .end = 0xffd8001f,
182 .flags = IORESOURCE_MEM, 292 .flags = IORESOURCE_MEM,
@@ -195,18 +305,18 @@ static struct platform_device tmu1_device = {
195 }, 305 },
196 .resource = tmu1_resources, 306 .resource = tmu1_resources,
197 .num_resources = ARRAY_SIZE(tmu1_resources), 307 .num_resources = ARRAY_SIZE(tmu1_resources),
308 .archdata = {
309 .hwblk_id = HWBLK_TMU0,
310 },
198}; 311};
199 312
200static struct sh_timer_config tmu2_platform_data = { 313static struct sh_timer_config tmu2_platform_data = {
201 .name = "TMU2",
202 .channel_offset = 0x1c, 314 .channel_offset = 0x1c,
203 .timer_bit = 2, 315 .timer_bit = 2,
204 .clk = "tmu0",
205}; 316};
206 317
207static struct resource tmu2_resources[] = { 318static struct resource tmu2_resources[] = {
208 [0] = { 319 [0] = {
209 .name = "TMU2",
210 .start = 0xffd80020, 320 .start = 0xffd80020,
211 .end = 0xffd8002b, 321 .end = 0xffd8002b,
212 .flags = IORESOURCE_MEM, 322 .flags = IORESOURCE_MEM,
@@ -225,18 +335,18 @@ static struct platform_device tmu2_device = {
225 }, 335 },
226 .resource = tmu2_resources, 336 .resource = tmu2_resources,
227 .num_resources = ARRAY_SIZE(tmu2_resources), 337 .num_resources = ARRAY_SIZE(tmu2_resources),
338 .archdata = {
339 .hwblk_id = HWBLK_TMU0,
340 },
228}; 341};
229 342
230static struct sh_timer_config tmu3_platform_data = { 343static struct sh_timer_config tmu3_platform_data = {
231 .name = "TMU3",
232 .channel_offset = 0x04, 344 .channel_offset = 0x04,
233 .timer_bit = 0, 345 .timer_bit = 0,
234 .clk = "tmu1",
235}; 346};
236 347
237static struct resource tmu3_resources[] = { 348static struct resource tmu3_resources[] = {
238 [0] = { 349 [0] = {
239 .name = "TMU3",
240 .start = 0xffd90008, 350 .start = 0xffd90008,
241 .end = 0xffd90013, 351 .end = 0xffd90013,
242 .flags = IORESOURCE_MEM, 352 .flags = IORESOURCE_MEM,
@@ -255,18 +365,18 @@ static struct platform_device tmu3_device = {
255 }, 365 },
256 .resource = tmu3_resources, 366 .resource = tmu3_resources,
257 .num_resources = ARRAY_SIZE(tmu3_resources), 367 .num_resources = ARRAY_SIZE(tmu3_resources),
368 .archdata = {
369 .hwblk_id = HWBLK_TMU1,
370 },
258}; 371};
259 372
260static struct sh_timer_config tmu4_platform_data = { 373static struct sh_timer_config tmu4_platform_data = {
261 .name = "TMU4",
262 .channel_offset = 0x10, 374 .channel_offset = 0x10,
263 .timer_bit = 1, 375 .timer_bit = 1,
264 .clk = "tmu1",
265}; 376};
266 377
267static struct resource tmu4_resources[] = { 378static struct resource tmu4_resources[] = {
268 [0] = { 379 [0] = {
269 .name = "TMU4",
270 .start = 0xffd90014, 380 .start = 0xffd90014,
271 .end = 0xffd9001f, 381 .end = 0xffd9001f,
272 .flags = IORESOURCE_MEM, 382 .flags = IORESOURCE_MEM,
@@ -285,18 +395,18 @@ static struct platform_device tmu4_device = {
285 }, 395 },
286 .resource = tmu4_resources, 396 .resource = tmu4_resources,
287 .num_resources = ARRAY_SIZE(tmu4_resources), 397 .num_resources = ARRAY_SIZE(tmu4_resources),
398 .archdata = {
399 .hwblk_id = HWBLK_TMU1,
400 },
288}; 401};
289 402
290static struct sh_timer_config tmu5_platform_data = { 403static struct sh_timer_config tmu5_platform_data = {
291 .name = "TMU5",
292 .channel_offset = 0x1c, 404 .channel_offset = 0x1c,
293 .timer_bit = 2, 405 .timer_bit = 2,
294 .clk = "tmu1",
295}; 406};
296 407
297static struct resource tmu5_resources[] = { 408static struct resource tmu5_resources[] = {
298 [0] = { 409 [0] = {
299 .name = "TMU5",
300 .start = 0xffd90020, 410 .start = 0xffd90020,
301 .end = 0xffd9002b, 411 .end = 0xffd9002b,
302 .flags = IORESOURCE_MEM, 412 .flags = IORESOURCE_MEM,
@@ -315,67 +425,8 @@ static struct platform_device tmu5_device = {
315 }, 425 },
316 .resource = tmu5_resources, 426 .resource = tmu5_resources,
317 .num_resources = ARRAY_SIZE(tmu5_resources), 427 .num_resources = ARRAY_SIZE(tmu5_resources),
318}; 428 .archdata = {
319 429 .hwblk_id = HWBLK_TMU1,
320static struct plat_sci_port sci_platform_data[] = {
321 {
322 .mapbase = 0xffe00000,
323 .flags = UPF_BOOT_AUTOCONF,
324 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
325 .scbrr_algo_id = SCBRR_ALGO_2,
326 .type = PORT_SCIF,
327 .irqs = { 80, 80, 80, 80 },
328 .clk = "scif0",
329 },{
330 .mapbase = 0xffe10000,
331 .flags = UPF_BOOT_AUTOCONF,
332 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
333 .scbrr_algo_id = SCBRR_ALGO_2,
334 .type = PORT_SCIF,
335 .irqs = { 81, 81, 81, 81 },
336 .clk = "scif1",
337 },{
338 .mapbase = 0xffe20000,
339 .flags = UPF_BOOT_AUTOCONF,
340 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
341 .scbrr_algo_id = SCBRR_ALGO_2,
342 .type = PORT_SCIF,
343 .irqs = { 82, 82, 82, 82 },
344 .clk = "scif2",
345 },{
346 .mapbase = 0xa4e30000,
347 .flags = UPF_BOOT_AUTOCONF,
348 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
349 .scbrr_algo_id = SCBRR_ALGO_3,
350 .type = PORT_SCIFA,
351 .irqs = { 56, 56, 56, 56 },
352 .clk = "scif3",
353 },{
354 .mapbase = 0xa4e40000,
355 .flags = UPF_BOOT_AUTOCONF,
356 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
357 .scbrr_algo_id = SCBRR_ALGO_3,
358 .type = PORT_SCIFA,
359 .irqs = { 88, 88, 88, 88 },
360 .clk = "scif4",
361 },{
362 .mapbase = 0xa4e50000,
363 .flags = UPF_BOOT_AUTOCONF,
364 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
365 .scbrr_algo_id = SCBRR_ALGO_3,
366 .type = PORT_SCIFA,
367 .irqs = { 109, 109, 109, 109 },
368 .clk = "scif5",
369 }, {
370 .flags = 0,
371 }
372};
373
374static struct platform_device sci_device = {
375 .name = "sh-sci",
376 .id = -1,
377 .dev = {
378 .platform_data = sci_platform_data,
379 }, 430 },
380}; 431};
381 432
@@ -407,10 +458,13 @@ static struct platform_device rtc_device = {
407 .id = -1, 458 .id = -1,
408 .num_resources = ARRAY_SIZE(rtc_resources), 459 .num_resources = ARRAY_SIZE(rtc_resources),
409 .resource = rtc_resources, 460 .resource = rtc_resources,
461 .archdata = {
462 .hwblk_id = HWBLK_RTC,
463 },
410}; 464};
411 465
412static struct r8a66597_platdata r8a66597_data = { 466static struct r8a66597_platdata r8a66597_data = {
413 /* This set zero to all members */ 467 .on_chip = 1,
414}; 468};
415 469
416static struct resource sh7723_usb_host_resources[] = { 470static struct resource sh7723_usb_host_resources[] = {
@@ -436,6 +490,9 @@ static struct platform_device sh7723_usb_host_device = {
436 }, 490 },
437 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), 491 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources),
438 .resource = sh7723_usb_host_resources, 492 .resource = sh7723_usb_host_resources,
493 .archdata = {
494 .hwblk_id = HWBLK_USB,
495 },
439}; 496};
440 497
441static struct resource iic_resources[] = { 498static struct resource iic_resources[] = {
@@ -457,9 +514,18 @@ static struct platform_device iic_device = {
457 .id = 0, /* "i2c0" clock */ 514 .id = 0, /* "i2c0" clock */
458 .num_resources = ARRAY_SIZE(iic_resources), 515 .num_resources = ARRAY_SIZE(iic_resources),
459 .resource = iic_resources, 516 .resource = iic_resources,
517 .archdata = {
518 .hwblk_id = HWBLK_IIC,
519 },
460}; 520};
461 521
462static struct platform_device *sh7723_devices[] __initdata = { 522static struct platform_device *sh7723_devices[] __initdata = {
523 &scif0_device,
524 &scif1_device,
525 &scif2_device,
526 &scif3_device,
527 &scif4_device,
528 &scif5_device,
463 &cmt_device, 529 &cmt_device,
464 &tmu0_device, 530 &tmu0_device,
465 &tmu1_device, 531 &tmu1_device,
@@ -467,7 +533,6 @@ static struct platform_device *sh7723_devices[] __initdata = {
467 &tmu3_device, 533 &tmu3_device,
468 &tmu4_device, 534 &tmu4_device,
469 &tmu5_device, 535 &tmu5_device,
470 &sci_device,
471 &rtc_device, 536 &rtc_device,
472 &iic_device, 537 &iic_device,
473 &sh7723_usb_host_device, 538 &sh7723_usb_host_device,
@@ -485,9 +550,15 @@ static int __init sh7723_devices_setup(void)
485 return platform_add_devices(sh7723_devices, 550 return platform_add_devices(sh7723_devices,
486 ARRAY_SIZE(sh7723_devices)); 551 ARRAY_SIZE(sh7723_devices));
487} 552}
488__initcall(sh7723_devices_setup); 553arch_initcall(sh7723_devices_setup);
489 554
490static struct platform_device *sh7723_early_devices[] __initdata = { 555static struct platform_device *sh7723_early_devices[] __initdata = {
556 &scif0_device,
557 &scif1_device,
558 &scif2_device,
559 &scif3_device,
560 &scif4_device,
561 &scif5_device,
491 &cmt_device, 562 &cmt_device,
492 &tmu0_device, 563 &tmu0_device,
493 &tmu1_device, 564 &tmu1_device,
@@ -506,14 +577,17 @@ void __init plat_early_device_setup(void)
506#define RAMCR_CACHE_L2FC 0x0002 577#define RAMCR_CACHE_L2FC 0x0002
507#define RAMCR_CACHE_L2E 0x0001 578#define RAMCR_CACHE_L2E 0x0001
508#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 579#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
509void __uses_jump_to_uncached l2_cache_init(void) 580
581void l2_cache_init(void)
510{ 582{
511 /* Enable L2 cache */ 583 /* Enable L2 cache */
512 ctrl_outl(L2_CACHE_ENABLE, RAMCR); 584 __raw_writel(L2_CACHE_ENABLE, RAMCR);
513} 585}
514 586
515enum { 587enum {
516 UNUSED=0, 588 UNUSED=0,
589 ENABLED,
590 DISABLED,
517 591
518 /* interrupt sources */ 592 /* interrupt sources */
519 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 593 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -536,7 +610,6 @@ enum {
536 SCIFA_SCIFA1, 610 SCIFA_SCIFA1,
537 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, 611 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
538 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, 612 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
539 SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
540 CMT_CMTI, 613 CMT_CMTI,
541 TSIF_TSIFI, 614 TSIF_TSIFI,
542 SIU_SIUI, 615 SIU_SIUI,
@@ -544,7 +617,6 @@ enum {
544 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 617 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
545 IRDA_IRDAI, 618 IRDA_IRDAI,
546 ATAPI_ATAPII, 619 ATAPI_ATAPII,
547 SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
548 VEU2H1_VEU2HI, 620 VEU2H1_VEU2HI,
549 LCDC_LCDCI, 621 LCDC_LCDCI,
550 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, 622 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
@@ -615,9 +687,9 @@ static struct intc_vect vectors[] __initdata = {
615 INTC_VECT(I2C_WAITI,0xE40), 687 INTC_VECT(I2C_WAITI,0xE40),
616 INTC_VECT(I2C_DTEI,0xE60), 688 INTC_VECT(I2C_DTEI,0xE60),
617 689
618 INTC_VECT(SDHI0_SDHII0,0xE80), 690 INTC_VECT(SDHI0, 0xE80),
619 INTC_VECT(SDHI0_SDHII1,0xEA0), 691 INTC_VECT(SDHI0, 0xEA0),
620 INTC_VECT(SDHI0_SDHII2,0xEC0), 692 INTC_VECT(SDHI0, 0xEC0),
621 693
622 INTC_VECT(CMT_CMTI,0xF00), 694 INTC_VECT(CMT_CMTI,0xF00),
623 INTC_VECT(TSIF_TSIFI,0xF20), 695 INTC_VECT(TSIF_TSIFI,0xF20),
@@ -631,9 +703,9 @@ static struct intc_vect vectors[] __initdata = {
631 INTC_VECT(IRDA_IRDAI,0x480), 703 INTC_VECT(IRDA_IRDAI,0x480),
632 INTC_VECT(ATAPI_ATAPII,0x4A0), 704 INTC_VECT(ATAPI_ATAPII,0x4A0),
633 705
634 INTC_VECT(SDHI1_SDHII0,0x4E0), 706 INTC_VECT(SDHI1, 0x4E0),
635 INTC_VECT(SDHI1_SDHII1,0x500), 707 INTC_VECT(SDHI1, 0x500),
636 INTC_VECT(SDHI1_SDHII2,0x520), 708 INTC_VECT(SDHI1, 0x520),
637 709
638 INTC_VECT(VEU2H1_VEU2HI,0x560), 710 INTC_VECT(VEU2H1_VEU2HI,0x560),
639 INTC_VECT(LCDC_LCDCI,0x580), 711 INTC_VECT(LCDC_LCDCI,0x580),
@@ -652,15 +724,14 @@ static struct intc_group groups[] __initdata = {
652 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), 724 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
653 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), 725 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
654 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), 726 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
655 INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
656 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), 727 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
657 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), 728 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
658 INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
659}; 729};
660 730
661static struct intc_mask_reg mask_registers[] __initdata = { 731static struct intc_mask_reg mask_registers[] __initdata = {
662 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 732 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
663 { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} }, 733 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
734 0, DISABLED, ENABLED, ENABLED } },
664 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 735 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
665 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, 736 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
666 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 737 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
@@ -677,7 +748,8 @@ static struct intc_mask_reg mask_registers[] __initdata = {
677 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 748 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
678 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 749 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
679 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 750 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
680 { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } }, 751 { 0, DISABLED, ENABLED, ENABLED,
752 0, 0, SCIFA_SCIFA2, SIU_SIUI } },
681 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 753 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
682 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, 754 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
683 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 755 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -717,9 +789,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
717 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 789 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
718}; 790};
719 791
720static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups, 792static struct intc_desc intc_desc __initdata = {
721 mask_registers, prio_registers, sense_registers, 793 .name = "sh7723",
722 ack_registers); 794 .force_enable = ENABLED,
795 .force_disable = DISABLED,
796 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
797 prio_registers, sense_registers, ack_registers),
798};
723 799
724void __init plat_irq_setup(void) 800void __init plat_irq_setup(void)
725{ 801{
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index c934b78e5658..4a8b751c5f17 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -18,71 +18,341 @@
18#include <linux/mm.h> 18#include <linux/mm.h>
19#include <linux/serial_sci.h> 19#include <linux/serial_sci.h>
20#include <linux/uio_driver.h> 20#include <linux/uio_driver.h>
21#include <linux/sh_dma.h>
21#include <linux/sh_timer.h> 22#include <linux/sh_timer.h>
22#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/notifier.h>
25
26#include <asm/suspend.h>
23#include <asm/clock.h> 27#include <asm/clock.h>
24#include <asm/mmzone.h> 28#include <asm/mmzone.h>
25 29
26/* Serial */ 30#include <cpu/dma-register.h>
27static struct plat_sci_port sci_platform_data[] = { 31#include <cpu/sh7724.h>
32
33/* DMA */
34static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
28 { 35 {
29 .mapbase = 0xffe00000, 36 .slave_id = SHDMA_SLAVE_SCIF0_TX,
30 .flags = UPF_BOOT_AUTOCONF, 37 .addr = 0xffe0000c,
31 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 38 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
32 .scbrr_algo_id = SCBRR_ALGO_2, 39 .mid_rid = 0x21,
33 .type = PORT_SCIF, 40 }, {
34 .irqs = { 80, 80, 80, 80 }, 41 .slave_id = SHDMA_SLAVE_SCIF0_RX,
35 .clk = "scif0", 42 .addr = 0xffe00014,
43 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
44 .mid_rid = 0x22,
45 }, {
46 .slave_id = SHDMA_SLAVE_SCIF1_TX,
47 .addr = 0xffe1000c,
48 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
49 .mid_rid = 0x25,
50 }, {
51 .slave_id = SHDMA_SLAVE_SCIF1_RX,
52 .addr = 0xffe10014,
53 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
54 .mid_rid = 0x26,
55 }, {
56 .slave_id = SHDMA_SLAVE_SCIF2_TX,
57 .addr = 0xffe2000c,
58 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
59 .mid_rid = 0x29,
36 }, { 60 }, {
37 .mapbase = 0xffe10000, 61 .slave_id = SHDMA_SLAVE_SCIF2_RX,
38 .flags = UPF_BOOT_AUTOCONF, 62 .addr = 0xffe20014,
39 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 63 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
40 .scbrr_algo_id = SCBRR_ALGO_2, 64 .mid_rid = 0x2a,
41 .type = PORT_SCIF,
42 .irqs = { 81, 81, 81, 81 },
43 .clk = "scif1",
44 }, { 65 }, {
45 .mapbase = 0xffe20000, 66 .slave_id = SHDMA_SLAVE_SCIF3_TX,
46 .flags = UPF_BOOT_AUTOCONF, 67 .addr = 0xa4e30020,
47 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 68 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
48 .scbrr_algo_id = SCBRR_ALGO_2, 69 .mid_rid = 0x2d,
49 .type = PORT_SCIF,
50 .irqs = { 82, 82, 82, 82 },
51 .clk = "scif2",
52 }, { 70 }, {
53 .mapbase = 0xa4e30000, 71 .slave_id = SHDMA_SLAVE_SCIF3_RX,
54 .flags = UPF_BOOT_AUTOCONF, 72 .addr = 0xa4e30024,
55 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 73 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
56 .scbrr_algo_id = SCBRR_ALGO_3, 74 .mid_rid = 0x2e,
57 .type = PORT_SCIFA,
58 .irqs = { 56, 56, 56, 56 },
59 .clk = "scif3",
60 }, { 75 }, {
61 .mapbase = 0xa4e40000, 76 .slave_id = SHDMA_SLAVE_SCIF4_TX,
62 .flags = UPF_BOOT_AUTOCONF, 77 .addr = 0xa4e40020,
63 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 78 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
64 .scbrr_algo_id = SCBRR_ALGO_3, 79 .mid_rid = 0x31,
65 .type = PORT_SCIFA,
66 .irqs = { 88, 88, 88, 88 },
67 .clk = "scif4",
68 }, { 80 }, {
69 .mapbase = 0xa4e50000, 81 .slave_id = SHDMA_SLAVE_SCIF4_RX,
70 .flags = UPF_BOOT_AUTOCONF, 82 .addr = 0xa4e40024,
71 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 83 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
72 .scbrr_algo_id = SCBRR_ALGO_3, 84 .mid_rid = 0x32,
73 .type = PORT_SCIFA,
74 .irqs = { 109, 109, 109, 109 },
75 .clk = "scif5",
76 }, { 85 }, {
77 .flags = 0, 86 .slave_id = SHDMA_SLAVE_SCIF5_TX,
87 .addr = 0xa4e50020,
88 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
89 .mid_rid = 0x35,
90 }, {
91 .slave_id = SHDMA_SLAVE_SCIF5_RX,
92 .addr = 0xa4e50024,
93 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
94 .mid_rid = 0x36,
95 }, {
96 .slave_id = SHDMA_SLAVE_SDHI0_TX,
97 .addr = 0x04ce0030,
98 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
99 .mid_rid = 0xc1,
100 }, {
101 .slave_id = SHDMA_SLAVE_SDHI0_RX,
102 .addr = 0x04ce0030,
103 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
104 .mid_rid = 0xc2,
105 }, {
106 .slave_id = SHDMA_SLAVE_SDHI1_TX,
107 .addr = 0x04cf0030,
108 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
109 .mid_rid = 0xc9,
110 }, {
111 .slave_id = SHDMA_SLAVE_SDHI1_RX,
112 .addr = 0x04cf0030,
113 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
114 .mid_rid = 0xca,
115 },
116};
117
118static const struct sh_dmae_channel sh7724_dmae_channels[] = {
119 {
120 .offset = 0,
121 .dmars = 0,
122 .dmars_bit = 0,
123 }, {
124 .offset = 0x10,
125 .dmars = 0,
126 .dmars_bit = 8,
127 }, {
128 .offset = 0x20,
129 .dmars = 4,
130 .dmars_bit = 0,
131 }, {
132 .offset = 0x30,
133 .dmars = 4,
134 .dmars_bit = 8,
135 }, {
136 .offset = 0x50,
137 .dmars = 8,
138 .dmars_bit = 0,
139 }, {
140 .offset = 0x60,
141 .dmars = 8,
142 .dmars_bit = 8,
78 } 143 }
79}; 144};
80 145
81static struct platform_device sci_device = { 146static const unsigned int ts_shift[] = TS_SHIFT;
147
148static struct sh_dmae_pdata dma_platform_data = {
149 .slave = sh7724_dmae_slaves,
150 .slave_num = ARRAY_SIZE(sh7724_dmae_slaves),
151 .channel = sh7724_dmae_channels,
152 .channel_num = ARRAY_SIZE(sh7724_dmae_channels),
153 .ts_low_shift = CHCR_TS_LOW_SHIFT,
154 .ts_low_mask = CHCR_TS_LOW_MASK,
155 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
156 .ts_high_mask = CHCR_TS_HIGH_MASK,
157 .ts_shift = ts_shift,
158 .ts_shift_num = ARRAY_SIZE(ts_shift),
159 .dmaor_init = DMAOR_INIT,
160};
161
162/* Resource order important! */
163static struct resource sh7724_dmae0_resources[] = {
164 {
165 /* Channel registers and DMAOR */
166 .start = 0xfe008020,
167 .end = 0xfe00808f,
168 .flags = IORESOURCE_MEM,
169 },
170 {
171 /* DMARSx */
172 .start = 0xfe009000,
173 .end = 0xfe00900b,
174 .flags = IORESOURCE_MEM,
175 },
176 {
177 /* DMA error IRQ */
178 .start = 78,
179 .end = 78,
180 .flags = IORESOURCE_IRQ,
181 },
182 {
183 /* IRQ for channels 0-3 */
184 .start = 48,
185 .end = 51,
186 .flags = IORESOURCE_IRQ,
187 },
188 {
189 /* IRQ for channels 4-5 */
190 .start = 76,
191 .end = 77,
192 .flags = IORESOURCE_IRQ,
193 },
194};
195
196/* Resource order important! */
197static struct resource sh7724_dmae1_resources[] = {
198 {
199 /* Channel registers and DMAOR */
200 .start = 0xfdc08020,
201 .end = 0xfdc0808f,
202 .flags = IORESOURCE_MEM,
203 },
204 {
205 /* DMARSx */
206 .start = 0xfdc09000,
207 .end = 0xfdc0900b,
208 .flags = IORESOURCE_MEM,
209 },
210 {
211 /* DMA error IRQ */
212 .start = 74,
213 .end = 74,
214 .flags = IORESOURCE_IRQ,
215 },
216 {
217 /* IRQ for channels 0-3 */
218 .start = 40,
219 .end = 43,
220 .flags = IORESOURCE_IRQ,
221 },
222 {
223 /* IRQ for channels 4-5 */
224 .start = 72,
225 .end = 73,
226 .flags = IORESOURCE_IRQ,
227 },
228};
229
230static struct platform_device dma0_device = {
231 .name = "sh-dma-engine",
232 .id = 0,
233 .resource = sh7724_dmae0_resources,
234 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
235 .dev = {
236 .platform_data = &dma_platform_data,
237 },
238 .archdata = {
239 .hwblk_id = HWBLK_DMAC0,
240 },
241};
242
243static struct platform_device dma1_device = {
244 .name = "sh-dma-engine",
245 .id = 1,
246 .resource = sh7724_dmae1_resources,
247 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
248 .dev = {
249 .platform_data = &dma_platform_data,
250 },
251 .archdata = {
252 .hwblk_id = HWBLK_DMAC1,
253 },
254};
255
256/* Serial */
257static struct plat_sci_port scif0_platform_data = {
258 .mapbase = 0xffe00000,
259 .flags = UPF_BOOT_AUTOCONF,
260 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
261 .scbrr_algo_id = SCBRR_ALGO_2,
262 .type = PORT_SCIF,
263 .irqs = { 80, 80, 80, 80 },
264};
265
266static struct platform_device scif0_device = {
82 .name = "sh-sci", 267 .name = "sh-sci",
83 .id = -1, 268 .id = 0,
269 .dev = {
270 .platform_data = &scif0_platform_data,
271 },
272};
273
274static struct plat_sci_port scif1_platform_data = {
275 .mapbase = 0xffe10000,
276 .flags = UPF_BOOT_AUTOCONF,
277 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
278 .scbrr_algo_id = SCBRR_ALGO_2,
279 .type = PORT_SCIF,
280 .irqs = { 81, 81, 81, 81 },
281};
282
283static struct platform_device scif1_device = {
284 .name = "sh-sci",
285 .id = 1,
286 .dev = {
287 .platform_data = &scif1_platform_data,
288 },
289};
290
291static struct plat_sci_port scif2_platform_data = {
292 .mapbase = 0xffe20000,
293 .flags = UPF_BOOT_AUTOCONF,
294 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
295 .scbrr_algo_id = SCBRR_ALGO_2,
296 .type = PORT_SCIF,
297 .irqs = { 82, 82, 82, 82 },
298};
299
300static struct platform_device scif2_device = {
301 .name = "sh-sci",
302 .id = 2,
84 .dev = { 303 .dev = {
85 .platform_data = sci_platform_data, 304 .platform_data = &scif2_platform_data,
305 },
306};
307
308static struct plat_sci_port scif3_platform_data = {
309 .mapbase = 0xa4e30000,
310 .flags = UPF_BOOT_AUTOCONF,
311 .scscr = SCSCR_RE | SCSCR_TE,
312 .scbrr_algo_id = SCBRR_ALGO_3,
313 .type = PORT_SCIFA,
314 .irqs = { 56, 56, 56, 56 },
315};
316
317static struct platform_device scif3_device = {
318 .name = "sh-sci",
319 .id = 3,
320 .dev = {
321 .platform_data = &scif3_platform_data,
322 },
323};
324
325static struct plat_sci_port scif4_platform_data = {
326 .mapbase = 0xa4e40000,
327 .flags = UPF_BOOT_AUTOCONF,
328 .scscr = SCSCR_RE | SCSCR_TE,
329 .scbrr_algo_id = SCBRR_ALGO_3,
330 .type = PORT_SCIFA,
331 .irqs = { 88, 88, 88, 88 },
332};
333
334static struct platform_device scif4_device = {
335 .name = "sh-sci",
336 .id = 4,
337 .dev = {
338 .platform_data = &scif4_platform_data,
339 },
340};
341
342static struct plat_sci_port scif5_platform_data = {
343 .mapbase = 0xa4e50000,
344 .flags = UPF_BOOT_AUTOCONF,
345 .scscr = SCSCR_RE | SCSCR_TE,
346 .scbrr_algo_id = SCBRR_ALGO_3,
347 .type = PORT_SCIFA,
348 .irqs = { 109, 109, 109, 109 },
349};
350
351static struct platform_device scif5_device = {
352 .name = "sh-sci",
353 .id = 5,
354 .dev = {
355 .platform_data = &scif5_platform_data,
86 }, 356 },
87}; 357};
88 358
@@ -115,6 +385,9 @@ static struct platform_device rtc_device = {
115 .id = -1, 385 .id = -1,
116 .num_resources = ARRAY_SIZE(rtc_resources), 386 .num_resources = ARRAY_SIZE(rtc_resources),
117 .resource = rtc_resources, 387 .resource = rtc_resources,
388 .archdata = {
389 .hwblk_id = HWBLK_RTC,
390 },
118}; 391};
119 392
120/* I2C0 */ 393/* I2C0 */
@@ -137,6 +410,9 @@ static struct platform_device iic0_device = {
137 .id = 0, /* "i2c0" clock */ 410 .id = 0, /* "i2c0" clock */
138 .num_resources = ARRAY_SIZE(iic0_resources), 411 .num_resources = ARRAY_SIZE(iic0_resources),
139 .resource = iic0_resources, 412 .resource = iic0_resources,
413 .archdata = {
414 .hwblk_id = HWBLK_IIC0,
415 },
140}; 416};
141 417
142/* I2C1 */ 418/* I2C1 */
@@ -159,6 +435,9 @@ static struct platform_device iic1_device = {
159 .id = 1, /* "i2c1" clock */ 435 .id = 1, /* "i2c1" clock */
160 .num_resources = ARRAY_SIZE(iic1_resources), 436 .num_resources = ARRAY_SIZE(iic1_resources),
161 .resource = iic1_resources, 437 .resource = iic1_resources,
438 .archdata = {
439 .hwblk_id = HWBLK_IIC1,
440 },
162}; 441};
163 442
164/* VPU */ 443/* VPU */
@@ -188,6 +467,9 @@ static struct platform_device vpu_device = {
188 }, 467 },
189 .resource = vpu_resources, 468 .resource = vpu_resources,
190 .num_resources = ARRAY_SIZE(vpu_resources), 469 .num_resources = ARRAY_SIZE(vpu_resources),
470 .archdata = {
471 .hwblk_id = HWBLK_VPU,
472 },
191}; 473};
192 474
193/* VEU0 */ 475/* VEU0 */
@@ -201,7 +483,7 @@ static struct resource veu0_resources[] = {
201 [0] = { 483 [0] = {
202 .name = "VEU3F0", 484 .name = "VEU3F0",
203 .start = 0xfe920000, 485 .start = 0xfe920000,
204 .end = 0xfe9200cb - 1, 486 .end = 0xfe9200cb,
205 .flags = IORESOURCE_MEM, 487 .flags = IORESOURCE_MEM,
206 }, 488 },
207 [1] = { 489 [1] = {
@@ -217,6 +499,9 @@ static struct platform_device veu0_device = {
217 }, 499 },
218 .resource = veu0_resources, 500 .resource = veu0_resources,
219 .num_resources = ARRAY_SIZE(veu0_resources), 501 .num_resources = ARRAY_SIZE(veu0_resources),
502 .archdata = {
503 .hwblk_id = HWBLK_VEU0,
504 },
220}; 505};
221 506
222/* VEU1 */ 507/* VEU1 */
@@ -230,7 +515,7 @@ static struct resource veu1_resources[] = {
230 [0] = { 515 [0] = {
231 .name = "VEU3F1", 516 .name = "VEU3F1",
232 .start = 0xfe924000, 517 .start = 0xfe924000,
233 .end = 0xfe9240cb - 1, 518 .end = 0xfe9240cb,
234 .flags = IORESOURCE_MEM, 519 .flags = IORESOURCE_MEM,
235 }, 520 },
236 [1] = { 521 [1] = {
@@ -246,20 +531,84 @@ static struct platform_device veu1_device = {
246 }, 531 },
247 .resource = veu1_resources, 532 .resource = veu1_resources,
248 .num_resources = ARRAY_SIZE(veu1_resources), 533 .num_resources = ARRAY_SIZE(veu1_resources),
534 .archdata = {
535 .hwblk_id = HWBLK_VEU1,
536 },
537};
538
539/* BEU0 */
540static struct uio_info beu0_platform_data = {
541 .name = "BEU0",
542 .version = "0",
543 .irq = evt2irq(0x8A0),
544};
545
546static struct resource beu0_resources[] = {
547 [0] = {
548 .name = "BEU0",
549 .start = 0xfe930000,
550 .end = 0xfe933400,
551 .flags = IORESOURCE_MEM,
552 },
553 [1] = {
554 /* place holder for contiguous memory */
555 },
556};
557
558static struct platform_device beu0_device = {
559 .name = "uio_pdrv_genirq",
560 .id = 6,
561 .dev = {
562 .platform_data = &beu0_platform_data,
563 },
564 .resource = beu0_resources,
565 .num_resources = ARRAY_SIZE(beu0_resources),
566 .archdata = {
567 .hwblk_id = HWBLK_BEU0,
568 },
569};
570
571/* BEU1 */
572static struct uio_info beu1_platform_data = {
573 .name = "BEU1",
574 .version = "0",
575 .irq = evt2irq(0xA00),
576};
577
578static struct resource beu1_resources[] = {
579 [0] = {
580 .name = "BEU1",
581 .start = 0xfe940000,
582 .end = 0xfe943400,
583 .flags = IORESOURCE_MEM,
584 },
585 [1] = {
586 /* place holder for contiguous memory */
587 },
588};
589
590static struct platform_device beu1_device = {
591 .name = "uio_pdrv_genirq",
592 .id = 7,
593 .dev = {
594 .platform_data = &beu1_platform_data,
595 },
596 .resource = beu1_resources,
597 .num_resources = ARRAY_SIZE(beu1_resources),
598 .archdata = {
599 .hwblk_id = HWBLK_BEU1,
600 },
249}; 601};
250 602
251static struct sh_timer_config cmt_platform_data = { 603static struct sh_timer_config cmt_platform_data = {
252 .name = "CMT",
253 .channel_offset = 0x60, 604 .channel_offset = 0x60,
254 .timer_bit = 5, 605 .timer_bit = 5,
255 .clk = "cmt0",
256 .clockevent_rating = 125, 606 .clockevent_rating = 125,
257 .clocksource_rating = 200, 607 .clocksource_rating = 200,
258}; 608};
259 609
260static struct resource cmt_resources[] = { 610static struct resource cmt_resources[] = {
261 [0] = { 611 [0] = {
262 .name = "CMT",
263 .start = 0x044a0060, 612 .start = 0x044a0060,
264 .end = 0x044a006b, 613 .end = 0x044a006b,
265 .flags = IORESOURCE_MEM, 614 .flags = IORESOURCE_MEM,
@@ -278,19 +627,19 @@ static struct platform_device cmt_device = {
278 }, 627 },
279 .resource = cmt_resources, 628 .resource = cmt_resources,
280 .num_resources = ARRAY_SIZE(cmt_resources), 629 .num_resources = ARRAY_SIZE(cmt_resources),
630 .archdata = {
631 .hwblk_id = HWBLK_CMT,
632 },
281}; 633};
282 634
283static struct sh_timer_config tmu0_platform_data = { 635static struct sh_timer_config tmu0_platform_data = {
284 .name = "TMU0",
285 .channel_offset = 0x04, 636 .channel_offset = 0x04,
286 .timer_bit = 0, 637 .timer_bit = 0,
287 .clk = "tmu0",
288 .clockevent_rating = 200, 638 .clockevent_rating = 200,
289}; 639};
290 640
291static struct resource tmu0_resources[] = { 641static struct resource tmu0_resources[] = {
292 [0] = { 642 [0] = {
293 .name = "TMU0",
294 .start = 0xffd80008, 643 .start = 0xffd80008,
295 .end = 0xffd80013, 644 .end = 0xffd80013,
296 .flags = IORESOURCE_MEM, 645 .flags = IORESOURCE_MEM,
@@ -309,19 +658,19 @@ static struct platform_device tmu0_device = {
309 }, 658 },
310 .resource = tmu0_resources, 659 .resource = tmu0_resources,
311 .num_resources = ARRAY_SIZE(tmu0_resources), 660 .num_resources = ARRAY_SIZE(tmu0_resources),
661 .archdata = {
662 .hwblk_id = HWBLK_TMU0,
663 },
312}; 664};
313 665
314static struct sh_timer_config tmu1_platform_data = { 666static struct sh_timer_config tmu1_platform_data = {
315 .name = "TMU1",
316 .channel_offset = 0x10, 667 .channel_offset = 0x10,
317 .timer_bit = 1, 668 .timer_bit = 1,
318 .clk = "tmu0",
319 .clocksource_rating = 200, 669 .clocksource_rating = 200,
320}; 670};
321 671
322static struct resource tmu1_resources[] = { 672static struct resource tmu1_resources[] = {
323 [0] = { 673 [0] = {
324 .name = "TMU1",
325 .start = 0xffd80014, 674 .start = 0xffd80014,
326 .end = 0xffd8001f, 675 .end = 0xffd8001f,
327 .flags = IORESOURCE_MEM, 676 .flags = IORESOURCE_MEM,
@@ -340,18 +689,18 @@ static struct platform_device tmu1_device = {
340 }, 689 },
341 .resource = tmu1_resources, 690 .resource = tmu1_resources,
342 .num_resources = ARRAY_SIZE(tmu1_resources), 691 .num_resources = ARRAY_SIZE(tmu1_resources),
692 .archdata = {
693 .hwblk_id = HWBLK_TMU0,
694 },
343}; 695};
344 696
345static struct sh_timer_config tmu2_platform_data = { 697static struct sh_timer_config tmu2_platform_data = {
346 .name = "TMU2",
347 .channel_offset = 0x1c, 698 .channel_offset = 0x1c,
348 .timer_bit = 2, 699 .timer_bit = 2,
349 .clk = "tmu0",
350}; 700};
351 701
352static struct resource tmu2_resources[] = { 702static struct resource tmu2_resources[] = {
353 [0] = { 703 [0] = {
354 .name = "TMU2",
355 .start = 0xffd80020, 704 .start = 0xffd80020,
356 .end = 0xffd8002b, 705 .end = 0xffd8002b,
357 .flags = IORESOURCE_MEM, 706 .flags = IORESOURCE_MEM,
@@ -370,19 +719,19 @@ static struct platform_device tmu2_device = {
370 }, 719 },
371 .resource = tmu2_resources, 720 .resource = tmu2_resources,
372 .num_resources = ARRAY_SIZE(tmu2_resources), 721 .num_resources = ARRAY_SIZE(tmu2_resources),
722 .archdata = {
723 .hwblk_id = HWBLK_TMU0,
724 },
373}; 725};
374 726
375 727
376static struct sh_timer_config tmu3_platform_data = { 728static struct sh_timer_config tmu3_platform_data = {
377 .name = "TMU3",
378 .channel_offset = 0x04, 729 .channel_offset = 0x04,
379 .timer_bit = 0, 730 .timer_bit = 0,
380 .clk = "tmu1",
381}; 731};
382 732
383static struct resource tmu3_resources[] = { 733static struct resource tmu3_resources[] = {
384 [0] = { 734 [0] = {
385 .name = "TMU3",
386 .start = 0xffd90008, 735 .start = 0xffd90008,
387 .end = 0xffd90013, 736 .end = 0xffd90013,
388 .flags = IORESOURCE_MEM, 737 .flags = IORESOURCE_MEM,
@@ -401,18 +750,18 @@ static struct platform_device tmu3_device = {
401 }, 750 },
402 .resource = tmu3_resources, 751 .resource = tmu3_resources,
403 .num_resources = ARRAY_SIZE(tmu3_resources), 752 .num_resources = ARRAY_SIZE(tmu3_resources),
753 .archdata = {
754 .hwblk_id = HWBLK_TMU1,
755 },
404}; 756};
405 757
406static struct sh_timer_config tmu4_platform_data = { 758static struct sh_timer_config tmu4_platform_data = {
407 .name = "TMU4",
408 .channel_offset = 0x10, 759 .channel_offset = 0x10,
409 .timer_bit = 1, 760 .timer_bit = 1,
410 .clk = "tmu1",
411}; 761};
412 762
413static struct resource tmu4_resources[] = { 763static struct resource tmu4_resources[] = {
414 [0] = { 764 [0] = {
415 .name = "TMU4",
416 .start = 0xffd90014, 765 .start = 0xffd90014,
417 .end = 0xffd9001f, 766 .end = 0xffd9001f,
418 .flags = IORESOURCE_MEM, 767 .flags = IORESOURCE_MEM,
@@ -431,18 +780,18 @@ static struct platform_device tmu4_device = {
431 }, 780 },
432 .resource = tmu4_resources, 781 .resource = tmu4_resources,
433 .num_resources = ARRAY_SIZE(tmu4_resources), 782 .num_resources = ARRAY_SIZE(tmu4_resources),
783 .archdata = {
784 .hwblk_id = HWBLK_TMU1,
785 },
434}; 786};
435 787
436static struct sh_timer_config tmu5_platform_data = { 788static struct sh_timer_config tmu5_platform_data = {
437 .name = "TMU5",
438 .channel_offset = 0x1c, 789 .channel_offset = 0x1c,
439 .timer_bit = 2, 790 .timer_bit = 2,
440 .clk = "tmu1",
441}; 791};
442 792
443static struct resource tmu5_resources[] = { 793static struct resource tmu5_resources[] = {
444 [0] = { 794 [0] = {
445 .name = "TMU5",
446 .start = 0xffd90020, 795 .start = 0xffd90020,
447 .end = 0xffd9002b, 796 .end = 0xffd9002b,
448 .flags = IORESOURCE_MEM, 797 .flags = IORESOURCE_MEM,
@@ -461,6 +810,9 @@ static struct platform_device tmu5_device = {
461 }, 810 },
462 .resource = tmu5_resources, 811 .resource = tmu5_resources,
463 .num_resources = ARRAY_SIZE(tmu5_resources), 812 .num_resources = ARRAY_SIZE(tmu5_resources),
813 .archdata = {
814 .hwblk_id = HWBLK_TMU1,
815 },
464}; 816};
465 817
466/* JPU */ 818/* JPU */
@@ -490,9 +842,82 @@ static struct platform_device jpu_device = {
490 }, 842 },
491 .resource = jpu_resources, 843 .resource = jpu_resources,
492 .num_resources = ARRAY_SIZE(jpu_resources), 844 .num_resources = ARRAY_SIZE(jpu_resources),
845 .archdata = {
846 .hwblk_id = HWBLK_JPU,
847 },
848};
849
850/* SPU2DSP0 */
851static struct uio_info spu0_platform_data = {
852 .name = "SPU2DSP0",
853 .version = "0",
854 .irq = 86,
855};
856
857static struct resource spu0_resources[] = {
858 [0] = {
859 .name = "SPU2DSP0",
860 .start = 0xFE200000,
861 .end = 0xFE2FFFFF,
862 .flags = IORESOURCE_MEM,
863 },
864 [1] = {
865 /* place holder for contiguous memory */
866 },
867};
868
869static struct platform_device spu0_device = {
870 .name = "uio_pdrv_genirq",
871 .id = 4,
872 .dev = {
873 .platform_data = &spu0_platform_data,
874 },
875 .resource = spu0_resources,
876 .num_resources = ARRAY_SIZE(spu0_resources),
877 .archdata = {
878 .hwblk_id = HWBLK_SPU,
879 },
880};
881
882/* SPU2DSP1 */
883static struct uio_info spu1_platform_data = {
884 .name = "SPU2DSP1",
885 .version = "0",
886 .irq = 87,
887};
888
889static struct resource spu1_resources[] = {
890 [0] = {
891 .name = "SPU2DSP1",
892 .start = 0xFE300000,
893 .end = 0xFE3FFFFF,
894 .flags = IORESOURCE_MEM,
895 },
896 [1] = {
897 /* place holder for contiguous memory */
898 },
899};
900
901static struct platform_device spu1_device = {
902 .name = "uio_pdrv_genirq",
903 .id = 5,
904 .dev = {
905 .platform_data = &spu1_platform_data,
906 },
907 .resource = spu1_resources,
908 .num_resources = ARRAY_SIZE(spu1_resources),
909 .archdata = {
910 .hwblk_id = HWBLK_SPU,
911 },
493}; 912};
494 913
495static struct platform_device *sh7724_devices[] __initdata = { 914static struct platform_device *sh7724_devices[] __initdata = {
915 &scif0_device,
916 &scif1_device,
917 &scif2_device,
918 &scif3_device,
919 &scif4_device,
920 &scif5_device,
496 &cmt_device, 921 &cmt_device,
497 &tmu0_device, 922 &tmu0_device,
498 &tmu1_device, 923 &tmu1_device,
@@ -500,14 +925,19 @@ static struct platform_device *sh7724_devices[] __initdata = {
500 &tmu3_device, 925 &tmu3_device,
501 &tmu4_device, 926 &tmu4_device,
502 &tmu5_device, 927 &tmu5_device,
503 &sci_device, 928 &dma0_device,
929 &dma1_device,
504 &rtc_device, 930 &rtc_device,
505 &iic0_device, 931 &iic0_device,
506 &iic1_device, 932 &iic1_device,
507 &vpu_device, 933 &vpu_device,
508 &veu0_device, 934 &veu0_device,
509 &veu1_device, 935 &veu1_device,
936 &beu0_device,
937 &beu1_device,
510 &jpu_device, 938 &jpu_device,
939 &spu0_device,
940 &spu1_device,
511}; 941};
512 942
513static int __init sh7724_devices_setup(void) 943static int __init sh7724_devices_setup(void)
@@ -516,13 +946,21 @@ static int __init sh7724_devices_setup(void)
516 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 946 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
517 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 947 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
518 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 948 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
949 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
950 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
519 951
520 return platform_add_devices(sh7724_devices, 952 return platform_add_devices(sh7724_devices,
521 ARRAY_SIZE(sh7724_devices)); 953 ARRAY_SIZE(sh7724_devices));
522} 954}
523device_initcall(sh7724_devices_setup); 955arch_initcall(sh7724_devices_setup);
524 956
525static struct platform_device *sh7724_early_devices[] __initdata = { 957static struct platform_device *sh7724_early_devices[] __initdata = {
958 &scif0_device,
959 &scif1_device,
960 &scif2_device,
961 &scif3_device,
962 &scif4_device,
963 &scif5_device,
526 &cmt_device, 964 &cmt_device,
527 &tmu0_device, 965 &tmu0_device,
528 &tmu1_device, 966 &tmu1_device,
@@ -541,14 +979,17 @@ void __init plat_early_device_setup(void)
541#define RAMCR_CACHE_L2FC 0x0002 979#define RAMCR_CACHE_L2FC 0x0002
542#define RAMCR_CACHE_L2E 0x0001 980#define RAMCR_CACHE_L2E 0x0001
543#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 981#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
544void __uses_jump_to_uncached l2_cache_init(void) 982
983void l2_cache_init(void)
545{ 984{
546 /* Enable L2 cache */ 985 /* Enable L2 cache */
547 ctrl_outl(L2_CACHE_ENABLE, RAMCR); 986 __raw_writel(L2_CACHE_ENABLE, RAMCR);
548} 987}
549 988
550enum { 989enum {
551 UNUSED = 0, 990 UNUSED = 0,
991 ENABLED,
992 DISABLED,
552 993
553 /* interrupt sources */ 994 /* interrupt sources */
554 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 995 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -577,14 +1018,12 @@ enum {
577 ETHI, 1018 ETHI,
578 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 1019 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
579 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 1020 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
580 SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3,
581 CMT, 1021 CMT,
582 TSIF, 1022 TSIF,
583 FSI, 1023 FSI,
584 SCIFA5, 1024 SCIFA5,
585 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 1025 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
586 IRDA, 1026 IRDA,
587 SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
588 JPU, 1027 JPU,
589 _2DDMAC, 1028 _2DDMAC,
590 MMC_MMC2I, MMC_MMC3I, 1029 MMC_MMC2I, MMC_MMC3I,
@@ -666,10 +1105,10 @@ static struct intc_vect vectors[] __initdata = {
666 INTC_VECT(I2C0_WAITI, 0xE40), 1105 INTC_VECT(I2C0_WAITI, 0xE40),
667 INTC_VECT(I2C0_DTEI, 0xE60), 1106 INTC_VECT(I2C0_DTEI, 0xE60),
668 1107
669 INTC_VECT(SDHI0_SDHII0, 0xE80), 1108 INTC_VECT(SDHI0, 0xE80),
670 INTC_VECT(SDHI0_SDHII1, 0xEA0), 1109 INTC_VECT(SDHI0, 0xEA0),
671 INTC_VECT(SDHI0_SDHII2, 0xEC0), 1110 INTC_VECT(SDHI0, 0xEC0),
672 INTC_VECT(SDHI0_SDHII3, 0xEE0), 1111 INTC_VECT(SDHI0, 0xEE0),
673 1112
674 INTC_VECT(CMT, 0xF00), 1113 INTC_VECT(CMT, 0xF00),
675 INTC_VECT(TSIF, 0xF20), 1114 INTC_VECT(TSIF, 0xF20),
@@ -682,9 +1121,9 @@ static struct intc_vect vectors[] __initdata = {
682 1121
683 INTC_VECT(IRDA, 0x480), 1122 INTC_VECT(IRDA, 0x480),
684 1123
685 INTC_VECT(SDHI1_SDHII0, 0x4E0), 1124 INTC_VECT(SDHI1, 0x4E0),
686 INTC_VECT(SDHI1_SDHII1, 0x500), 1125 INTC_VECT(SDHI1, 0x500),
687 INTC_VECT(SDHI1_SDHII2, 0x520), 1126 INTC_VECT(SDHI1, 0x520),
688 1127
689 INTC_VECT(JPU, 0x560), 1128 INTC_VECT(JPU, 0x560),
690 INTC_VECT(_2DDMAC, 0x4A0), 1129 INTC_VECT(_2DDMAC, 0x4A0),
@@ -710,8 +1149,6 @@ static struct intc_group groups[] __initdata = {
710 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), 1149 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
711 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 1150 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
712 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 1151 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
713 INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3),
714 INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
715 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), 1152 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
716 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I), 1153 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
717}; 1154};
@@ -719,7 +1156,7 @@ static struct intc_group groups[] __initdata = {
719static struct intc_mask_reg mask_registers[] __initdata = { 1156static struct intc_mask_reg mask_registers[] __initdata = {
720 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 1157 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
721 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 1158 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
722 0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } }, 1159 0, DISABLED, ENABLED, ENABLED } },
723 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 1160 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
724 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, 1161 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
725 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, 1162 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
@@ -741,7 +1178,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
741 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 1178 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
742 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, 1179 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
743 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 1180 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
744 { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0, 1181 { DISABLED, DISABLED, ENABLED, ENABLED,
745 0, 0, SCIFA5, FSI } }, 1182 0, 0, SCIFA5, FSI } },
746 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 1183 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
747 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, 1184 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
@@ -788,11 +1225,205 @@ static struct intc_mask_reg ack_registers[] __initdata = {
788 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1225 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
789}; 1226};
790 1227
791static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups, 1228static struct intc_desc intc_desc __initdata = {
792 mask_registers, prio_registers, sense_registers, 1229 .name = "sh7724",
793 ack_registers); 1230 .force_enable = ENABLED,
1231 .force_disable = DISABLED,
1232 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
1233 prio_registers, sense_registers, ack_registers),
1234};
794 1235
795void __init plat_irq_setup(void) 1236void __init plat_irq_setup(void)
796{ 1237{
797 register_intc_controller(&intc_desc); 1238 register_intc_controller(&intc_desc);
798} 1239}
1240
1241static struct {
1242 /* BSC */
1243 unsigned long mmselr;
1244 unsigned long cs0bcr;
1245 unsigned long cs4bcr;
1246 unsigned long cs5abcr;
1247 unsigned long cs5bbcr;
1248 unsigned long cs6abcr;
1249 unsigned long cs6bbcr;
1250 unsigned long cs4wcr;
1251 unsigned long cs5awcr;
1252 unsigned long cs5bwcr;
1253 unsigned long cs6awcr;
1254 unsigned long cs6bwcr;
1255 /* INTC */
1256 unsigned short ipra;
1257 unsigned short iprb;
1258 unsigned short iprc;
1259 unsigned short iprd;
1260 unsigned short ipre;
1261 unsigned short iprf;
1262 unsigned short iprg;
1263 unsigned short iprh;
1264 unsigned short ipri;
1265 unsigned short iprj;
1266 unsigned short iprk;
1267 unsigned short iprl;
1268 unsigned char imr0;
1269 unsigned char imr1;
1270 unsigned char imr2;
1271 unsigned char imr3;
1272 unsigned char imr4;
1273 unsigned char imr5;
1274 unsigned char imr6;
1275 unsigned char imr7;
1276 unsigned char imr8;
1277 unsigned char imr9;
1278 unsigned char imr10;
1279 unsigned char imr11;
1280 unsigned char imr12;
1281 /* RWDT */
1282 unsigned short rwtcnt;
1283 unsigned short rwtcsr;
1284 /* CPG */
1285 unsigned long irdaclk;
1286 unsigned long spuclk;
1287} sh7724_rstandby_state;
1288
1289static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1290 unsigned long flags, void *unused)
1291{
1292 if (!(flags & SUSP_SH_RSTANDBY))
1293 return NOTIFY_DONE;
1294
1295 /* BCR */
1296 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
1297 sh7724_rstandby_state.mmselr |= 0xa5a50000;
1298 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
1299 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
1300 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
1301 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
1302 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
1303 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
1304 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
1305 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
1306 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
1307 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
1308 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
1309
1310 /* INTC */
1311 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
1312 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
1313 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
1314 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
1315 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
1316 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
1317 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
1318 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
1319 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
1320 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
1321 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
1322 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
1323 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
1324 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
1325 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
1326 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
1327 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
1328 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
1329 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
1330 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
1331 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
1332 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
1333 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
1334 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
1335 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
1336
1337 /* RWDT */
1338 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
1339 sh7724_rstandby_state.rwtcnt |= 0x5a00;
1340 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1341 sh7724_rstandby_state.rwtcsr |= 0xa500;
1342 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1343
1344 /* CPG */
1345 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1346 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1347
1348 return NOTIFY_DONE;
1349}
1350
1351static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1352 unsigned long flags, void *unused)
1353{
1354 if (!(flags & SUSP_SH_RSTANDBY))
1355 return NOTIFY_DONE;
1356
1357 /* BCR */
1358 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1359 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1360 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1361 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1362 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1363 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1364 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1365 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1366 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1367 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1368 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1369 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1370
1371 /* INTC */
1372 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1373 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1374 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1375 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1376 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1377 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1378 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1379 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1380 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1381 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1382 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1383 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1384 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1385 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1386 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1387 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1388 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1389 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1390 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1391 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1392 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1393 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1394 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1395 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1396 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1397
1398 /* RWDT */
1399 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1400 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1401
1402 /* CPG */
1403 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1404 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1405
1406 return NOTIFY_DONE;
1407}
1408
1409static struct notifier_block sh7724_pre_sleep_notifier = {
1410 .notifier_call = sh7724_pre_sleep_notifier_call,
1411 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1412};
1413
1414static struct notifier_block sh7724_post_sleep_notifier = {
1415 .notifier_call = sh7724_post_sleep_notifier_call,
1416 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1417};
1418
1419static int __init sh7724_sleep_setup(void)
1420{
1421 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1422 &sh7724_pre_sleep_notifier);
1423
1424 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1425 &sh7724_post_sleep_notifier);
1426 return 0;
1427}
1428arch_initcall(sh7724_sleep_setup);
1429
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
new file mode 100644
index 000000000000..9c1de2633ac3
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -0,0 +1,623 @@
1/*
2 * SH7757 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/platform_device.h>
13#include <linux/init.h>
14#include <linux/serial.h>
15#include <linux/serial_sci.h>
16#include <linux/io.h>
17#include <linux/mm.h>
18#include <linux/sh_timer.h>
19
20static struct plat_sci_port scif2_platform_data = {
21 .mapbase = 0xfe4b0000, /* SCIF2 */
22 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
24 .scbrr_algo_id = SCBRR_ALGO_2,
25 .type = PORT_SCIF,
26 .irqs = { 40, 40, 40, 40 },
27};
28
29static struct platform_device scif2_device = {
30 .name = "sh-sci",
31 .id = 0,
32 .dev = {
33 .platform_data = &scif2_platform_data,
34 },
35};
36
37static struct plat_sci_port scif3_platform_data = {
38 .mapbase = 0xfe4c0000, /* SCIF3 */
39 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
41 .scbrr_algo_id = SCBRR_ALGO_2,
42 .type = PORT_SCIF,
43 .irqs = { 76, 76, 76, 76 },
44};
45
46static struct platform_device scif3_device = {
47 .name = "sh-sci",
48 .id = 1,
49 .dev = {
50 .platform_data = &scif3_platform_data,
51 },
52};
53
54static struct plat_sci_port scif4_platform_data = {
55 .mapbase = 0xfe4d0000, /* SCIF4 */
56 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
58 .scbrr_algo_id = SCBRR_ALGO_2,
59 .type = PORT_SCIF,
60 .irqs = { 104, 104, 104, 104 },
61};
62
63static struct platform_device scif4_device = {
64 .name = "sh-sci",
65 .id = 2,
66 .dev = {
67 .platform_data = &scif4_platform_data,
68 },
69};
70
71static struct sh_timer_config tmu0_platform_data = {
72 .channel_offset = 0x04,
73 .timer_bit = 0,
74 .clockevent_rating = 200,
75};
76
77static struct resource tmu0_resources[] = {
78 [0] = {
79 .start = 0xfe430008,
80 .end = 0xfe430013,
81 .flags = IORESOURCE_MEM,
82 },
83 [1] = {
84 .start = 28,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89static struct platform_device tmu0_device = {
90 .name = "sh_tmu",
91 .id = 0,
92 .dev = {
93 .platform_data = &tmu0_platform_data,
94 },
95 .resource = tmu0_resources,
96 .num_resources = ARRAY_SIZE(tmu0_resources),
97};
98
99static struct sh_timer_config tmu1_platform_data = {
100 .channel_offset = 0x10,
101 .timer_bit = 1,
102 .clocksource_rating = 200,
103};
104
105static struct resource tmu1_resources[] = {
106 [0] = {
107 .start = 0xfe430014,
108 .end = 0xfe43001f,
109 .flags = IORESOURCE_MEM,
110 },
111 [1] = {
112 .start = 29,
113 .flags = IORESOURCE_IRQ,
114 },
115};
116
117static struct platform_device tmu1_device = {
118 .name = "sh_tmu",
119 .id = 1,
120 .dev = {
121 .platform_data = &tmu1_platform_data,
122 },
123 .resource = tmu1_resources,
124 .num_resources = ARRAY_SIZE(tmu1_resources),
125};
126
127static struct platform_device *sh7757_devices[] __initdata = {
128 &scif2_device,
129 &scif3_device,
130 &scif4_device,
131 &tmu0_device,
132 &tmu1_device,
133};
134
135static int __init sh7757_devices_setup(void)
136{
137 return platform_add_devices(sh7757_devices,
138 ARRAY_SIZE(sh7757_devices));
139}
140arch_initcall(sh7757_devices_setup);
141
142static struct platform_device *sh7757_early_devices[] __initdata = {
143 &scif2_device,
144 &scif3_device,
145 &scif4_device,
146 &tmu0_device,
147 &tmu1_device,
148};
149
150void __init plat_early_device_setup(void)
151{
152 early_platform_add_devices(sh7757_early_devices,
153 ARRAY_SIZE(sh7757_early_devices));
154}
155
156enum {
157 UNUSED = 0,
158
159 /* interrupt sources */
160
161 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
162 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
163 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
164 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
165
166 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
167 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
168 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
169 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
170 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
171
172 SDHI, DVC,
173 IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
174 TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
175 HUDI,
176 ARC4,
177 DMAC0_5, DMAC6_7, DMAC8_11,
178 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
179 USB0, USB1,
180 JMC,
181 SPI0, SPI1,
182 TMR01, TMR23, TMR45,
183 FRT,
184 LPC, LPC5, LPC6, LPC7, LPC8,
185 PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
186 ETHERC,
187 ADC0, ADC1,
188 SIM,
189 IIC0_0, IIC0_1, IIC0_2, IIC0_3,
190 IIC1_0, IIC1_1, IIC1_2, IIC1_3,
191 IIC2_0, IIC2_1, IIC2_2, IIC2_3,
192 IIC3_0, IIC3_1, IIC3_2, IIC3_3,
193 IIC4_0, IIC4_1, IIC4_2, IIC4_3,
194 IIC5_0, IIC5_1, IIC5_2, IIC5_3,
195 IIC6_0, IIC6_1, IIC6_2, IIC6_3,
196 IIC7_0, IIC7_1, IIC7_2, IIC7_3,
197 IIC8_0, IIC8_1, IIC8_2, IIC8_3,
198 IIC9_0, IIC9_1, IIC9_2, IIC9_3,
199 ONFICTL,
200 MMC1, MMC2,
201 ECCU,
202 PCIC,
203 G200,
204 RSPI,
205 SGPIO,
206 DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
207 DMINT20, DMINT21, DMINT22, DMINT23,
208 DDRECC,
209 TSIP,
210 PCIE_BRIDGE,
211 WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
212 GETHER0, GETHER1, GETHER2,
213 PBIA, PBIB, PBIC,
214 DMAE2, DMAE3,
215 SERMUX2, SERMUX3,
216
217 /* interrupt groups */
218
219 TMU012, TMU345,
220};
221
222static struct intc_vect vectors[] __initdata = {
223 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
224 INTC_VECT(SDHI, 0x4c0),
225 INTC_VECT(DVC, 0x4e0),
226 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
227 INTC_VECT(IRQ10, 0x540),
228 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
229 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
230 INTC_VECT(HUDI, 0x600),
231 INTC_VECT(ARC4, 0x620),
232 INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
233 INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
234 INTC_VECT(DMAC0_5, 0x6c0),
235 INTC_VECT(IRQ11, 0x6e0),
236 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
237 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
238 INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
239 INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
240 INTC_VECT(USB0, 0x840),
241 INTC_VECT(IRQ12, 0x880),
242 INTC_VECT(JMC, 0x8a0),
243 INTC_VECT(SPI1, 0x8c0),
244 INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
245 INTC_VECT(USB1, 0x920),
246 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
247 INTC_VECT(TMR45, 0xa40),
248 INTC_VECT(FRT, 0xa80),
249 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
250 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
251 INTC_VECT(LPC, 0xb20),
252 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
253 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
254 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
255 INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
256 INTC_VECT(PECI2, 0xc40),
257 INTC_VECT(IRQ15, 0xc60),
258 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
259 INTC_VECT(SPI0, 0xcc0),
260 INTC_VECT(ADC1, 0xce0),
261 INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
262 INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
263 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
264 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
265 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
266 INTC_VECT(TMU5, 0xe40),
267 INTC_VECT(ADC0, 0xe60),
268 INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
269 INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
270 INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
271 INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
272 INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
273 INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
274 INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
275 INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
276 INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
277 INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
278 INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
279 INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
280 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
281 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
282 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
283 INTC_VECT(IIC6_2, 0x1920),
284 INTC_VECT(ONFICTL, 0x1960),
285 INTC_VECT(IIC6_3, 0x1980),
286 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
287 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
288 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
289 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
290 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
291 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
292 INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
293 INTC_VECT(ECCU, 0x1cc0),
294 INTC_VECT(PCIC, 0x1ce0),
295 INTC_VECT(G200, 0x1d00),
296 INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
297 INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
298 INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
299 INTC_VECT(PECI5, 0x1f00),
300 INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
301 INTC_VECT(SGPIO, 0x1fc0),
302 INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
303 INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
304 INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
305 INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
306 INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
307 INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
308 INTC_VECT(DDRECC, 0x2620),
309 INTC_VECT(TSIP, 0x2640),
310 INTC_VECT(PCIE_BRIDGE, 0x27c0),
311 INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
312 INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
313 INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
314 INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
315 INTC_VECT(WDT8B, 0x2900),
316 INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
317 INTC_VECT(GETHER2, 0x29a0),
318 INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
319 INTC_VECT(PBIC, 0x2a40),
320 INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
321 INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
322 INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
323 INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
324};
325
326static struct intc_group groups[] __initdata = {
327 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
328 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
329};
330
331static struct intc_mask_reg mask_registers[] __initdata = {
332 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
333 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
334
335 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
336 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
337 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
338 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
339 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
340 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
341 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
342 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
343 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
344
345 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
346 { 0, 0, 0, 0, 0, 0, 0, 0,
347 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
348 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
349 HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
350 } },
351
352 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
353 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
354 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
355 ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
356 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
357 } },
358
359 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
360 { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
361 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
362 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
363 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
364 } },
365
366 { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
367 { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
368 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
369 PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
370 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
371 } },
372
373 { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
374 { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
375 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
376 PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
377 DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
378 } },
379
380 { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
381 { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
382 DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
383 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
384 DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
385 } },
386};
387
388#define INTPRI 0xffd00010
389#define INT2PRI0 0xffd40000
390#define INT2PRI1 0xffd40004
391#define INT2PRI2 0xffd40008
392#define INT2PRI3 0xffd4000c
393#define INT2PRI4 0xffd40010
394#define INT2PRI5 0xffd40014
395#define INT2PRI6 0xffd40018
396#define INT2PRI7 0xffd4001c
397#define INT2PRI8 0xffd400a0
398#define INT2PRI9 0xffd400a4
399#define INT2PRI10 0xffd400a8
400#define INT2PRI11 0xffd400ac
401#define INT2PRI12 0xffd400b0
402#define INT2PRI13 0xffd400b4
403#define INT2PRI14 0xffd400b8
404#define INT2PRI15 0xffd400bc
405#define INT2PRI16 0xffd10000
406#define INT2PRI17 0xffd10004
407#define INT2PRI18 0xffd10008
408#define INT2PRI19 0xffd1000c
409#define INT2PRI20 0xffd10010
410#define INT2PRI21 0xffd10014
411#define INT2PRI22 0xffd10018
412#define INT2PRI23 0xffd1001c
413#define INT2PRI24 0xffd100a0
414#define INT2PRI25 0xffd100a4
415#define INT2PRI26 0xffd100a8
416#define INT2PRI27 0xffd100ac
417#define INT2PRI28 0xffd100b0
418#define INT2PRI29 0xffd100b4
419#define INT2PRI30 0xffd100b8
420#define INT2PRI31 0xffd100bc
421#define INT2PRI32 0xffd20000
422#define INT2PRI33 0xffd20004
423#define INT2PRI34 0xffd20008
424#define INT2PRI35 0xffd2000c
425#define INT2PRI36 0xffd20010
426#define INT2PRI37 0xffd20014
427#define INT2PRI38 0xffd20018
428#define INT2PRI39 0xffd2001c
429#define INT2PRI40 0xffd200a0
430#define INT2PRI41 0xffd200a4
431#define INT2PRI42 0xffd200a8
432#define INT2PRI43 0xffd200ac
433#define INT2PRI44 0xffd200b0
434#define INT2PRI45 0xffd200b4
435#define INT2PRI46 0xffd200b8
436#define INT2PRI47 0xffd200bc
437
438static struct intc_prio_reg prio_registers[] __initdata = {
439 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
440 IRQ4, IRQ5, IRQ6, IRQ7 } },
441
442 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
443 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
444 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
445 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
446 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
447 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
448 { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
449 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
450 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
451 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
452 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
453 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
454 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
455 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
456
457 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
458 { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
459 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
460 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
461 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
462 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
463 { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
464 { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
465 { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
466 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
467 { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
468 { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
469 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
470 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
471 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
472 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
473 { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
474 { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
475 { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
476 { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
477 { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
478 { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
479 { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
480 { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
481 { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
482 { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
483 { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
484 { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
485 { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
486 { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
487 { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
488 { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
489};
490
491static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
492 { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12,
493 IRQ11, IRQ10, IRQ9, IRQ8 } },
494};
495
496static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
497 mask_registers, prio_registers,
498 sense_registers_irq8to15);
499
500/* Support for external interrupt pins in IRQ mode */
501static struct intc_vect vectors_irq0123[] __initdata = {
502 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
503 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
504};
505
506static struct intc_vect vectors_irq4567[] __initdata = {
507 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
508 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
509};
510
511static struct intc_sense_reg sense_registers[] __initdata = {
512 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
513 IRQ4, IRQ5, IRQ6, IRQ7 } },
514};
515
516static struct intc_mask_reg ack_registers[] __initdata = {
517 { 0xffd00024, 0, 32, /* INTREQ */
518 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
519};
520
521static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
522 vectors_irq0123, NULL, mask_registers,
523 prio_registers, sense_registers, ack_registers);
524
525static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
526 vectors_irq4567, NULL, mask_registers,
527 prio_registers, sense_registers, ack_registers);
528
529/* External interrupt pins in IRL mode */
530static struct intc_vect vectors_irl0123[] __initdata = {
531 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
532 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
533 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
534 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
535 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
536 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
537 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
538 INTC_VECT(IRL0_HHHL, 0x3c0),
539};
540
541static struct intc_vect vectors_irl4567[] __initdata = {
542 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
543 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
544 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
545 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
546 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
547 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
548 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
549 INTC_VECT(IRL4_HHHL, 0xcc0),
550};
551
552static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
553 NULL, mask_registers, NULL, NULL);
554
555static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
556 NULL, mask_registers, NULL, NULL);
557
558#define INTC_ICR0 0xffd00000
559#define INTC_INTMSK0 0xffd00044
560#define INTC_INTMSK1 0xffd00048
561#define INTC_INTMSK2 0xffd40080
562#define INTC_INTMSKCLR1 0xffd00068
563#define INTC_INTMSKCLR2 0xffd40084
564
565void __init plat_irq_setup(void)
566{
567 /* disable IRQ3-0 + IRQ7-4 */
568 __raw_writel(0xff000000, INTC_INTMSK0);
569
570 /* disable IRL3-0 + IRL7-4 */
571 __raw_writel(0xc0000000, INTC_INTMSK1);
572 __raw_writel(0xfffefffe, INTC_INTMSK2);
573
574 /* select IRL mode for IRL3-0 + IRL7-4 */
575 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
576
577 /* disable holding function, ie enable "SH-4 Mode" */
578 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
579
580 register_intc_controller(&intc_desc);
581}
582
583void __init plat_irq_setup_pins(int mode)
584{
585 switch (mode) {
586 case IRQ_MODE_IRQ7654:
587 /* select IRQ mode for IRL7-4 */
588 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
589 register_intc_controller(&intc_desc_irq4567);
590 break;
591 case IRQ_MODE_IRQ3210:
592 /* select IRQ mode for IRL3-0 */
593 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
594 register_intc_controller(&intc_desc_irq0123);
595 break;
596 case IRQ_MODE_IRL7654:
597 /* enable IRL7-4 but don't provide any masking */
598 __raw_writel(0x40000000, INTC_INTMSKCLR1);
599 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
600 break;
601 case IRQ_MODE_IRL3210:
602 /* enable IRL0-3 but don't provide any masking */
603 __raw_writel(0x80000000, INTC_INTMSKCLR1);
604 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
605 break;
606 case IRQ_MODE_IRL7654_MASK:
607 /* enable IRL7-4 and mask using cpu intc controller */
608 __raw_writel(0x40000000, INTC_INTMSKCLR1);
609 register_intc_controller(&intc_desc_irl4567);
610 break;
611 case IRQ_MODE_IRL3210_MASK:
612 /* enable IRL0-3 and mask using cpu intc controller */
613 __raw_writel(0x80000000, INTC_INTMSKCLR1);
614 register_intc_controller(&intc_desc_irl0123);
615 break;
616 default:
617 BUG();
618 }
619}
620
621void __init plat_mem_setup(void)
622{
623}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index ab02771ee888..593eca6509b5 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -16,6 +16,57 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/serial_sci.h> 17#include <linux/serial_sci.h>
18 18
19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = 0xffe00000,
21 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF,
25 .irqs = { 40, 40, 40, 40 },
26};
27
28static struct platform_device scif0_device = {
29 .name = "sh-sci",
30 .id = 0,
31 .dev = {
32 .platform_data = &scif0_platform_data,
33 },
34};
35
36static struct plat_sci_port scif1_platform_data = {
37 .mapbase = 0xffe08000,
38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
40 .scbrr_algo_id = SCBRR_ALGO_2,
41 .type = PORT_SCIF,
42 .irqs = { 76, 76, 76, 76 },
43};
44
45static struct platform_device scif1_device = {
46 .name = "sh-sci",
47 .id = 1,
48 .dev = {
49 .platform_data = &scif1_platform_data,
50 },
51};
52
53static struct plat_sci_port scif2_platform_data = {
54 .mapbase = 0xffe10000,
55 .flags = UPF_BOOT_AUTOCONF,
56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
57 .scbrr_algo_id = SCBRR_ALGO_2,
58 .type = PORT_SCIF,
59 .irqs = { 104, 104, 104, 104 },
60};
61
62static struct platform_device scif2_device = {
63 .name = "sh-sci",
64 .id = 2,
65 .dev = {
66 .platform_data = &scif2_platform_data,
67 },
68};
69
19static struct resource rtc_resources[] = { 70static struct resource rtc_resources[] = {
20 [0] = { 71 [0] = {
21 .start = 0xffe80000, 72 .start = 0xffe80000,
@@ -36,41 +87,6 @@ static struct platform_device rtc_device = {
36 .resource = rtc_resources, 87 .resource = rtc_resources,
37}; 88};
38 89
39static struct plat_sci_port sci_platform_data[] = {
40 {
41 .mapbase = 0xffe00000,
42 .flags = UPF_BOOT_AUTOCONF,
43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
44 .scbrr_algo_id = SCBRR_ALGO_2,
45 .type = PORT_SCIF,
46 .irqs = { 40, 40, 40, 40 },
47 }, {
48 .mapbase = 0xffe08000,
49 .flags = UPF_BOOT_AUTOCONF,
50 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
51 .scbrr_algo_id = SCBRR_ALGO_2,
52 .type = PORT_SCIF,
53 .irqs = { 76, 76, 76, 76 },
54 }, {
55 .mapbase = 0xffe10000,
56 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
58 .scbrr_algo_id = SCBRR_ALGO_2,
59 .type = PORT_SCIF,
60 .irqs = { 104, 104, 104, 104 },
61 }, {
62 .flags = 0,
63 }
64};
65
66static struct platform_device sci_device = {
67 .name = "sh-sci",
68 .id = -1,
69 .dev = {
70 .platform_data = sci_platform_data,
71 },
72};
73
74static struct resource usb_ohci_resources[] = { 90static struct resource usb_ohci_resources[] = {
75 [0] = { 91 [0] = {
76 .start = 0xffec8000, 92 .start = 0xffec8000,
@@ -121,16 +137,13 @@ static struct platform_device usbf_device = {
121}; 137};
122 138
123static struct sh_timer_config tmu0_platform_data = { 139static struct sh_timer_config tmu0_platform_data = {
124 .name = "TMU0",
125 .channel_offset = 0x04, 140 .channel_offset = 0x04,
126 .timer_bit = 0, 141 .timer_bit = 0,
127 .clk = "peripheral_clk",
128 .clockevent_rating = 200, 142 .clockevent_rating = 200,
129}; 143};
130 144
131static struct resource tmu0_resources[] = { 145static struct resource tmu0_resources[] = {
132 [0] = { 146 [0] = {
133 .name = "TMU0",
134 .start = 0xffd80008, 147 .start = 0xffd80008,
135 .end = 0xffd80013, 148 .end = 0xffd80013,
136 .flags = IORESOURCE_MEM, 149 .flags = IORESOURCE_MEM,
@@ -152,16 +165,13 @@ static struct platform_device tmu0_device = {
152}; 165};
153 166
154static struct sh_timer_config tmu1_platform_data = { 167static struct sh_timer_config tmu1_platform_data = {
155 .name = "TMU1",
156 .channel_offset = 0x10, 168 .channel_offset = 0x10,
157 .timer_bit = 1, 169 .timer_bit = 1,
158 .clk = "peripheral_clk",
159 .clocksource_rating = 200, 170 .clocksource_rating = 200,
160}; 171};
161 172
162static struct resource tmu1_resources[] = { 173static struct resource tmu1_resources[] = {
163 [0] = { 174 [0] = {
164 .name = "TMU1",
165 .start = 0xffd80014, 175 .start = 0xffd80014,
166 .end = 0xffd8001f, 176 .end = 0xffd8001f,
167 .flags = IORESOURCE_MEM, 177 .flags = IORESOURCE_MEM,
@@ -183,15 +193,12 @@ static struct platform_device tmu1_device = {
183}; 193};
184 194
185static struct sh_timer_config tmu2_platform_data = { 195static struct sh_timer_config tmu2_platform_data = {
186 .name = "TMU2",
187 .channel_offset = 0x1c, 196 .channel_offset = 0x1c,
188 .timer_bit = 2, 197 .timer_bit = 2,
189 .clk = "peripheral_clk",
190}; 198};
191 199
192static struct resource tmu2_resources[] = { 200static struct resource tmu2_resources[] = {
193 [0] = { 201 [0] = {
194 .name = "TMU2",
195 .start = 0xffd80020, 202 .start = 0xffd80020,
196 .end = 0xffd8002f, 203 .end = 0xffd8002f,
197 .flags = IORESOURCE_MEM, 204 .flags = IORESOURCE_MEM,
@@ -213,15 +220,12 @@ static struct platform_device tmu2_device = {
213}; 220};
214 221
215static struct sh_timer_config tmu3_platform_data = { 222static struct sh_timer_config tmu3_platform_data = {
216 .name = "TMU3",
217 .channel_offset = 0x04, 223 .channel_offset = 0x04,
218 .timer_bit = 0, 224 .timer_bit = 0,
219 .clk = "peripheral_clk",
220}; 225};
221 226
222static struct resource tmu3_resources[] = { 227static struct resource tmu3_resources[] = {
223 [0] = { 228 [0] = {
224 .name = "TMU3",
225 .start = 0xffd88008, 229 .start = 0xffd88008,
226 .end = 0xffd88013, 230 .end = 0xffd88013,
227 .flags = IORESOURCE_MEM, 231 .flags = IORESOURCE_MEM,
@@ -243,15 +247,12 @@ static struct platform_device tmu3_device = {
243}; 247};
244 248
245static struct sh_timer_config tmu4_platform_data = { 249static struct sh_timer_config tmu4_platform_data = {
246 .name = "TMU4",
247 .channel_offset = 0x10, 250 .channel_offset = 0x10,
248 .timer_bit = 1, 251 .timer_bit = 1,
249 .clk = "peripheral_clk",
250}; 252};
251 253
252static struct resource tmu4_resources[] = { 254static struct resource tmu4_resources[] = {
253 [0] = { 255 [0] = {
254 .name = "TMU4",
255 .start = 0xffd88014, 256 .start = 0xffd88014,
256 .end = 0xffd8801f, 257 .end = 0xffd8801f,
257 .flags = IORESOURCE_MEM, 258 .flags = IORESOURCE_MEM,
@@ -273,15 +274,12 @@ static struct platform_device tmu4_device = {
273}; 274};
274 275
275static struct sh_timer_config tmu5_platform_data = { 276static struct sh_timer_config tmu5_platform_data = {
276 .name = "TMU5",
277 .channel_offset = 0x1c, 277 .channel_offset = 0x1c,
278 .timer_bit = 2, 278 .timer_bit = 2,
279 .clk = "peripheral_clk",
280}; 279};
281 280
282static struct resource tmu5_resources[] = { 281static struct resource tmu5_resources[] = {
283 [0] = { 282 [0] = {
284 .name = "TMU5",
285 .start = 0xffd88020, 283 .start = 0xffd88020,
286 .end = 0xffd8802b, 284 .end = 0xffd8802b,
287 .flags = IORESOURCE_MEM, 285 .flags = IORESOURCE_MEM,
@@ -303,6 +301,9 @@ static struct platform_device tmu5_device = {
303}; 301};
304 302
305static struct platform_device *sh7763_devices[] __initdata = { 303static struct platform_device *sh7763_devices[] __initdata = {
304 &scif0_device,
305 &scif1_device,
306 &scif2_device,
306 &tmu0_device, 307 &tmu0_device,
307 &tmu1_device, 308 &tmu1_device,
308 &tmu2_device, 309 &tmu2_device,
@@ -310,7 +311,6 @@ static struct platform_device *sh7763_devices[] __initdata = {
310 &tmu4_device, 311 &tmu4_device,
311 &tmu5_device, 312 &tmu5_device,
312 &rtc_device, 313 &rtc_device,
313 &sci_device,
314 &usb_ohci_device, 314 &usb_ohci_device,
315 &usbf_device, 315 &usbf_device,
316}; 316};
@@ -320,9 +320,12 @@ static int __init sh7763_devices_setup(void)
320 return platform_add_devices(sh7763_devices, 320 return platform_add_devices(sh7763_devices,
321 ARRAY_SIZE(sh7763_devices)); 321 ARRAY_SIZE(sh7763_devices));
322} 322}
323__initcall(sh7763_devices_setup); 323arch_initcall(sh7763_devices_setup);
324 324
325static struct platform_device *sh7763_early_devices[] __initdata = { 325static struct platform_device *sh7763_early_devices[] __initdata = {
326 &scif0_device,
327 &scif1_device,
328 &scif2_device,
326 &tmu0_device, 329 &tmu0_device,
327 &tmu1_device, 330 &tmu1_device,
328 &tmu2_device, 331 &tmu2_device,
@@ -523,11 +526,11 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
523void __init plat_irq_setup(void) 526void __init plat_irq_setup(void)
524{ 527{
525 /* disable IRQ7-0 */ 528 /* disable IRQ7-0 */
526 ctrl_outl(0xff000000, INTC_INTMSK0); 529 __raw_writel(0xff000000, INTC_INTMSK0);
527 530
528 /* disable IRL3-0 + IRL7-4 */ 531 /* disable IRL3-0 + IRL7-4 */
529 ctrl_outl(0xc0000000, INTC_INTMSK1); 532 __raw_writel(0xc0000000, INTC_INTMSK1);
530 ctrl_outl(0xfffefffe, INTC_INTMSK2); 533 __raw_writel(0xfffefffe, INTC_INTMSK2);
531 534
532 register_intc_controller(&intc_desc); 535 register_intc_controller(&intc_desc);
533} 536}
@@ -537,27 +540,27 @@ void __init plat_irq_setup_pins(int mode)
537 switch (mode) { 540 switch (mode) {
538 case IRQ_MODE_IRQ: 541 case IRQ_MODE_IRQ:
539 /* select IRQ mode for IRL3-0 + IRL7-4 */ 542 /* select IRQ mode for IRL3-0 + IRL7-4 */
540 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 543 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
541 register_intc_controller(&intc_irq_desc); 544 register_intc_controller(&intc_irq_desc);
542 break; 545 break;
543 case IRQ_MODE_IRL7654: 546 case IRQ_MODE_IRL7654:
544 /* enable IRL7-4 but don't provide any masking */ 547 /* enable IRL7-4 but don't provide any masking */
545 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 548 __raw_writel(0x40000000, INTC_INTMSKCLR1);
546 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 549 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
547 break; 550 break;
548 case IRQ_MODE_IRL3210: 551 case IRQ_MODE_IRL3210:
549 /* enable IRL0-3 but don't provide any masking */ 552 /* enable IRL0-3 but don't provide any masking */
550 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 553 __raw_writel(0x80000000, INTC_INTMSKCLR1);
551 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 554 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
552 break; 555 break;
553 case IRQ_MODE_IRL7654_MASK: 556 case IRQ_MODE_IRL7654_MASK:
554 /* enable IRL7-4 and mask using cpu intc controller */ 557 /* enable IRL7-4 and mask using cpu intc controller */
555 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 558 __raw_writel(0x40000000, INTC_INTMSKCLR1);
556 register_intc_controller(&intc_irl7654_desc); 559 register_intc_controller(&intc_irl7654_desc);
557 break; 560 break;
558 case IRQ_MODE_IRL3210_MASK: 561 case IRQ_MODE_IRL3210_MASK:
559 /* enable IRL0-3 and mask using cpu intc controller */ 562 /* enable IRL0-3 and mask using cpu intc controller */
560 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 563 __raw_writel(0x80000000, INTC_INTMSKCLR1);
561 register_intc_controller(&intc_irl3210_desc); 564 register_intc_controller(&intc_irl3210_desc);
562 break; 565 break;
563 default: 566 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 746f4fb9ccf0..2c6aa22cf5f6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -14,101 +14,184 @@
14#include <linux/sh_timer.h> 14#include <linux/sh_timer.h>
15#include <linux/io.h> 15#include <linux/io.h>
16 16
17static struct plat_sci_port sci_platform_data[] = { 17static struct plat_sci_port scif0_platform_data = {
18 { 18 .mapbase = 0xff923000,
19 .mapbase = 0xff923000, 19 .flags = UPF_BOOT_AUTOCONF,
20 .flags = UPF_BOOT_AUTOCONF, 20 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 21 .scbrr_algo_id = SCBRR_ALGO_2,
22 .scbrr_algo_id = SCBRR_ALGO_2, 22 .type = PORT_SCIF,
23 .type = PORT_SCIF, 23 .irqs = { 61, 61, 61, 61 },
24 .irqs = { 61, 61, 61, 61 }, 24};
25 }, { 25
26 .mapbase = 0xff924000, 26static struct platform_device scif0_device = {
27 .flags = UPF_BOOT_AUTOCONF, 27 .name = "sh-sci",
28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 28 .id = 0,
29 .scbrr_algo_id = SCBRR_ALGO_2, 29 .dev = {
30 .type = PORT_SCIF, 30 .platform_data = &scif0_platform_data,
31 .irqs = { 62, 62, 62, 62 }, 31 },
32 }, { 32};
33 .mapbase = 0xff925000, 33
34 .flags = UPF_BOOT_AUTOCONF, 34static struct plat_sci_port scif1_platform_data = {
35 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 35 .mapbase = 0xff924000,
36 .scbrr_algo_id = SCBRR_ALGO_2, 36 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF, 37 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
38 .irqs = { 63, 63, 63, 63 }, 38 .scbrr_algo_id = SCBRR_ALGO_2,
39 }, { 39 .type = PORT_SCIF,
40 .mapbase = 0xff926000, 40 .irqs = { 62, 62, 62, 62 },
41 .flags = UPF_BOOT_AUTOCONF, 41};
42 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 42
43 .scbrr_algo_id = SCBRR_ALGO_2, 43static struct platform_device scif1_device = {
44 .type = PORT_SCIF, 44 .name = "sh-sci",
45 .irqs = { 64, 64, 64, 64 }, 45 .id = 1,
46 }, { 46 .dev = {
47 .mapbase = 0xff927000, 47 .platform_data = &scif1_platform_data,
48 .flags = UPF_BOOT_AUTOCONF, 48 },
49 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 49};
50 .scbrr_algo_id = SCBRR_ALGO_2, 50
51 .type = PORT_SCIF, 51static struct plat_sci_port scif2_platform_data = {
52 .irqs = { 65, 65, 65, 65 }, 52 .mapbase = 0xff925000,
53 }, { 53 .flags = UPF_BOOT_AUTOCONF,
54 .mapbase = 0xff928000, 54 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
55 .flags = UPF_BOOT_AUTOCONF, 55 .scbrr_algo_id = SCBRR_ALGO_2,
56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 56 .type = PORT_SCIF,
57 .scbrr_algo_id = SCBRR_ALGO_2, 57 .irqs = { 63, 63, 63, 63 },
58 .type = PORT_SCIF, 58};
59 .irqs = { 66, 66, 66, 66 }, 59
60 }, { 60static struct platform_device scif2_device = {
61 .mapbase = 0xff929000, 61 .name = "sh-sci",
62 .flags = UPF_BOOT_AUTOCONF, 62 .id = 2,
63 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 63 .dev = {
64 .scbrr_algo_id = SCBRR_ALGO_2, 64 .platform_data = &scif2_platform_data,
65 .type = PORT_SCIF, 65 },
66 .irqs = { 67, 67, 67, 67 }, 66};
67 }, { 67
68 .mapbase = 0xff92a000, 68static struct plat_sci_port scif3_platform_data = {
69 .flags = UPF_BOOT_AUTOCONF, 69 .mapbase = 0xff926000,
70 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 70 .flags = UPF_BOOT_AUTOCONF,
71 .scbrr_algo_id = SCBRR_ALGO_2, 71 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
72 .type = PORT_SCIF, 72 .scbrr_algo_id = SCBRR_ALGO_2,
73 .irqs = { 68, 68, 68, 68 }, 73 .type = PORT_SCIF,
74 }, { 74 .irqs = { 64, 64, 64, 64 },
75 .mapbase = 0xff92b000, 75};
76 .flags = UPF_BOOT_AUTOCONF, 76
77 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 77static struct platform_device scif3_device = {
78 .scbrr_algo_id = SCBRR_ALGO_2, 78 .name = "sh-sci",
79 .type = PORT_SCIF, 79 .id = 3,
80 .irqs = { 69, 69, 69, 69 }, 80 .dev = {
81 }, { 81 .platform_data = &scif3_platform_data,
82 .mapbase = 0xff92c000, 82 },
83 .flags = UPF_BOOT_AUTOCONF, 83};
84 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 84
85 .scbrr_algo_id = SCBRR_ALGO_2, 85static struct plat_sci_port scif4_platform_data = {
86 .type = PORT_SCIF, 86 .mapbase = 0xff927000,
87 .irqs = { 70, 70, 70, 70 }, 87 .flags = UPF_BOOT_AUTOCONF,
88 }, { 88 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
89 .flags = 0, 89 .scbrr_algo_id = SCBRR_ALGO_2,
90 } 90 .type = PORT_SCIF,
91 .irqs = { 65, 65, 65, 65 },
92};
93
94static struct platform_device scif4_device = {
95 .name = "sh-sci",
96 .id = 4,
97 .dev = {
98 .platform_data = &scif4_platform_data,
99 },
100};
101
102static struct plat_sci_port scif5_platform_data = {
103 .mapbase = 0xff928000,
104 .flags = UPF_BOOT_AUTOCONF,
105 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
106 .scbrr_algo_id = SCBRR_ALGO_2,
107 .type = PORT_SCIF,
108 .irqs = { 66, 66, 66, 66 },
109};
110
111static struct platform_device scif5_device = {
112 .name = "sh-sci",
113 .id = 5,
114 .dev = {
115 .platform_data = &scif5_platform_data,
116 },
117};
118
119static struct plat_sci_port scif6_platform_data = {
120 .mapbase = 0xff929000,
121 .flags = UPF_BOOT_AUTOCONF,
122 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
123 .scbrr_algo_id = SCBRR_ALGO_2,
124 .type = PORT_SCIF,
125 .irqs = { 67, 67, 67, 67 },
126};
127
128static struct platform_device scif6_device = {
129 .name = "sh-sci",
130 .id = 6,
131 .dev = {
132 .platform_data = &scif6_platform_data,
133 },
134};
135
136static struct plat_sci_port scif7_platform_data = {
137 .mapbase = 0xff92a000,
138 .flags = UPF_BOOT_AUTOCONF,
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
140 .scbrr_algo_id = SCBRR_ALGO_2,
141 .type = PORT_SCIF,
142 .irqs = { 68, 68, 68, 68 },
143};
144
145static struct platform_device scif7_device = {
146 .name = "sh-sci",
147 .id = 7,
148 .dev = {
149 .platform_data = &scif7_platform_data,
150 },
151};
152
153static struct plat_sci_port scif8_platform_data = {
154 .mapbase = 0xff92b000,
155 .flags = UPF_BOOT_AUTOCONF,
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
157 .scbrr_algo_id = SCBRR_ALGO_2,
158 .type = PORT_SCIF,
159 .irqs = { 69, 69, 69, 69 },
160};
161
162static struct platform_device scif8_device = {
163 .name = "sh-sci",
164 .id = 8,
165 .dev = {
166 .platform_data = &scif8_platform_data,
167 },
168};
169
170static struct plat_sci_port scif9_platform_data = {
171 .mapbase = 0xff92c000,
172 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
174 .scbrr_algo_id = SCBRR_ALGO_2,
175 .type = PORT_SCIF,
176 .irqs = { 70, 70, 70, 70 },
91}; 177};
92 178
93static struct platform_device sci_device = { 179static struct platform_device scif9_device = {
94 .name = "sh-sci", 180 .name = "sh-sci",
95 .id = -1, 181 .id = 9,
96 .dev = { 182 .dev = {
97 .platform_data = sci_platform_data, 183 .platform_data = &scif9_platform_data,
98 }, 184 },
99}; 185};
100 186
101static struct sh_timer_config tmu0_platform_data = { 187static struct sh_timer_config tmu0_platform_data = {
102 .name = "TMU0",
103 .channel_offset = 0x04, 188 .channel_offset = 0x04,
104 .timer_bit = 0, 189 .timer_bit = 0,
105 .clk = "peripheral_clk",
106 .clockevent_rating = 200, 190 .clockevent_rating = 200,
107}; 191};
108 192
109static struct resource tmu0_resources[] = { 193static struct resource tmu0_resources[] = {
110 [0] = { 194 [0] = {
111 .name = "TMU0",
112 .start = 0xffd80008, 195 .start = 0xffd80008,
113 .end = 0xffd80013, 196 .end = 0xffd80013,
114 .flags = IORESOURCE_MEM, 197 .flags = IORESOURCE_MEM,
@@ -130,16 +213,13 @@ static struct platform_device tmu0_device = {
130}; 213};
131 214
132static struct sh_timer_config tmu1_platform_data = { 215static struct sh_timer_config tmu1_platform_data = {
133 .name = "TMU1",
134 .channel_offset = 0x10, 216 .channel_offset = 0x10,
135 .timer_bit = 1, 217 .timer_bit = 1,
136 .clk = "peripheral_clk",
137 .clocksource_rating = 200, 218 .clocksource_rating = 200,
138}; 219};
139 220
140static struct resource tmu1_resources[] = { 221static struct resource tmu1_resources[] = {
141 [0] = { 222 [0] = {
142 .name = "TMU1",
143 .start = 0xffd80014, 223 .start = 0xffd80014,
144 .end = 0xffd8001f, 224 .end = 0xffd8001f,
145 .flags = IORESOURCE_MEM, 225 .flags = IORESOURCE_MEM,
@@ -161,15 +241,12 @@ static struct platform_device tmu1_device = {
161}; 241};
162 242
163static struct sh_timer_config tmu2_platform_data = { 243static struct sh_timer_config tmu2_platform_data = {
164 .name = "TMU2",
165 .channel_offset = 0x1c, 244 .channel_offset = 0x1c,
166 .timer_bit = 2, 245 .timer_bit = 2,
167 .clk = "peripheral_clk",
168}; 246};
169 247
170static struct resource tmu2_resources[] = { 248static struct resource tmu2_resources[] = {
171 [0] = { 249 [0] = {
172 .name = "TMU2",
173 .start = 0xffd80020, 250 .start = 0xffd80020,
174 .end = 0xffd8002f, 251 .end = 0xffd8002f,
175 .flags = IORESOURCE_MEM, 252 .flags = IORESOURCE_MEM,
@@ -191,15 +268,12 @@ static struct platform_device tmu2_device = {
191}; 268};
192 269
193static struct sh_timer_config tmu3_platform_data = { 270static struct sh_timer_config tmu3_platform_data = {
194 .name = "TMU3",
195 .channel_offset = 0x04, 271 .channel_offset = 0x04,
196 .timer_bit = 0, 272 .timer_bit = 0,
197 .clk = "peripheral_clk",
198}; 273};
199 274
200static struct resource tmu3_resources[] = { 275static struct resource tmu3_resources[] = {
201 [0] = { 276 [0] = {
202 .name = "TMU3",
203 .start = 0xffd81008, 277 .start = 0xffd81008,
204 .end = 0xffd81013, 278 .end = 0xffd81013,
205 .flags = IORESOURCE_MEM, 279 .flags = IORESOURCE_MEM,
@@ -221,15 +295,12 @@ static struct platform_device tmu3_device = {
221}; 295};
222 296
223static struct sh_timer_config tmu4_platform_data = { 297static struct sh_timer_config tmu4_platform_data = {
224 .name = "TMU4",
225 .channel_offset = 0x10, 298 .channel_offset = 0x10,
226 .timer_bit = 1, 299 .timer_bit = 1,
227 .clk = "peripheral_clk",
228}; 300};
229 301
230static struct resource tmu4_resources[] = { 302static struct resource tmu4_resources[] = {
231 [0] = { 303 [0] = {
232 .name = "TMU4",
233 .start = 0xffd81014, 304 .start = 0xffd81014,
234 .end = 0xffd8101f, 305 .end = 0xffd8101f,
235 .flags = IORESOURCE_MEM, 306 .flags = IORESOURCE_MEM,
@@ -251,15 +322,12 @@ static struct platform_device tmu4_device = {
251}; 322};
252 323
253static struct sh_timer_config tmu5_platform_data = { 324static struct sh_timer_config tmu5_platform_data = {
254 .name = "TMU5",
255 .channel_offset = 0x1c, 325 .channel_offset = 0x1c,
256 .timer_bit = 2, 326 .timer_bit = 2,
257 .clk = "peripheral_clk",
258}; 327};
259 328
260static struct resource tmu5_resources[] = { 329static struct resource tmu5_resources[] = {
261 [0] = { 330 [0] = {
262 .name = "TMU5",
263 .start = 0xffd81020, 331 .start = 0xffd81020,
264 .end = 0xffd8102f, 332 .end = 0xffd8102f,
265 .flags = IORESOURCE_MEM, 333 .flags = IORESOURCE_MEM,
@@ -281,15 +349,12 @@ static struct platform_device tmu5_device = {
281}; 349};
282 350
283static struct sh_timer_config tmu6_platform_data = { 351static struct sh_timer_config tmu6_platform_data = {
284 .name = "TMU6",
285 .channel_offset = 0x04, 352 .channel_offset = 0x04,
286 .timer_bit = 0, 353 .timer_bit = 0,
287 .clk = "peripheral_clk",
288}; 354};
289 355
290static struct resource tmu6_resources[] = { 356static struct resource tmu6_resources[] = {
291 [0] = { 357 [0] = {
292 .name = "TMU6",
293 .start = 0xffd82008, 358 .start = 0xffd82008,
294 .end = 0xffd82013, 359 .end = 0xffd82013,
295 .flags = IORESOURCE_MEM, 360 .flags = IORESOURCE_MEM,
@@ -311,15 +376,12 @@ static struct platform_device tmu6_device = {
311}; 376};
312 377
313static struct sh_timer_config tmu7_platform_data = { 378static struct sh_timer_config tmu7_platform_data = {
314 .name = "TMU7",
315 .channel_offset = 0x10, 379 .channel_offset = 0x10,
316 .timer_bit = 1, 380 .timer_bit = 1,
317 .clk = "peripheral_clk",
318}; 381};
319 382
320static struct resource tmu7_resources[] = { 383static struct resource tmu7_resources[] = {
321 [0] = { 384 [0] = {
322 .name = "TMU7",
323 .start = 0xffd82014, 385 .start = 0xffd82014,
324 .end = 0xffd8201f, 386 .end = 0xffd8201f,
325 .flags = IORESOURCE_MEM, 387 .flags = IORESOURCE_MEM,
@@ -341,15 +403,12 @@ static struct platform_device tmu7_device = {
341}; 403};
342 404
343static struct sh_timer_config tmu8_platform_data = { 405static struct sh_timer_config tmu8_platform_data = {
344 .name = "TMU8",
345 .channel_offset = 0x1c, 406 .channel_offset = 0x1c,
346 .timer_bit = 2, 407 .timer_bit = 2,
347 .clk = "peripheral_clk",
348}; 408};
349 409
350static struct resource tmu8_resources[] = { 410static struct resource tmu8_resources[] = {
351 [0] = { 411 [0] = {
352 .name = "TMU8",
353 .start = 0xffd82020, 412 .start = 0xffd82020,
354 .end = 0xffd8202b, 413 .end = 0xffd8202b,
355 .flags = IORESOURCE_MEM, 414 .flags = IORESOURCE_MEM,
@@ -371,6 +430,16 @@ static struct platform_device tmu8_device = {
371}; 430};
372 431
373static struct platform_device *sh7770_devices[] __initdata = { 432static struct platform_device *sh7770_devices[] __initdata = {
433 &scif0_device,
434 &scif1_device,
435 &scif2_device,
436 &scif3_device,
437 &scif4_device,
438 &scif5_device,
439 &scif6_device,
440 &scif7_device,
441 &scif8_device,
442 &scif9_device,
374 &tmu0_device, 443 &tmu0_device,
375 &tmu1_device, 444 &tmu1_device,
376 &tmu2_device, 445 &tmu2_device,
@@ -380,7 +449,6 @@ static struct platform_device *sh7770_devices[] __initdata = {
380 &tmu6_device, 449 &tmu6_device,
381 &tmu7_device, 450 &tmu7_device,
382 &tmu8_device, 451 &tmu8_device,
383 &sci_device,
384}; 452};
385 453
386static int __init sh7770_devices_setup(void) 454static int __init sh7770_devices_setup(void)
@@ -388,9 +456,19 @@ static int __init sh7770_devices_setup(void)
388 return platform_add_devices(sh7770_devices, 456 return platform_add_devices(sh7770_devices,
389 ARRAY_SIZE(sh7770_devices)); 457 ARRAY_SIZE(sh7770_devices));
390} 458}
391__initcall(sh7770_devices_setup); 459arch_initcall(sh7770_devices_setup);
392 460
393static struct platform_device *sh7770_early_devices[] __initdata = { 461static struct platform_device *sh7770_early_devices[] __initdata = {
462 &scif0_device,
463 &scif1_device,
464 &scif2_device,
465 &scif3_device,
466 &scif4_device,
467 &scif5_device,
468 &scif6_device,
469 &scif7_device,
470 &scif8_device,
471 &scif9_device,
394 &tmu0_device, 472 &tmu0_device,
395 &tmu1_device, 473 &tmu1_device,
396 &tmu2_device, 474 &tmu2_device,
@@ -609,17 +687,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
609void __init plat_irq_setup(void) 687void __init plat_irq_setup(void)
610{ 688{
611 /* disable IRQ7-0 */ 689 /* disable IRQ7-0 */
612 ctrl_outl(0xff000000, INTC_INTMSK0); 690 __raw_writel(0xff000000, INTC_INTMSK0);
613 691
614 /* disable IRL3-0 + IRL7-4 */ 692 /* disable IRL3-0 + IRL7-4 */
615 ctrl_outl(0xc0000000, INTC_INTMSK1); 693 __raw_writel(0xc0000000, INTC_INTMSK1);
616 ctrl_outl(0xfffefffe, INTC_INTMSK2); 694 __raw_writel(0xfffefffe, INTC_INTMSK2);
617 695
618 /* select IRL mode for IRL3-0 + IRL7-4 */ 696 /* select IRL mode for IRL3-0 + IRL7-4 */
619 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 697 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
620 698
621 /* disable holding function, ie enable "SH-4 Mode" */ 699 /* disable holding function, ie enable "SH-4 Mode" */
622 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 700 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
623 701
624 register_intc_controller(&intc_desc); 702 register_intc_controller(&intc_desc);
625} 703}
@@ -629,27 +707,27 @@ void __init plat_irq_setup_pins(int mode)
629 switch (mode) { 707 switch (mode) {
630 case IRQ_MODE_IRQ: 708 case IRQ_MODE_IRQ:
631 /* select IRQ mode for IRL3-0 + IRL7-4 */ 709 /* select IRQ mode for IRL3-0 + IRL7-4 */
632 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 710 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
633 register_intc_controller(&intc_irq_desc); 711 register_intc_controller(&intc_irq_desc);
634 break; 712 break;
635 case IRQ_MODE_IRL7654: 713 case IRQ_MODE_IRL7654:
636 /* enable IRL7-4 but don't provide any masking */ 714 /* enable IRL7-4 but don't provide any masking */
637 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 715 __raw_writel(0x40000000, INTC_INTMSKCLR1);
638 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 716 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
639 break; 717 break;
640 case IRQ_MODE_IRL3210: 718 case IRQ_MODE_IRL3210:
641 /* enable IRL0-3 but don't provide any masking */ 719 /* enable IRL0-3 but don't provide any masking */
642 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 720 __raw_writel(0x80000000, INTC_INTMSKCLR1);
643 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 721 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
644 break; 722 break;
645 case IRQ_MODE_IRL7654_MASK: 723 case IRQ_MODE_IRL7654_MASK:
646 /* enable IRL7-4 and mask using cpu intc controller */ 724 /* enable IRL7-4 and mask using cpu intc controller */
647 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 725 __raw_writel(0x40000000, INTC_INTMSKCLR1);
648 register_intc_controller(&intc_irl7654_desc); 726 register_intc_controller(&intc_irl7654_desc);
649 break; 727 break;
650 case IRQ_MODE_IRL3210_MASK: 728 case IRQ_MODE_IRL3210_MASK:
651 /* enable IRL0-3 and mask using cpu intc controller */ 729 /* enable IRL0-3 and mask using cpu intc controller */
652 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 730 __raw_writel(0x80000000, INTC_INTMSKCLR1);
653 register_intc_controller(&intc_irl3210_desc); 731 register_intc_controller(&intc_irl3210_desc);
654 break; 732 break;
655 default: 733 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index bcd411eb9cb0..08add7fa6849 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -12,19 +12,53 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_dma.h>
15#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
16 17
18#include <cpu/dma-register.h>
19
20static struct plat_sci_port scif0_platform_data = {
21 .mapbase = 0xffe00000,
22 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
24 .scbrr_algo_id = SCBRR_ALGO_1,
25 .type = PORT_SCIF,
26 .irqs = { 40, 40, 40, 40 },
27};
28
29static struct platform_device scif0_device = {
30 .name = "sh-sci",
31 .id = 0,
32 .dev = {
33 .platform_data = &scif0_platform_data,
34 },
35};
36
37static struct plat_sci_port scif1_platform_data = {
38 .mapbase = 0xffe10000,
39 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
41 .scbrr_algo_id = SCBRR_ALGO_1,
42 .type = PORT_SCIF,
43 .irqs = { 76, 76, 76, 76 },
44};
45
46static struct platform_device scif1_device = {
47 .name = "sh-sci",
48 .id = 1,
49 .dev = {
50 .platform_data = &scif1_platform_data,
51 },
52};
53
17static struct sh_timer_config tmu0_platform_data = { 54static struct sh_timer_config tmu0_platform_data = {
18 .name = "TMU0",
19 .channel_offset = 0x04, 55 .channel_offset = 0x04,
20 .timer_bit = 0, 56 .timer_bit = 0,
21 .clk = "peripheral_clk",
22 .clockevent_rating = 200, 57 .clockevent_rating = 200,
23}; 58};
24 59
25static struct resource tmu0_resources[] = { 60static struct resource tmu0_resources[] = {
26 [0] = { 61 [0] = {
27 .name = "TMU0",
28 .start = 0xffd80008, 62 .start = 0xffd80008,
29 .end = 0xffd80013, 63 .end = 0xffd80013,
30 .flags = IORESOURCE_MEM, 64 .flags = IORESOURCE_MEM,
@@ -46,16 +80,13 @@ static struct platform_device tmu0_device = {
46}; 80};
47 81
48static struct sh_timer_config tmu1_platform_data = { 82static struct sh_timer_config tmu1_platform_data = {
49 .name = "TMU1",
50 .channel_offset = 0x10, 83 .channel_offset = 0x10,
51 .timer_bit = 1, 84 .timer_bit = 1,
52 .clk = "peripheral_clk",
53 .clocksource_rating = 200, 85 .clocksource_rating = 200,
54}; 86};
55 87
56static struct resource tmu1_resources[] = { 88static struct resource tmu1_resources[] = {
57 [0] = { 89 [0] = {
58 .name = "TMU1",
59 .start = 0xffd80014, 90 .start = 0xffd80014,
60 .end = 0xffd8001f, 91 .end = 0xffd8001f,
61 .flags = IORESOURCE_MEM, 92 .flags = IORESOURCE_MEM,
@@ -77,15 +108,12 @@ static struct platform_device tmu1_device = {
77}; 108};
78 109
79static struct sh_timer_config tmu2_platform_data = { 110static struct sh_timer_config tmu2_platform_data = {
80 .name = "TMU2",
81 .channel_offset = 0x1c, 111 .channel_offset = 0x1c,
82 .timer_bit = 2, 112 .timer_bit = 2,
83 .clk = "peripheral_clk",
84}; 113};
85 114
86static struct resource tmu2_resources[] = { 115static struct resource tmu2_resources[] = {
87 [0] = { 116 [0] = {
88 .name = "TMU2",
89 .start = 0xffd80020, 117 .start = 0xffd80020,
90 .end = 0xffd8002f, 118 .end = 0xffd8002f,
91 .flags = IORESOURCE_MEM, 119 .flags = IORESOURCE_MEM,
@@ -107,15 +135,12 @@ static struct platform_device tmu2_device = {
107}; 135};
108 136
109static struct sh_timer_config tmu3_platform_data = { 137static struct sh_timer_config tmu3_platform_data = {
110 .name = "TMU3",
111 .channel_offset = 0x04, 138 .channel_offset = 0x04,
112 .timer_bit = 0, 139 .timer_bit = 0,
113 .clk = "peripheral_clk",
114}; 140};
115 141
116static struct resource tmu3_resources[] = { 142static struct resource tmu3_resources[] = {
117 [0] = { 143 [0] = {
118 .name = "TMU3",
119 .start = 0xffdc0008, 144 .start = 0xffdc0008,
120 .end = 0xffdc0013, 145 .end = 0xffdc0013,
121 .flags = IORESOURCE_MEM, 146 .flags = IORESOURCE_MEM,
@@ -137,15 +162,12 @@ static struct platform_device tmu3_device = {
137}; 162};
138 163
139static struct sh_timer_config tmu4_platform_data = { 164static struct sh_timer_config tmu4_platform_data = {
140 .name = "TMU4",
141 .channel_offset = 0x10, 165 .channel_offset = 0x10,
142 .timer_bit = 1, 166 .timer_bit = 1,
143 .clk = "peripheral_clk",
144}; 167};
145 168
146static struct resource tmu4_resources[] = { 169static struct resource tmu4_resources[] = {
147 [0] = { 170 [0] = {
148 .name = "TMU4",
149 .start = 0xffdc0014, 171 .start = 0xffdc0014,
150 .end = 0xffdc001f, 172 .end = 0xffdc001f,
151 .flags = IORESOURCE_MEM, 173 .flags = IORESOURCE_MEM,
@@ -167,15 +189,12 @@ static struct platform_device tmu4_device = {
167}; 189};
168 190
169static struct sh_timer_config tmu5_platform_data = { 191static struct sh_timer_config tmu5_platform_data = {
170 .name = "TMU5",
171 .channel_offset = 0x1c, 192 .channel_offset = 0x1c,
172 .timer_bit = 2, 193 .timer_bit = 2,
173 .clk = "peripheral_clk",
174}; 194};
175 195
176static struct resource tmu5_resources[] = { 196static struct resource tmu5_resources[] = {
177 [0] = { 197 [0] = {
178 .name = "TMU5",
179 .start = 0xffdc0020, 198 .start = 0xffdc0020,
180 .end = 0xffdc002b, 199 .end = 0xffdc002b,
181 .flags = IORESOURCE_MEM, 200 .flags = IORESOURCE_MEM,
@@ -216,35 +235,137 @@ static struct platform_device rtc_device = {
216 .resource = rtc_resources, 235 .resource = rtc_resources,
217}; 236};
218 237
219static struct plat_sci_port sci_platform_data[] = { 238/* DMA */
239static const struct sh_dmae_channel sh7780_dmae0_channels[] = {
220 { 240 {
221 .mapbase = 0xffe00000, 241 .offset = 0,
222 .flags = UPF_BOOT_AUTOCONF, 242 .dmars = 0,
223 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 243 .dmars_bit = 0,
224 .scbrr_algo_id = SCBRR_ALGO_1, 244 }, {
225 .type = PORT_SCIF, 245 .offset = 0x10,
226 .irqs = { 40, 40, 40, 40 }, 246 .dmars = 0,
247 .dmars_bit = 8,
248 }, {
249 .offset = 0x20,
250 .dmars = 4,
251 .dmars_bit = 0,
227 }, { 252 }, {
228 .mapbase = 0xffe10000, 253 .offset = 0x30,
229 .flags = UPF_BOOT_AUTOCONF, 254 .dmars = 4,
230 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 255 .dmars_bit = 8,
231 .scbrr_algo_id = SCBRR_ALGO_1,
232 .type = PORT_SCIF,
233 .irqs = { 76, 76, 76, 76 },
234 }, { 256 }, {
235 .flags = 0, 257 .offset = 0x50,
258 .dmars = 8,
259 .dmars_bit = 0,
260 }, {
261 .offset = 0x60,
262 .dmars = 8,
263 .dmars_bit = 8,
236 } 264 }
237}; 265};
238 266
239static struct platform_device sci_device = { 267static const struct sh_dmae_channel sh7780_dmae1_channels[] = {
240 .name = "sh-sci", 268 {
241 .id = -1, 269 .offset = 0,
270 }, {
271 .offset = 0x10,
272 }, {
273 .offset = 0x20,
274 }, {
275 .offset = 0x30,
276 }, {
277 .offset = 0x50,
278 }, {
279 .offset = 0x60,
280 }
281};
282
283static const unsigned int ts_shift[] = TS_SHIFT;
284
285static struct sh_dmae_pdata dma0_platform_data = {
286 .channel = sh7780_dmae0_channels,
287 .channel_num = ARRAY_SIZE(sh7780_dmae0_channels),
288 .ts_low_shift = CHCR_TS_LOW_SHIFT,
289 .ts_low_mask = CHCR_TS_LOW_MASK,
290 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
291 .ts_high_mask = CHCR_TS_HIGH_MASK,
292 .ts_shift = ts_shift,
293 .ts_shift_num = ARRAY_SIZE(ts_shift),
294 .dmaor_init = DMAOR_INIT,
295};
296
297static struct sh_dmae_pdata dma1_platform_data = {
298 .channel = sh7780_dmae1_channels,
299 .channel_num = ARRAY_SIZE(sh7780_dmae1_channels),
300 .ts_low_shift = CHCR_TS_LOW_SHIFT,
301 .ts_low_mask = CHCR_TS_LOW_MASK,
302 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
303 .ts_high_mask = CHCR_TS_HIGH_MASK,
304 .ts_shift = ts_shift,
305 .ts_shift_num = ARRAY_SIZE(ts_shift),
306 .dmaor_init = DMAOR_INIT,
307};
308
309static struct resource sh7780_dmae0_resources[] = {
310 [0] = {
311 /* Channel registers and DMAOR */
312 .start = 0xfc808020,
313 .end = 0xfc80808f,
314 .flags = IORESOURCE_MEM,
315 },
316 [1] = {
317 /* DMARSx */
318 .start = 0xfc809000,
319 .end = 0xfc80900b,
320 .flags = IORESOURCE_MEM,
321 },
322 {
323 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
324 .start = 34,
325 .end = 34,
326 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
327 },
328};
329
330static struct resource sh7780_dmae1_resources[] = {
331 [0] = {
332 /* Channel registers and DMAOR */
333 .start = 0xfc818020,
334 .end = 0xfc81808f,
335 .flags = IORESOURCE_MEM,
336 },
337 /* DMAC1 has no DMARS */
338 {
339 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
340 .start = 46,
341 .end = 46,
342 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
343 },
344};
345
346static struct platform_device dma0_device = {
347 .name = "sh-dma-engine",
348 .id = 0,
349 .resource = sh7780_dmae0_resources,
350 .num_resources = ARRAY_SIZE(sh7780_dmae0_resources),
351 .dev = {
352 .platform_data = &dma0_platform_data,
353 },
354};
355
356static struct platform_device dma1_device = {
357 .name = "sh-dma-engine",
358 .id = 1,
359 .resource = sh7780_dmae1_resources,
360 .num_resources = ARRAY_SIZE(sh7780_dmae1_resources),
242 .dev = { 361 .dev = {
243 .platform_data = sci_platform_data, 362 .platform_data = &dma1_platform_data,
244 }, 363 },
245}; 364};
246 365
247static struct platform_device *sh7780_devices[] __initdata = { 366static struct platform_device *sh7780_devices[] __initdata = {
367 &scif0_device,
368 &scif1_device,
248 &tmu0_device, 369 &tmu0_device,
249 &tmu1_device, 370 &tmu1_device,
250 &tmu2_device, 371 &tmu2_device,
@@ -252,7 +373,8 @@ static struct platform_device *sh7780_devices[] __initdata = {
252 &tmu4_device, 373 &tmu4_device,
253 &tmu5_device, 374 &tmu5_device,
254 &rtc_device, 375 &rtc_device,
255 &sci_device, 376 &dma0_device,
377 &dma1_device,
256}; 378};
257 379
258static int __init sh7780_devices_setup(void) 380static int __init sh7780_devices_setup(void)
@@ -260,9 +382,11 @@ static int __init sh7780_devices_setup(void)
260 return platform_add_devices(sh7780_devices, 382 return platform_add_devices(sh7780_devices,
261 ARRAY_SIZE(sh7780_devices)); 383 ARRAY_SIZE(sh7780_devices));
262} 384}
263__initcall(sh7780_devices_setup); 385arch_initcall(sh7780_devices_setup);
264 386
265static struct platform_device *sh7780_early_devices[] __initdata = { 387static struct platform_device *sh7780_early_devices[] __initdata = {
388 &scif0_device,
389 &scif1_device,
266 &tmu0_device, 390 &tmu0_device,
267 &tmu1_device, 391 &tmu1_device,
268 &tmu2_device, 392 &tmu2_device,
@@ -273,6 +397,13 @@ static struct platform_device *sh7780_early_devices[] __initdata = {
273 397
274void __init plat_early_device_setup(void) 398void __init plat_early_device_setup(void)
275{ 399{
400 if (mach_is_sh2007()) {
401 scif0_platform_data.scscr &= ~SCSCR_CKE1;
402 scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
403 scif1_platform_data.scscr &= ~SCSCR_CKE1;
404 scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
405 }
406
276 early_platform_add_devices(sh7780_early_devices, 407 early_platform_add_devices(sh7780_early_devices,
277 ARRAY_SIZE(sh7780_early_devices)); 408 ARRAY_SIZE(sh7780_early_devices));
278} 409}
@@ -443,17 +574,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
443void __init plat_irq_setup(void) 574void __init plat_irq_setup(void)
444{ 575{
445 /* disable IRQ7-0 */ 576 /* disable IRQ7-0 */
446 ctrl_outl(0xff000000, INTC_INTMSK0); 577 __raw_writel(0xff000000, INTC_INTMSK0);
447 578
448 /* disable IRL3-0 + IRL7-4 */ 579 /* disable IRL3-0 + IRL7-4 */
449 ctrl_outl(0xc0000000, INTC_INTMSK1); 580 __raw_writel(0xc0000000, INTC_INTMSK1);
450 ctrl_outl(0xfffefffe, INTC_INTMSK2); 581 __raw_writel(0xfffefffe, INTC_INTMSK2);
451 582
452 /* select IRL mode for IRL3-0 + IRL7-4 */ 583 /* select IRL mode for IRL3-0 + IRL7-4 */
453 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 584 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
454 585
455 /* disable holding function, ie enable "SH-4 Mode" */ 586 /* disable holding function, ie enable "SH-4 Mode" */
456 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 587 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
457 588
458 register_intc_controller(&intc_desc); 589 register_intc_controller(&intc_desc);
459} 590}
@@ -463,27 +594,27 @@ void __init plat_irq_setup_pins(int mode)
463 switch (mode) { 594 switch (mode) {
464 case IRQ_MODE_IRQ: 595 case IRQ_MODE_IRQ:
465 /* select IRQ mode for IRL3-0 + IRL7-4 */ 596 /* select IRQ mode for IRL3-0 + IRL7-4 */
466 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 597 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
467 register_intc_controller(&intc_irq_desc); 598 register_intc_controller(&intc_irq_desc);
468 break; 599 break;
469 case IRQ_MODE_IRL7654: 600 case IRQ_MODE_IRL7654:
470 /* enable IRL7-4 but don't provide any masking */ 601 /* enable IRL7-4 but don't provide any masking */
471 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 602 __raw_writel(0x40000000, INTC_INTMSKCLR1);
472 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 603 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
473 break; 604 break;
474 case IRQ_MODE_IRL3210: 605 case IRQ_MODE_IRL3210:
475 /* enable IRL0-3 but don't provide any masking */ 606 /* enable IRL0-3 but don't provide any masking */
476 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 607 __raw_writel(0x80000000, INTC_INTMSKCLR1);
477 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 608 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
478 break; 609 break;
479 case IRQ_MODE_IRL7654_MASK: 610 case IRQ_MODE_IRL7654_MASK:
480 /* enable IRL7-4 and mask using cpu intc controller */ 611 /* enable IRL7-4 and mask using cpu intc controller */
481 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 612 __raw_writel(0x40000000, INTC_INTMSKCLR1);
482 register_intc_controller(&intc_irl7654_desc); 613 register_intc_controller(&intc_irl7654_desc);
483 break; 614 break;
484 case IRQ_MODE_IRL3210_MASK: 615 case IRQ_MODE_IRL3210_MASK:
485 /* enable IRL0-3 and mask using cpu intc controller */ 616 /* enable IRL0-3 and mask using cpu intc controller */
486 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 617 __raw_writel(0x80000000, INTC_INTMSKCLR1);
487 register_intc_controller(&intc_irl3210_desc); 618 register_intc_controller(&intc_irl3210_desc);
488 break; 619 break;
489 default: 620 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 3ae2e2071009..18d8fc136fb2 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -13,20 +13,123 @@
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/mm.h> 15#include <linux/mm.h>
16#include <linux/sh_dma.h>
16#include <linux/sh_timer.h> 17#include <linux/sh_timer.h>
18
17#include <asm/mmzone.h> 19#include <asm/mmzone.h>
18 20
21#include <cpu/dma-register.h>
22
23static struct plat_sci_port scif0_platform_data = {
24 .mapbase = 0xffea0000,
25 .flags = UPF_BOOT_AUTOCONF,
26 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
27 .scbrr_algo_id = SCBRR_ALGO_1,
28 .type = PORT_SCIF,
29 .irqs = { 40, 40, 40, 40 },
30};
31
32static struct platform_device scif0_device = {
33 .name = "sh-sci",
34 .id = 0,
35 .dev = {
36 .platform_data = &scif0_platform_data,
37 },
38};
39
40static struct plat_sci_port scif1_platform_data = {
41 .mapbase = 0xffeb0000,
42 .flags = UPF_BOOT_AUTOCONF,
43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
44 .scbrr_algo_id = SCBRR_ALGO_1,
45 .type = PORT_SCIF,
46 .irqs = { 44, 44, 44, 44 },
47};
48
49static struct platform_device scif1_device = {
50 .name = "sh-sci",
51 .id = 1,
52 .dev = {
53 .platform_data = &scif1_platform_data,
54 },
55};
56
57static struct plat_sci_port scif2_platform_data = {
58 .mapbase = 0xffec0000,
59 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
61 .scbrr_algo_id = SCBRR_ALGO_1,
62 .type = PORT_SCIF,
63 .irqs = { 60, 60, 60, 60 },
64};
65
66static struct platform_device scif2_device = {
67 .name = "sh-sci",
68 .id = 2,
69 .dev = {
70 .platform_data = &scif2_platform_data,
71 },
72};
73
74static struct plat_sci_port scif3_platform_data = {
75 .mapbase = 0xffed0000,
76 .flags = UPF_BOOT_AUTOCONF,
77 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
78 .scbrr_algo_id = SCBRR_ALGO_1,
79 .type = PORT_SCIF,
80 .irqs = { 61, 61, 61, 61 },
81};
82
83static struct platform_device scif3_device = {
84 .name = "sh-sci",
85 .id = 3,
86 .dev = {
87 .platform_data = &scif3_platform_data,
88 },
89};
90
91static struct plat_sci_port scif4_platform_data = {
92 .mapbase = 0xffee0000,
93 .flags = UPF_BOOT_AUTOCONF,
94 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
95 .scbrr_algo_id = SCBRR_ALGO_1,
96 .type = PORT_SCIF,
97 .irqs = { 62, 62, 62, 62 },
98};
99
100static struct platform_device scif4_device = {
101 .name = "sh-sci",
102 .id = 4,
103 .dev = {
104 .platform_data = &scif4_platform_data,
105 },
106};
107
108static struct plat_sci_port scif5_platform_data = {
109 .mapbase = 0xffef0000,
110 .flags = UPF_BOOT_AUTOCONF,
111 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
112 .scbrr_algo_id = SCBRR_ALGO_1,
113 .type = PORT_SCIF,
114 .irqs = { 63, 63, 63, 63 },
115};
116
117static struct platform_device scif5_device = {
118 .name = "sh-sci",
119 .id = 5,
120 .dev = {
121 .platform_data = &scif5_platform_data,
122 },
123};
124
19static struct sh_timer_config tmu0_platform_data = { 125static struct sh_timer_config tmu0_platform_data = {
20 .name = "TMU0",
21 .channel_offset = 0x04, 126 .channel_offset = 0x04,
22 .timer_bit = 0, 127 .timer_bit = 0,
23 .clk = "tmu012_fck",
24 .clockevent_rating = 200, 128 .clockevent_rating = 200,
25}; 129};
26 130
27static struct resource tmu0_resources[] = { 131static struct resource tmu0_resources[] = {
28 [0] = { 132 [0] = {
29 .name = "TMU0",
30 .start = 0xffd80008, 133 .start = 0xffd80008,
31 .end = 0xffd80013, 134 .end = 0xffd80013,
32 .flags = IORESOURCE_MEM, 135 .flags = IORESOURCE_MEM,
@@ -48,16 +151,13 @@ static struct platform_device tmu0_device = {
48}; 151};
49 152
50static struct sh_timer_config tmu1_platform_data = { 153static struct sh_timer_config tmu1_platform_data = {
51 .name = "TMU1",
52 .channel_offset = 0x10, 154 .channel_offset = 0x10,
53 .timer_bit = 1, 155 .timer_bit = 1,
54 .clk = "tmu012_fck",
55 .clocksource_rating = 200, 156 .clocksource_rating = 200,
56}; 157};
57 158
58static struct resource tmu1_resources[] = { 159static struct resource tmu1_resources[] = {
59 [0] = { 160 [0] = {
60 .name = "TMU1",
61 .start = 0xffd80014, 161 .start = 0xffd80014,
62 .end = 0xffd8001f, 162 .end = 0xffd8001f,
63 .flags = IORESOURCE_MEM, 163 .flags = IORESOURCE_MEM,
@@ -79,15 +179,12 @@ static struct platform_device tmu1_device = {
79}; 179};
80 180
81static struct sh_timer_config tmu2_platform_data = { 181static struct sh_timer_config tmu2_platform_data = {
82 .name = "TMU2",
83 .channel_offset = 0x1c, 182 .channel_offset = 0x1c,
84 .timer_bit = 2, 183 .timer_bit = 2,
85 .clk = "tmu012_fck",
86}; 184};
87 185
88static struct resource tmu2_resources[] = { 186static struct resource tmu2_resources[] = {
89 [0] = { 187 [0] = {
90 .name = "TMU2",
91 .start = 0xffd80020, 188 .start = 0xffd80020,
92 .end = 0xffd8002f, 189 .end = 0xffd8002f,
93 .flags = IORESOURCE_MEM, 190 .flags = IORESOURCE_MEM,
@@ -109,15 +206,12 @@ static struct platform_device tmu2_device = {
109}; 206};
110 207
111static struct sh_timer_config tmu3_platform_data = { 208static struct sh_timer_config tmu3_platform_data = {
112 .name = "TMU3",
113 .channel_offset = 0x04, 209 .channel_offset = 0x04,
114 .timer_bit = 0, 210 .timer_bit = 0,
115 .clk = "tmu345_fck",
116}; 211};
117 212
118static struct resource tmu3_resources[] = { 213static struct resource tmu3_resources[] = {
119 [0] = { 214 [0] = {
120 .name = "TMU3",
121 .start = 0xffdc0008, 215 .start = 0xffdc0008,
122 .end = 0xffdc0013, 216 .end = 0xffdc0013,
123 .flags = IORESOURCE_MEM, 217 .flags = IORESOURCE_MEM,
@@ -139,15 +233,12 @@ static struct platform_device tmu3_device = {
139}; 233};
140 234
141static struct sh_timer_config tmu4_platform_data = { 235static struct sh_timer_config tmu4_platform_data = {
142 .name = "TMU4",
143 .channel_offset = 0x10, 236 .channel_offset = 0x10,
144 .timer_bit = 1, 237 .timer_bit = 1,
145 .clk = "tmu345_fck",
146}; 238};
147 239
148static struct resource tmu4_resources[] = { 240static struct resource tmu4_resources[] = {
149 [0] = { 241 [0] = {
150 .name = "TMU4",
151 .start = 0xffdc0014, 242 .start = 0xffdc0014,
152 .end = 0xffdc001f, 243 .end = 0xffdc001f,
153 .flags = IORESOURCE_MEM, 244 .flags = IORESOURCE_MEM,
@@ -169,15 +260,12 @@ static struct platform_device tmu4_device = {
169}; 260};
170 261
171static struct sh_timer_config tmu5_platform_data = { 262static struct sh_timer_config tmu5_platform_data = {
172 .name = "TMU5",
173 .channel_offset = 0x1c, 263 .channel_offset = 0x1c,
174 .timer_bit = 2, 264 .timer_bit = 2,
175 .clk = "tmu345_fck",
176}; 265};
177 266
178static struct resource tmu5_resources[] = { 267static struct resource tmu5_resources[] = {
179 [0] = { 268 [0] = {
180 .name = "TMU5",
181 .start = 0xffdc0020, 269 .start = 0xffdc0020,
182 .end = 0xffdc002b, 270 .end = 0xffdc002b,
183 .flags = IORESOURCE_MEM, 271 .flags = IORESOURCE_MEM,
@@ -198,76 +286,149 @@ static struct platform_device tmu5_device = {
198 .num_resources = ARRAY_SIZE(tmu5_resources), 286 .num_resources = ARRAY_SIZE(tmu5_resources),
199}; 287};
200 288
201static struct plat_sci_port sci_platform_data[] = { 289/* DMA */
290static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
202 { 291 {
203 .mapbase = 0xffea0000, 292 .offset = 0,
204 .flags = UPF_BOOT_AUTOCONF, 293 .dmars = 0,
205 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 294 .dmars_bit = 0,
206 .scbrr_algo_id = SCBRR_ALGO_1,
207 .type = PORT_SCIF,
208 .irqs = { 40, 40, 40, 40 },
209 .clk = "scif_fck",
210 }, { 295 }, {
211 .mapbase = 0xffeb0000, 296 .offset = 0x10,
212 .flags = UPF_BOOT_AUTOCONF, 297 .dmars = 0,
213 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 298 .dmars_bit = 8,
214 .scbrr_algo_id = SCBRR_ALGO_1,
215 .type = PORT_SCIF,
216 .irqs = { 44, 44, 44, 44 },
217 .clk = "scif_fck",
218 }, { 299 }, {
219 .mapbase = 0xffec0000, 300 .offset = 0x20,
220 .flags = UPF_BOOT_AUTOCONF, 301 .dmars = 4,
221 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 302 .dmars_bit = 0,
222 .scbrr_algo_id = SCBRR_ALGO_1,
223 .type = PORT_SCIF,
224 .irqs = { 60, 60, 60, 60 },
225 .clk = "scif_fck",
226 }, { 303 }, {
227 .mapbase = 0xffed0000, 304 .offset = 0x30,
228 .flags = UPF_BOOT_AUTOCONF, 305 .dmars = 4,
229 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 306 .dmars_bit = 8,
230 .scbrr_algo_id = SCBRR_ALGO_1,
231 .type = PORT_SCIF,
232 .irqs = { 61, 61, 61, 61 },
233 .clk = "scif_fck",
234 }, { 307 }, {
235 .mapbase = 0xffee0000, 308 .offset = 0x50,
236 .flags = UPF_BOOT_AUTOCONF, 309 .dmars = 8,
237 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 310 .dmars_bit = 0,
238 .scbrr_algo_id = SCBRR_ALGO_1,
239 .type = PORT_SCIF,
240 .irqs = { 62, 62, 62, 62 },
241 .clk = "scif_fck",
242 }, { 311 }, {
243 .mapbase = 0xffef0000, 312 .offset = 0x60,
244 .flags = UPF_BOOT_AUTOCONF, 313 .dmars = 8,
245 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 314 .dmars_bit = 8,
246 .scbrr_algo_id = SCBRR_ALGO_1, 315 }
247 .type = PORT_SCIF, 316};
248 .irqs = { 63, 63, 63, 63 }, 317
249 .clk = "scif_fck", 318static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
319 {
320 .offset = 0,
250 }, { 321 }, {
251 .flags = 0, 322 .offset = 0x10,
323 }, {
324 .offset = 0x20,
325 }, {
326 .offset = 0x30,
327 }, {
328 .offset = 0x50,
329 }, {
330 .offset = 0x60,
252 } 331 }
253}; 332};
254 333
255static struct platform_device sci_device = { 334static const unsigned int ts_shift[] = TS_SHIFT;
256 .name = "sh-sci", 335
257 .id = -1, 336static struct sh_dmae_pdata dma0_platform_data = {
337 .channel = sh7785_dmae0_channels,
338 .channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
339 .ts_low_shift = CHCR_TS_LOW_SHIFT,
340 .ts_low_mask = CHCR_TS_LOW_MASK,
341 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
342 .ts_high_mask = CHCR_TS_HIGH_MASK,
343 .ts_shift = ts_shift,
344 .ts_shift_num = ARRAY_SIZE(ts_shift),
345 .dmaor_init = DMAOR_INIT,
346};
347
348static struct sh_dmae_pdata dma1_platform_data = {
349 .channel = sh7785_dmae1_channels,
350 .channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
351 .ts_low_shift = CHCR_TS_LOW_SHIFT,
352 .ts_low_mask = CHCR_TS_LOW_MASK,
353 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
354 .ts_high_mask = CHCR_TS_HIGH_MASK,
355 .ts_shift = ts_shift,
356 .ts_shift_num = ARRAY_SIZE(ts_shift),
357 .dmaor_init = DMAOR_INIT,
358};
359
360static struct resource sh7785_dmae0_resources[] = {
361 [0] = {
362 /* Channel registers and DMAOR */
363 .start = 0xfc808020,
364 .end = 0xfc80808f,
365 .flags = IORESOURCE_MEM,
366 },
367 [1] = {
368 /* DMARSx */
369 .start = 0xfc809000,
370 .end = 0xfc80900b,
371 .flags = IORESOURCE_MEM,
372 },
373 {
374 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
375 .start = 33,
376 .end = 33,
377 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
378 },
379};
380
381static struct resource sh7785_dmae1_resources[] = {
382 [0] = {
383 /* Channel registers and DMAOR */
384 .start = 0xfcc08020,
385 .end = 0xfcc0808f,
386 .flags = IORESOURCE_MEM,
387 },
388 /* DMAC1 has no DMARS */
389 {
390 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
391 .start = 52,
392 .end = 52,
393 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
394 },
395};
396
397static struct platform_device dma0_device = {
398 .name = "sh-dma-engine",
399 .id = 0,
400 .resource = sh7785_dmae0_resources,
401 .num_resources = ARRAY_SIZE(sh7785_dmae0_resources),
402 .dev = {
403 .platform_data = &dma0_platform_data,
404 },
405};
406
407static struct platform_device dma1_device = {
408 .name = "sh-dma-engine",
409 .id = 1,
410 .resource = sh7785_dmae1_resources,
411 .num_resources = ARRAY_SIZE(sh7785_dmae1_resources),
258 .dev = { 412 .dev = {
259 .platform_data = sci_platform_data, 413 .platform_data = &dma1_platform_data,
260 }, 414 },
261}; 415};
262 416
263static struct platform_device *sh7785_devices[] __initdata = { 417static struct platform_device *sh7785_devices[] __initdata = {
418 &scif0_device,
419 &scif1_device,
420 &scif2_device,
421 &scif3_device,
422 &scif4_device,
423 &scif5_device,
264 &tmu0_device, 424 &tmu0_device,
265 &tmu1_device, 425 &tmu1_device,
266 &tmu2_device, 426 &tmu2_device,
267 &tmu3_device, 427 &tmu3_device,
268 &tmu4_device, 428 &tmu4_device,
269 &tmu5_device, 429 &tmu5_device,
270 &sci_device, 430 &dma0_device,
431 &dma1_device,
271}; 432};
272 433
273static int __init sh7785_devices_setup(void) 434static int __init sh7785_devices_setup(void)
@@ -275,9 +436,15 @@ static int __init sh7785_devices_setup(void)
275 return platform_add_devices(sh7785_devices, 436 return platform_add_devices(sh7785_devices,
276 ARRAY_SIZE(sh7785_devices)); 437 ARRAY_SIZE(sh7785_devices));
277} 438}
278__initcall(sh7785_devices_setup); 439arch_initcall(sh7785_devices_setup);
279 440
280static struct platform_device *sh7785_early_devices[] __initdata = { 441static struct platform_device *sh7785_early_devices[] __initdata = {
442 &scif0_device,
443 &scif1_device,
444 &scif2_device,
445 &scif3_device,
446 &scif4_device,
447 &scif5_device,
281 &tmu0_device, 448 &tmu0_device,
282 &tmu1_device, 449 &tmu1_device,
283 &tmu2_device, 450 &tmu2_device,
@@ -482,17 +649,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
482void __init plat_irq_setup(void) 649void __init plat_irq_setup(void)
483{ 650{
484 /* disable IRQ3-0 + IRQ7-4 */ 651 /* disable IRQ3-0 + IRQ7-4 */
485 ctrl_outl(0xff000000, INTC_INTMSK0); 652 __raw_writel(0xff000000, INTC_INTMSK0);
486 653
487 /* disable IRL3-0 + IRL7-4 */ 654 /* disable IRL3-0 + IRL7-4 */
488 ctrl_outl(0xc0000000, INTC_INTMSK1); 655 __raw_writel(0xc0000000, INTC_INTMSK1);
489 ctrl_outl(0xfffefffe, INTC_INTMSK2); 656 __raw_writel(0xfffefffe, INTC_INTMSK2);
490 657
491 /* select IRL mode for IRL3-0 + IRL7-4 */ 658 /* select IRL mode for IRL3-0 + IRL7-4 */
492 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 659 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
493 660
494 /* disable holding function, ie enable "SH-4 Mode" */ 661 /* disable holding function, ie enable "SH-4 Mode" */
495 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 662 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
496 663
497 register_intc_controller(&intc_desc); 664 register_intc_controller(&intc_desc);
498} 665}
@@ -502,32 +669,32 @@ void __init plat_irq_setup_pins(int mode)
502 switch (mode) { 669 switch (mode) {
503 case IRQ_MODE_IRQ7654: 670 case IRQ_MODE_IRQ7654:
504 /* select IRQ mode for IRL7-4 */ 671 /* select IRQ mode for IRL7-4 */
505 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0); 672 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
506 register_intc_controller(&intc_desc_irq4567); 673 register_intc_controller(&intc_desc_irq4567);
507 break; 674 break;
508 case IRQ_MODE_IRQ3210: 675 case IRQ_MODE_IRQ3210:
509 /* select IRQ mode for IRL3-0 */ 676 /* select IRQ mode for IRL3-0 */
510 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0); 677 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
511 register_intc_controller(&intc_desc_irq0123); 678 register_intc_controller(&intc_desc_irq0123);
512 break; 679 break;
513 case IRQ_MODE_IRL7654: 680 case IRQ_MODE_IRL7654:
514 /* enable IRL7-4 but don't provide any masking */ 681 /* enable IRL7-4 but don't provide any masking */
515 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 682 __raw_writel(0x40000000, INTC_INTMSKCLR1);
516 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 683 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
517 break; 684 break;
518 case IRQ_MODE_IRL3210: 685 case IRQ_MODE_IRL3210:
519 /* enable IRL0-3 but don't provide any masking */ 686 /* enable IRL0-3 but don't provide any masking */
520 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 687 __raw_writel(0x80000000, INTC_INTMSKCLR1);
521 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 688 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
522 break; 689 break;
523 case IRQ_MODE_IRL7654_MASK: 690 case IRQ_MODE_IRL7654_MASK:
524 /* enable IRL7-4 and mask using cpu intc controller */ 691 /* enable IRL7-4 and mask using cpu intc controller */
525 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 692 __raw_writel(0x40000000, INTC_INTMSKCLR1);
526 register_intc_controller(&intc_desc_irl4567); 693 register_intc_controller(&intc_desc_irl4567);
527 break; 694 break;
528 case IRQ_MODE_IRL3210_MASK: 695 case IRQ_MODE_IRL3210_MASK:
529 /* enable IRL0-3 and mask using cpu intc controller */ 696 /* enable IRL0-3 and mask using cpu intc controller */
530 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 697 __raw_writel(0x80000000, INTC_INTMSKCLR1);
531 register_intc_controller(&intc_desc_irl0123); 698 register_intc_controller(&intc_desc_irl0123);
532 break; 699 break;
533 default: 700 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 8b7ea4bd965d..1656b8c91faf 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7786 Setup 2 * SH7786 Setup
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009 - 2010 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * Paul Mundt <paul.mundt@renesas.com> 6 * Paul Mundt <paul.mundt@renesas.com>
7 * 7 *
@@ -21,79 +21,124 @@
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/dma-mapping.h> 22#include <linux/dma-mapping.h>
23#include <linux/sh_timer.h> 23#include <linux/sh_timer.h>
24#include <linux/sh_dma.h>
25#include <linux/sh_intc.h>
26#include <cpu/dma-register.h>
24#include <asm/mmzone.h> 27#include <asm/mmzone.h>
25 28
26static struct plat_sci_port sci_platform_data[] = { 29static struct plat_sci_port scif0_platform_data = {
27 { 30 .mapbase = 0xffea0000,
28 .mapbase = 0xffea0000, 31 .flags = UPF_BOOT_AUTOCONF,
29 .flags = UPF_BOOT_AUTOCONF, 32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
30 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 33 .scbrr_algo_id = SCBRR_ALGO_1,
31 .scbrr_algo_id = SCBRR_ALGO_1, 34 .type = PORT_SCIF,
32 .type = PORT_SCIF, 35 .irqs = { 40, 41, 43, 42 },
33 .irqs = { 40, 41, 43, 42 }, 36};
37
38static struct platform_device scif0_device = {
39 .name = "sh-sci",
40 .id = 0,
41 .dev = {
42 .platform_data = &scif0_platform_data,
34 }, 43 },
35 /*
36 * The rest of these all have multiplexed IRQs
37 */
38 {
39 .mapbase = 0xffeb0000,
40 .flags = UPF_BOOT_AUTOCONF,
41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
42 .scbrr_algo_id = SCBRR_ALGO_1,
43 .type = PORT_SCIF,
44 .irqs = { 44, 44, 44, 44 },
45 }, {
46 .mapbase = 0xffec0000,
47 .flags = UPF_BOOT_AUTOCONF,
48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
49 .scbrr_algo_id = SCBRR_ALGO_1,
50 .type = PORT_SCIF,
51 .irqs = { 50, 50, 50, 50 },
52 }, {
53 .mapbase = 0xffed0000,
54 .flags = UPF_BOOT_AUTOCONF,
55 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
56 .scbrr_algo_id = SCBRR_ALGO_1,
57 .type = PORT_SCIF,
58 .irqs = { 51, 51, 51, 51 },
59 }, {
60 .mapbase = 0xffee0000,
61 .flags = UPF_BOOT_AUTOCONF,
62 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
63 .scbrr_algo_id = SCBRR_ALGO_1,
64 .type = PORT_SCIF,
65 .irqs = { 52, 52, 52, 52 },
66 }, {
67 .mapbase = 0xffef0000,
68 .flags = UPF_BOOT_AUTOCONF,
69 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
70 .scbrr_algo_id = SCBRR_ALGO_1,
71 .type = PORT_SCIF,
72 .irqs = { 53, 53, 53, 53 },
73 }, {
74 .flags = 0,
75 }
76}; 44};
77 45
78static struct platform_device sci_device = { 46/*
47 * The rest of these all have multiplexed IRQs
48 */
49static struct plat_sci_port scif1_platform_data = {
50 .mapbase = 0xffeb0000,
51 .flags = UPF_BOOT_AUTOCONF,
52 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
53 .scbrr_algo_id = SCBRR_ALGO_1,
54 .type = PORT_SCIF,
55 .irqs = { 44, 44, 44, 44 },
56};
57
58static struct platform_device scif1_device = {
79 .name = "sh-sci", 59 .name = "sh-sci",
80 .id = -1, 60 .id = 1,
61 .dev = {
62 .platform_data = &scif1_platform_data,
63 },
64};
65
66static struct plat_sci_port scif2_platform_data = {
67 .mapbase = 0xffec0000,
68 .flags = UPF_BOOT_AUTOCONF,
69 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
70 .scbrr_algo_id = SCBRR_ALGO_1,
71 .type = PORT_SCIF,
72 .irqs = { 50, 50, 50, 50 },
73};
74
75static struct platform_device scif2_device = {
76 .name = "sh-sci",
77 .id = 2,
81 .dev = { 78 .dev = {
82 .platform_data = sci_platform_data, 79 .platform_data = &scif2_platform_data,
80 },
81};
82
83static struct plat_sci_port scif3_platform_data = {
84 .mapbase = 0xffed0000,
85 .flags = UPF_BOOT_AUTOCONF,
86 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
87 .scbrr_algo_id = SCBRR_ALGO_1,
88 .type = PORT_SCIF,
89 .irqs = { 51, 51, 51, 51 },
90};
91
92static struct platform_device scif3_device = {
93 .name = "sh-sci",
94 .id = 3,
95 .dev = {
96 .platform_data = &scif3_platform_data,
97 },
98};
99
100static struct plat_sci_port scif4_platform_data = {
101 .mapbase = 0xffee0000,
102 .flags = UPF_BOOT_AUTOCONF,
103 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
104 .scbrr_algo_id = SCBRR_ALGO_1,
105 .type = PORT_SCIF,
106 .irqs = { 52, 52, 52, 52 },
107};
108
109static struct platform_device scif4_device = {
110 .name = "sh-sci",
111 .id = 4,
112 .dev = {
113 .platform_data = &scif4_platform_data,
114 },
115};
116
117static struct plat_sci_port scif5_platform_data = {
118 .mapbase = 0xffef0000,
119 .flags = UPF_BOOT_AUTOCONF,
120 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
121 .scbrr_algo_id = SCBRR_ALGO_1,
122 .type = PORT_SCIF,
123 .irqs = { 53, 53, 53, 53 },
124};
125
126static struct platform_device scif5_device = {
127 .name = "sh-sci",
128 .id = 5,
129 .dev = {
130 .platform_data = &scif5_platform_data,
83 }, 131 },
84}; 132};
85 133
86static struct sh_timer_config tmu0_platform_data = { 134static struct sh_timer_config tmu0_platform_data = {
87 .name = "TMU0",
88 .channel_offset = 0x04, 135 .channel_offset = 0x04,
89 .timer_bit = 0, 136 .timer_bit = 0,
90 .clk = "peripheral_clk",
91 .clockevent_rating = 200, 137 .clockevent_rating = 200,
92}; 138};
93 139
94static struct resource tmu0_resources[] = { 140static struct resource tmu0_resources[] = {
95 [0] = { 141 [0] = {
96 .name = "TMU0",
97 .start = 0xffd80008, 142 .start = 0xffd80008,
98 .end = 0xffd80013, 143 .end = 0xffd80013,
99 .flags = IORESOURCE_MEM, 144 .flags = IORESOURCE_MEM,
@@ -115,16 +160,13 @@ static struct platform_device tmu0_device = {
115}; 160};
116 161
117static struct sh_timer_config tmu1_platform_data = { 162static struct sh_timer_config tmu1_platform_data = {
118 .name = "TMU1",
119 .channel_offset = 0x10, 163 .channel_offset = 0x10,
120 .timer_bit = 1, 164 .timer_bit = 1,
121 .clk = "peripheral_clk",
122 .clocksource_rating = 200, 165 .clocksource_rating = 200,
123}; 166};
124 167
125static struct resource tmu1_resources[] = { 168static struct resource tmu1_resources[] = {
126 [0] = { 169 [0] = {
127 .name = "TMU1",
128 .start = 0xffd80014, 170 .start = 0xffd80014,
129 .end = 0xffd8001f, 171 .end = 0xffd8001f,
130 .flags = IORESOURCE_MEM, 172 .flags = IORESOURCE_MEM,
@@ -146,15 +188,12 @@ static struct platform_device tmu1_device = {
146}; 188};
147 189
148static struct sh_timer_config tmu2_platform_data = { 190static struct sh_timer_config tmu2_platform_data = {
149 .name = "TMU2",
150 .channel_offset = 0x1c, 191 .channel_offset = 0x1c,
151 .timer_bit = 2, 192 .timer_bit = 2,
152 .clk = "peripheral_clk",
153}; 193};
154 194
155static struct resource tmu2_resources[] = { 195static struct resource tmu2_resources[] = {
156 [0] = { 196 [0] = {
157 .name = "TMU2",
158 .start = 0xffd80020, 197 .start = 0xffd80020,
159 .end = 0xffd8002f, 198 .end = 0xffd8002f,
160 .flags = IORESOURCE_MEM, 199 .flags = IORESOURCE_MEM,
@@ -176,15 +215,12 @@ static struct platform_device tmu2_device = {
176}; 215};
177 216
178static struct sh_timer_config tmu3_platform_data = { 217static struct sh_timer_config tmu3_platform_data = {
179 .name = "TMU3",
180 .channel_offset = 0x04, 218 .channel_offset = 0x04,
181 .timer_bit = 0, 219 .timer_bit = 0,
182 .clk = "peripheral_clk",
183}; 220};
184 221
185static struct resource tmu3_resources[] = { 222static struct resource tmu3_resources[] = {
186 [0] = { 223 [0] = {
187 .name = "TMU3",
188 .start = 0xffda0008, 224 .start = 0xffda0008,
189 .end = 0xffda0013, 225 .end = 0xffda0013,
190 .flags = IORESOURCE_MEM, 226 .flags = IORESOURCE_MEM,
@@ -206,15 +242,12 @@ static struct platform_device tmu3_device = {
206}; 242};
207 243
208static struct sh_timer_config tmu4_platform_data = { 244static struct sh_timer_config tmu4_platform_data = {
209 .name = "TMU4",
210 .channel_offset = 0x10, 245 .channel_offset = 0x10,
211 .timer_bit = 1, 246 .timer_bit = 1,
212 .clk = "peripheral_clk",
213}; 247};
214 248
215static struct resource tmu4_resources[] = { 249static struct resource tmu4_resources[] = {
216 [0] = { 250 [0] = {
217 .name = "TMU4",
218 .start = 0xffda0014, 251 .start = 0xffda0014,
219 .end = 0xffda001f, 252 .end = 0xffda001f,
220 .flags = IORESOURCE_MEM, 253 .flags = IORESOURCE_MEM,
@@ -236,15 +269,12 @@ static struct platform_device tmu4_device = {
236}; 269};
237 270
238static struct sh_timer_config tmu5_platform_data = { 271static struct sh_timer_config tmu5_platform_data = {
239 .name = "TMU5",
240 .channel_offset = 0x1c, 272 .channel_offset = 0x1c,
241 .timer_bit = 2, 273 .timer_bit = 2,
242 .clk = "peripheral_clk",
243}; 274};
244 275
245static struct resource tmu5_resources[] = { 276static struct resource tmu5_resources[] = {
246 [0] = { 277 [0] = {
247 .name = "TMU5",
248 .start = 0xffda0020, 278 .start = 0xffda0020,
249 .end = 0xffda002b, 279 .end = 0xffda002b,
250 .flags = IORESOURCE_MEM, 280 .flags = IORESOURCE_MEM,
@@ -266,15 +296,12 @@ static struct platform_device tmu5_device = {
266}; 296};
267 297
268static struct sh_timer_config tmu6_platform_data = { 298static struct sh_timer_config tmu6_platform_data = {
269 .name = "TMU6",
270 .channel_offset = 0x04, 299 .channel_offset = 0x04,
271 .timer_bit = 0, 300 .timer_bit = 0,
272 .clk = "peripheral_clk",
273}; 301};
274 302
275static struct resource tmu6_resources[] = { 303static struct resource tmu6_resources[] = {
276 [0] = { 304 [0] = {
277 .name = "TMU6",
278 .start = 0xffdc0008, 305 .start = 0xffdc0008,
279 .end = 0xffdc0013, 306 .end = 0xffdc0013,
280 .flags = IORESOURCE_MEM, 307 .flags = IORESOURCE_MEM,
@@ -296,15 +323,12 @@ static struct platform_device tmu6_device = {
296}; 323};
297 324
298static struct sh_timer_config tmu7_platform_data = { 325static struct sh_timer_config tmu7_platform_data = {
299 .name = "TMU7",
300 .channel_offset = 0x10, 326 .channel_offset = 0x10,
301 .timer_bit = 1, 327 .timer_bit = 1,
302 .clk = "peripheral_clk",
303}; 328};
304 329
305static struct resource tmu7_resources[] = { 330static struct resource tmu7_resources[] = {
306 [0] = { 331 [0] = {
307 .name = "TMU7",
308 .start = 0xffdc0014, 332 .start = 0xffdc0014,
309 .end = 0xffdc001f, 333 .end = 0xffdc001f,
310 .flags = IORESOURCE_MEM, 334 .flags = IORESOURCE_MEM,
@@ -326,15 +350,12 @@ static struct platform_device tmu7_device = {
326}; 350};
327 351
328static struct sh_timer_config tmu8_platform_data = { 352static struct sh_timer_config tmu8_platform_data = {
329 .name = "TMU8",
330 .channel_offset = 0x1c, 353 .channel_offset = 0x1c,
331 .timer_bit = 2, 354 .timer_bit = 2,
332 .clk = "peripheral_clk",
333}; 355};
334 356
335static struct resource tmu8_resources[] = { 357static struct resource tmu8_resources[] = {
336 [0] = { 358 [0] = {
337 .name = "TMU8",
338 .start = 0xffdc0020, 359 .start = 0xffdc0020,
339 .end = 0xffdc002b, 360 .end = 0xffdc002b,
340 .flags = IORESOURCE_MEM, 361 .flags = IORESOURCE_MEM,
@@ -356,15 +377,12 @@ static struct platform_device tmu8_device = {
356}; 377};
357 378
358static struct sh_timer_config tmu9_platform_data = { 379static struct sh_timer_config tmu9_platform_data = {
359 .name = "TMU9",
360 .channel_offset = 0x04, 380 .channel_offset = 0x04,
361 .timer_bit = 0, 381 .timer_bit = 0,
362 .clk = "peripheral_clk",
363}; 382};
364 383
365static struct resource tmu9_resources[] = { 384static struct resource tmu9_resources[] = {
366 [0] = { 385 [0] = {
367 .name = "TMU9",
368 .start = 0xffde0008, 386 .start = 0xffde0008,
369 .end = 0xffde0013, 387 .end = 0xffde0013,
370 .flags = IORESOURCE_MEM, 388 .flags = IORESOURCE_MEM,
@@ -386,15 +404,12 @@ static struct platform_device tmu9_device = {
386}; 404};
387 405
388static struct sh_timer_config tmu10_platform_data = { 406static struct sh_timer_config tmu10_platform_data = {
389 .name = "TMU10",
390 .channel_offset = 0x10, 407 .channel_offset = 0x10,
391 .timer_bit = 1, 408 .timer_bit = 1,
392 .clk = "peripheral_clk",
393}; 409};
394 410
395static struct resource tmu10_resources[] = { 411static struct resource tmu10_resources[] = {
396 [0] = { 412 [0] = {
397 .name = "TMU10",
398 .start = 0xffde0014, 413 .start = 0xffde0014,
399 .end = 0xffde001f, 414 .end = 0xffde001f,
400 .flags = IORESOURCE_MEM, 415 .flags = IORESOURCE_MEM,
@@ -416,15 +431,12 @@ static struct platform_device tmu10_device = {
416}; 431};
417 432
418static struct sh_timer_config tmu11_platform_data = { 433static struct sh_timer_config tmu11_platform_data = {
419 .name = "TMU11",
420 .channel_offset = 0x1c, 434 .channel_offset = 0x1c,
421 .timer_bit = 2, 435 .timer_bit = 2,
422 .clk = "peripheral_clk",
423}; 436};
424 437
425static struct resource tmu11_resources[] = { 438static struct resource tmu11_resources[] = {
426 [0] = { 439 [0] = {
427 .name = "TMU11",
428 .start = 0xffde0020, 440 .start = 0xffde0020,
429 .end = 0xffde002b, 441 .end = 0xffde002b,
430 .flags = IORESOURCE_MEM, 442 .flags = IORESOURCE_MEM,
@@ -445,10 +457,114 @@ static struct platform_device tmu11_device = {
445 .num_resources = ARRAY_SIZE(tmu11_resources), 457 .num_resources = ARRAY_SIZE(tmu11_resources),
446}; 458};
447 459
460static const struct sh_dmae_channel dmac0_channels[] = {
461 {
462 .offset = 0,
463 .dmars = 0,
464 .dmars_bit = 0,
465 }, {
466 .offset = 0x10,
467 .dmars = 0,
468 .dmars_bit = 8,
469 }, {
470 .offset = 0x20,
471 .dmars = 4,
472 .dmars_bit = 0,
473 }, {
474 .offset = 0x30,
475 .dmars = 4,
476 .dmars_bit = 8,
477 }, {
478 .offset = 0x50,
479 .dmars = 8,
480 .dmars_bit = 0,
481 }, {
482 .offset = 0x60,
483 .dmars = 8,
484 .dmars_bit = 8,
485 }
486};
487
488static const unsigned int ts_shift[] = TS_SHIFT;
489
490static struct sh_dmae_pdata dma0_platform_data = {
491 .channel = dmac0_channels,
492 .channel_num = ARRAY_SIZE(dmac0_channels),
493 .ts_low_shift = CHCR_TS_LOW_SHIFT,
494 .ts_low_mask = CHCR_TS_LOW_MASK,
495 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
496 .ts_high_mask = CHCR_TS_HIGH_MASK,
497 .ts_shift = ts_shift,
498 .ts_shift_num = ARRAY_SIZE(ts_shift),
499 .dmaor_init = DMAOR_INIT,
500};
501
502/* Resource order important! */
503static struct resource dmac0_resources[] = {
504 {
505 /* Channel registers and DMAOR */
506 .start = 0xfe008020,
507 .end = 0xfe00808f,
508 .flags = IORESOURCE_MEM,
509 }, {
510 /* DMARSx */
511 .start = 0xfe009000,
512 .end = 0xfe00900b,
513 .flags = IORESOURCE_MEM,
514 }, {
515 /* DMA error IRQ */
516 .start = evt2irq(0x5c0),
517 .end = evt2irq(0x5c0),
518 .flags = IORESOURCE_IRQ,
519 }, {
520 /* IRQ for channels 0-5 */
521 .start = evt2irq(0x500),
522 .end = evt2irq(0x5a0),
523 .flags = IORESOURCE_IRQ,
524 },
525};
526
527static struct platform_device dma0_device = {
528 .name = "sh-dma-engine",
529 .id = 0,
530 .resource = dmac0_resources,
531 .num_resources = ARRAY_SIZE(dmac0_resources),
532 .dev = {
533 .platform_data = &dma0_platform_data,
534 },
535};
536
537#define USB_EHCI_START 0xffe70000
538#define USB_OHCI_START 0xffe70400
539
540static struct resource usb_ehci_resources[] = {
541 [0] = {
542 .start = USB_EHCI_START,
543 .end = USB_EHCI_START + 0x3ff,
544 .flags = IORESOURCE_MEM,
545 },
546 [1] = {
547 .start = 77,
548 .end = 77,
549 .flags = IORESOURCE_IRQ,
550 },
551};
552
553static struct platform_device usb_ehci_device = {
554 .name = "sh_ehci",
555 .id = -1,
556 .dev = {
557 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
558 .coherent_dma_mask = DMA_BIT_MASK(32),
559 },
560 .num_resources = ARRAY_SIZE(usb_ehci_resources),
561 .resource = usb_ehci_resources,
562};
563
448static struct resource usb_ohci_resources[] = { 564static struct resource usb_ohci_resources[] = {
449 [0] = { 565 [0] = {
450 .start = 0xffe70400, 566 .start = USB_OHCI_START,
451 .end = 0xffe704ff, 567 .end = USB_OHCI_START + 0x3ff,
452 .flags = IORESOURCE_MEM, 568 .flags = IORESOURCE_MEM,
453 }, 569 },
454 [1] = { 570 [1] = {
@@ -458,12 +574,11 @@ static struct resource usb_ohci_resources[] = {
458 }, 574 },
459}; 575};
460 576
461static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
462static struct platform_device usb_ohci_device = { 577static struct platform_device usb_ohci_device = {
463 .name = "sh_ohci", 578 .name = "sh_ohci",
464 .id = -1, 579 .id = -1,
465 .dev = { 580 .dev = {
466 .dma_mask = &usb_ohci_dma_mask, 581 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
467 .coherent_dma_mask = DMA_BIT_MASK(32), 582 .coherent_dma_mask = DMA_BIT_MASK(32),
468 }, 583 },
469 .num_resources = ARRAY_SIZE(usb_ohci_resources), 584 .num_resources = ARRAY_SIZE(usb_ohci_resources),
@@ -471,6 +586,12 @@ static struct platform_device usb_ohci_device = {
471}; 586};
472 587
473static struct platform_device *sh7786_early_devices[] __initdata = { 588static struct platform_device *sh7786_early_devices[] __initdata = {
589 &scif0_device,
590 &scif1_device,
591 &scif2_device,
592 &scif3_device,
593 &scif4_device,
594 &scif5_device,
474 &tmu0_device, 595 &tmu0_device,
475 &tmu1_device, 596 &tmu1_device,
476 &tmu2_device, 597 &tmu2_device,
@@ -486,11 +607,11 @@ static struct platform_device *sh7786_early_devices[] __initdata = {
486}; 607};
487 608
488static struct platform_device *sh7786_devices[] __initdata = { 609static struct platform_device *sh7786_devices[] __initdata = {
489 &sci_device, 610 &dma0_device,
611 &usb_ehci_device,
490 &usb_ohci_device, 612 &usb_ohci_device,
491}; 613};
492 614
493
494/* 615/*
495 * Please call this function if your platform board 616 * Please call this function if your platform board
496 * use external clock for USB 617 * use external clock for USB
@@ -498,6 +619,7 @@ static struct platform_device *sh7786_devices[] __initdata = {
498#define USBCTL0 0xffe70858 619#define USBCTL0 0xffe70858
499#define CLOCK_MODE_MASK 0xffffff7f 620#define CLOCK_MODE_MASK 0xffffff7f
500#define EXT_CLOCK_MODE 0x00000080 621#define EXT_CLOCK_MODE 0x00000080
622
501void __init sh7786_usb_use_exclock(void) 623void __init sh7786_usb_use_exclock(void)
502{ 624{
503 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK; 625 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
@@ -515,6 +637,7 @@ void __init sh7786_usb_use_exclock(void)
515#define PLL_ENB 0x00000002 637#define PLL_ENB 0x00000002
516#define PHY_RST 0x00000004 638#define PHY_RST 0x00000004
517#define ACT_PLL_STATUS 0xc0000000 639#define ACT_PLL_STATUS 0xc0000000
640
518static void __init sh7786_usb_setup(void) 641static void __init sh7786_usb_setup(void)
519{ 642{
520 int i = 1000000; 643 int i = 1000000;
@@ -545,33 +668,10 @@ static void __init sh7786_usb_setup(void)
545 } 668 }
546} 669}
547 670
548static int __init sh7786_devices_setup(void)
549{
550 int ret;
551
552 sh7786_usb_setup();
553
554 ret = platform_add_devices(sh7786_early_devices,
555 ARRAY_SIZE(sh7786_early_devices));
556 if (unlikely(ret != 0))
557 return ret;
558
559 return platform_add_devices(sh7786_devices,
560 ARRAY_SIZE(sh7786_devices));
561}
562device_initcall(sh7786_devices_setup);
563
564void __init plat_early_device_setup(void)
565{
566 early_platform_add_devices(sh7786_early_devices,
567 ARRAY_SIZE(sh7786_early_devices));
568}
569
570enum { 671enum {
571 UNUSED = 0, 672 UNUSED = 0,
572 673
573 /* interrupt sources */ 674 /* interrupt sources */
574
575 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 675 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
576 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 676 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
577 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 677 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
@@ -609,9 +709,12 @@ enum {
609 Thermal, 709 Thermal,
610 INTICI0, INTICI1, INTICI2, INTICI3, 710 INTICI0, INTICI1, INTICI2, INTICI3,
611 INTICI4, INTICI5, INTICI6, INTICI7, 711 INTICI4, INTICI5, INTICI6, INTICI7,
712
713 /* Muxed sub-events */
714 TXI1, BRI1, RXI1, ERI1,
612}; 715};
613 716
614static struct intc_vect vectors[] __initdata = { 717static struct intc_vect sh7786_vectors[] __initdata = {
615 INTC_VECT(WDT, 0x3e0), 718 INTC_VECT(WDT, 0x3e0),
616 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420), 719 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
617 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460), 720 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
@@ -670,9 +773,17 @@ static struct intc_vect vectors[] __initdata = {
670#define INTMSK2 0xfe410068 773#define INTMSK2 0xfe410068
671#define INTMSKCLR2 0xfe41006c 774#define INTMSKCLR2 0xfe41006c
672 775
673static struct intc_mask_reg mask_registers[] __initdata = { 776#define INTDISTCR0 0xfe4100b0
777#define INTDISTCR1 0xfe4100b4
778#define INT2DISTCR0 0xfe410900
779#define INT2DISTCR1 0xfe410904
780#define INT2DISTCR2 0xfe410908
781#define INT2DISTCR3 0xfe41090c
782
783static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
674 { CnINTMSK0, CnINTMSKCLR0, 32, 784 { CnINTMSK0, CnINTMSKCLR0, 32,
675 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 785 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
786 INTC_SMP_BALANCING(INTDISTCR0) },
676 { INTMSK2, INTMSKCLR2, 32, 787 { INTMSK2, INTMSKCLR2, 32,
677 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 788 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
678 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 789 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
@@ -684,7 +795,8 @@ static struct intc_mask_reg mask_registers[] __initdata = {
684 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, 795 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
685 { CnINT2MSKR0, CnINT2MSKCR0 , 32, 796 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
686 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 797 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
687 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } }, 798 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
799 INTC_SMP_BALANCING(INT2DISTCR0) },
688 { CnINT2MSKR1, CnINT2MSKCR1, 32, 800 { CnINT2MSKR1, CnINT2MSKCR1, 32,
689 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0, 801 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
690 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6, 802 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
@@ -693,14 +805,14 @@ static struct intc_mask_reg mask_registers[] __initdata = {
693 HPB_0, HPB_1, HPB_2, 805 HPB_0, HPB_1, HPB_2,
694 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3, 806 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
695 SCIF1, 807 SCIF1,
696 TMU2, TMU3, 0, } }, 808 TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
697 { CnINT2MSKR2, CnINT2MSKCR2, 32, 809 { CnINT2MSKR2, CnINT2MSKCR2, 32,
698 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5, 810 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
699 Eth_0, Eth_1, 811 Eth_0, Eth_1,
700 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 812 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
701 PCIeC0_0, PCIeC0_1, PCIeC0_2, 813 PCIeC0_0, PCIeC0_1, PCIeC0_2,
702 PCIeC1_0, PCIeC1_1, PCIeC1_2, 814 PCIeC1_0, PCIeC1_1, PCIeC1_2,
703 USB, 0, 0 } }, 815 USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
704 { CnINT2MSKR3, CnINT2MSKCR3, 32, 816 { CnINT2MSKR3, CnINT2MSKCR3, 32,
705 { 0, 0, 0, 0, 0, 0, 817 { 0, 0, 0, 0, 0, 0,
706 I2C0, I2C1, 818 I2C0, I2C1,
@@ -709,10 +821,10 @@ static struct intc_mask_reg mask_registers[] __initdata = {
709 HAC0, HAC1, 821 HAC0, HAC1,
710 FLCTL, 0, 822 FLCTL, 0,
711 HSPI, GPIO0, GPIO1, Thermal, 823 HSPI, GPIO0, GPIO1, Thermal,
712 0, 0, 0, 0, 0, 0, 0, 0 } }, 824 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
713}; 825};
714 826
715static struct intc_prio_reg prio_registers[] __initdata = { 827static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
716 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 828 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
717 IRQ4, IRQ5, IRQ6, IRQ7 } }, 829 IRQ4, IRQ5, IRQ6, IRQ7 } },
718 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } }, 830 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
@@ -756,11 +868,27 @@ static struct intc_prio_reg prio_registers[] __initdata = {
756 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) }, 868 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
757}; 869};
758 870
759static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL, 871static struct intc_subgroup sh7786_subgroups[] __initdata = {
760 mask_registers, prio_registers, NULL); 872 { 0xfe410c20, 32, SCIF1,
873 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
874 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
875};
761 876
762/* Support for external interrupt pins in IRQ mode */ 877static struct intc_desc sh7786_intc_desc __initdata = {
878 .name = "sh7786",
879 .hw = {
880 .vectors = sh7786_vectors,
881 .nr_vectors = ARRAY_SIZE(sh7786_vectors),
882 .mask_regs = sh7786_mask_registers,
883 .nr_mask_regs = ARRAY_SIZE(sh7786_mask_registers),
884 .subgroups = sh7786_subgroups,
885 .nr_subgroups = ARRAY_SIZE(sh7786_subgroups),
886 .prio_regs = sh7786_prio_registers,
887 .nr_prio_regs = ARRAY_SIZE(sh7786_prio_registers),
888 },
889};
763 890
891/* Support for external interrupt pins in IRQ mode */
764static struct intc_vect vectors_irq0123[] __initdata = { 892static struct intc_vect vectors_irq0123[] __initdata = {
765 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240), 893 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
766 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0), 894 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
@@ -771,23 +899,25 @@ static struct intc_vect vectors_irq4567[] __initdata = {
771 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0), 899 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
772}; 900};
773 901
774static struct intc_sense_reg sense_registers[] __initdata = { 902static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
775 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 903 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
776 IRQ4, IRQ5, IRQ6, IRQ7 } }, 904 IRQ4, IRQ5, IRQ6, IRQ7 } },
777}; 905};
778 906
779static struct intc_mask_reg ack_registers[] __initdata = { 907static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
780 { 0xfe410024, 0, 32, /* INTREQ */ 908 { 0xfe410024, 0, 32, /* INTREQ */
781 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 909 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
782}; 910};
783 911
784static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123", 912static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
785 vectors_irq0123, NULL, mask_registers, 913 vectors_irq0123, NULL, sh7786_mask_registers,
786 prio_registers, sense_registers, ack_registers); 914 sh7786_prio_registers, sh7786_sense_registers,
915 sh7786_ack_registers);
787 916
788static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567", 917static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
789 vectors_irq4567, NULL, mask_registers, 918 vectors_irq4567, NULL, sh7786_mask_registers,
790 prio_registers, sense_registers, ack_registers); 919 sh7786_prio_registers, sh7786_sense_registers,
920 sh7786_ack_registers);
791 921
792/* External interrupt pins in IRL mode */ 922/* External interrupt pins in IRL mode */
793 923
@@ -814,10 +944,10 @@ static struct intc_vect vectors_irl4567[] __initdata = {
814}; 944};
815 945
816static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123, 946static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
817 NULL, mask_registers, NULL, NULL); 947 NULL, sh7786_mask_registers, NULL, NULL);
818 948
819static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567, 949static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
820 NULL, mask_registers, NULL, NULL); 950 NULL, sh7786_mask_registers, NULL, NULL);
821 951
822#define INTC_ICR0 0xfe410000 952#define INTC_ICR0 0xfe410000
823#define INTC_INTMSK0 CnINTMSK0 953#define INTC_INTMSK0 CnINTMSK0
@@ -829,16 +959,16 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
829void __init plat_irq_setup(void) 959void __init plat_irq_setup(void)
830{ 960{
831 /* disable IRQ3-0 + IRQ7-4 */ 961 /* disable IRQ3-0 + IRQ7-4 */
832 ctrl_outl(0xff000000, INTC_INTMSK0); 962 __raw_writel(0xff000000, INTC_INTMSK0);
833 963
834 /* disable IRL3-0 + IRL7-4 */ 964 /* disable IRL3-0 + IRL7-4 */
835 ctrl_outl(0xc0000000, INTC_INTMSK1); 965 __raw_writel(0xc0000000, INTC_INTMSK1);
836 ctrl_outl(0xfffefffe, INTC_INTMSK2); 966 __raw_writel(0xfffefffe, INTC_INTMSK2);
837 967
838 /* select IRL mode for IRL3-0 + IRL7-4 */ 968 /* select IRL mode for IRL3-0 + IRL7-4 */
839 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 969 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
840 970
841 register_intc_controller(&intc_desc); 971 register_intc_controller(&sh7786_intc_desc);
842} 972}
843 973
844void __init plat_irq_setup_pins(int mode) 974void __init plat_irq_setup_pins(int mode)
@@ -846,32 +976,32 @@ void __init plat_irq_setup_pins(int mode)
846 switch (mode) { 976 switch (mode) {
847 case IRQ_MODE_IRQ7654: 977 case IRQ_MODE_IRQ7654:
848 /* select IRQ mode for IRL7-4 */ 978 /* select IRQ mode for IRL7-4 */
849 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0); 979 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
850 register_intc_controller(&intc_desc_irq4567); 980 register_intc_controller(&intc_desc_irq4567);
851 break; 981 break;
852 case IRQ_MODE_IRQ3210: 982 case IRQ_MODE_IRQ3210:
853 /* select IRQ mode for IRL3-0 */ 983 /* select IRQ mode for IRL3-0 */
854 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0); 984 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
855 register_intc_controller(&intc_desc_irq0123); 985 register_intc_controller(&intc_desc_irq0123);
856 break; 986 break;
857 case IRQ_MODE_IRL7654: 987 case IRQ_MODE_IRL7654:
858 /* enable IRL7-4 but don't provide any masking */ 988 /* enable IRL7-4 but don't provide any masking */
859 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 989 __raw_writel(0x40000000, INTC_INTMSKCLR1);
860 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 990 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
861 break; 991 break;
862 case IRQ_MODE_IRL3210: 992 case IRQ_MODE_IRL3210:
863 /* enable IRL0-3 but don't provide any masking */ 993 /* enable IRL0-3 but don't provide any masking */
864 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 994 __raw_writel(0x80000000, INTC_INTMSKCLR1);
865 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 995 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
866 break; 996 break;
867 case IRQ_MODE_IRL7654_MASK: 997 case IRQ_MODE_IRL7654_MASK:
868 /* enable IRL7-4 and mask using cpu intc controller */ 998 /* enable IRL7-4 and mask using cpu intc controller */
869 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 999 __raw_writel(0x40000000, INTC_INTMSKCLR1);
870 register_intc_controller(&intc_desc_irl4567); 1000 register_intc_controller(&intc_desc_irl4567);
871 break; 1001 break;
872 case IRQ_MODE_IRL3210_MASK: 1002 case IRQ_MODE_IRL3210_MASK:
873 /* enable IRL0-3 and mask using cpu intc controller */ 1003 /* enable IRL0-3 and mask using cpu intc controller */
874 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 1004 __raw_writel(0x80000000, INTC_INTMSKCLR1);
875 register_intc_controller(&intc_desc_irl0123); 1005 register_intc_controller(&intc_desc_irl0123);
876 break; 1006 break;
877 default: 1007 default:
@@ -882,3 +1012,39 @@ void __init plat_irq_setup_pins(int mode)
882void __init plat_mem_setup(void) 1012void __init plat_mem_setup(void)
883{ 1013{
884} 1014}
1015
1016static int __init sh7786_devices_setup(void)
1017{
1018 int ret, irq;
1019
1020 sh7786_usb_setup();
1021
1022 /*
1023 * De-mux SCIF1 IRQs if possible
1024 */
1025 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
1026 if (irq > 0) {
1027 scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq;
1028 scif1_platform_data.irqs[SCIx_ERI_IRQ] =
1029 intc_irq_lookup(sh7786_intc_desc.name, ERI1);
1030 scif1_platform_data.irqs[SCIx_BRI_IRQ] =
1031 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
1032 scif1_platform_data.irqs[SCIx_RXI_IRQ] =
1033 intc_irq_lookup(sh7786_intc_desc.name, RXI1);
1034 }
1035
1036 ret = platform_add_devices(sh7786_early_devices,
1037 ARRAY_SIZE(sh7786_early_devices));
1038 if (unlikely(ret != 0))
1039 return ret;
1040
1041 return platform_add_devices(sh7786_devices,
1042 ARRAY_SIZE(sh7786_devices));
1043}
1044arch_initcall(sh7786_devices_setup);
1045
1046void __init plat_early_device_setup(void)
1047{
1048 early_platform_add_devices(sh7786_early_devices,
1049 ARRAY_SIZE(sh7786_early_devices));
1050}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 4a26cc304139..bb208806dc1a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH-X3 Prototype Setup 2 * SH-X3 Prototype Setup
3 * 3 *
4 * Copyright (C) 2007 - 2009 Paul Mundt 4 * Copyright (C) 2007 - 2010 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -12,62 +12,79 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/gpio.h>
15#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17#include <cpu/shx3.h>
16#include <asm/mmzone.h> 18#include <asm/mmzone.h>
17 19
18static struct plat_sci_port sci_platform_data[] = { 20/*
19 { 21 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
20 .mapbase = 0xffc30000, 22 * INTEVT values overlap with the FPU EXPEVT ones, requiring special
21 .flags = UPF_BOOT_AUTOCONF, 23 * demuxing in the exception dispatch path.
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 24 *
23 .scbrr_algo_id = SCBRR_ALGO_2, 25 * As this overlap is something that never should have made it in to
24 .type = PORT_SCIF, 26 * silicon in the first place, we just refuse to deal with the port at
25 .irqs = { 40, 41, 43, 42 }, 27 * all rather than adding infrastructure to hack around it.
26 }, { 28 */
27 .mapbase = 0xffc40000, 29static struct plat_sci_port scif0_platform_data = {
28 .flags = UPF_BOOT_AUTOCONF, 30 .mapbase = 0xffc30000,
29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 31 .flags = UPF_BOOT_AUTOCONF,
30 .scbrr_algo_id = SCBRR_ALGO_2, 32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
31 .type = PORT_SCIF, 33 .scbrr_algo_id = SCBRR_ALGO_2,
32 .irqs = { 44, 45, 47, 46 }, 34 .type = PORT_SCIF,
33 }, { 35 .irqs = { 40, 41, 43, 42 },
34 .mapbase = 0xffc50000, 36};
35 .flags = UPF_BOOT_AUTOCONF, 37
36 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 38static struct platform_device scif0_device = {
37 .scbrr_algo_id = SCBRR_ALGO_2, 39 .name = "sh-sci",
38 .type = PORT_SCIF, 40 .id = 0,
39 .irqs = { 48, 49, 51, 50 }, 41 .dev = {
40 }, { 42 .platform_data = &scif0_platform_data,
41 .mapbase = 0xffc60000, 43 },
42 .flags = UPF_BOOT_AUTOCONF, 44};
43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 45
44 .scbrr_algo_id = SCBRR_ALGO_2, 46static struct plat_sci_port scif1_platform_data = {
45 .type = PORT_SCIF, 47 .mapbase = 0xffc40000,
46 .irqs = { 52, 53, 55, 54 }, 48 .flags = UPF_BOOT_AUTOCONF,
47 }, { 49 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
48 .flags = 0, 50 .scbrr_algo_id = SCBRR_ALGO_2,
49 } 51 .type = PORT_SCIF,
52 .irqs = { 44, 45, 47, 46 },
53};
54
55static struct platform_device scif1_device = {
56 .name = "sh-sci",
57 .id = 1,
58 .dev = {
59 .platform_data = &scif1_platform_data,
60 },
61};
62
63static struct plat_sci_port scif2_platform_data = {
64 .mapbase = 0xffc60000,
65 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF,
69 .irqs = { 52, 53, 55, 54 },
50}; 70};
51 71
52static struct platform_device sci_device = { 72static struct platform_device scif2_device = {
53 .name = "sh-sci", 73 .name = "sh-sci",
54 .id = -1, 74 .id = 2,
55 .dev = { 75 .dev = {
56 .platform_data = sci_platform_data, 76 .platform_data = &scif2_platform_data,
57 }, 77 },
58}; 78};
59 79
60static struct sh_timer_config tmu0_platform_data = { 80static struct sh_timer_config tmu0_platform_data = {
61 .name = "TMU0",
62 .channel_offset = 0x04, 81 .channel_offset = 0x04,
63 .timer_bit = 0, 82 .timer_bit = 0,
64 .clk = "peripheral_clk",
65 .clockevent_rating = 200, 83 .clockevent_rating = 200,
66}; 84};
67 85
68static struct resource tmu0_resources[] = { 86static struct resource tmu0_resources[] = {
69 [0] = { 87 [0] = {
70 .name = "TMU0",
71 .start = 0xffc10008, 88 .start = 0xffc10008,
72 .end = 0xffc10013, 89 .end = 0xffc10013,
73 .flags = IORESOURCE_MEM, 90 .flags = IORESOURCE_MEM,
@@ -89,16 +106,13 @@ static struct platform_device tmu0_device = {
89}; 106};
90 107
91static struct sh_timer_config tmu1_platform_data = { 108static struct sh_timer_config tmu1_platform_data = {
92 .name = "TMU1",
93 .channel_offset = 0x10, 109 .channel_offset = 0x10,
94 .timer_bit = 1, 110 .timer_bit = 1,
95 .clk = "peripheral_clk",
96 .clocksource_rating = 200, 111 .clocksource_rating = 200,
97}; 112};
98 113
99static struct resource tmu1_resources[] = { 114static struct resource tmu1_resources[] = {
100 [0] = { 115 [0] = {
101 .name = "TMU1",
102 .start = 0xffc10014, 116 .start = 0xffc10014,
103 .end = 0xffc1001f, 117 .end = 0xffc1001f,
104 .flags = IORESOURCE_MEM, 118 .flags = IORESOURCE_MEM,
@@ -120,15 +134,12 @@ static struct platform_device tmu1_device = {
120}; 134};
121 135
122static struct sh_timer_config tmu2_platform_data = { 136static struct sh_timer_config tmu2_platform_data = {
123 .name = "TMU2",
124 .channel_offset = 0x1c, 137 .channel_offset = 0x1c,
125 .timer_bit = 2, 138 .timer_bit = 2,
126 .clk = "peripheral_clk",
127}; 139};
128 140
129static struct resource tmu2_resources[] = { 141static struct resource tmu2_resources[] = {
130 [0] = { 142 [0] = {
131 .name = "TMU2",
132 .start = 0xffc10020, 143 .start = 0xffc10020,
133 .end = 0xffc1002f, 144 .end = 0xffc1002f,
134 .flags = IORESOURCE_MEM, 145 .flags = IORESOURCE_MEM,
@@ -150,15 +161,12 @@ static struct platform_device tmu2_device = {
150}; 161};
151 162
152static struct sh_timer_config tmu3_platform_data = { 163static struct sh_timer_config tmu3_platform_data = {
153 .name = "TMU3",
154 .channel_offset = 0x04, 164 .channel_offset = 0x04,
155 .timer_bit = 0, 165 .timer_bit = 0,
156 .clk = "peripheral_clk",
157}; 166};
158 167
159static struct resource tmu3_resources[] = { 168static struct resource tmu3_resources[] = {
160 [0] = { 169 [0] = {
161 .name = "TMU3",
162 .start = 0xffc20008, 170 .start = 0xffc20008,
163 .end = 0xffc20013, 171 .end = 0xffc20013,
164 .flags = IORESOURCE_MEM, 172 .flags = IORESOURCE_MEM,
@@ -180,15 +188,12 @@ static struct platform_device tmu3_device = {
180}; 188};
181 189
182static struct sh_timer_config tmu4_platform_data = { 190static struct sh_timer_config tmu4_platform_data = {
183 .name = "TMU4",
184 .channel_offset = 0x10, 191 .channel_offset = 0x10,
185 .timer_bit = 1, 192 .timer_bit = 1,
186 .clk = "peripheral_clk",
187}; 193};
188 194
189static struct resource tmu4_resources[] = { 195static struct resource tmu4_resources[] = {
190 [0] = { 196 [0] = {
191 .name = "TMU4",
192 .start = 0xffc20014, 197 .start = 0xffc20014,
193 .end = 0xffc2001f, 198 .end = 0xffc2001f,
194 .flags = IORESOURCE_MEM, 199 .flags = IORESOURCE_MEM,
@@ -210,15 +215,12 @@ static struct platform_device tmu4_device = {
210}; 215};
211 216
212static struct sh_timer_config tmu5_platform_data = { 217static struct sh_timer_config tmu5_platform_data = {
213 .name = "TMU5",
214 .channel_offset = 0x1c, 218 .channel_offset = 0x1c,
215 .timer_bit = 2, 219 .timer_bit = 2,
216 .clk = "peripheral_clk",
217}; 220};
218 221
219static struct resource tmu5_resources[] = { 222static struct resource tmu5_resources[] = {
220 [0] = { 223 [0] = {
221 .name = "TMU5",
222 .start = 0xffc20020, 224 .start = 0xffc20020,
223 .end = 0xffc2002b, 225 .end = 0xffc2002b,
224 .flags = IORESOURCE_MEM, 226 .flags = IORESOURCE_MEM,
@@ -240,6 +242,9 @@ static struct platform_device tmu5_device = {
240}; 242};
241 243
242static struct platform_device *shx3_early_devices[] __initdata = { 244static struct platform_device *shx3_early_devices[] __initdata = {
245 &scif0_device,
246 &scif1_device,
247 &scif2_device,
243 &tmu0_device, 248 &tmu0_device,
244 &tmu1_device, 249 &tmu1_device,
245 &tmu2_device, 250 &tmu2_device,
@@ -248,23 +253,12 @@ static struct platform_device *shx3_early_devices[] __initdata = {
248 &tmu5_device, 253 &tmu5_device,
249}; 254};
250 255
251static struct platform_device *shx3_devices[] __initdata = {
252 &sci_device,
253};
254
255static int __init shx3_devices_setup(void) 256static int __init shx3_devices_setup(void)
256{ 257{
257 int ret; 258 return platform_add_devices(shx3_early_devices,
258
259 ret = platform_add_devices(shx3_early_devices,
260 ARRAY_SIZE(shx3_early_devices)); 259 ARRAY_SIZE(shx3_early_devices));
261 if (unlikely(ret != 0))
262 return ret;
263
264 return platform_add_devices(shx3_devices,
265 ARRAY_SIZE(shx3_devices));
266} 260}
267__initcall(shx3_devices_setup); 261arch_initcall(shx3_devices_setup);
268 262
269void __init plat_early_device_setup(void) 263void __init plat_early_device_setup(void)
270{ 264{
@@ -295,10 +289,7 @@ enum {
295 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9, 289 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
296 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE, 290 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
297 IIC, VIN0, VIN1, VCORE0, ATAPI, 291 IIC, VIN0, VIN1, VCORE0, ATAPI,
298 DTU0_TEND, DTU0_AE, DTU0_TMISS, 292 DTU0, DTU1, DTU2, DTU3,
299 DTU1_TEND, DTU1_AE, DTU1_TMISS,
300 DTU2_TEND, DTU2_AE, DTU2_TMISS,
301 DTU3_TEND, DTU3_AE, DTU3_TMISS,
302 FE0, FE1, 293 FE0, FE1,
303 GPIO0, GPIO1, GPIO2, GPIO3, 294 GPIO0, GPIO1, GPIO2, GPIO3,
304 PAM, IRM, 295 PAM, IRM,
@@ -307,7 +298,7 @@ enum {
307 298
308 /* interrupt groups */ 299 /* interrupt groups */
309 IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3, 300 IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
310 DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3, 301 DMAC0, DMAC1,
311}; 302};
312 303
313static struct intc_vect vectors[] __initdata = { 304static struct intc_vect vectors[] __initdata = {
@@ -324,8 +315,6 @@ static struct intc_vect vectors[] __initdata = {
324 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), 315 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
325 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0), 316 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
326 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0), 317 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
327 INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820),
328 INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860),
329 INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0), 318 INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
330 INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0), 319 INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
331 INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920), 320 INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
@@ -340,14 +329,14 @@ static struct intc_vect vectors[] __initdata = {
340 INTC_VECT(IIC, 0xae0), 329 INTC_VECT(IIC, 0xae0),
341 INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20), 330 INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
342 INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60), 331 INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
343 INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20), 332 INTC_VECT(DTU0, 0xc00), INTC_VECT(DTU0, 0xc20),
344 INTC_VECT(DTU0_TMISS, 0xc40), 333 INTC_VECT(DTU0, 0xc40),
345 INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80), 334 INTC_VECT(DTU1, 0xc60), INTC_VECT(DTU1, 0xc80),
346 INTC_VECT(DTU1_TMISS, 0xca0), 335 INTC_VECT(DTU1, 0xca0),
347 INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0), 336 INTC_VECT(DTU2, 0xcc0), INTC_VECT(DTU2, 0xce0),
348 INTC_VECT(DTU2_TMISS, 0xd00), 337 INTC_VECT(DTU2, 0xd00),
349 INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40), 338 INTC_VECT(DTU3, 0xd20), INTC_VECT(DTU3, 0xd40),
350 INTC_VECT(DTU3_TMISS, 0xd60), 339 INTC_VECT(DTU3, 0xd60),
351 INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20), 340 INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
352 INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60), 341 INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
353 INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0), 342 INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
@@ -366,18 +355,17 @@ static struct intc_group groups[] __initdata = {
366 INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9), 355 INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
367 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), 356 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
368 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), 357 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
369 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
370 INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI), 358 INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI),
371 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, 359 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
372 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE), 360 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
373 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, 361 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
374 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11), 362 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
375 INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS),
376 INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS),
377 INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS),
378 INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
379}; 363};
380 364
365#define INT2DISTCR0 0xfe4108a0
366#define INT2DISTCR1 0xfe4108a4
367#define INT2DISTCR2 0xfe4108a8
368
381static struct intc_mask_reg mask_registers[] __initdata = { 369static struct intc_mask_reg mask_registers[] __initdata = {
382 { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */ 370 { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
383 { IRQ0, IRQ1, IRQ2, IRQ3 } }, 371 { IRQ0, IRQ1, IRQ2, IRQ3 } },
@@ -387,20 +375,23 @@ static struct intc_mask_reg mask_registers[] __initdata = {
387 { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC, 375 { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
388 DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0, 376 DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
389 0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */ 377 0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
390 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } }, 378 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, },
379 INTC_SMP_BALANCING(INT2DISTCR0) },
391 { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */ 380 { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
392 { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */ 381 { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
393 PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2, 382 PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
394 PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11, 383 PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
395 DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7, 384 DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
396 DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4, 385 DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
397 DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } }, 386 DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 },
387 INTC_SMP_BALANCING(INT2DISTCR1) },
398 { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */ 388 { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
399 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 389 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
400 SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI, 390 SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
401 SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI, 391 SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
402 SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI, 392 SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
403 SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } }, 393 SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI },
394 INTC_SMP_BALANCING(INT2DISTCR2) },
404}; 395};
405 396
406static struct intc_prio_reg prio_registers[] __initdata = { 397static struct intc_prio_reg prio_registers[] __initdata = {
@@ -457,11 +448,33 @@ static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
457 448
458void __init plat_irq_setup_pins(int mode) 449void __init plat_irq_setup_pins(int mode)
459{ 450{
451 int ret = 0;
452
460 switch (mode) { 453 switch (mode) {
461 case IRQ_MODE_IRQ: 454 case IRQ_MODE_IRQ:
455 ret |= gpio_request(GPIO_FN_IRQ3, intc_desc_irq.name);
456 ret |= gpio_request(GPIO_FN_IRQ2, intc_desc_irq.name);
457 ret |= gpio_request(GPIO_FN_IRQ1, intc_desc_irq.name);
458 ret |= gpio_request(GPIO_FN_IRQ0, intc_desc_irq.name);
459
460 if (unlikely(ret)) {
461 pr_err("Failed to set IRQ mode\n");
462 return;
463 }
464
462 register_intc_controller(&intc_desc_irq); 465 register_intc_controller(&intc_desc_irq);
463 break; 466 break;
464 case IRQ_MODE_IRL3210: 467 case IRQ_MODE_IRL3210:
468 ret |= gpio_request(GPIO_FN_IRL3, intc_desc_irl.name);
469 ret |= gpio_request(GPIO_FN_IRL2, intc_desc_irl.name);
470 ret |= gpio_request(GPIO_FN_IRL1, intc_desc_irl.name);
471 ret |= gpio_request(GPIO_FN_IRL0, intc_desc_irl.name);
472
473 if (unlikely(ret)) {
474 pr_err("Failed to set IRL mode\n");
475 return;
476 }
477
465 register_intc_controller(&intc_desc_irl); 478 register_intc_controller(&intc_desc_irl);
466 break; 479 break;
467 default: 480 default:
@@ -471,6 +484,9 @@ void __init plat_irq_setup_pins(int mode)
471 484
472void __init plat_irq_setup(void) 485void __init plat_irq_setup(void)
473{ 486{
487 reserve_intc_vectors(vectors_irq, ARRAY_SIZE(vectors_irq));
488 reserve_intc_vectors(vectors_irl, ARRAY_SIZE(vectors_irl));
489
474 register_intc_controller(&intc_desc); 490 register_intc_controller(&intc_desc);
475} 491}
476 492
diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
index 2b6b0d50c576..de865cac02ee 100644
--- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH-X3 SMP 2 * SH-X3 SMP
3 * 3 *
4 * Copyright (C) 2007 - 2008 Paul Mundt 4 * Copyright (C) 2007 - 2010 Paul Mundt
5 * Copyright (C) 2007 Magnus Damm 5 * Copyright (C) 2007 Magnus Damm
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
@@ -9,10 +9,23 @@
9 * for more details. 9 * for more details.
10 */ 10 */
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/kernel.h>
12#include <linux/cpumask.h> 13#include <linux/cpumask.h>
13#include <linux/smp.h> 14#include <linux/smp.h>
14#include <linux/interrupt.h> 15#include <linux/interrupt.h>
15#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/sched.h>
18#include <linux/delay.h>
19#include <linux/cpu.h>
20#include <asm/sections.h>
21
22#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
23#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
24
25#define STBCR_MSTP 0x00000001
26#define STBCR_RESET 0x00000002
27#define STBCR_SLEEP 0x00000004
28#define STBCR_LTSLP 0x80000000
16 29
17static irqreturn_t ipi_interrupt_handler(int irq, void *arg) 30static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
18{ 31{
@@ -21,22 +34,25 @@ static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
21 unsigned int offs = 4 * cpu; 34 unsigned int offs = 4 * cpu;
22 unsigned int x; 35 unsigned int x;
23 36
24 x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */ 37 x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
25 x &= (1 << (message << 2)); 38 x &= (1 << (message << 2));
26 ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */ 39 __raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
27 40
28 smp_message_recv(message); 41 smp_message_recv(message);
29 42
30 return IRQ_HANDLED; 43 return IRQ_HANDLED;
31} 44}
32 45
33void __init plat_smp_setup(void) 46static void shx3_smp_setup(void)
34{ 47{
35 unsigned int cpu = 0; 48 unsigned int cpu = 0;
36 int i, num; 49 int i, num;
37 50
38 init_cpu_possible(cpumask_of(cpu)); 51 init_cpu_possible(cpumask_of(cpu));
39 52
53 /* Enable light sleep for the boot CPU */
54 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu));
55
40 __cpu_number_map[0] = 0; 56 __cpu_number_map[0] = 0;
41 __cpu_logical_map[0] = 0; 57 __cpu_logical_map[0] = 0;
42 58
@@ -53,50 +69,98 @@ void __init plat_smp_setup(void)
53 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); 69 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
54} 70}
55 71
56void __init plat_prepare_cpus(unsigned int max_cpus) 72static void shx3_prepare_cpus(unsigned int max_cpus)
57{ 73{
58 int i; 74 int i;
59 75
76 local_timer_setup(0);
77
60 BUILD_BUG_ON(SMP_MSG_NR >= 8); 78 BUILD_BUG_ON(SMP_MSG_NR >= 8);
61 79
62 for (i = 0; i < SMP_MSG_NR; i++) 80 for (i = 0; i < SMP_MSG_NR; i++)
63 request_irq(104 + i, ipi_interrupt_handler, IRQF_DISABLED, 81 request_irq(104 + i, ipi_interrupt_handler,
64 "IPI", (void *)(long)i); 82 IRQF_DISABLED | IRQF_PERCPU, "IPI", (void *)(long)i);
65}
66
67#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
68#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
69 83
70#define STBCR_MSTP 0x00000001 84 for (i = 0; i < max_cpus; i++)
71#define STBCR_RESET 0x00000002 85 set_cpu_present(i, true);
72#define STBCR_LTSLP 0x80000000 86}
73
74#define STBCR_AP_VAL (STBCR_RESET | STBCR_LTSLP)
75 87
76void plat_start_cpu(unsigned int cpu, unsigned long entry_point) 88static void shx3_start_cpu(unsigned int cpu, unsigned long entry_point)
77{ 89{
78 ctrl_outl(entry_point, RESET_REG(cpu)); 90 if (__in_29bit_mode())
91 __raw_writel(entry_point, RESET_REG(cpu));
92 else
93 __raw_writel(virt_to_phys(entry_point), RESET_REG(cpu));
79 94
80 if (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP)) 95 if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
81 ctrl_outl(STBCR_MSTP, STBCR_REG(cpu)); 96 __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
82 97
83 while (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP)) 98 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
84 cpu_relax(); 99 cpu_relax();
85 100
86 /* Start up secondary processor by sending a reset */ 101 /* Start up secondary processor by sending a reset */
87 ctrl_outl(STBCR_AP_VAL, STBCR_REG(cpu)); 102 __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu));
88} 103}
89 104
90int plat_smp_processor_id(void) 105static unsigned int shx3_smp_processor_id(void)
91{ 106{
92 return ctrl_inl(0xff000048); /* CPIDR */ 107 return __raw_readl(0xff000048); /* CPIDR */
93} 108}
94 109
95void plat_send_ipi(unsigned int cpu, unsigned int message) 110static void shx3_send_ipi(unsigned int cpu, unsigned int message)
96{ 111{
97 unsigned long addr = 0xfe410070 + (cpu * 4); 112 unsigned long addr = 0xfe410070 + (cpu * 4);
98 113
99 BUG_ON(cpu >= 4); 114 BUG_ON(cpu >= 4);
100 115
101 ctrl_outl(1 << (message << 2), addr); /* C0INTICI..CnINTICI */ 116 __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
117}
118
119static void shx3_update_boot_vector(unsigned int cpu)
120{
121 __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
122 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
123 cpu_relax();
124 __raw_writel(STBCR_RESET, STBCR_REG(cpu));
125}
126
127static int __cpuinit
128shx3_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
129{
130 unsigned int cpu = (unsigned int)hcpu;
131
132 switch (action) {
133 case CPU_UP_PREPARE:
134 shx3_update_boot_vector(cpu);
135 break;
136 case CPU_ONLINE:
137 pr_info("CPU %u is now online\n", cpu);
138 break;
139 case CPU_DEAD:
140 break;
141 }
142
143 return NOTIFY_OK;
144}
145
146static struct notifier_block __cpuinitdata shx3_cpu_notifier = {
147 .notifier_call = shx3_cpu_callback,
148};
149
150static int __cpuinit register_shx3_cpu_notifier(void)
151{
152 register_hotcpu_notifier(&shx3_cpu_notifier);
153 return 0;
102} 154}
155late_initcall(register_shx3_cpu_notifier);
156
157struct plat_smp_ops shx3_smp_ops = {
158 .smp_setup = shx3_smp_setup,
159 .prepare_cpus = shx3_prepare_cpus,
160 .start_cpu = shx3_start_cpu,
161 .smp_processor_id = shx3_smp_processor_id,
162 .send_ipi = shx3_send_ipi,
163 .cpu_die = native_cpu_die,
164 .cpu_disable = native_cpu_disable,
165 .play_dead = native_play_dead,
166};
diff --git a/arch/sh/kernel/cpu/sh4a/ubc.c b/arch/sh/kernel/cpu/sh4a/ubc.c
new file mode 100644
index 000000000000..efb2745bcb36
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/ubc.c
@@ -0,0 +1,133 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/ubc.c
3 *
4 * On-chip UBC support for SH-4A CPUs.
5 *
6 * Copyright (C) 2009 - 2010 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <asm/hw_breakpoint.h>
17
18#define UBC_CBR(idx) (0xff200000 + (0x20 * idx))
19#define UBC_CRR(idx) (0xff200004 + (0x20 * idx))
20#define UBC_CAR(idx) (0xff200008 + (0x20 * idx))
21#define UBC_CAMR(idx) (0xff20000c + (0x20 * idx))
22
23#define UBC_CCMFR 0xff200600
24#define UBC_CBCR 0xff200620
25
26/* CRR */
27#define UBC_CRR_PCB (1 << 1)
28#define UBC_CRR_BIE (1 << 0)
29
30/* CBR */
31#define UBC_CBR_CE (1 << 0)
32
33static struct sh_ubc sh4a_ubc;
34
35static void sh4a_ubc_enable(struct arch_hw_breakpoint *info, int idx)
36{
37 __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx));
38 __raw_writel(info->address, UBC_CAR(idx));
39}
40
41static void sh4a_ubc_disable(struct arch_hw_breakpoint *info, int idx)
42{
43 __raw_writel(0, UBC_CBR(idx));
44 __raw_writel(0, UBC_CAR(idx));
45}
46
47static void sh4a_ubc_enable_all(unsigned long mask)
48{
49 int i;
50
51 for (i = 0; i < sh4a_ubc.num_events; i++)
52 if (mask & (1 << i))
53 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE,
54 UBC_CBR(i));
55}
56
57static void sh4a_ubc_disable_all(void)
58{
59 int i;
60
61 for (i = 0; i < sh4a_ubc.num_events; i++)
62 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE,
63 UBC_CBR(i));
64}
65
66static unsigned long sh4a_ubc_active_mask(void)
67{
68 unsigned long active = 0;
69 int i;
70
71 for (i = 0; i < sh4a_ubc.num_events; i++)
72 if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE)
73 active |= (1 << i);
74
75 return active;
76}
77
78static unsigned long sh4a_ubc_triggered_mask(void)
79{
80 return __raw_readl(UBC_CCMFR);
81}
82
83static void sh4a_ubc_clear_triggered_mask(unsigned long mask)
84{
85 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR);
86}
87
88static struct sh_ubc sh4a_ubc = {
89 .name = "SH-4A",
90 .num_events = 2,
91 .trap_nr = 0x1e0,
92 .enable = sh4a_ubc_enable,
93 .disable = sh4a_ubc_disable,
94 .enable_all = sh4a_ubc_enable_all,
95 .disable_all = sh4a_ubc_disable_all,
96 .active_mask = sh4a_ubc_active_mask,
97 .triggered_mask = sh4a_ubc_triggered_mask,
98 .clear_triggered_mask = sh4a_ubc_clear_triggered_mask,
99};
100
101static int __init sh4a_ubc_init(void)
102{
103 struct clk *ubc_iclk = clk_get(NULL, "ubc0");
104 int i;
105
106 /*
107 * The UBC MSTP bit is optional, as not all platforms will have
108 * it. Just ignore it if we can't find it.
109 */
110 if (IS_ERR(ubc_iclk))
111 ubc_iclk = NULL;
112
113 clk_enable(ubc_iclk);
114
115 __raw_writel(0, UBC_CBCR);
116
117 for (i = 0; i < sh4a_ubc.num_events; i++) {
118 __raw_writel(0, UBC_CAMR(i));
119 __raw_writel(0, UBC_CBR(i));
120
121 __raw_writel(UBC_CRR_BIE | UBC_CRR_PCB, UBC_CRR(i));
122
123 /* dummy read for write posting */
124 (void)__raw_readl(UBC_CRR(i));
125 }
126
127 clk_disable(ubc_iclk);
128
129 sh4a_ubc.clk = ubc_iclk;
130
131 return register_sh_ubc(&sh4a_ubc);
132}
133arch_initcall(sh4a_ubc_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 06:01:58 -0500