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authorJames Morris <jmorris@namei.org>2009-03-26 17:28:11 -0400
committerJames Morris <jmorris@namei.org>2009-03-26 17:28:11 -0400
commit1987f17d2266e882862528841429b5bf67bc8fe5 (patch)
tree5c3fbee88018ab7259a18c10e6320e575d0ed679 /arch/sh/kernel/cpu/sh4a
parent7198e2eeb44b3fe7cc97f997824002da47a9c644 (diff)
parent0384e2959127a56d0640505d004d8dd92f9c29f5 (diff)
Merge branch 'master' into next
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a')
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile3
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c148
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c950
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c114
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c97
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c95
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c490
11 files changed, 1827 insertions, 206 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 8e344ec5847e..1a92361feeb9 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
7obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o 7obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
8obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o 8obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
@@ -21,6 +22,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o
21clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o 22clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
22clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o 23clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
23clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o 24clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
25clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
24clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o 26clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o
25clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 27clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
26clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o
@@ -31,6 +33,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
31pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o 33pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
32pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o 34pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
33pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 35pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
36pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
34 37
35obj-y += $(clock-y) 38obj-y += $(clock-y)
36obj-$(CONFIG_SMP) += $(smp-y) 39obj-$(CONFIG_SMP) += $(smp-y)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
new file mode 100644
index 000000000000..f84a9c134471
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -0,0 +1,148 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
3 *
4 * SH7786 support for the clock framework
5 *
6 * Copyright (C) 2008, 2009 Renesas Solutions Corp.
7 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 *
9 * Based on SH7785
10 * Copyright (C) 2007 Paul Mundt
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <asm/clock.h>
19#include <asm/freq.h>
20#include <asm/io.h>
21
22static int ifc_divisors[] = { 1, 2, 4, 1 };
23static int sfc_divisors[] = { 1, 1, 4, 1 };
24static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
25 24, 32, 1, 1, 1, 1, 1, 1 };
26static int mfc_divisors[] = { 1, 1, 4, 1 };
27static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
28 24, 32, 1, 48, 1, 1, 1, 1 };
29
30static void master_clk_init(struct clk *clk)
31{
32 clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
33}
34
35static struct clk_ops sh7786_master_clk_ops = {
36 .init = master_clk_init,
37};
38
39static void module_clk_recalc(struct clk *clk)
40{
41 int idx = (ctrl_inl(FRQMR1) & 0x000f);
42 clk->rate = clk->parent->rate / pfc_divisors[idx];
43}
44
45static struct clk_ops sh7786_module_clk_ops = {
46 .recalc = module_clk_recalc,
47};
48
49static void bus_clk_recalc(struct clk *clk)
50{
51 int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
52 clk->rate = clk->parent->rate / bfc_divisors[idx];
53}
54
55static struct clk_ops sh7786_bus_clk_ops = {
56 .recalc = bus_clk_recalc,
57};
58
59static void cpu_clk_recalc(struct clk *clk)
60{
61 int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
62 clk->rate = clk->parent->rate / ifc_divisors[idx];
63}
64
65static struct clk_ops sh7786_cpu_clk_ops = {
66 .recalc = cpu_clk_recalc,
67};
68
69static struct clk_ops *sh7786_clk_ops[] = {
70 &sh7786_master_clk_ops,
71 &sh7786_module_clk_ops,
72 &sh7786_bus_clk_ops,
73 &sh7786_cpu_clk_ops,
74};
75
76void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
77{
78 if (idx < ARRAY_SIZE(sh7786_clk_ops))
79 *ops = sh7786_clk_ops[idx];
80}
81
82static void shyway_clk_recalc(struct clk *clk)
83{
84 int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
85 clk->rate = clk->parent->rate / sfc_divisors[idx];
86}
87
88static struct clk_ops sh7786_shyway_clk_ops = {
89 .recalc = shyway_clk_recalc,
90};
91
92static struct clk sh7786_shyway_clk = {
93 .name = "shyway_clk",
94 .flags = CLK_ALWAYS_ENABLED,
95 .ops = &sh7786_shyway_clk_ops,
96};
97
98static void ddr_clk_recalc(struct clk *clk)
99{
100 int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
101 clk->rate = clk->parent->rate / mfc_divisors[idx];
102}
103
104static struct clk_ops sh7786_ddr_clk_ops = {
105 .recalc = ddr_clk_recalc,
106};
107
108static struct clk sh7786_ddr_clk = {
109 .name = "ddr_clk",
110 .flags = CLK_ALWAYS_ENABLED,
111 .ops = &sh7786_ddr_clk_ops,
112};
113
114/*
115 * Additional SH7786-specific on-chip clocks that aren't already part of the
116 * clock framework
117 */
118static struct clk *sh7786_onchip_clocks[] = {
119 &sh7786_shyway_clk,
120 &sh7786_ddr_clk,
121};
122
123static int __init sh7786_clk_init(void)
124{
125 struct clk *clk = clk_get(NULL, "master_clk");
126 int i;
127
128 for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
129 struct clk *clkp = sh7786_onchip_clocks[i];
130
131 clkp->parent = clk;
132 clk_register(clkp);
133 clk_enable(clkp);
134 }
135
136 /*
137 * Now that we have the rest of the clocks registered, we need to
138 * force the parent clock to propagate so that these clocks will
139 * automatically figure out their rate. We cheat by handing the
140 * parent clock its current rate and forcing child propagation.
141 */
142 clk_set_rate(clk, clk_get_rate(clk));
143
144 clk_put(clk);
145
146 return 0;
147}
148arch_initcall(sh7786_clk_init);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
new file mode 100644
index 000000000000..373b3447bfdf
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
@@ -0,0 +1,950 @@
1/*
2 * SH7786 Pinmux
3 *
4 * Copyright (C) 2008, 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on SH7785 pinmux
8 *
9 * Copyright (C) 2008 Magnus Damm
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <cpu/sh7786.h>
20
21enum {
22 PINMUX_RESERVED = 0,
23
24 PINMUX_DATA_BEGIN,
25 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
26 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
27 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
28 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
29 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
30 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
31 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
32 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
33 PE7_DATA, PE6_DATA,
34 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
35 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
36 PG7_DATA, PG6_DATA, PG5_DATA,
37 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
38 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
39 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
40 PJ3_DATA, PJ2_DATA, PJ1_DATA,
41 PINMUX_DATA_END,
42
43 PINMUX_INPUT_BEGIN,
44 PA7_IN, PA6_IN, PA5_IN, PA4_IN,
45 PA3_IN, PA2_IN, PA1_IN, PA0_IN,
46 PB7_IN, PB6_IN, PB5_IN, PB4_IN,
47 PB3_IN, PB2_IN, PB1_IN, PB0_IN,
48 PC7_IN, PC6_IN, PC5_IN, PC4_IN,
49 PC3_IN, PC2_IN, PC1_IN, PC0_IN,
50 PD7_IN, PD6_IN, PD5_IN, PD4_IN,
51 PD3_IN, PD2_IN, PD1_IN, PD0_IN,
52 PE7_IN, PE6_IN,
53 PF7_IN, PF6_IN, PF5_IN, PF4_IN,
54 PF3_IN, PF2_IN, PF1_IN, PF0_IN,
55 PG7_IN, PG6_IN, PG5_IN,
56 PH7_IN, PH6_IN, PH5_IN, PH4_IN,
57 PH3_IN, PH2_IN, PH1_IN, PH0_IN,
58 PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
59 PJ3_IN, PJ2_IN, PJ1_IN,
60 PINMUX_INPUT_END,
61
62 PINMUX_INPUT_PULLUP_BEGIN,
63 PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
64 PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
65 PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
66 PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
67 PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
68 PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
69 PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
70 PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
71 PE7_IN_PU, PE6_IN_PU,
72 PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
73 PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
74 PG7_IN_PU, PG6_IN_PU, PG5_IN_PU,
75 PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU,
76 PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
77 PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU,
78 PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU,
79 PINMUX_INPUT_PULLUP_END,
80
81 PINMUX_OUTPUT_BEGIN,
82 PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
83 PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
84 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
85 PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
86 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
87 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
88 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
89 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
90 PE7_OUT, PE6_OUT,
91 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
92 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
93 PG7_OUT, PG6_OUT, PG5_OUT,
94 PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
95 PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
96 PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
97 PJ3_OUT, PJ2_OUT, PJ1_OUT,
98 PINMUX_OUTPUT_END,
99
100 PINMUX_FUNCTION_BEGIN,
101 PA7_FN, PA6_FN, PA5_FN, PA4_FN,
102 PA3_FN, PA2_FN, PA1_FN, PA0_FN,
103 PB7_FN, PB6_FN, PB5_FN, PB4_FN,
104 PB3_FN, PB2_FN, PB1_FN, PB0_FN,
105 PC7_FN, PC6_FN, PC5_FN, PC4_FN,
106 PC3_FN, PC2_FN, PC1_FN, PC0_FN,
107 PD7_FN, PD6_FN, PD5_FN, PD4_FN,
108 PD3_FN, PD2_FN, PD1_FN, PD0_FN,
109 PE7_FN, PE6_FN,
110 PF7_FN, PF6_FN, PF5_FN, PF4_FN,
111 PF3_FN, PF2_FN, PF1_FN, PF0_FN,
112 PG7_FN, PG6_FN, PG5_FN,
113 PH7_FN, PH6_FN, PH5_FN, PH4_FN,
114 PH3_FN, PH2_FN, PH1_FN, PH0_FN,
115 PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
116 PJ3_FN, PJ2_FN, PJ1_FN,
117 P1MSEL14_0, P1MSEL14_1,
118 P1MSEL13_0, P1MSEL13_1,
119 P1MSEL12_0, P1MSEL12_1,
120 P1MSEL11_0, P1MSEL11_1,
121 P1MSEL10_0, P1MSEL10_1,
122 P1MSEL9_0, P1MSEL9_1,
123 P1MSEL8_0, P1MSEL8_1,
124 P1MSEL7_0, P1MSEL7_1,
125 P1MSEL6_0, P1MSEL6_1,
126 P1MSEL5_0, P1MSEL5_1,
127 P1MSEL4_0, P1MSEL4_1,
128 P1MSEL3_0, P1MSEL3_1,
129 P1MSEL2_0, P1MSEL2_1,
130 P1MSEL1_0, P1MSEL1_1,
131 P1MSEL0_0, P1MSEL0_1,
132
133 P2MSEL15_0, P2MSEL15_1,
134 P2MSEL14_0, P2MSEL14_1,
135 P2MSEL13_0, P2MSEL13_1,
136 P2MSEL12_0, P2MSEL12_1,
137 P2MSEL11_0, P2MSEL11_1,
138 P2MSEL10_0, P2MSEL10_1,
139 P2MSEL9_0, P2MSEL9_1,
140 P2MSEL8_0, P2MSEL8_1,
141 P2MSEL7_0, P2MSEL7_1,
142 P2MSEL6_0, P2MSEL6_1,
143 P2MSEL5_0, P2MSEL5_1,
144 P2MSEL4_0, P2MSEL4_1,
145 P2MSEL3_0, P2MSEL3_1,
146 P2MSEL2_0, P2MSEL2_1,
147 P2MSEL1_0, P2MSEL1_1,
148 P2MSEL0_0, P2MSEL0_1,
149 PINMUX_FUNCTION_END,
150
151 PINMUX_MARK_BEGIN,
152 CDE_MARK,
153 ETH_MAGIC_MARK,
154 DISP_MARK,
155 ETH_LINK_MARK,
156 DR5_MARK,
157 ETH_TX_ER_MARK,
158 DR4_MARK,
159 ETH_TX_EN_MARK,
160 DR3_MARK,
161 ETH_TXD3_MARK,
162 DR2_MARK,
163 ETH_TXD2_MARK,
164 DR1_MARK,
165 ETH_TXD1_MARK,
166 DR0_MARK,
167 ETH_TXD0_MARK,
168
169 VSYNC_MARK,
170 HSPI_CLK_MARK,
171 ODDF_MARK,
172 HSPI_CS_MARK,
173 DG5_MARK,
174 ETH_MDIO_MARK,
175 DG4_MARK,
176 ETH_RX_CLK_MARK,
177 DG3_MARK,
178 ETH_MDC_MARK,
179 DG2_MARK,
180 ETH_COL_MARK,
181 DG1_MARK,
182 ETH_TX_CLK_MARK,
183 DG0_MARK,
184 ETH_CRS_MARK,
185
186 DCLKIN_MARK,
187 HSPI_RX_MARK,
188 HSYNC_MARK,
189 HSPI_TX_MARK,
190 DB5_MARK,
191 ETH_RXD3_MARK,
192 DB4_MARK,
193 ETH_RXD2_MARK,
194 DB3_MARK,
195 ETH_RXD1_MARK,
196 DB2_MARK,
197 ETH_RXD0_MARK,
198 DB1_MARK,
199 ETH_RX_DV_MARK,
200 DB0_MARK,
201 ETH_RX_ER_MARK,
202
203 DCLKOUT_MARK,
204 SCIF1_SLK_MARK,
205 SCIF1_RXD_MARK,
206 SCIF1_TXD_MARK,
207 DACK1_MARK,
208 BACK_MARK,
209 FALE_MARK,
210 DACK0_MARK,
211 FCLE_MARK,
212 DREQ1_MARK,
213 BREQ_MARK,
214 USB_OVC1_MARK,
215 DREQ0_MARK,
216 USB_OVC0_MARK,
217
218 USB_PENC1_MARK,
219 USB_PENC0_MARK,
220
221 HAC1_SDOUT_MARK,
222 SSI1_SDATA_MARK,
223 SDIF1CMD_MARK,
224 HAC1_SDIN_MARK,
225 SSI1_SCK_MARK,
226 SDIF1CD_MARK,
227 HAC1_SYNC_MARK,
228 SSI1_WS_MARK,
229 SDIF1WP_MARK,
230 HAC1_BITCLK_MARK,
231 SSI1_CLK_MARK,
232 SDIF1CLK_MARK,
233 HAC0_SDOUT_MARK,
234 SSI0_SDATA_MARK,
235 SDIF1D3_MARK,
236 HAC0_SDIN_MARK,
237 SSI0_SCK_MARK,
238 SDIF1D2_MARK,
239 HAC0_SYNC_MARK,
240 SSI0_WS_MARK,
241 SDIF1D1_MARK,
242 HAC0_BITCLK_MARK,
243 SSI0_CLK_MARK,
244 SDIF1D0_MARK,
245
246 SCIF3_SCK_MARK,
247 SSI2_SDATA_MARK,
248 SCIF3_RXD_MARK,
249 TCLK_MARK,
250 SSI2_SCK_MARK,
251 SCIF3_TXD_MARK,
252 HAC_RES_MARK,
253 SSI2_WS_MARK,
254
255 DACK3_MARK,
256 SDIF0CMD_MARK,
257 DACK2_MARK,
258 SDIF0CD_MARK,
259 DREQ3_MARK,
260 SDIF0WP_MARK,
261 SCIF0_CTS_MARK,
262 DREQ2_MARK,
263 SDIF0CLK_MARK,
264 SCIF0_RTS_MARK,
265 IRL7_MARK,
266 SDIF0D3_MARK,
267 SCIF0_SCK_MARK,
268 IRL6_MARK,
269 SDIF0D2_MARK,
270 SCIF0_RXD_MARK,
271 IRL5_MARK,
272 SDIF0D1_MARK,
273 SCIF0_TXD_MARK,
274 IRL4_MARK,
275 SDIF0D0_MARK,
276
277 SCIF5_SCK_MARK,
278 FRB_MARK,
279 SCIF5_RXD_MARK,
280 IOIS16_MARK,
281 SCIF5_TXD_MARK,
282 CE2B_MARK,
283 DRAK3_MARK,
284 CE2A_MARK,
285 SCIF4_SCK_MARK,
286 DRAK2_MARK,
287 SSI3_WS_MARK,
288 SCIF4_RXD_MARK,
289 DRAK1_MARK,
290 SSI3_SDATA_MARK,
291 FSTATUS_MARK,
292 SCIF4_TXD_MARK,
293 DRAK0_MARK,
294 SSI3_SCK_MARK,
295 FSE_MARK,
296 PINMUX_MARK_END,
297};
298
299static pinmux_enum_t pinmux_data[] = {
300
301 /* PA GPIO */
302 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
303 PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
304 PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
305 PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
306 PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
307 PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
308 PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
309 PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
310
311 /* PB GPIO */
312 PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
313 PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
314 PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
315 PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
316 PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
317 PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
318 PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
319 PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
320
321 /* PC GPIO */
322 PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
323 PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
324 PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
325 PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
326 PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
327 PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
328 PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
329 PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
330
331 /* PD GPIO */
332 PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
333 PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
334 PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
335 PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
336 PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
337 PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
338 PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
339 PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
340
341 /* PE GPIO */
342 PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
343 PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
344
345 /* PF GPIO */
346 PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
347 PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
348 PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
349 PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
350 PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
351 PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
352 PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
353 PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
354
355 /* PG GPIO */
356 PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
357 PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
358 PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
359
360 /* PH GPIO */
361 PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU),
362 PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU),
363 PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
364 PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
365 PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
366 PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
367 PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
368 PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
369
370 /* PJ GPIO */
371 PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU),
372 PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU),
373 PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU),
374 PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU),
375 PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU),
376 PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU),
377 PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU),
378
379 /* PA FN */
380 PINMUX_MARK_BEGIN,
381 PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN),
382 PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN),
383 PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN),
384 PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN),
385 PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN),
386 PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN),
387 PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN),
388 PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN),
389 PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN),
390 PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN),
391 PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN),
392 PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN),
393 PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN),
394 PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN),
395 PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN),
396 PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN),
397
398 /* PB FN */
399 PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN),
400 PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN),
401 PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN),
402 PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN),
403 PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN),
404 PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN),
405 PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN),
406 PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN),
407 PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN),
408 PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN),
409 PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN),
410 PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN),
411 PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN),
412 PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN),
413 PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN),
414 PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN),
415
416 /* PC FN */
417 PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN),
418 PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN),
419 PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN),
420 PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN),
421 PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN),
422 PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN),
423 PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN),
424 PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN),
425
426 PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN),
427 PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN),
428 PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN),
429 PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN),
430 PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN),
431 PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN),
432 PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN),
433 PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN),
434
435 /* PD FN */
436 PINMUX_DATA(DCLKOUT_MARK, PD7_FN),
437 PINMUX_DATA(SCIF1_SLK_MARK, PD6_FN),
438 PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN),
439 PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN),
440 PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN),
441 PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN),
442 PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN),
443 PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN),
444 PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN),
445 PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN),
446 PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN),
447 PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN),
448 PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN),
449 PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN),
450
451 /* PE FN */
452 PINMUX_DATA(USB_PENC1_MARK, PE7_FN),
453 PINMUX_DATA(USB_PENC0_MARK, PE6_FN),
454
455 /* PF FN */
456 PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN),
457 PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN),
458 PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN),
459 PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN),
460 PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN),
461 PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN),
462 PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN),
463 PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN),
464 PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN),
465 PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN),
466 PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN),
467 PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN),
468 PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN),
469 PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN),
470 PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN),
471 PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN),
472 PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN),
473 PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN),
474 PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN),
475 PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN),
476 PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN),
477 PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN),
478 PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN),
479 PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN),
480
481 /* PG FN */
482 PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN),
483 PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN),
484 PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN),
485 PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN),
486 PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN),
487 PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN),
488 PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN),
489 PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN),
490
491 /* PH FN */
492 PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN),
493 PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN),
494 PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN),
495 PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN),
496 PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN),
497 PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN),
498 PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN),
499 PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN),
500 PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN),
501 PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN),
502 PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN),
503 PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN),
504 PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN),
505 PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN),
506 PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN),
507 PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN),
508 PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN),
509 PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN),
510 PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN),
511 PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN),
512 PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN),
513
514 /* PJ FN */
515 PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN),
516 PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN),
517 PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN),
518 PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN),
519 PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN),
520 PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN),
521 PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN),
522 PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN),
523 PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN),
524 PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN),
525 PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN),
526 PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN),
527 PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN),
528 PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN),
529 PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN),
530 PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN),
531 PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN),
532 PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN),
533 PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
534};
535
536static struct pinmux_gpio pinmux_gpios[] = {
537 /* PA */
538 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
539 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
540 PINMUX_GPIO(GPIO_PA5, PA5_DATA),
541 PINMUX_GPIO(GPIO_PA4, PA4_DATA),
542 PINMUX_GPIO(GPIO_PA3, PA3_DATA),
543 PINMUX_GPIO(GPIO_PA2, PA2_DATA),
544 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
545 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
546
547 /* PB */
548 PINMUX_GPIO(GPIO_PB7, PB7_DATA),
549 PINMUX_GPIO(GPIO_PB6, PB6_DATA),
550 PINMUX_GPIO(GPIO_PB5, PB5_DATA),
551 PINMUX_GPIO(GPIO_PB4, PB4_DATA),
552 PINMUX_GPIO(GPIO_PB3, PB3_DATA),
553 PINMUX_GPIO(GPIO_PB2, PB2_DATA),
554 PINMUX_GPIO(GPIO_PB1, PB1_DATA),
555 PINMUX_GPIO(GPIO_PB0, PB0_DATA),
556
557 /* PC */
558 PINMUX_GPIO(GPIO_PC7, PC7_DATA),
559 PINMUX_GPIO(GPIO_PC6, PC6_DATA),
560 PINMUX_GPIO(GPIO_PC5, PC5_DATA),
561 PINMUX_GPIO(GPIO_PC4, PC4_DATA),
562 PINMUX_GPIO(GPIO_PC3, PC3_DATA),
563 PINMUX_GPIO(GPIO_PC2, PC2_DATA),
564 PINMUX_GPIO(GPIO_PC1, PC1_DATA),
565 PINMUX_GPIO(GPIO_PC0, PC0_DATA),
566
567 /* PD */
568 PINMUX_GPIO(GPIO_PD7, PD7_DATA),
569 PINMUX_GPIO(GPIO_PD6, PD6_DATA),
570 PINMUX_GPIO(GPIO_PD5, PD5_DATA),
571 PINMUX_GPIO(GPIO_PD4, PD4_DATA),
572 PINMUX_GPIO(GPIO_PD3, PD3_DATA),
573 PINMUX_GPIO(GPIO_PD2, PD2_DATA),
574 PINMUX_GPIO(GPIO_PD1, PD1_DATA),
575 PINMUX_GPIO(GPIO_PD0, PD0_DATA),
576
577 /* PE */
578 PINMUX_GPIO(GPIO_PE5, PE7_DATA),
579 PINMUX_GPIO(GPIO_PE4, PE6_DATA),
580
581 /* PF */
582 PINMUX_GPIO(GPIO_PF7, PF7_DATA),
583 PINMUX_GPIO(GPIO_PF6, PF6_DATA),
584 PINMUX_GPIO(GPIO_PF5, PF5_DATA),
585 PINMUX_GPIO(GPIO_PF4, PF4_DATA),
586 PINMUX_GPIO(GPIO_PF3, PF3_DATA),
587 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
588 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
589 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
590
591 /* PG */
592 PINMUX_GPIO(GPIO_PG7, PG7_DATA),
593 PINMUX_GPIO(GPIO_PG6, PG6_DATA),
594 PINMUX_GPIO(GPIO_PG5, PG5_DATA),
595
596 /* PH */
597 PINMUX_GPIO(GPIO_PH7, PH7_DATA),
598 PINMUX_GPIO(GPIO_PH6, PH6_DATA),
599 PINMUX_GPIO(GPIO_PH5, PH5_DATA),
600 PINMUX_GPIO(GPIO_PH4, PH4_DATA),
601 PINMUX_GPIO(GPIO_PH3, PH3_DATA),
602 PINMUX_GPIO(GPIO_PH2, PH2_DATA),
603 PINMUX_GPIO(GPIO_PH1, PH1_DATA),
604 PINMUX_GPIO(GPIO_PH0, PH0_DATA),
605
606 /* PJ */
607 PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
608 PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
609 PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
610 PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
611 PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
612 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
613 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
614
615 /* FN */
616 PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK),
617 PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK),
618 PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK),
619 PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK),
620 PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK),
621 PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK),
622 PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK),
623 PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK),
624 PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK),
625 PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK),
626 PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK),
627 PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK),
628 PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK),
629 PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK),
630 PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK),
631 PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK),
632 PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK),
633 PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK),
634 PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK),
635 PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK),
636 PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK),
637 PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK),
638 PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK),
639 PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK),
640 PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK),
641 PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK),
642 PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK),
643 PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK),
644 PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK),
645 PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK),
646 PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK),
647 PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK),
648 PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK),
649 PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK),
650 PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK),
651 PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK),
652 PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK),
653 PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK),
654 PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK),
655 PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK),
656 PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK),
657 PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK),
658 PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK),
659 PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK),
660 PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK),
661 PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK),
662 PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK),
663 PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK),
664 PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK),
665 PINMUX_GPIO(GPIO_FN_SCIF1_SLK, SCIF1_SLK_MARK),
666 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
667 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
668 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
669 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
670 PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK),
671 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
672 PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK),
673 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
674 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
675 PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK),
676 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
677 PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK),
678 PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK),
679 PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK),
680 PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK),
681 PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK),
682 PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK),
683 PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK),
684 PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK),
685 PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK),
686 PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK),
687 PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK),
688 PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK),
689 PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK),
690 PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK),
691 PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK),
692 PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK),
693 PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK),
694 PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK),
695 PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK),
696 PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK),
697 PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK),
698 PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK),
699 PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK),
700 PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK),
701 PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK),
702 PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK),
703 PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK),
704 PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK),
705 PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK),
706 PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK),
707 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
708 PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK),
709 PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK),
710 PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK),
711 PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK),
712 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
713 PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK),
714 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
715 PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK),
716 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
717 PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK),
718 PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
719 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
720 PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK),
721 PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
722 PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK),
723 PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK),
724 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
725 PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK),
726 PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK),
727 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
728 PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK),
729 PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK),
730 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
731 PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK),
732 PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK),
733 PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
734 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
735 PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
736 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
737 PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
738 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
739 PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
740 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
741 PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
742 PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
743 PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK),
744 PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
745 PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
746 PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK),
747 PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK),
748 PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
749 PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
750 PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK),
751 PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK),
752};
753
754static struct pinmux_cfg_reg pinmux_config_regs[] = {
755 { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
756 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
757 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
758 PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
759 PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
760 PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
761 PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
762 PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
763 PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
764 },
765 { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
766 PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
767 PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
768 PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
769 PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
770 PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
771 PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
772 PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
773 PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU }
774 },
775 { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) {
776 PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
777 PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
778 PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
779 PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
780 PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
781 PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
782 PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
783 PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU }
784 },
785 { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) {
786 PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
787 PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
788 PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
789 PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
790 PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
791 PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
792 PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
793 PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU }
794 },
795 { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) {
796 PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
797 PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
798 0, 0, 0, 0,
799 0, 0, 0, 0,
800 0, 0, 0, 0,
801 0, 0, 0, 0,
802 0, 0, 0, 0,
803 0, 0, 0, 0, }
804 },
805 { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) {
806 PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
807 PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
808 PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
809 PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
810 PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
811 PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
812 PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
813 PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU }
814 },
815 { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) {
816 PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
817 PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
818 PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
819 0, 0, 0, 0,
820 0, 0, 0, 0,
821 0, 0, 0, 0,
822 0, 0, 0, 0,
823 0, 0, 0, 0, }
824 },
825 { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) {
826 PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU,
827 PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU,
828 PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
829 PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
830 PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
831 PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
832 PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
833 PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU }
834 },
835 { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) {
836 PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU,
837 PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU,
838 PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU,
839 PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU,
840 PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU,
841 PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU,
842 PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU,
843 0, 0, 0, 0, }
844 },
845 { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) {
846 0, 0,
847 P1MSEL14_0, P1MSEL14_1,
848 P1MSEL13_0, P1MSEL13_1,
849 P1MSEL12_0, P1MSEL12_1,
850 P1MSEL11_0, P1MSEL11_1,
851 P1MSEL10_0, P1MSEL10_1,
852 P1MSEL9_0, P1MSEL9_1,
853 P1MSEL8_0, P1MSEL8_1,
854 P1MSEL7_0, P1MSEL7_1,
855 P1MSEL6_0, P1MSEL6_1,
856 P1MSEL5_0, P1MSEL5_1,
857 P1MSEL4_0, P1MSEL4_1,
858 P1MSEL3_0, P1MSEL3_1,
859 P1MSEL2_0, P1MSEL2_1,
860 P1MSEL1_0, P1MSEL1_1,
861 P1MSEL0_0, P1MSEL0_1 }
862 },
863 { PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) {
864 P2MSEL15_0, P2MSEL15_1,
865 P2MSEL14_0, P2MSEL14_1,
866 P2MSEL13_0, P2MSEL13_1,
867 P2MSEL12_0, P2MSEL12_1,
868 P2MSEL11_0, P2MSEL11_1,
869 P2MSEL10_0, P2MSEL10_1,
870 P2MSEL9_0, P2MSEL9_1,
871 P2MSEL8_0, P2MSEL8_1,
872 P2MSEL7_0, P2MSEL7_1,
873 P2MSEL6_0, P2MSEL6_1,
874 P2MSEL5_0, P2MSEL5_1,
875 P2MSEL4_0, P2MSEL4_1,
876 P2MSEL3_0, P2MSEL3_1,
877 P2MSEL2_0, P2MSEL2_1,
878 P2MSEL1_0, P2MSEL1_1,
879 P2MSEL0_0, P2MSEL0_1 }
880 },
881 {}
882};
883
884static struct pinmux_data_reg pinmux_data_regs[] = {
885 { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
886 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
887 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
888 },
889 { PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) {
890 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
891 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
892 },
893 { PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) {
894 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
895 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
896 },
897 { PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) {
898 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
899 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
900 },
901 { PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) {
902 PE7_DATA, PE6_DATA,
903 0, 0, 0, 0, 0, 0 }
904 },
905 { PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) {
906 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
907 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
908 },
909 { PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) {
910 PG7_DATA, PG6_DATA, PG5_DATA, 0,
911 0, 0, 0, 0 }
912 },
913 { PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) {
914 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
915 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
916 },
917 { PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) {
918 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
919 PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 }
920 },
921 { },
922};
923
924static struct pinmux_info sh7786_pinmux_info = {
925 .name = "sh7786_pfc",
926 .reserved_id = PINMUX_RESERVED,
927 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
928 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
929 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
930 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
931 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
932 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
933
934 .first_gpio = GPIO_PA7,
935 .last_gpio = GPIO_FN_FSE,
936
937 .gpios = pinmux_gpios,
938 .cfg_regs = pinmux_config_regs,
939 .data_regs = pinmux_data_regs,
940
941 .gpio_data = pinmux_data,
942 .gpio_data_size = ARRAY_SIZE(pinmux_data),
943};
944
945static int __init plat_pinmux_setup(void)
946{
947 return register_pinmux(&sh7786_pinmux_info);
948}
949
950arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 4ff4dc64520c..c1549382c87c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -12,6 +12,7 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/uio_driver.h> 14#include <linux/uio_driver.h>
15#include <linux/sh_cmt.h>
15#include <asm/clock.h> 16#include <asm/clock.h>
16 17
17static struct resource iic0_resources[] = { 18static struct resource iic0_resources[] = {
@@ -140,6 +141,38 @@ static struct platform_device jpu_device = {
140 .num_resources = ARRAY_SIZE(jpu_resources), 141 .num_resources = ARRAY_SIZE(jpu_resources),
141}; 142};
142 143
144static struct sh_cmt_config cmt_platform_data = {
145 .name = "CMT",
146 .channel_offset = 0x60,
147 .timer_bit = 5,
148 .clk = "cmt0",
149 .clockevent_rating = 125,
150 .clocksource_rating = 200,
151};
152
153static struct resource cmt_resources[] = {
154 [0] = {
155 .name = "CMT",
156 .start = 0x044a0060,
157 .end = 0x044a006b,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = 104,
162 .flags = IORESOURCE_IRQ,
163 },
164};
165
166static struct platform_device cmt_device = {
167 .name = "sh_cmt",
168 .id = 0,
169 .dev = {
170 .platform_data = &cmt_platform_data,
171 },
172 .resource = cmt_resources,
173 .num_resources = ARRAY_SIZE(cmt_resources),
174};
175
143static struct plat_sci_port sci_platform_data[] = { 176static struct plat_sci_port sci_platform_data[] = {
144 { 177 {
145 .mapbase = 0xffe00000, 178 .mapbase = 0xffe00000,
@@ -175,6 +208,7 @@ static struct platform_device sci_device = {
175}; 208};
176 209
177static struct platform_device *sh7343_devices[] __initdata = { 210static struct platform_device *sh7343_devices[] __initdata = {
211 &cmt_device,
178 &iic0_device, 212 &iic0_device,
179 &iic1_device, 213 &iic1_device,
180 &sci_device, 214 &sci_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 839ae97a7fd2..93ecf8ed5c6c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -14,6 +14,7 @@
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/uio_driver.h> 16#include <linux/uio_driver.h>
17#include <linux/sh_cmt.h>
17#include <asm/clock.h> 18#include <asm/clock.h>
18 19
19static struct resource iic_resources[] = { 20static struct resource iic_resources[] = {
@@ -147,6 +148,38 @@ static struct platform_device veu1_device = {
147 .num_resources = ARRAY_SIZE(veu1_resources), 148 .num_resources = ARRAY_SIZE(veu1_resources),
148}; 149};
149 150
151static struct sh_cmt_config cmt_platform_data = {
152 .name = "CMT",
153 .channel_offset = 0x60,
154 .timer_bit = 5,
155 .clk = "cmt0",
156 .clockevent_rating = 125,
157 .clocksource_rating = 200,
158};
159
160static struct resource cmt_resources[] = {
161 [0] = {
162 .name = "CMT",
163 .start = 0x044a0060,
164 .end = 0x044a006b,
165 .flags = IORESOURCE_MEM,
166 },
167 [1] = {
168 .start = 104,
169 .flags = IORESOURCE_IRQ,
170 },
171};
172
173static struct platform_device cmt_device = {
174 .name = "sh_cmt",
175 .id = 0,
176 .dev = {
177 .platform_data = &cmt_platform_data,
178 },
179 .resource = cmt_resources,
180 .num_resources = ARRAY_SIZE(cmt_resources),
181};
182
150static struct plat_sci_port sci_platform_data[] = { 183static struct plat_sci_port sci_platform_data[] = {
151 { 184 {
152 .mapbase = 0xffe00000, 185 .mapbase = 0xffe00000,
@@ -167,6 +200,7 @@ static struct platform_device sci_device = {
167}; 200};
168 201
169static struct platform_device *sh7366_devices[] __initdata = { 202static struct platform_device *sh7366_devices[] __initdata = {
203 &cmt_device,
170 &iic_device, 204 &iic_device,
171 &sci_device, 205 &sci_device,
172 &usb_host_device, 206 &usb_host_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 5146afc156e0..0e5d204bc792 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -13,6 +13,7 @@
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/uio_driver.h> 15#include <linux/uio_driver.h>
16#include <linux/sh_cmt.h>
16#include <asm/clock.h> 17#include <asm/clock.h>
17#include <asm/mmzone.h> 18#include <asm/mmzone.h>
18 19
@@ -176,6 +177,38 @@ static struct platform_device jpu_device = {
176 .num_resources = ARRAY_SIZE(jpu_resources), 177 .num_resources = ARRAY_SIZE(jpu_resources),
177}; 178};
178 179
180static struct sh_cmt_config cmt_platform_data = {
181 .name = "CMT",
182 .channel_offset = 0x60,
183 .timer_bit = 5,
184 .clk = "cmt0",
185 .clockevent_rating = 125,
186 .clocksource_rating = 200,
187};
188
189static struct resource cmt_resources[] = {
190 [0] = {
191 .name = "CMT",
192 .start = 0x044a0060,
193 .end = 0x044a006b,
194 .flags = IORESOURCE_MEM,
195 },
196 [1] = {
197 .start = 104,
198 .flags = IORESOURCE_IRQ,
199 },
200};
201
202static struct platform_device cmt_device = {
203 .name = "sh_cmt",
204 .id = 0,
205 .dev = {
206 .platform_data = &cmt_platform_data,
207 },
208 .resource = cmt_resources,
209 .num_resources = ARRAY_SIZE(cmt_resources),
210};
211
179static struct plat_sci_port sci_platform_data[] = { 212static struct plat_sci_port sci_platform_data[] = {
180 { 213 {
181 .mapbase = 0xffe00000, 214 .mapbase = 0xffe00000,
@@ -209,6 +242,7 @@ static struct platform_device sci_device = {
209}; 242};
210 243
211static struct platform_device *sh7722_devices[] __initdata = { 244static struct platform_device *sh7722_devices[] __initdata = {
245 &cmt_device,
212 &rtc_device, 246 &rtc_device,
213 &usbf_device, 247 &usbf_device,
214 &iic_device, 248 &iic_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 849770d780ae..5338dacbcfba 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -13,6 +13,7 @@
13#include <linux/mm.h> 13#include <linux/mm.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/uio_driver.h> 15#include <linux/uio_driver.h>
16#include <linux/sh_cmt.h>
16#include <asm/clock.h> 17#include <asm/clock.h>
17#include <asm/mmzone.h> 18#include <asm/mmzone.h>
18 19
@@ -100,6 +101,38 @@ static struct platform_device veu1_device = {
100 .num_resources = ARRAY_SIZE(veu1_resources), 101 .num_resources = ARRAY_SIZE(veu1_resources),
101}; 102};
102 103
104static struct sh_cmt_config cmt_platform_data = {
105 .name = "CMT",
106 .channel_offset = 0x60,
107 .timer_bit = 5,
108 .clk = "cmt0",
109 .clockevent_rating = 125,
110 .clocksource_rating = 200,
111};
112
113static struct resource cmt_resources[] = {
114 [0] = {
115 .name = "CMT",
116 .start = 0x044a0060,
117 .end = 0x044a006b,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = 104,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126static struct platform_device cmt_device = {
127 .name = "sh_cmt",
128 .id = 0,
129 .dev = {
130 .platform_data = &cmt_platform_data,
131 },
132 .resource = cmt_resources,
133 .num_resources = ARRAY_SIZE(cmt_resources),
134};
135
103static struct plat_sci_port sci_platform_data[] = { 136static struct plat_sci_port sci_platform_data[] = {
104 { 137 {
105 .mapbase = 0xffe00000, 138 .mapbase = 0xffe00000,
@@ -221,6 +254,7 @@ static struct platform_device iic_device = {
221}; 254};
222 255
223static struct platform_device *sh7723_devices[] __initdata = { 256static struct platform_device *sh7723_devices[] __initdata = {
257 &cmt_device,
224 &sci_device, 258 &sci_device,
225 &rtc_device, 259 &rtc_device,
226 &iic_device, 260 &iic_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 3c5b629887a8..bdf0f61ae1ed 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2006 Paul Mundt 4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2007 Yoshihiro Shimoda 5 * Copyright (C) 2007 Yoshihiro Shimoda
6 * Copyright (C) 2008 Nobuhiro Iwamatsu 6 * Copyright (C) 2008, 2009 Nobuhiro Iwamatsu
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -22,18 +22,8 @@ static struct resource rtc_resources[] = {
22 .flags = IORESOURCE_IO, 22 .flags = IORESOURCE_IO,
23 }, 23 },
24 [1] = { 24 [1] = {
25 /* Period IRQ */ 25 /* Shared Period/Carry/Alarm IRQ */
26 .start = 21, 26 .start = 20,
27 .flags = IORESOURCE_IRQ,
28 },
29 [2] = {
30 /* Carry IRQ */
31 .start = 22,
32 .flags = IORESOURCE_IRQ,
33 },
34 [3] = {
35 /* Alarm IRQ */
36 .start = 20,
37 .flags = IORESOURCE_IRQ, 27 .flags = IORESOURCE_IRQ,
38 }, 28 },
39}; 29};
@@ -50,17 +40,17 @@ static struct plat_sci_port sci_platform_data[] = {
50 .mapbase = 0xffe00000, 40 .mapbase = 0xffe00000,
51 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
52 .type = PORT_SCIF, 42 .type = PORT_SCIF,
53 .irqs = { 40, 41, 43, 42 }, 43 .irqs = { 40, 40, 40, 40 },
54 }, { 44 }, {
55 .mapbase = 0xffe08000, 45 .mapbase = 0xffe08000,
56 .flags = UPF_BOOT_AUTOCONF, 46 .flags = UPF_BOOT_AUTOCONF,
57 .type = PORT_SCIF, 47 .type = PORT_SCIF,
58 .irqs = { 76, 77, 79, 78 }, 48 .irqs = { 76, 76, 76, 76 },
59 }, { 49 }, {
60 .mapbase = 0xffe10000, 50 .mapbase = 0xffe10000,
61 .flags = UPF_BOOT_AUTOCONF, 51 .flags = UPF_BOOT_AUTOCONF,
62 .type = PORT_SCIF, 52 .type = PORT_SCIF,
63 .irqs = { 104, 105, 107, 106 }, 53 .irqs = { 104, 104, 104, 104 },
64 }, { 54 }, {
65 .flags = 0, 55 .flags = 0,
66 } 56 }
@@ -148,93 +138,65 @@ enum {
148 IRL_HHLL, IRL_HHLH, IRL_HHHL, 138 IRL_HHLL, IRL_HHLH, IRL_HHHL,
149 139
150 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 140 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
151 RTC_ATI, RTC_PRI, RTC_CUI, 141 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
152 WDT, TMU0, TMU1, TMU2, TMU2_TICPI, 142 HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
153 HUDI, LCDC, 143 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
154 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE, 144 STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
155 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, 145 USBH, USBF, TPU, PCC, MMCIF, SIM,
156 DMAC0_DMINT4, DMAC0_DMINT5,
157 IIC0, IIC1,
158 CMT,
159 GEINT0, GEINT1, GEINT2,
160 HAC,
161 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
162 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
163 STIF0, STIF1,
164 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
165 SIOF0, SIOF1, SIOF2,
166 USBH, USBFI0, USBFI1,
167 TPU, PCC,
168 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
169 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND,
170 TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3, 146 TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
171 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, 147 SCIF2, GPIO,
172 GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3,
173 148
174 /* interrupt groups */ 149 /* interrupt groups */
175 150
176 TMU012, TMU345, RTC, DMAC, SCIF0, GETHER, PCIC5, 151 TMU012, TMU345,
177 SCIF1, USBF, MMCIF, SIM, SCIF2, GPIO,
178}; 152};
179 153
180static struct intc_vect vectors[] __initdata = { 154static struct intc_vect vectors[] __initdata = {
181 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 155 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
182 INTC_VECT(RTC_CUI, 0x4c0), 156 INTC_VECT(RTC, 0x4c0),
183 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580), 157 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
184 INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0), 158 INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
185 INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600), 159 INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
186 INTC_VECT(LCDC, 0x620), 160 INTC_VECT(LCDC, 0x620),
187 INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660), 161 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
188 INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0), 162 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
189 INTC_VECT(DMAC0_DMAE, 0x6c0), 163 INTC_VECT(DMAC, 0x6c0),
190 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), 164 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
191 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), 165 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
192 INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0), 166 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
193 INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0), 167 INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
194 INTC_VECT(CMT, 0x900), INTC_VECT(GEINT0, 0x920), 168 INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
195 INTC_VECT(GEINT1, 0x940), INTC_VECT(GEINT2, 0x960), 169 INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
196 INTC_VECT(HAC, 0x980), 170 INTC_VECT(HAC, 0x980),
197 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 171 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
198 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 172 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
199 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0), 173 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
200 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0), 174 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
201 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20), 175 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
202 INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60), 176 INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
203 INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0), 177 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
204 INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0), 178 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
205 INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20), 179 INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
206 INTC_VECT(USBH, 0xc60), INTC_VECT(USBFI0, 0xc80), 180 INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
207 INTC_VECT(USBFI1, 0xca0), 181 INTC_VECT(USBF, 0xca0),
208 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0), 182 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
209 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20), 183 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
210 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60), 184 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
211 INTC_VECT(SIM_ERI, 0xd80), INTC_VECT(SIM_RXI, 0xda0), 185 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
212 INTC_VECT(SIM_TXI, 0xdc0), INTC_VECT(SIM_TEND, 0xde0), 186 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
213 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 187 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
214 INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60), 188 INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
215 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), 189 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
216 INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0), 190 INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
217 INTC_VECT(SCIF2_ERI, 0xf00), INTC_VECT(SCIF2_RXI, 0xf20), 191 INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
218 INTC_VECT(SCIF2_BRI, 0xf40), INTC_VECT(SCIF2_TXI, 0xf60), 192 INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
219 INTC_VECT(GPIO_CH0, 0xf80), INTC_VECT(GPIO_CH1, 0xfa0), 193 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
220 INTC_VECT(GPIO_CH2, 0xfc0), INTC_VECT(GPIO_CH3, 0xfe0), 194 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
221}; 195};
222 196
223static struct intc_group groups[] __initdata = { 197static struct intc_group groups[] __initdata = {
224 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 198 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
225 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 199 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
226 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
227 INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
228 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
229 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
230 INTC_GROUP(GETHER, GEINT0, GEINT1, GEINT2),
231 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
232 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
233 INTC_GROUP(USBF, USBFI0, USBFI1),
234 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
235 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
236 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
237 INTC_GROUP(GPIO, GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3),
238}; 200};
239 201
240static struct intc_mask_reg mask_registers[] __initdata = { 202static struct intc_mask_reg mask_registers[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index fb8200cc7440..6f7227cd65bf 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -20,17 +20,7 @@ static struct resource rtc_resources[] = {
20 .flags = IORESOURCE_IO, 20 .flags = IORESOURCE_IO,
21 }, 21 },
22 [1] = { 22 [1] = {
23 /* Period IRQ */ 23 /* Shared Period/Carry/Alarm IRQ */
24 .start = 21,
25 .flags = IORESOURCE_IRQ,
26 },
27 [2] = {
28 /* Carry IRQ */
29 .start = 22,
30 .flags = IORESOURCE_IRQ,
31 },
32 [3] = {
33 /* Alarm IRQ */
34 .start = 20, 24 .start = 20,
35 .flags = IORESOURCE_IRQ, 25 .flags = IORESOURCE_IRQ,
36 }, 26 },
@@ -48,12 +38,12 @@ static struct plat_sci_port sci_platform_data[] = {
48 .mapbase = 0xffe00000, 38 .mapbase = 0xffe00000,
49 .flags = UPF_BOOT_AUTOCONF, 39 .flags = UPF_BOOT_AUTOCONF,
50 .type = PORT_SCIF, 40 .type = PORT_SCIF,
51 .irqs = { 40, 41, 43, 42 }, 41 .irqs = { 40, 40, 40, 40 },
52 }, { 42 }, {
53 .mapbase = 0xffe10000, 43 .mapbase = 0xffe10000,
54 .flags = UPF_BOOT_AUTOCONF, 44 .flags = UPF_BOOT_AUTOCONF,
55 .type = PORT_SCIF, 45 .type = PORT_SCIF,
56 .irqs = { 76, 77, 79, 78 }, 46 .irqs = { 76, 76, 76, 76 },
57 }, { 47 }, {
58 .flags = 0, 48 .flags = 0,
59 } 49 }
@@ -90,82 +80,55 @@ enum {
90 IRL_HHLL, IRL_HHLH, IRL_HHHL, 80 IRL_HHLL, IRL_HHLH, IRL_HHHL,
91 81
92 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 82 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
93 RTC_ATI, RTC_PRI, RTC_CUI, 83 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
94 WDT, 84 HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
95 TMU0, TMU1, TMU2, TMU2_TICPI, 85 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
96 HUDI, 86 SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
97 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE,
98 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
99 DMAC0_DMINT4, DMAC0_DMINT5, DMAC1_DMINT6, DMAC1_DMINT7,
100 CMT, HAC,
101 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
102 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
103 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
104 SIOF, HSPI,
105 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
106 DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11,
107 TMU3, TMU4, TMU5,
108 SSI,
109 FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
110 GPIOI0, GPIOI1, GPIOI2, GPIOI3,
111 87
112 /* interrupt groups */ 88 /* interrupt groups */
113 89
114 RTC, TMU012, DMAC0, SCIF0, DMAC45, DMAC1, 90 TMU012, TMU345,
115 PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
116}; 91};
117 92
118static struct intc_vect vectors[] __initdata = { 93static struct intc_vect vectors[] __initdata = {
119 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 94 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
120 INTC_VECT(RTC_CUI, 0x4c0), 95 INTC_VECT(RTC, 0x4c0),
121 INTC_VECT(WDT, 0x560), 96 INTC_VECT(WDT, 0x560),
122 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 97 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
123 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 98 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
124 INTC_VECT(HUDI, 0x600), 99 INTC_VECT(HUDI, 0x600),
125 INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660), 100 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
126 INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0), 101 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
127 INTC_VECT(DMAC0_DMAE, 0x6c0), 102 INTC_VECT(DMAC0, 0x6c0),
128 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), 103 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
129 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), 104 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
130 INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0), 105 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
131 INTC_VECT(DMAC1_DMINT6, 0x7c0), INTC_VECT(DMAC1_DMINT7, 0x7e0), 106 INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
132 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980), 107 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
133 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 108 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
134 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 109 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
135 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0), 110 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
136 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0), 111 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
137 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20), 112 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
138 INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0), 113 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
139 INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0), 114 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
140 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80), 115 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
141 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20), 116 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
142 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60), 117 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
143 INTC_VECT(DMAC1_DMINT8, 0xd80), INTC_VECT(DMAC1_DMINT9, 0xda0), 118 INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
144 INTC_VECT(DMAC1_DMINT10, 0xdc0), INTC_VECT(DMAC1_DMINT11, 0xde0), 119 INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
145 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 120 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
146 INTC_VECT(TMU5, 0xe40), 121 INTC_VECT(TMU5, 0xe40),
147 INTC_VECT(SSI, 0xe80), 122 INTC_VECT(SSI, 0xe80),
148 INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20), 123 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
149 INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60), 124 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
150 INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0), 125 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
151 INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0), 126 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
152}; 127};
153 128
154static struct intc_group groups[] __initdata = { 129static struct intc_group groups[] __initdata = {
155 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
156 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 130 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
157 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
158 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
159 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
160 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
161 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
162 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
163 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
164 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
165 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 131 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
166 INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
167 FLCTL_FLTRQ0, FLCTL_FLTRQ1),
168 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
169}; 132};
170 133
171static struct intc_mask_reg mask_registers[] __initdata = { 134static struct intc_mask_reg mask_registers[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 30baa63b24c8..d80802a49dbd 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -20,18 +20,13 @@ static struct plat_sci_port sci_platform_data[] = {
20 .mapbase = 0xffea0000, 20 .mapbase = 0xffea0000,
21 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
22 .type = PORT_SCIF, 22 .type = PORT_SCIF,
23 .irqs = { 40, 41, 43, 42 }, 23 .irqs = { 40, 40, 40, 40 },
24 }, { 24 }, {
25 .mapbase = 0xffeb0000, 25 .mapbase = 0xffeb0000,
26 .flags = UPF_BOOT_AUTOCONF, 26 .flags = UPF_BOOT_AUTOCONF,
27 .type = PORT_SCIF, 27 .type = PORT_SCIF,
28 .irqs = { 44, 45, 47, 46 }, 28 .irqs = { 44, 44, 44, 44 },
29 }, 29 }, {
30
31 /*
32 * The rest of these all have multiplexed IRQs
33 */
34 {
35 .mapbase = 0xffec0000, 30 .mapbase = 0xffec0000,
36 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF, 32 .type = PORT_SCIF,
@@ -91,33 +86,19 @@ enum {
91 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 86 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
92 87
93 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 88 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
94 WDT, 89 WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
95 TMU0, TMU1, TMU2, TMU2_TICPI, 90 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
96 HUDI,
97 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
98 DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
99 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
100 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
101 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
102 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
103 HSPI,
104 SCIF2, SCIF3, SCIF4, SCIF5, 91 SCIF2, SCIF3, SCIF4, SCIF5,
105 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, 92 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
106 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0, 93 SIOF, MMCIF, DU, GDTA,
107 SIOF,
108 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
109 DU,
110 GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI,
111 TMU3, TMU4, TMU5, 94 TMU3, TMU4, TMU5,
112 SSI0, SSI1, 95 SSI0, SSI1,
113 HAC0, HAC1, 96 HAC0, HAC1,
114 FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1, 97 FLCTL, GPIO,
115 GPIOI0, GPIOI1, GPIOI2, GPIOI3,
116 98
117 /* interrupt groups */ 99 /* interrupt groups */
118 100
119 TMU012, DMAC0, SCIF0, SCIF1, DMAC1, 101 TMU012, TMU345
120 PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
121}; 102};
122 103
123static struct intc_vect vectors[] __initdata = { 104static struct intc_vect vectors[] __initdata = {
@@ -125,57 +106,45 @@ static struct intc_vect vectors[] __initdata = {
125 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 106 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
126 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 107 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
127 INTC_VECT(HUDI, 0x600), 108 INTC_VECT(HUDI, 0x600),
128 INTC_VECT(DMAC0_DMINT0, 0x620), INTC_VECT(DMAC0_DMINT1, 0x640), 109 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
129 INTC_VECT(DMAC0_DMINT2, 0x660), INTC_VECT(DMAC0_DMINT3, 0x680), 110 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
130 INTC_VECT(DMAC0_DMINT4, 0x6a0), INTC_VECT(DMAC0_DMINT5, 0x6c0), 111 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
131 INTC_VECT(DMAC0_DMAE, 0x6e0), 112 INTC_VECT(DMAC0, 0x6e0),
132 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), 113 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
133 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), 114 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
134 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0), 115 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
135 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0), 116 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
136 INTC_VECT(DMAC1_DMINT6, 0x880), INTC_VECT(DMAC1_DMINT7, 0x8a0), 117 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
137 INTC_VECT(DMAC1_DMINT8, 0x8c0), INTC_VECT(DMAC1_DMINT9, 0x8e0), 118 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
138 INTC_VECT(DMAC1_DMINT10, 0x900), INTC_VECT(DMAC1_DMINT11, 0x920), 119 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
139 INTC_VECT(DMAC1_DMAE, 0x940), 120 INTC_VECT(DMAC1, 0x940),
140 INTC_VECT(HSPI, 0x960), 121 INTC_VECT(HSPI, 0x960),
141 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0), 122 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
142 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0), 123 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
143 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 124 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
144 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 125 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
145 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0), 126 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
146 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0), 127 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
147 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20), 128 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
148 INTC_VECT(SIOF, 0xc00), 129 INTC_VECT(SIOF, 0xc00),
149 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20), 130 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
150 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60), 131 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
151 INTC_VECT(DU, 0xd80), 132 INTC_VECT(DU, 0xd80),
152 INTC_VECT(GDTA_GACLI, 0xda0), INTC_VECT(GDTA_GAMCI, 0xdc0), 133 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
153 INTC_VECT(GDTA_GAERI, 0xde0), 134 INTC_VECT(GDTA, 0xde0),
154 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 135 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
155 INTC_VECT(TMU5, 0xe40), 136 INTC_VECT(TMU5, 0xe40),
156 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), 137 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
157 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0), 138 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
158 INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20), 139 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
159 INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60), 140 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
160 INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0), 141 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
161 INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0), 142 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
162}; 143};
163 144
164static struct intc_group groups[] __initdata = { 145static struct intc_group groups[] __initdata = {
165 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 146 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
166 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
167 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
168 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
169 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
170 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
171 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE),
172 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
173 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
174 INTC_GROUP(GDTA, GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI),
175 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 147 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
176 INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
177 FLCTL_FLTRQ0, FLCTL_FLTRQ1),
178 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
179}; 148};
180 149
181static struct intc_mask_reg mask_registers[] __initdata = { 150static struct intc_mask_reg mask_registers[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
new file mode 100644
index 000000000000..5a47e1cf442e
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -0,0 +1,490 @@
1/*
2 * SH7786 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on SH7785 Setup
8 *
9 * Copyright (C) 2007 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial.h>
18#include <linux/serial_sci.h>
19#include <linux/io.h>
20#include <linux/mm.h>
21#include <linux/dma-mapping.h>
22#include <asm/mmzone.h>
23
24static struct plat_sci_port sci_platform_data[] = {
25 {
26 .mapbase = 0xffea0000,
27 .flags = UPF_BOOT_AUTOCONF,
28 .type = PORT_SCIF,
29 .irqs = { 40, 41, 43, 42 },
30 },
31 /*
32 * The rest of these all have multiplexed IRQs
33 */
34 {
35 .mapbase = 0xffeb0000,
36 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF,
38 .irqs = { 44, 44, 44, 44 },
39 }, {
40 .mapbase = 0xffec0000,
41 .flags = UPF_BOOT_AUTOCONF,
42 .type = PORT_SCIF,
43 .irqs = { 50, 50, 50, 50 },
44 }, {
45 .mapbase = 0xffed0000,
46 .flags = UPF_BOOT_AUTOCONF,
47 .type = PORT_SCIF,
48 .irqs = { 51, 51, 51, 51 },
49 }, {
50 .mapbase = 0xffee0000,
51 .flags = UPF_BOOT_AUTOCONF,
52 .type = PORT_SCIF,
53 .irqs = { 52, 52, 52, 52 },
54 }, {
55 .mapbase = 0xffef0000,
56 .flags = UPF_BOOT_AUTOCONF,
57 .type = PORT_SCIF,
58 .irqs = { 53, 53, 53, 53 },
59 }, {
60 .flags = 0,
61 }
62};
63
64static struct platform_device sci_device = {
65 .name = "sh-sci",
66 .id = -1,
67 .dev = {
68 .platform_data = sci_platform_data,
69 },
70};
71
72static struct resource usb_ohci_resources[] = {
73 [0] = {
74 .start = 0xffe70400,
75 .end = 0xffe704ff,
76 .flags = IORESOURCE_MEM,
77 },
78 [1] = {
79 .start = 77,
80 .end = 77,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
86static struct platform_device usb_ohci_device = {
87 .name = "sh_ohci",
88 .id = -1,
89 .dev = {
90 .dma_mask = &usb_ohci_dma_mask,
91 .coherent_dma_mask = DMA_BIT_MASK(32),
92 },
93 .num_resources = ARRAY_SIZE(usb_ohci_resources),
94 .resource = usb_ohci_resources,
95};
96
97static struct platform_device *sh7786_devices[] __initdata = {
98 &sci_device,
99 &usb_ohci_device,
100};
101
102
103/*
104 * Please call this function if your platform board
105 * use external clock for USB
106 * */
107#define USBCTL0 0xffe70858
108#define CLOCK_MODE_MASK 0xffffff7f
109#define EXT_CLOCK_MODE 0x00000080
110void __init sh7786_usb_use_exclock(void)
111{
112 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
113 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
114}
115
116#define USBINITREG1 0xffe70094
117#define USBINITREG2 0xffe7009c
118#define USBINITVAL1 0x00ff0040
119#define USBINITVAL2 0x00000001
120
121#define USBPCTL1 0xffe70804
122#define USBST 0xffe70808
123#define PHY_ENB 0x00000001
124#define PLL_ENB 0x00000002
125#define PHY_RST 0x00000004
126#define ACT_PLL_STATUS 0xc0000000
127static void __init sh7786_usb_setup(void)
128{
129 int i = 1000000;
130
131 /*
132 * USB initial settings
133 *
134 * The following settings are necessary
135 * for using the USB modules.
136 *
137 * see "USB Inital Settings" for detail
138 */
139 __raw_writel(USBINITVAL1, USBINITREG1);
140 __raw_writel(USBINITVAL2, USBINITREG2);
141
142 /*
143 * Set the PHY and PLL enable bit
144 */
145 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
146 while (i-- &&
147 ((__raw_readl(USBST) & ACT_PLL_STATUS) != ACT_PLL_STATUS))
148 cpu_relax();
149
150 if (i) {
151 /* Set the PHY RST bit */
152 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
153 printk(KERN_INFO "sh7786 usb setup done\n");
154 }
155}
156
157static int __init sh7786_devices_setup(void)
158{
159 sh7786_usb_setup();
160 return platform_add_devices(sh7786_devices,
161 ARRAY_SIZE(sh7786_devices));
162}
163device_initcall(sh7786_devices_setup);
164
165enum {
166 UNUSED = 0,
167
168 /* interrupt sources */
169
170 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
171 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
172 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
173 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
174
175 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
176 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
177 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
178 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
179
180 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
181 WDT,
182 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
183 TMU1_0, TMU1_1, TMU1_2,
184 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
185 HUDI1, HUDI0,
186 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
187 HPB_0, HPB_1, HPB_2,
188 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
189 SCIF1,
190 TMU2, TMU3,
191 SCIF2, SCIF3, SCIF4, SCIF5,
192 Eth_0, Eth_1,
193 PCIeC0_0, PCIeC0_1, PCIeC0_2,
194 PCIeC1_0, PCIeC1_1, PCIeC1_2,
195 USB,
196 I2C0, I2C1,
197 DU,
198 SSI0, SSI1, SSI2, SSI3,
199 PCIeC2_0, PCIeC2_1, PCIeC2_2,
200 HAC0, HAC1,
201 FLCTL,
202 HSPI,
203 GPIO0, GPIO1,
204 Thermal,
205 INTC0, INTC1, INTC2, INTC3, INTC4, INTC5, INTC6, INTC7,
206
207 /* interrupt groups */
208};
209
210static struct intc_vect vectors[] __initdata = {
211 INTC_VECT(WDT, 0x3e0),
212 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
213 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
214 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
215 INTC_VECT(TMU1_2, 0x4c0),
216 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
217 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
218 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
219 INTC_VECT(DMAC0_6, 0x5c0),
220 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
221 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
222 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
223 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
224 INTC_VECT(HPB_2, 0x6e0),
225 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
226 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
227 INTC_VECT(SCIF1, 0x780),
228 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
229 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
230 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
231 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
232 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
233 INTC_VECT(PCIeC0_2, 0xb20),
234 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
235 INTC_VECT(PCIeC1_2, 0xb80),
236 INTC_VECT(USB, 0xba0),
237 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
238 INTC_VECT(DU, 0xd00),
239 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
240 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
241 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
242 INTC_VECT(PCIeC2_2, 0xde0),
243 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
244 INTC_VECT(FLCTL, 0xe40),
245 INTC_VECT(HSPI, 0xe80),
246 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
247 INTC_VECT(Thermal, 0xee0),
248};
249
250/* FIXME: Main CPU support only now */
251#if 1 /* Main CPU */
252#define CnINTMSK0 0xfe410030
253#define CnINTMSK1 0xfe410040
254#define CnINTMSKCLR0 0xfe410050
255#define CnINTMSKCLR1 0xfe410060
256#define CnINT2MSKR0 0xfe410a20
257#define CnINT2MSKR1 0xfe410a24
258#define CnINT2MSKR2 0xfe410a28
259#define CnINT2MSKR3 0xfe410a2c
260#define CnINT2MSKCR0 0xfe410a30
261#define CnINT2MSKCR1 0xfe410a34
262#define CnINT2MSKCR2 0xfe410a38
263#define CnINT2MSKCR3 0xfe410a3c
264#else /* Sub CPU */
265#define CnINTMSK0 0xfe410034
266#define CnINTMSK1 0xfe410044
267#define CnINTMSKCLR0 0xfe410054
268#define CnINTMSKCLR1 0xfe410064
269#define CnINT2MSKR0 0xfe410b20
270#define CnINT2MSKR1 0xfe410b24
271#define CnINT2MSKR2 0xfe410b28
272#define CnINT2MSKR3 0xfe410b2c
273#define CnINT2MSKCR0 0xfe410b30
274#define CnINT2MSKCR1 0xfe410b34
275#define CnINT2MSKCR2 0xfe410b38
276#define CnINT2MSKCR3 0xfe410b3c
277#endif
278
279#define INTMSK2 0xfe410068
280#define INTMSKCLR2 0xfe41006c
281
282static struct intc_mask_reg mask_registers[] __initdata = {
283 { CnINTMSK0, CnINTMSKCLR0, 32,
284 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
285 { INTMSK2, INTMSKCLR2, 32,
286 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
287 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
288 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
289 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
290 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
291 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
292 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
293 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
294 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
295 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
296 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
297 { CnINT2MSKR1, CnINT2MSKCR1, 32,
298 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
299 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
300 HUDI1, HUDI0,
301 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
302 HPB_0, HPB_1, HPB_2,
303 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
304 SCIF1,
305 TMU2, TMU3, 0, } },
306 { CnINT2MSKR2, CnINT2MSKCR2, 32,
307 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
308 Eth_0, Eth_1,
309 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
310 PCIeC0_0, PCIeC0_1, PCIeC0_2,
311 PCIeC1_0, PCIeC1_1, PCIeC1_2,
312 USB, 0, 0 } },
313 { CnINT2MSKR3, CnINT2MSKCR3, 32,
314 { 0, 0, 0, 0, 0, 0,
315 I2C0, I2C1,
316 DU, SSI0, SSI1, SSI2, SSI3,
317 PCIeC2_0, PCIeC2_1, PCIeC2_2,
318 HAC0, HAC1,
319 FLCTL, 0,
320 HSPI, GPIO0, GPIO1, Thermal,
321 0, 0, 0, 0, 0, 0, 0, 0 } },
322};
323
324static struct intc_prio_reg prio_registers[] __initdata = {
325 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
326 IRQ4, IRQ5, IRQ6, IRQ7 } },
327 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
328 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
329 TMU0_2, TMU0_3 } },
330 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
331 TMU1_2, 0 } },
332 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
333 DMAC0_2, DMAC0_3 } },
334 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
335 DMAC0_6, HUDI1 } },
336 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
337 DMAC1_1, DMAC1_2 } },
338 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
339 HPB_1, HPB_2 } },
340 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
341 SCIF0_2, SCIF0_3 } },
342 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
343 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
344 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
345 Eth_0, Eth_1 } },
346 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
347 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
348 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
349 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
350 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
351 PCIeC1_0, PCIeC1_1 } },
352 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
353 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
354 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
355 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
356 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
357 PCIeC2_1, PCIeC2_2 } },
358 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
359 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
360 GPIO1, Thermal } },
361 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
362 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
363};
364
365static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
366 mask_registers, prio_registers, NULL);
367
368/* Support for external interrupt pins in IRQ mode */
369
370static struct intc_vect vectors_irq0123[] __initdata = {
371 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
372 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
373};
374
375static struct intc_vect vectors_irq4567[] __initdata = {
376 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
377 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
378};
379
380static struct intc_sense_reg sense_registers[] __initdata = {
381 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
382 IRQ4, IRQ5, IRQ6, IRQ7 } },
383};
384
385static struct intc_mask_reg ack_registers[] __initdata = {
386 { 0xfe410024, 0, 32, /* INTREQ */
387 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
388};
389
390static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
391 vectors_irq0123, NULL, mask_registers,
392 prio_registers, sense_registers, ack_registers);
393
394static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
395 vectors_irq4567, NULL, mask_registers,
396 prio_registers, sense_registers, ack_registers);
397
398/* External interrupt pins in IRL mode */
399
400static struct intc_vect vectors_irl0123[] __initdata = {
401 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
402 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
403 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
404 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
405 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
406 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
407 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
408 INTC_VECT(IRL0_HHHL, 0x3c0),
409};
410
411static struct intc_vect vectors_irl4567[] __initdata = {
412 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
413 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
414 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
415 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
416 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
417 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
418 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
419 INTC_VECT(IRL4_HHHL, 0xac0),
420};
421
422static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
423 NULL, mask_registers, NULL, NULL);
424
425static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
426 NULL, mask_registers, NULL, NULL);
427
428#define INTC_ICR0 0xfe410000
429#define INTC_INTMSK0 CnINTMSK0
430#define INTC_INTMSK1 CnINTMSK1
431#define INTC_INTMSK2 INTMSK2
432#define INTC_INTMSKCLR1 CnINTMSKCLR1
433#define INTC_INTMSKCLR2 INTMSKCLR2
434
435void __init plat_irq_setup(void)
436{
437 /* disable IRQ3-0 + IRQ7-4 */
438 ctrl_outl(0xff000000, INTC_INTMSK0);
439
440 /* disable IRL3-0 + IRL7-4 */
441 ctrl_outl(0xc0000000, INTC_INTMSK1);
442 ctrl_outl(0xfffefffe, INTC_INTMSK2);
443
444 /* select IRL mode for IRL3-0 + IRL7-4 */
445 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
446
447 register_intc_controller(&intc_desc);
448}
449
450void __init plat_irq_setup_pins(int mode)
451{
452 switch (mode) {
453 case IRQ_MODE_IRQ7654:
454 /* select IRQ mode for IRL7-4 */
455 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
456 register_intc_controller(&intc_desc_irq4567);
457 break;
458 case IRQ_MODE_IRQ3210:
459 /* select IRQ mode for IRL3-0 */
460 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
461 register_intc_controller(&intc_desc_irq0123);
462 break;
463 case IRQ_MODE_IRL7654:
464 /* enable IRL7-4 but don't provide any masking */
465 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
466 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
467 break;
468 case IRQ_MODE_IRL3210:
469 /* enable IRL0-3 but don't provide any masking */
470 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
471 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
472 break;
473 case IRQ_MODE_IRL7654_MASK:
474 /* enable IRL7-4 and mask using cpu intc controller */
475 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
476 register_intc_controller(&intc_desc_irl4567);
477 break;
478 case IRQ_MODE_IRL3210_MASK:
479 /* enable IRL0-3 and mask using cpu intc controller */
480 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
481 register_intc_controller(&intc_desc_irl0123);
482 break;
483 default:
484 BUG();
485 }
486}
487
488void __init plat_mem_setup(void)
489{
490}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 18:29:01 -0500