Merge branch 'master' into sh/st-integration

1 files changed, 19 insertions, 18 deletions

diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
index 185ec3976a25..5863e0c4d02f 100644
--- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
@@ -14,6 +14,13 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 
+#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
+#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
+
+#define STBCR_MSTP      0x00000001
+#define STBCR_RESET     0x00000002
+#define STBCR_LTSLP     0x80000000
+
 static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
 {
         unsigned int message = (unsigned int)(long)arg;
@@ -21,9 +28,9 @@ static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
         unsigned int offs = 4 * cpu;
         unsigned int x;
 
-        x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
+        x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
         x &= (1 << (message << 2));
-        ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
+        __raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
 
         smp_message_recv(message);
 
@@ -37,6 +44,9 @@ void __init plat_smp_setup(void)
 
         init_cpu_possible(cpumask_of(cpu));
 
+        /* Enable light sleep for the boot CPU */
+        __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu));
+
         __cpu_number_map[0] = 0;
         __cpu_logical_map[0] = 0;
 
@@ -66,32 +76,23 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
                             "IPI", (void *)(long)i);
 }
 
-#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
-#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
-
-#define STBCR_MSTP      0x00000001
-#define STBCR_RESET     0x00000002
-#define STBCR_LTSLP     0x80000000
-
-#define STBCR_AP_VAL    (STBCR_RESET | STBCR_LTSLP)
-
 void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
 {
-        ctrl_outl(entry_point, RESET_REG(cpu));
+        __raw_writel(entry_point, RESET_REG(cpu));
 
-        if (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
-                ctrl_outl(STBCR_MSTP, STBCR_REG(cpu));
+        if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
+                __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
 
-        while (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
+        while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
                 cpu_relax();
 
         /* Start up secondary processor by sending a reset */
-        ctrl_outl(STBCR_AP_VAL, STBCR_REG(cpu));
+        __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu));
 }
 
 int plat_smp_processor_id(void)
 {
-        return ctrl_inl(0xff000048); /* CPIDR */
+        return __raw_readl(0xff000048); /* CPIDR */
 }
 
 void plat_send_ipi(unsigned int cpu, unsigned int message)
@@ -100,5 +101,5 @@ void plat_send_ipi(unsigned int cpu, unsigned int message)
 
         BUG_ON(cpu >= 4);
 
-        ctrl_outl(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
+        __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
 }