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authorKuninori Morimoto <morimoto.kuninori@renesas.com>2009-03-03 01:40:25 -0500
committerPaul Mundt <lethal@linux-sh.org>2009-03-03 01:40:25 -0500
commit55ba99eb211a06709237cb322ecd8c8b6faf6159 (patch)
treedc22ab87110e3e8fd26496fe6eebfbf261cc6c62 /arch/sh/kernel/cpu/sh4a/setup-sh7786.c
parent93fde774546c947ac8563da431f0a6d47452551d (diff)
sh: Add support for SH7786 CPU subtype.
This adds preliminary support for the SH7786 CPU subtype. While this is a dual-core CPU, only UP is supported for now. L2 cache support is likewise not yet implemented. More information on this particular CPU subtype is available at: http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/ Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7786.c')
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c407
1 files changed, 407 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
new file mode 100644
index 000000000000..249b99e1adb5
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -0,0 +1,407 @@
1/*
2 * SH7786 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on SH7785 Setup
8 *
9 * Copyright (C) 2007 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial.h>
18#include <linux/serial_sci.h>
19#include <linux/io.h>
20#include <linux/mm.h>
21#include <asm/mmzone.h>
22
23static struct plat_sci_port sci_platform_data[] = {
24 {
25 .mapbase = 0xffea0000,
26 .flags = UPF_BOOT_AUTOCONF,
27 .type = PORT_SCIF,
28 .irqs = { 40, 41, 43, 42 },
29 },
30 /*
31 * The rest of these all have multiplexed IRQs
32 */
33 {
34 .mapbase = 0xffeb0000,
35 .flags = UPF_BOOT_AUTOCONF,
36 .type = PORT_SCIF,
37 .irqs = { 44, 44, 44, 44 },
38 }, {
39 .mapbase = 0xffec0000,
40 .flags = UPF_BOOT_AUTOCONF,
41 .type = PORT_SCIF,
42 .irqs = { 50, 50, 50, 50 },
43 }, {
44 .mapbase = 0xffed0000,
45 .flags = UPF_BOOT_AUTOCONF,
46 .type = PORT_SCIF,
47 .irqs = { 51, 51, 51, 51 },
48 }, {
49 .mapbase = 0xffee0000,
50 .flags = UPF_BOOT_AUTOCONF,
51 .type = PORT_SCIF,
52 .irqs = { 52, 52, 52, 52 },
53 }, {
54 .mapbase = 0xffef0000,
55 .flags = UPF_BOOT_AUTOCONF,
56 .type = PORT_SCIF,
57 .irqs = { 53, 53, 53, 53 },
58 }, {
59 .flags = 0,
60 }
61};
62
63static struct platform_device sci_device = {
64 .name = "sh-sci",
65 .id = -1,
66 .dev = {
67 .platform_data = sci_platform_data,
68 },
69};
70
71static struct platform_device *sh7786_devices[] __initdata = {
72 &sci_device,
73};
74
75static int __init sh7786_devices_setup(void)
76{
77 return platform_add_devices(sh7786_devices,
78 ARRAY_SIZE(sh7786_devices));
79}
80device_initcall(sh7786_devices_setup);
81
82enum {
83 UNUSED = 0,
84
85 /* interrupt sources */
86
87 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
88 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
89 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
90 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
91
92 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
93 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
94 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
95 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
96
97 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
98 WDT,
99 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
100 TMU1_0, TMU1_1, TMU1_2,
101 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
102 HUDI1, HUDI0,
103 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
104 HPB_0, HPB_1, HPB_2,
105 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
106 SCIF1,
107 TMU2, TMU3,
108 SCIF2, SCIF3, SCIF4, SCIF5,
109 Eth_0, Eth_1,
110 PCIeC0_0, PCIeC0_1, PCIeC0_2,
111 PCIeC1_0, PCIeC1_1, PCIeC1_2,
112 USB,
113 I2C0, I2C1,
114 DU,
115 SSI0, SSI1, SSI2, SSI3,
116 PCIeC2_0, PCIeC2_1, PCIeC2_2,
117 HAC0, HAC1,
118 FLCTL,
119 HSPI,
120 GPIO0, GPIO1,
121 Thermal,
122 INTC0, INTC1, INTC2, INTC3, INTC4, INTC5, INTC6, INTC7,
123
124 /* interrupt groups */
125};
126
127static struct intc_vect vectors[] __initdata = {
128 INTC_VECT(WDT, 0x3e0),
129 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
130 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
131 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
132 INTC_VECT(TMU1_2, 0x4c0),
133 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
134 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
135 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
136 INTC_VECT(DMAC0_6, 0x5c0),
137 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
138 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
139 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
140 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
141 INTC_VECT(HPB_2, 0x6e0),
142 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
143 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
144 INTC_VECT(SCIF1, 0x780),
145 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
146 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
147 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
148 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
149 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
150 INTC_VECT(PCIeC0_2, 0xb20),
151 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
152 INTC_VECT(PCIeC1_2, 0xb80),
153 INTC_VECT(USB, 0xba0),
154 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
155 INTC_VECT(DU, 0xd00),
156 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
157 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
158 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
159 INTC_VECT(PCIeC2_2, 0xde0),
160 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
161 INTC_VECT(FLCTL, 0xe40),
162 INTC_VECT(HSPI, 0xe80),
163 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
164 INTC_VECT(Thermal, 0xee0),
165};
166
167/* FIXME: Main CPU support only now */
168#if 1 /* Main CPU */
169#define CnINTMSK0 0xfe410030
170#define CnINTMSK1 0xfe410040
171#define CnINTMSKCLR0 0xfe410050
172#define CnINTMSKCLR1 0xfe410060
173#define CnINT2MSKR0 0xfe410a20
174#define CnINT2MSKR1 0xfe410a24
175#define CnINT2MSKR2 0xfe410a28
176#define CnINT2MSKR3 0xfe410a2c
177#define CnINT2MSKCR0 0xfe410a30
178#define CnINT2MSKCR1 0xfe410a34
179#define CnINT2MSKCR2 0xfe410a38
180#define CnINT2MSKCR3 0xfe410a3c
181#else /* Sub CPU */
182#define CnINTMSK0 0xfe410034
183#define CnINTMSK1 0xfe410044
184#define CnINTMSKCLR0 0xfe410054
185#define CnINTMSKCLR1 0xfe410064
186#define CnINT2MSKR0 0xfe410b20
187#define CnINT2MSKR1 0xfe410b24
188#define CnINT2MSKR2 0xfe410b28
189#define CnINT2MSKR3 0xfe410b2c
190#define CnINT2MSKCR0 0xfe410b30
191#define CnINT2MSKCR1 0xfe410b34
192#define CnINT2MSKCR2 0xfe410b38
193#define CnINT2MSKCR3 0xfe410b3c
194#endif
195
196#define INTMSK2 0xfe410068
197#define INTMSKCLR2 0xfe41006c
198
199static struct intc_mask_reg mask_registers[] __initdata = {
200 { CnINTMSK0, CnINTMSKCLR0, 32,
201 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
202 { INTMSK2, INTMSKCLR2, 32,
203 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
204 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
205 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
206 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
207 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
208 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
209 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
210 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
211 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
212 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
213 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
214 { CnINT2MSKR1, CnINT2MSKCR1, 32,
215 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
216 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
217 HUDI1, HUDI0,
218 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
219 HPB_0, HPB_1, HPB_2,
220 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
221 SCIF1,
222 TMU2, TMU3, 0, } },
223 { CnINT2MSKR2, CnINT2MSKCR2, 32,
224 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
225 Eth_0, Eth_1,
226 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
227 PCIeC0_0, PCIeC0_1, PCIeC0_2,
228 PCIeC1_0, PCIeC1_1, PCIeC1_2,
229 USB, 0, 0 } },
230 { CnINT2MSKR3, CnINT2MSKCR3, 32,
231 { 0, 0, 0, 0, 0, 0,
232 I2C0, I2C1,
233 DU, SSI0, SSI1, SSI2, SSI3,
234 PCIeC2_0, PCIeC2_1, PCIeC2_2,
235 HAC0, HAC1,
236 FLCTL, 0,
237 HSPI, GPIO0, GPIO1, Thermal,
238 0, 0, 0, 0, 0, 0, 0, 0 } },
239};
240
241static struct intc_prio_reg prio_registers[] __initdata = {
242 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
243 IRQ4, IRQ5, IRQ6, IRQ7 } },
244 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
245 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
246 TMU0_2, TMU0_3 } },
247 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
248 TMU1_2, 0 } },
249 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
250 DMAC0_2, DMAC0_3 } },
251 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
252 DMAC0_6, HUDI1 } },
253 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
254 DMAC1_1, DMAC1_2 } },
255 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
256 HPB_1, HPB_2 } },
257 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
258 SCIF0_2, SCIF0_3 } },
259 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
260 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
261 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
262 Eth_0, Eth_1 } },
263 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
264 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
265 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
266 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
267 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
268 PCIeC1_0, PCIeC1_1 } },
269 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
270 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
271 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
272 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
273 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
274 PCIeC2_1, PCIeC2_2 } },
275 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
276 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
277 GPIO1, Thermal } },
278 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
279 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
280};
281
282static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
283 mask_registers, prio_registers, NULL);
284
285/* Support for external interrupt pins in IRQ mode */
286
287static struct intc_vect vectors_irq0123[] __initdata = {
288 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
289 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
290};
291
292static struct intc_vect vectors_irq4567[] __initdata = {
293 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
294 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
295};
296
297static struct intc_sense_reg sense_registers[] __initdata = {
298 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
299 IRQ4, IRQ5, IRQ6, IRQ7 } },
300};
301
302static struct intc_mask_reg ack_registers[] __initdata = {
303 { 0xfe410024, 0, 32, /* INTREQ */
304 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
305};
306
307static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
308 vectors_irq0123, NULL, mask_registers,
309 prio_registers, sense_registers, ack_registers);
310
311static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
312 vectors_irq4567, NULL, mask_registers,
313 prio_registers, sense_registers, ack_registers);
314
315/* External interrupt pins in IRL mode */
316
317static struct intc_vect vectors_irl0123[] __initdata = {
318 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
319 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
320 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
321 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
322 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
323 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
324 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
325 INTC_VECT(IRL0_HHHL, 0x3c0),
326};
327
328static struct intc_vect vectors_irl4567[] __initdata = {
329 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
330 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
331 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
332 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
333 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
334 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
335 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
336 INTC_VECT(IRL4_HHHL, 0xac0),
337};
338
339static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
340 NULL, mask_registers, NULL, NULL);
341
342static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
343 NULL, mask_registers, NULL, NULL);
344
345#define INTC_ICR0 0xfe410000
346#define INTC_INTMSK0 CnINTMSK0
347#define INTC_INTMSK1 CnINTMSK1
348#define INTC_INTMSK2 INTMSK2
349#define INTC_INTMSKCLR1 CnINTMSKCLR1
350#define INTC_INTMSKCLR2 INTMSKCLR2
351
352void __init plat_irq_setup(void)
353{
354 /* disable IRQ3-0 + IRQ7-4 */
355 ctrl_outl(0xff000000, INTC_INTMSK0);
356
357 /* disable IRL3-0 + IRL7-4 */
358 ctrl_outl(0xc0000000, INTC_INTMSK1);
359 ctrl_outl(0xfffefffe, INTC_INTMSK2);
360
361 /* select IRL mode for IRL3-0 + IRL7-4 */
362 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
363
364 register_intc_controller(&intc_desc);
365}
366
367void __init plat_irq_setup_pins(int mode)
368{
369 switch (mode) {
370 case IRQ_MODE_IRQ7654:
371 /* select IRQ mode for IRL7-4 */
372 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
373 register_intc_controller(&intc_desc_irq4567);
374 break;
375 case IRQ_MODE_IRQ3210:
376 /* select IRQ mode for IRL3-0 */
377 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
378 register_intc_controller(&intc_desc_irq0123);
379 break;
380 case IRQ_MODE_IRL7654:
381 /* enable IRL7-4 but don't provide any masking */
382 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
383 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
384 break;
385 case IRQ_MODE_IRL3210:
386 /* enable IRL0-3 but don't provide any masking */
387 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
388 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
389 break;
390 case IRQ_MODE_IRL7654_MASK:
391 /* enable IRL7-4 and mask using cpu intc controller */
392 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
393 register_intc_controller(&intc_desc_irl4567);
394 break;
395 case IRQ_MODE_IRL3210_MASK:
396 /* enable IRL0-3 and mask using cpu intc controller */
397 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
398 register_intc_controller(&intc_desc_irl0123);
399 break;
400 default:
401 BUG();
402 }
403}
404
405void __init plat_mem_setup(void)
406{
407}
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