Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into common/serial-rework

Conflicts:
	arch/sh/kernel/cpu/sh2/setup-sh7619.c
	arch/sh/kernel/cpu/sh2a/setup-mxg.c
	arch/sh/kernel/cpu/sh2a/setup-sh7201.c
	arch/sh/kernel/cpu/sh2a/setup-sh7203.c
	arch/sh/kernel/cpu/sh2a/setup-sh7206.c
	arch/sh/kernel/cpu/sh3/setup-sh7705.c
	arch/sh/kernel/cpu/sh3/setup-sh770x.c
	arch/sh/kernel/cpu/sh3/setup-sh7710.c
	arch/sh/kernel/cpu/sh3/setup-sh7720.c
	arch/sh/kernel/cpu/sh4/setup-sh4-202.c
	arch/sh/kernel/cpu/sh4/setup-sh7750.c
	arch/sh/kernel/cpu/sh4/setup-sh7760.c
	arch/sh/kernel/cpu/sh4a/setup-sh7343.c
	arch/sh/kernel/cpu/sh4a/setup-sh7366.c
	arch/sh/kernel/cpu/sh4a/setup-sh7722.c
	arch/sh/kernel/cpu/sh4a/setup-sh7723.c
	arch/sh/kernel/cpu/sh4a/setup-sh7724.c
	arch/sh/kernel/cpu/sh4a/setup-sh7763.c
	arch/sh/kernel/cpu/sh4a/setup-sh7770.c
	arch/sh/kernel/cpu/sh4a/setup-sh7780.c
	arch/sh/kernel/cpu/sh4a/setup-sh7785.c
	arch/sh/kernel/cpu/sh4a/setup-sh7786.c
	arch/sh/kernel/cpu/sh4a/setup-shx3.c
	arch/sh/kernel/cpu/sh5/setup-sh5.c
	drivers/serial/sh-sci.c
	drivers/serial/sh-sci.h
	include/linux/serial_sci.h

1 files changed, 248 insertions, 81 deletions

diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 3ae2e2071009..18d8fc136fb2 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -13,20 +13,123 @@
 #include <linux/serial_sci.h>
 #include <linux/io.h>
 #include <linux/mm.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
+
 #include <asm/mmzone.h>
 
+#include <cpu/dma-register.h>
+
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffea0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 40, 40, 40 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffeb0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 44, 44, 44, 44 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffec0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 60, 60, 60, 60 },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xffed0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 61, 61, 61, 61 },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xffee0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 62, 62, 62, 62 },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xffef0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
+        .type           = PORT_SCIF,
+        .irqs           = { 63, 63, 63, 63 },
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "tmu012_fck",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffd80008,
                 .end    = 0xffd80013,
                 .flags  = IORESOURCE_MEM,
@@ -48,16 +151,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "tmu012_fck",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffd80014,
                 .end    = 0xffd8001f,
                 .flags  = IORESOURCE_MEM,
@@ -79,15 +179,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "tmu012_fck",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffd80020,
                 .end    = 0xffd8002f,
                 .flags  = IORESOURCE_MEM,
@@ -109,15 +206,12 @@ static struct platform_device tmu2_device = {
 };
 
 static struct sh_timer_config tmu3_platform_data = {
-        .name = "TMU3",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "tmu345_fck",
 };
 
 static struct resource tmu3_resources[] = {
         [0] = {
-                .name   = "TMU3",
                 .start  = 0xffdc0008,
                 .end    = 0xffdc0013,
                 .flags  = IORESOURCE_MEM,
@@ -139,15 +233,12 @@ static struct platform_device tmu3_device = {
 };
 
 static struct sh_timer_config tmu4_platform_data = {
-        .name = "TMU4",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "tmu345_fck",
 };
 
 static struct resource tmu4_resources[] = {
         [0] = {
-                .name   = "TMU4",
                 .start  = 0xffdc0014,
                 .end    = 0xffdc001f,
                 .flags  = IORESOURCE_MEM,
@@ -169,15 +260,12 @@ static struct platform_device tmu4_device = {
 };
 
 static struct sh_timer_config tmu5_platform_data = {
-        .name = "TMU5",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "tmu345_fck",
 };
 
 static struct resource tmu5_resources[] = {
         [0] = {
-                .name   = "TMU5",
                 .start  = 0xffdc0020,
                 .end    = 0xffdc002b,
                 .flags  = IORESOURCE_MEM,
@@ -198,76 +286,149 @@ static struct platform_device tmu5_device = {
         .num_resources  = ARRAY_SIZE(tmu5_resources),
 };
 
-static struct plat_sci_port sci_platform_data[] = {
+/* DMA */
+static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
         {
-                .mapbase        = 0xffea0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 40, 40, 40 },
-                .clk            = "scif_fck",
+                .offset = 0,
+                .dmars = 0,
+                .dmars_bit = 0,
         }, {
-                .mapbase        = 0xffeb0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 44, 44, 44, 44 },
-                .clk            = "scif_fck",
+                .offset = 0x10,
+                .dmars = 0,
+                .dmars_bit = 8,
         }, {
-                .mapbase        = 0xffec0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 60, 60, 60, 60 },
-                .clk            = "scif_fck",
+                .offset = 0x20,
+                .dmars = 4,
+                .dmars_bit = 0,
         }, {
-                .mapbase        = 0xffed0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 61, 61, 61, 61 },
-                .clk            = "scif_fck",
+                .offset = 0x30,
+                .dmars = 4,
+                .dmars_bit = 8,
         }, {
-                .mapbase        = 0xffee0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 62, 62, 62, 62 },
-                .clk            = "scif_fck",
+                .offset = 0x50,
+                .dmars = 8,
+                .dmars_bit = 0,
         }, {
-                .mapbase        = 0xffef0000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
-                .scbrr_algo_id  = SCBRR_ALGO_1,
-                .type           = PORT_SCIF,
-                .irqs           = { 63, 63, 63, 63 },
-                .clk            = "scif_fck",
+                .offset = 0x60,
+                .dmars = 8,
+                .dmars_bit = 8,
+        }
+};
+
+static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
+        {
+                .offset = 0,
         }, {
-                .flags = 0,
+                .offset = 0x10,
+        }, {
+                .offset = 0x20,
+        }, {
+                .offset = 0x30,
+        }, {
+                .offset = 0x50,
+        }, {
+                .offset = 0x60,
         }
 };
 
-static struct platform_device sci_device = {
-        .name           = "sh-sci",
-        .id             = -1,
+static const unsigned int ts_shift[] = TS_SHIFT;
+
+static struct sh_dmae_pdata dma0_platform_data = {
+        .channel        = sh7785_dmae0_channels,
+        .channel_num    = ARRAY_SIZE(sh7785_dmae0_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+static struct sh_dmae_pdata dma1_platform_data = {
+        .channel        = sh7785_dmae1_channels,
+        .channel_num    = ARRAY_SIZE(sh7785_dmae1_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+static struct resource sh7785_dmae0_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xfc808020,
+                .end    = 0xfc80808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* DMARSx */
+                .start  = 0xfc809000,
+                .end    = 0xfc80900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
+                .start  = 33,
+                .end    = 33,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+};
+
+static struct resource sh7785_dmae1_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xfcc08020,
+                .end    = 0xfcc0808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        /* DMAC1 has no DMARS */
+        {
+                /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
+                .start  = 52,
+                .end    = 52,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+};
+
+static struct platform_device dma0_device = {
+        .name           = "sh-dma-engine",
+        .id             = 0,
+        .resource       = sh7785_dmae0_resources,
+        .num_resources  = ARRAY_SIZE(sh7785_dmae0_resources),
+        .dev            = {
+                .platform_data  = &dma0_platform_data,
+        },
+};
+
+static struct platform_device dma1_device = {
+        .name           = "sh-dma-engine",
+        .id             = 1,
+        .resource       = sh7785_dmae1_resources,
+        .num_resources  = ARRAY_SIZE(sh7785_dmae1_resources),
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &dma1_platform_data,
         },
 };
 
 static struct platform_device *sh7785_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
         &tmu3_device,
         &tmu4_device,
         &tmu5_device,
-        &sci_device,
+        &dma0_device,
+        &dma1_device,
 };
 
 static int __init sh7785_devices_setup(void)
@@ -275,9 +436,15 @@ static int __init sh7785_devices_setup(void)
         return platform_add_devices(sh7785_devices,
                                     ARRAY_SIZE(sh7785_devices));
 }
-__initcall(sh7785_devices_setup);
+arch_initcall(sh7785_devices_setup);
 
 static struct platform_device *sh7785_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -482,17 +649,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ3-0 + IRQ7-4 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         /* disable holding function, ie enable "SH-4 Mode" */
-        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -502,32 +669,32 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ7654:
                 /* select IRQ mode for IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq4567);
                 break;
         case IRQ_MODE_IRQ3210:
                 /* select IRQ mode for IRL3-0 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq0123);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl4567);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl0123);
                 break;
         default: