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authorPaul Mundt <lethal@linux-sh.org>2009-05-14 04:38:46 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-05-14 04:38:46 -0400
commit549b5e358d17a8c04953ed80896ce07d37722451 (patch)
treec9cf2badccaf4868f3ba014b67a73983e7f7d1a9 /arch/sh/kernel/cpu/sh4a/setup-sh7785.c
parentcedcf3366f2191885aff92d33d6078ef08203e52 (diff)
sh: clkfwk: Add MSTP bits to SH7785 clock framework.
This plugs in all of the MSTP functions in to the clock framework, and hands them off to the platform devices that want them. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7785.c')
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c18
1 files changed, 12 insertions, 6 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index d7e77bc77e28..af561402570b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -20,7 +20,7 @@ static struct sh_timer_config tmu0_platform_data = {
20 .name = "TMU0", 20 .name = "TMU0",
21 .channel_offset = 0x04, 21 .channel_offset = 0x04,
22 .timer_bit = 0, 22 .timer_bit = 0,
23 .clk = "peripheral_clk", 23 .clk = "tmu012_fck",
24 .clockevent_rating = 200, 24 .clockevent_rating = 200,
25}; 25};
26 26
@@ -51,7 +51,7 @@ static struct sh_timer_config tmu1_platform_data = {
51 .name = "TMU1", 51 .name = "TMU1",
52 .channel_offset = 0x10, 52 .channel_offset = 0x10,
53 .timer_bit = 1, 53 .timer_bit = 1,
54 .clk = "peripheral_clk", 54 .clk = "tmu012_fck",
55 .clocksource_rating = 200, 55 .clocksource_rating = 200,
56}; 56};
57 57
@@ -82,7 +82,7 @@ static struct sh_timer_config tmu2_platform_data = {
82 .name = "TMU2", 82 .name = "TMU2",
83 .channel_offset = 0x1c, 83 .channel_offset = 0x1c,
84 .timer_bit = 2, 84 .timer_bit = 2,
85 .clk = "peripheral_clk", 85 .clk = "tmu012_fck",
86}; 86};
87 87
88static struct resource tmu2_resources[] = { 88static struct resource tmu2_resources[] = {
@@ -112,7 +112,7 @@ static struct sh_timer_config tmu3_platform_data = {
112 .name = "TMU3", 112 .name = "TMU3",
113 .channel_offset = 0x04, 113 .channel_offset = 0x04,
114 .timer_bit = 0, 114 .timer_bit = 0,
115 .clk = "peripheral_clk", 115 .clk = "tmu345_fck",
116}; 116};
117 117
118static struct resource tmu3_resources[] = { 118static struct resource tmu3_resources[] = {
@@ -142,7 +142,7 @@ static struct sh_timer_config tmu4_platform_data = {
142 .name = "TMU4", 142 .name = "TMU4",
143 .channel_offset = 0x10, 143 .channel_offset = 0x10,
144 .timer_bit = 1, 144 .timer_bit = 1,
145 .clk = "peripheral_clk", 145 .clk = "tmu345_fck",
146}; 146};
147 147
148static struct resource tmu4_resources[] = { 148static struct resource tmu4_resources[] = {
@@ -172,7 +172,7 @@ static struct sh_timer_config tmu5_platform_data = {
172 .name = "TMU5", 172 .name = "TMU5",
173 .channel_offset = 0x1c, 173 .channel_offset = 0x1c,
174 .timer_bit = 2, 174 .timer_bit = 2,
175 .clk = "peripheral_clk", 175 .clk = "tmu345_fck",
176}; 176};
177 177
178static struct resource tmu5_resources[] = { 178static struct resource tmu5_resources[] = {
@@ -204,31 +204,37 @@ static struct plat_sci_port sci_platform_data[] = {
204 .flags = UPF_BOOT_AUTOCONF, 204 .flags = UPF_BOOT_AUTOCONF,
205 .type = PORT_SCIF, 205 .type = PORT_SCIF,
206 .irqs = { 40, 40, 40, 40 }, 206 .irqs = { 40, 40, 40, 40 },
207 .clk = "scif_fck",
207 }, { 208 }, {
208 .mapbase = 0xffeb0000, 209 .mapbase = 0xffeb0000,
209 .flags = UPF_BOOT_AUTOCONF, 210 .flags = UPF_BOOT_AUTOCONF,
210 .type = PORT_SCIF, 211 .type = PORT_SCIF,
211 .irqs = { 44, 44, 44, 44 }, 212 .irqs = { 44, 44, 44, 44 },
213 .clk = "scif_fck",
212 }, { 214 }, {
213 .mapbase = 0xffec0000, 215 .mapbase = 0xffec0000,
214 .flags = UPF_BOOT_AUTOCONF, 216 .flags = UPF_BOOT_AUTOCONF,
215 .type = PORT_SCIF, 217 .type = PORT_SCIF,
216 .irqs = { 60, 60, 60, 60 }, 218 .irqs = { 60, 60, 60, 60 },
219 .clk = "scif_fck",
217 }, { 220 }, {
218 .mapbase = 0xffed0000, 221 .mapbase = 0xffed0000,
219 .flags = UPF_BOOT_AUTOCONF, 222 .flags = UPF_BOOT_AUTOCONF,
220 .type = PORT_SCIF, 223 .type = PORT_SCIF,
221 .irqs = { 61, 61, 61, 61 }, 224 .irqs = { 61, 61, 61, 61 },
225 .clk = "scif_fck",
222 }, { 226 }, {
223 .mapbase = 0xffee0000, 227 .mapbase = 0xffee0000,
224 .flags = UPF_BOOT_AUTOCONF, 228 .flags = UPF_BOOT_AUTOCONF,
225 .type = PORT_SCIF, 229 .type = PORT_SCIF,
226 .irqs = { 62, 62, 62, 62 }, 230 .irqs = { 62, 62, 62, 62 },
231 .clk = "scif_fck",
227 }, { 232 }, {
228 .mapbase = 0xffef0000, 233 .mapbase = 0xffef0000,
229 .flags = UPF_BOOT_AUTOCONF, 234 .flags = UPF_BOOT_AUTOCONF,
230 .type = PORT_SCIF, 235 .type = PORT_SCIF,
231 .irqs = { 63, 63, 63, 63 }, 236 .irqs = { 63, 63, 63, 63 },
237 .clk = "scif_fck",
232 }, { 238 }, {
233 .flags = 0, 239 .flags = 0,
234 } 240 }