diff options
author | Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | 2008-07-07 08:11:51 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2008-07-28 05:10:34 -0400 |
commit | a4e1d08491b06b17eb77c92caacd40b330ca8146 (patch) | |
tree | 9a32eeb9286d917a5f28932f7a77988451960da4 /arch/sh/kernel/cpu/sh4a/setup-sh7343.c | |
parent | 73382f710b83b84b3cffb1f4850f5292c12edfd2 (diff) |
sh: update sh7343 code
updated the following codes for SH7343:
- add register_intc_controller()
- add EARLY_SCIF_CONSOLE_PORT
- add define of CPG register
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7343.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7343.c | 135 |
1 files changed, 135 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c index 612002e9b261..3e3b5029599a 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c | |||
@@ -84,6 +84,141 @@ static int __init sh7343_devices_setup(void) | |||
84 | } | 84 | } |
85 | __initcall(sh7343_devices_setup); | 85 | __initcall(sh7343_devices_setup); |
86 | 86 | ||
87 | enum { | ||
88 | UNUSED = 0, | ||
89 | |||
90 | /* interrupt sources */ | ||
91 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, | ||
92 | DMAC0, DMAC1, DMAC2, DMAC3, | ||
93 | VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, | ||
94 | MFI, VPU, TPU, Z3D4, USBI0, USBI1, | ||
95 | MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY, | ||
96 | DMAC4, DMAC5, DMAC_DADERR, | ||
97 | KEYSC, | ||
98 | SCIF, SCIF1, SCIF2, SCIF3, SCIF4, | ||
99 | SIOF0, SIOF1, SIO, | ||
100 | FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, | ||
101 | I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, | ||
102 | I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, | ||
103 | SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, | ||
104 | IRDA, | ||
105 | SDHI0, SDHI1, SDHI2, SDHI3, | ||
106 | CMT, TSIF, SIU, | ||
107 | TMU0, TMU1, TMU2, | ||
108 | JPU, LCDC, | ||
109 | |||
110 | /* interrupt groups */ | ||
111 | |||
112 | DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB, | ||
113 | }; | ||
114 | |||
115 | static struct intc_vect vectors[] __initdata = { | ||
116 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), | ||
117 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), | ||
118 | INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), | ||
119 | INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), | ||
120 | INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0), | ||
121 | INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0), | ||
122 | INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), | ||
123 | INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), | ||
124 | INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), | ||
125 | INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), | ||
126 | INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), | ||
127 | INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0), | ||
128 | INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40), | ||
129 | INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20), | ||
130 | INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60), | ||
131 | INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), | ||
132 | INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), | ||
133 | INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20), | ||
134 | INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60), | ||
135 | INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0), | ||
136 | INTC_VECT(SIO, 0xd00), | ||
137 | INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), | ||
138 | INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), | ||
139 | INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20), | ||
140 | INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60), | ||
141 | INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), | ||
142 | INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), | ||
143 | INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), | ||
144 | INTC_VECT(SIU, 0xf80), | ||
145 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), | ||
146 | INTC_VECT(TMU2, 0x440), | ||
147 | INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), | ||
148 | }; | ||
149 | |||
150 | static struct intc_group groups[] __initdata = { | ||
151 | INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), | ||
152 | INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), | ||
153 | INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR), | ||
154 | INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), | ||
155 | INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, | ||
156 | FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), | ||
157 | INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), | ||
158 | INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), | ||
159 | INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI), | ||
160 | INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), | ||
161 | INTC_GROUP(USB, USBI0, USBI1), | ||
162 | }; | ||
163 | |||
164 | static struct intc_mask_reg mask_registers[] __initdata = { | ||
165 | { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ | ||
166 | { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, | ||
167 | { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ | ||
168 | { 0, 0, 0, VPU, 0, 0, 0, MFI } }, | ||
169 | { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ | ||
170 | { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, | ||
171 | { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ | ||
172 | { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, | ||
173 | { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ | ||
174 | { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } }, | ||
175 | { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ | ||
176 | { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } }, | ||
177 | { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ | ||
178 | { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, | ||
179 | FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, | ||
180 | { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ | ||
181 | { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } }, | ||
182 | { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ | ||
183 | { 0, 0, 0, CMT, 0, USBI1, USBI0 } }, | ||
184 | { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ | ||
185 | { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } }, | ||
186 | { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ | ||
187 | { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } }, | ||
188 | { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ | ||
189 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | ||
190 | }; | ||
191 | |||
192 | static struct intc_prio_reg prio_registers[] __initdata = { | ||
193 | { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, | ||
194 | { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, | ||
195 | { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } }, | ||
196 | { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, | ||
197 | { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } }, | ||
198 | { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } }, | ||
199 | { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } }, | ||
200 | { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } }, | ||
201 | { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } }, | ||
202 | { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } }, | ||
203 | { 0xa4140010, 0, 32, 4, /* INTPRI00 */ | ||
204 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | ||
205 | }; | ||
206 | |||
207 | static struct intc_sense_reg sense_registers[] __initdata = { | ||
208 | { 0xa414001c, 16, 2, /* ICR1 */ | ||
209 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | ||
210 | }; | ||
211 | |||
212 | static struct intc_mask_reg ack_registers[] __initdata = { | ||
213 | { 0xa4140024, 0, 8, /* INTREQ00 */ | ||
214 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | ||
215 | }; | ||
216 | |||
217 | static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups, | ||
218 | mask_registers, prio_registers, sense_registers, | ||
219 | ack_registers); | ||
220 | |||
87 | void __init plat_irq_setup(void) | 221 | void __init plat_irq_setup(void) |
88 | { | 222 | { |
223 | register_intc_controller(&intc_desc); | ||
89 | } | 224 | } |