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authorMagnus Damm <damm@opensource.se>2010-05-11 03:06:13 -0400
committerPaul Mundt <lethal@linux-sh.org>2010-05-13 04:35:05 -0400
commit914ebf0bbb24696cd7eecee8942efecca5653126 (patch)
tree5ca384ba927ada56c6a3462977dc6268d6f72b16 /arch/sh/kernel/cpu/sh4a/clock-sh7723.c
parent1fe3d19883b1f6a243b03456a47e0fdc9629bea6 (diff)
sh: get rid of div4 clock name
Remove the name parameter from SH_CLK_DIV4() and adjust the processor specific code. The lookup happens using clkdev so the name is unused. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/clock-sh7723.c')
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 05b112dedd1a..7685504369cc 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -125,29 +125,29 @@ static struct clk_div4_table div4_table = {
125 125
126enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; 126enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
127 127
128#define DIV4(_str, _reg, _bit, _mask, _flags) \ 128#define DIV4(_reg, _bit, _mask, _flags) \
129 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 129 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
130 130
131struct clk div4_clks[DIV4_NR] = { 131struct clk div4_clks[DIV4_NR] = {
132 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), 132 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
133 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), 133 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
134 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), 134 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
135 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), 135 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
136 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), 136 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
137 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0), 137 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
138}; 138};
139 139
140enum { DIV4_IRDA, DIV4_ENABLE_NR }; 140enum { DIV4_IRDA, DIV4_ENABLE_NR };
141 141
142struct clk div4_enable_clks[DIV4_ENABLE_NR] = { 142struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
143 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0), 143 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
144}; 144};
145 145
146enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; 146enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
147 147
148struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { 148struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
149 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0), 149 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
150 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0), 150 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
151}; 151};
152enum { DIV6_V, DIV6_NR }; 152enum { DIV6_V, DIV6_NR };
153 153