sh: TLB miss fast-path optimizations.

Handle simple TLB miss faults which can be resolved completely
from the page table in assembler.

Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

1 files changed, 11 insertions, 8 deletions

diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index c294de1e14a3..afe0f1b1c030 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -79,16 +79,16 @@ int __init detect_cpu_and_cache_system(void)
         case 0x205:
                 cpu_data->type = CPU_SH7750;
                 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
-                                   CPU_HAS_PERF_COUNTER | CPU_HAS_PTEA;
+                                   CPU_HAS_PERF_COUNTER;
                 break;
         case 0x206:
                 cpu_data->type = CPU_SH7750S;
                 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
-                                   CPU_HAS_PERF_COUNTER | CPU_HAS_PTEA;
+                                   CPU_HAS_PERF_COUNTER;
                 break;
         case 0x1100:
                 cpu_data->type = CPU_SH7751;
-                cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
+                cpu_data->flags |= CPU_HAS_FPU;
                 break;
         case 0x2000:
                 cpu_data->type = CPU_SH73180;
@@ -126,23 +126,22 @@ int __init detect_cpu_and_cache_system(void)
                 break;
         case 0x8000:
                 cpu_data->type = CPU_ST40RA;
-                cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
+                cpu_data->flags |= CPU_HAS_FPU;
                 break;
         case 0x8100:
                 cpu_data->type = CPU_ST40GX1;
-                cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
+                cpu_data->flags |= CPU_HAS_FPU;
                 break;
         case 0x700:
                 cpu_data->type = CPU_SH4_501;
                 cpu_data->icache.ways = 2;
                 cpu_data->dcache.ways = 2;
-                cpu_data->flags |= CPU_HAS_PTEA;
                 break;
         case 0x600:
                 cpu_data->type = CPU_SH4_202;
                 cpu_data->icache.ways = 2;
                 cpu_data->dcache.ways = 2;
-                cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
+                cpu_data->flags |= CPU_HAS_FPU;
                 break;
         case 0x500 ... 0x501:
                 switch (prr) {
@@ -160,7 +159,7 @@ int __init detect_cpu_and_cache_system(void)
                 cpu_data->icache.ways = 2;
                 cpu_data->dcache.ways = 2;
 
-                cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
+                cpu_data->flags |= CPU_HAS_FPU;
 
                 break;
         default:
@@ -173,6 +172,10 @@ int __init detect_cpu_and_cache_system(void)
         cpu_data->dcache.ways = 1;
 #endif
 
+#ifdef CONFIG_CPU_HAS_PTEA
+        cpu_data->flags |= CPU_HAS_PTEA;
+#endif
+
         /*
          * On anything that's not a direct-mapped cache, look to the CVR
          * for I/D-cache specifics.